Interface Logic Octal Transparent Latch, Three-State CD54/74FCT37

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Interface Logic Octal Transparent Latch, Three-State CD54/74FCT37

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CD54/74FCT373, CD54/74FCT373AT, CD54/74FCT533
Interface Logic Octal Transparent Latch, Three-State
CD54/74FCT373, 373AT, octal transparent latches small-geometry BiCMOS technology. output stage combination bipolar CMOS transistors that limits output-HIGH level diode drops below VCC. This resultant lowering output swing 3.7V) reduces power ringing source EMI) minimizes bounce ground bounce their effects during simultaneous output switching. output configuration also enhances switching speed capable sinking 32mA 48mA. CD54/74FCT373, 373AT, outputs transparent inputs when Latch Enable (LE) HIGH. When Latch Enable (LE) goes LOW, data latched. Output Enable (OE) controls three-state outputs. When Output Enable (OE) HIGH, outputs highimpedance state. latch operation independent state Output Enable.
February 1996
Features
CD54/74FCT373, CD54/74FCT373AT Non-Inverting CD54/74FCT533 Inverting Buffered inputs Typical Propagation Delay: 3.9ns +25oC, 50pF (FCT373AT) SCR-Latchup-Resistant BiCMOS Process Circuit Design FCTXXX Types Speed Bipolar FAST®/AS/S; FCTXXXAT Types Faster than FAST/AS/S with Significantly Reduced Power Consumption 48mA 32mA Output Sink Current (Commercial/ Extended Industrial) Output Voltage Swing Limited 3.7V Controlled Output-Edge Rates Input/Output Isolation BiCMOS Technology with Quiescent Power
Ordering Information
PART NUMBER CD54/74FCT373E CD54/74FCT373ATE CD54/74FCT533E CD54/74FCT373M CD54/74FCT373ACD54/74FCT533M CD54/74FCT373SM CD54/74FCT533SM CD54FCT373H CD54FCT533H TEMP. RANGE (oC) 125, 125, 125, 125, 125, 125, 125, 125, PACKAGE PDIP PDIP PDIP SOIC SOIC SOIC SSOP SSOP
Functional Diagram
TRUTH TABLE
OUTPUT ENABLE
LATCH ENABLE
DATA
373, 373AT OUTPUT
OUTPUT
HIGH voltage level. voltage level. Irrelevant. HIGH Impedance.
voltage level setup time prior high-to-low latch enable transition. HIGH voltage level setup time prior high-to-low latch enable transition.
FAST® registered trademark Fairchild Semiconductor Corporation.
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
Harris Corporation 1996
File Number
2230.2
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Copyright 1999, Texas Instruments Incorporated

Interface Logic Octal Transparent Latch, Three-State CD54/74FCT37

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