SMJ: Processing MIL-PRF-38535 Standard Processing TMP: Commercial Leve

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SMJ: Processing MIL-PRF-38535 Standard Processing TMP: Commercial Leve

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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
SMJ: Processing MIL-PRF-38535 Standard Processing TMP: Commercial Level Processing Operating Temperature Ranges: Military -55°C 125°C Special -55°C 100°C Commercial -25°C 85°C Commercial 70°C Highest Performance Floating-Point Digital Signal Processor (DSP) 'C40-60: 33-ns Instruction Cycle Time: MFLOPS, MIPS, MOPS, MBps 'C40-50: 40-ns Instruction Cycle Time: MFLOPS, MIPS, MOPS, MBps 'C40-40: 50-ns Instruction Cycle Time: MFLOPS, MIPS, MOPS, MBps Communications Ports 6-Channel Direct Memory Access (DMA) Coprocessor Single-Cycle Conversion From IEEE-745 Floating-Point Format Single Cycle 1/x, Source-Code Compatible With SMJ320C30 Validated Compiler Single-Cycle 40-Bit Floating-Point, 32-Bit Integer Multipliers 40-Bit Registers, Auxiliary Registers, Control Registers, Timers
IEEE Standard 1149.1 Test-Access Port
(JTAG)
Identical External Data Address
Buses Supporting Shared Memory Systems High Data-Rate, Single-Cycle Transfers: High Port-Data Rate MBytes/s (Each Bus) 16G-Byte Continuous Program/Data/Peripheral Address Space Memory-Access Request Fast, Intelligent Arbitration Separate Address-, Data-, Control-Enable Pins Four Sets Memory-Control Signals Support Different Speed Memories Hardware Packaging: 325-Pin Ceramic Grid Array Suffix) 352-Lead Ceramic Quad Flatpack (HFH Suffix) 324-Pad JEDEC-Standard Frame Fabricated Using 0.72-µm Enhanced Performance Implanted CMOS (EPICTM) Technology Texas Instruments (TITM) Separate Internal Program, Data, Coprocessor Buses Support Massive Concurrent Input/Output (I/O) Program Data Throughput, Maximizing Sustained Central Processing Unit (CPU) Performance On-Chip Program Cache Dual-Access/Single-Cycle Increased Memory-Access Performance 512-Byte Instruction Cache Bytes Single-Cycle Dual-Access Program Data ROM-Based Bootloader Supports Program Bootup Using 16-, 32-Bit Memories Over Communications Ports
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port Boundary-Scan Architecture. EPIC trademarks Texas Instruments Incorporated.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2000, Texas Instruments Incorporated
products compliant 38535, parameters tested unless otherwise noted. other products, production processing does necessarily include testing parameters.
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
description
352-LEAD QUAD FLATPACK PACKAGE (TOP VIEW)
325-PIN GRID ARRAY PACKAGE (BOTTOM VIEW)
325-LEAD OLB/ILB TAPE AUTOMATED BONDING (TAB) PACKAGE (TOP VIEW)
assignments tables signal description table location description pins.
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
description (continued)
'320C40 digital signal processors (DSPs) 32-bit, floating-point processors manufactured 0.72-µm, double-level metal CMOS technology. '320C40 part fourth-generation DSPs from Texas Instruments designed primarily parallel processing.
operation
'320C40 on-chip communication ports processor-to-processor communication with external hardware simple communication software. This allows connectivity other 'C4x processors with external-glue logic. communication ports remove input/output bottlenecks, independent smart coprocessor able handle input/output burden. central processing unit '320C40 configured high-speed internal parallelism highest sustained performance. features are:
Eight operations/cycle:
40/32-bit floating-point/integer multiply 40/32-bit floating-point/integer arithmetic logic unit (ALU) operation data accesses address-register updates
IEEE floating-point conversion Divide square-root support 'C3x assembly language compatibility Byte halfword accessibility
coprocessor coprocessor allows concurrent processing highest sustained performance. features processor are:
Link pointers that allow channels autoinitialize without intervention Parallel operation transfers channels that support memory-to-memory data transfers Split-mode operation doubles available channels when data transfers from communication port required.
communication ports '320C40 first with on-chip communication ports processor-to-processor communication with external hardware simple communication software. features communication ports are:
Direct interprocessor communication processor communication ports direct interprocessor communication processor 20M-byte/s bidirectional interface each communication port high-speed multiprocessor interface Separate 8-word-deep input output FIFO buffers processor-to-processor communication Automatic arbitration handshaking direct processor-to-processor connection
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
communication-port software reset ('C40 silicon revision 5.0) input output FIFO levels communication port flushed writing least back-to-back values communication-port software-reset address specified Table This feature present 'C40 silicon revision 5.0. This software reset flushes word byte already present FIFOs does affect status communication-port pins. Figure shows example communication-port-software reset. Table Communication-Port Software-Reset Address
0x0100043 0x0100053 0x0100063 0x0100073 0x0100083 0x0100093
RESET1:Flush's FIFO data communication port RESET1 push Save registers push push ldhi 010h,AR0 base address 050h,AR0 flush: rpts Flush FIFO data with back-to-back write R0,*+AR0(3) rpts Wait *+AR0(0),R0 Check data from other port 01FE0h,R0 flush Restore registers rets Return
Figure Example Communication-Port-Software Reset
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
with bus-grant feature ('C40 silicon revision 5.0) '320C40 devices have software-configurable feature that forces internal-peripheral ready when signal asserted. This feature present 'C40 silicon revision 5.0. bus-grant feature enabled when bits 19-18 status register (ST) 10b. When enabled, peripheral bus-grant signal generated falling edge NMI. When asserted this feature enabled, stalls access peripheral ready. stall condition occurs when writing full FIFO reading empty FIFO. This feature useful correcting communication-port errors when used conjunction with communication-port software-reset feature. IDLE2 clock-stop power-down mode ('C40 silicon revision 5.0) '320C40 clock-stop mode power-down mode (IDLE2) achieve extremely power consumption. When IDLE2 instruction executed, clocks halted with being held high. exit IDLE2, assert IIOF3-IIOF0 pins configured external interrupt instead general-purpose I/O. macro showing generate IDLE2 opcode given Figure During this power-down mode:
instructions executed CPU, peripherals, internal memory retain their previous state. external-bus outputs idle. address lines remain their previous state, data lines
high-impedance state, output-control signals inactive.
IDLE2: Macro generate idle2 opcode IDLE2 .macro .word 06000001h .endm
Figure Example Software Subroutine Using IDLE2 IDLE2 exited when five external interrupts (NMI IIOF3-IIOF0) asserted least four input clocks (two cycles). clocks then start after delay input clocks (one cycle). clocks start opposite phase; that high when high before clocks were stopped. However, clocks remain 180° phase with each other. During IDLE2 operation, external interrupt recognized serviced enabled before entering IDLE2 asserted least cycles. processor recognize only interrupt, interrupt must configured edge-trigger mode asserted less than three cycles level-trigger mode. external interrupt wake device from IDLE2, recognize that interrupt, must also enabled. interrupt recognized executed CPU, instruction following IDLE2 instruction executed until after execution return opcode. When device emulation mode, executes IDLE2 instruction were IDLE instruction. clocks continue correct operation emulator.
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
development tools 'C40 supported host parallel-processing development tools developing simulating code easily debugging parallel-processing systems. code generation tools include:
ANSI compiler optimized with runtime support library that supports communication ports
DMA.
Third-party support C++, compilers Several operating systems available parallel-processing support, well communication
port drivers
assembler linker with support mapping program data parallel processors
simulation tools include:
Parallel system-level simulation with hardware verification (HV) model full function (FF) model software simulator with high-level language debugger interface simulating single processor
hardware development verification tools include:
Parallel processor in-circuit emulator high-level language debugger: XDS510D Parallel processor development system (PPDS) with four '320C40s, local global memory,
communication port connections
XDS510 trademark Texas Instruments Incorporated.
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
block diagram
Cache (512 Bytes) Block Bytes) Block Bytes) Block (Reserved)
PDATA D31-D0 A30-A0 STAT3-STAT0 LOCK STRB0,STRB1 R/W0,RW1 PAGE0,PAGE1 RDY0,RDY1 CE0,CE1 PADDR DDATA DADDR DADDR DMADATA DMAADDR Continued next page CPU1 CPU2 REG1 REG2 Multiplier Extended Precision Registers (R0-R11)
DISP, IR0, ARAU0 ARAU1
X2/CLKIN ROMEN RESET RESETLOC0, RESETLOC1 IIOF3-IIOF0 IACK CVSS DVDD DVSS IVSS LADVDD LDDVDD VDDL VSSL SUBS
32-Bit Barrel Shifter
Other Registers (14) Auxiliary Registers (AR0-AR7)
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
block diagram (continued)
Continued from previous page
PDATA PADDR DDATA DADDR DADDR DMADATA DMAADDR
LD31-LD0 LA30-LA0 LSTAT3-LSTAT0 LLOCK LSTRB0-LSTRB1 LR/W0-LR/W1 LPAGE0-LPAGE1 LRDY0-LRDY1 LCE0, LCE1
Coprocessor Channel Channel Channel Channel Channel Channel Port Input FIFO Output FIFO Port Control Registers
Channels
Port Input FIFO Output FIFO Port Control Registers Timer Global Control Register Time Period Register Timer Counter Register Timer Global Control Register Time Period Register Timer Counter Register Port Control Global Local
CREQ5 CACK5 CSTRB5 CRDY5 C5D7-C5D0
TCLK0
TCLK1
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Communication Ports
CREQ0 CACK0 CSTRB0 CRDY0 C0D7-C0D0
SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
memory
Figure shows memory '320C40. TMS320C4x User's Guide (literature number SPRU063) detailed description this memory mapping.
000000000h Structure Depends Upon ROMEN Accessible Local (External) 000000FFFh 000001000h Boot-Loader (Internal)
Reserved 0000FFFFFh 000100000h 0001000FFh 000100100h Reserved 0001FFFFFh 000200000h Reserved 0002FF7FFh 0002FF800h 0002FFBFFh 0002FFC00h 0002FFFFFh 000300000h Reserved Reserved
Peripherals (Internal)
Peripherals (Internal)
(Internal) (Internal)
(Internal) (Internal)
Structure Identical
2G-3M Local (External) Local (External)
07FFFFFFFh 080000000h
Global (External)
Global (External)
0FFFFFFFFh Internal Disabled (ROMEN Microprocessor Mode Internal Enabled (ROMEN Microcomputer Mode
Figure Memory '320C40
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
signal descriptions
This section gives signal descriptions SMJ320C40 device. SMJ320C40 signal descriptions table lists each signal, number pins, operating mode(s) (that input, output, high-impedance state indicated respectively), function. pins labeled connected user. line over signal name (for example, RESET) indicates that signal active (true logic-0 level). signals grouped according functions.
SMJ320C40 Signal Descriptions
SIGNAL NAME PINS TYPE DESCRIPTION GLOBAL EXTERNAL INTERFACE PINS) D31-D0 A30-A0 STAT3-STAT0 LOCK STRB0 R/W0 PAGE0 RDY0 STRB1 R/W1 PAGE1 RDY1 LD31-LD0 LA30-LA0 LSTAT3-LSTAT0 LLOCK LSTRB0 LR/W0 LPAGE0 LRDY0 LCE0 LSTRB1 I/O/Z I/O/Z 32-bit data port global external interface Data-bus-enable signal global external interface 31-bit address port global external interface Address-bus-enable signal global external interface Status signals global external interface Lock signal global external interface Access strobe global external interface Read/write signal STRB0 accesses Page signal STRB0 accesses Ready signal STRB0 accesses Control enable STRB0, PAGE0, R/W0 signals Access strobe global external interface Read/write signal STRB1 accesses Page signal STRB1 accesses Ready signal STRB1 accesses Control enable STRB1, PAGE1, R/W1 signals LOCAL EXTERNAL INTERFACE PINS) 32-bit data port local external interface Data-bus-enable signal local external interface 31-bit address port local external interface Address-bus-enable signal local external interface Status signals local external interface Lock signal local external interface Access strobe local external interface Read/write signal LSTRB0 accesses Page signal LSTRB0 accesses Ready signal LSTRB0 accesses Control enable LSTRB0, LPAGE0, LR/W0 signals Access strobe local external interface
LR/W1 Read/write signal LSTRB1 accesses input, output, high impedance STRB0, STRB1 associated signals (R/W1, R/W0, PAGE0, PAGE1, etc.) effective over address ranges defined STRB ACTIVE bits. package additional power ground pins reduce noise problems.
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
signal descriptions (continued)
SMJ320C40 Signal Descriptions (Continued)
SIGNAL NAME PINS TYPE DESCRIPTION
LOCAL EXTERNAL INTERFACE PINS) (CONTINUED) LPAGE1 LRDY1 LCE1 C0D7-C0D0 CREQ0 CACK0 CSTRB0 CRDY0 C1D7-C1D0 CREQ1 CACK1 CSTRB1 CRDY1 C2D7-C2D0 CREQ2 CACK2 CSTRB2 CRDY2 C3D7-C3D0 CREQ3 CACK3 CSTRB3 CRDY3 C4D7-C4D0 CREQ4 CACK4 CSTRB4 Page signal LSTRB1 accesses Ready signal LSTRB1 accesses Control enable LSTRB1, LPAGE1, LR/W1 signals COMMUNICATION PORT INTERFACE PINS) Communication port data Communication port token-request signal Communication port token-request-acknowledge signal Communication port data-strobe signal Communication port data-ready signal COMMUNICATION PORT INTERFACE PINS) Communication port data Communication port token-request signal Communication port token-request-acknowledge signal Communication port data-strobe signal Communication port data-ready signal COMMUNICATION PORT INTERFACE PINS) Communication port data Communication port token-request signal Communication port token-request-acknowledge signal Communication port data-strobe signal Communication port data-ready signal COMMUNICATION PORT INTERFACE PINS) Communication port data Communication port token-request signal Communication port token-request-acknowledge signal Communication port data-strobe signal Communication port data-ready signal COMMUNICATION PORT INTERFACE PINS) Communication port data Communication port token-request signal Communication port token-request-acknowledge signal Communication port data-strobe signal
CRDY4 Communication port data-ready signal input, output, high impedance STRB0, STRB1 associated signals (R/W1, R/W0, PAGE0, PAGE1, etc.) effective over address ranges defined STRB ACTIVE bits. package additional power ground pins reduce noise problems.
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
signal descriptions (continued)
SMJ320C40 Signal Descriptions (Continued)
SIGNAL NAME PINS TYPE DESCRIPTION COMMUNICATION PORT INTERFACE PINS) C5D7-C5D0 CREQ5 CACK5 CSTRB5 CRDY5 IIOF3-IIOF0 IACK RESET RESETLOC1- RESETLOC0 ROMEN TCLK0 TCLK1 X2/CLKIN CVSS DVSS IVSS DVDD GADVDD GDDVDD LADVDD LDDVDD SUBS VDDL VSSL Communication port data Communication port token-request signal Communication port token-request-acknowledge signal Communication port data-strobe signal Communication port data-ready signal INTERRUPTS, FLAGS, RESET, TIMER PINS) Interrupt flags Nonmaskable interrupt. sensitive low-going edge. Interrupt acknowledge Reset signal Reset-vector location pins On-chip enable disable, enable) Timer Timer CLOCK PINS) Crystal Crystal/oscillator clock clock POWER GROUND Ground pins Ground pins Ground pins 5-VDC supply pins 5-VDC supply pins 5-VDC supply pins 5-VDC supply pins 5-VDC supply pins Substrate (tie ground) 5-VDC supply pins Ground pins
input, output, high impedance STRB0, STRB1 associated signals (R/W1, R/W0, PAGE0, PAGE1, etc.) effective over address ranges defined STRB ACTIVE bits. package additional power ground pins reduce noise problems.
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
signal descriptions (continued)
SMJ320C40 Signal Descriptions (Continued)
SIGNAL NAME PINS TYPE EMULATION PINS) TRST EMU0 IEEE 1149.1 test port clock IEEE 1149.1 test port data IEEE 1149.1 test port data IEEE 1149.1 test port mode select IEEE 1149.1 test port reset Emulation DESCRIPTION
EMU1 Emulation input, output, high impedance STRB0, STRB1 associated signals (R/W1, R/W0, PAGE0, PAGE1, etc.) effective over address ranges defined STRB ACTIVE bits. package additional power ground pins reduce noise problems.
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
package assignments alphabetical listing
NAME C0D0 C0D1 C0D2 C0D3 C0D4 C0D5 AG31 NAME C0D6 C0D7 C1D0 C1D1 C1D2 C1D3 C1D4 C1D5 C1D6 C1D7 C2D0 C2D1 C2D2 C2D3 C2D4 C2D5 C2D6 C2D7 C3D0 C3D1 C3D2 C3D3 C3D4 C3D5 C3D6 C3D7 C4D0 C4D1 C4D2 C4D3 C4D4 C4D5 C4D6 C4D7 C5D0 C5D1 C5D2 C5D3 AK12 AK10 AP10 AM18 AN19 AL19 AP20 AM20 AN21 AL21 AP22 AM22 AN23 AL23 AP24 AM24 AN25 AL25 AP26 AN27 AM26 AK24 AL27 AP28 AK26 AN29 AM28 AL29 AP30 AK28 AN31 NAME C5D4 C5D5 C5D6 C5D7 CACK0 CACK1 CACK2 CACK3 CACK4 CACK5 CRDY0 CRDY1 CRDY2 CRDY3 CRDY4 CRDY5 CREQ0 CREQ1 CREQ2 CREQ3 CREQ4 CREQ5 CSTRB0 CSTRB1 CSTRB2 CSTRB3 CSTRB4 CSTRB5 CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS AM30 AP32 AM32 AL31 AN11 AN13 AM14 AM16 AK32 AJ31 AA33 AP12 AP14 AL15 AL17 AH30 AH32 AM10 AM12 AN15 AN17 AN33 AL33 AL11 AL13 AP16 AP18 AM34 AK34 AR19 AL35 NAME CVSS CVSS CVSS CVSS CVSS CVSS CVSS AR25 AR13 NAME DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS EMU0 EMU1 GADVDD GADVDD GADVDD GDDVDD GDDVDD GDDVDD AA31 AR11 AR29 AR23 AR17 AJ35 AR21 AR15 AR27 AA35 AD34
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
package assignments alphabetical listing (continued)
NAME IACK IIOF0 IIOF1 IIOF2 IIOF3 IVSS IVSS IVSS IVSS IVSS IVSS LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 AR31 AG35 NAME LA25 LA26 LA27 LA28 LA29 LA30 LADVDD LADVDD LADVDD LCE0 LCE1 LD10 LD11 LD12 LD13 LD14 LD15 LD16 LD17 LD18 LD19 LD20 LD21 LD22 LD23 LD24 LD25 AP34 NAME LD26 LD27 LD28 LD29 LD30 LD31 LDDVDD LDDVDD LDDVDD LLOCK LOCK LPAGE0 LPAGE1 LRDY0 LRDY1 LR/W0 LR/W1 LSTAT0 LSTAT1 LSTAT2 LSTAT3 LSTRB0 LSTRB1 PAGE0 PAGE1 RDY0 RDY1 RESETLOC0 RESETLOC1 RESET ROMEN R/W0 R/W1 AR35 AG33 AB32 AF30 AH34 AJ33 AF32 AC31 NAME STAT0 STAT1 STAT2 STAT3 STRB0 STRB1 SUBS TCLK0 TCLK1 TRST VDDL VDDL VDDL VDDL VSSL VSSL VSSL VSSL X2/CLKIN AD32 AE33 AF34 AE31 AD30 AC33 AB34 AC35 AE35 AN35 AR33
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
package assignments numerical listing
AA31 AA33 AA35 AB32 AB34 AC31 AC33 AC35 NAME GDDVDD VSSL IVSS DVDD CVSS DVSS DVDD DVSS DVDD CVSS DVSS DVDD DVSS CVSS DVDD IVSS VSSL GDDVDD X2/CLKIN LSTAT0 LLOCK EMU0 LADVDD PAGE1 DVDD R/W1 STRB1 TCLK1 LSTRB1 AD30 AD32 AD34 AE31 AE33 AE35 AF30 AF32 AF34 AG31 AG33 AG35 AH30 AH32 AH34 AJ31 AJ33 AJ35 AK10 AK12 NAME STRB0 STAT0 EMU1 CVSS TCLK0 LRDY1 STAT3 STAT1 TRST LCE1 LR/W1 LRDY0 RESETLOC0 R/W0 STAT2 DVSS LPAGE1 LCE0 PAGE0 IVSS LPAGE0 LR/W0 IIOF2 CRDY4 CRDY5 RESETLOC1 DVDD LSTRB0 CACK5 RESET DVSS IIOF3 ROMEN C0D7 C1D4 C1D3 AK24 AK26 AK28 AK32 AK34 AL11 AL13 AL15 AL17 AL19 AL21 AL23 AL25 AL27 AL29 AL31 AL33 AL35 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 NAME C4D2 C4D5 C5D2 CACK4 CSTRB5 CVSS IIOF1 C0D1 C1D0 C1D6 CSTRB0 CSTRB1 CRDY2 CRDY3 C2D2 C2D6 C3D2 C3D6 C4D3 C5D0 C5D7 CREQ5 CVSS DVSS C0D3 C0D5 C1D2 CREQ0 CREQ1 CACK2 CACK3 C2D0 C2D4 C3D0 C3D4 C4D1 C4D7 AM30 AM32 AM34 AN11 AN13 AN15 AN17 AN19 AN21 AN23 AN25 AN27 AN29 AN31 AN33 AN35 AP10 AP12 AP14 AP16 AP18 AP20 AP22 AP24 AP26 AP28 AP30 AP32 AP34 NAME C5D4 C5D6 CSTRB4 VDDL IIOF0 C0D2 C0D6 C1D5 CACK0 CACK1 CREQ2 CREQ3 C2D1 C2D5 C3D1 C3D5 C4D0 C4D6 C5D3 CREQ4 VDDL LDDVDD C0D0 C0D4 C1D1 C1D7 CRDY0 CRDY1 CSTRB2 CSTRB3 C2D3 C2D7 C3D3 C3D7 C4D4 C5D1 C5D5 LADVD
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
package assignments numerical listing (continued)
AR11 AR13 AR15 AR17 AR19 AR21 AR23 AR25 AR27 AR29 AR31 AR33 AR35 NAME GADVDD VSSL IVSS CVSS DVSS DVDD CVSS DVSS DVDD CVSS DVSS DVDD CVSS DVSS DVDD IVSS VSSL LDDVDD GADVDD LD26 LD22 LD18 LD12 LADVDD NAME VDDL LD29 LD24 LD20 LD14 LD10 SUBS VDDL LD28 LD23 LD17 LD13 NAME CVSS LD30 LD25 LD19 LD15 LD11 CVSS LD31 LD27 LD21 LD16 DVSS DVSS NAME IVSS LA13 LA12 CVSS LA15 LA14 LA10 DVDD LA16 LA17 DVDD LA18 LA19 LA11 CVSS LA20 LA21 DVSS NAME LA22 LA23 DVSS LA24 LA25 CVSS LA26 LA28 LDDVDD LA27 LA30 GADVDD GDDVDD LA29 IACK LSTAT3 RDY1 LOCK LSTAT2 LSTAT1 RDY0
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
package assignments alphabetical listing
NAME C0D0 C0D1 C0D2 C0D3 C0D4 C0D5 C0D6 NAME C1D0 C1D1 C1D2 C1D3 C1D4 C1D5 C1D6 C1D7 C2D0 C2D1 C2D2 C2D3 C2D4 C2D5 C2D6 C2D7 C3D0 C3D1 C3D2 C3D3 C3D4 C3D5 C3D6 C3D7 C4D0 C4D1 C4D2 C4D3 C4D4 C4D5 C4D6 C4D7 C5D0 C5D1 C5D2 C5D3 C5D4 C5D5 C5D6 NAME CACK0 CACK1 CACK2 CACK3 CACK4 CACK5 CRDY0 CRDY1 CRDY2 CRDY3 CRDY4 CRDY5 CREQ0 CREQ1 CREQ2 CREQ3 CREQ4 CREQ5 CSTRB0 CSTRB1 CSTRB2 CSTRB3 CSTRB4 CSTRB5 CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS NAME CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS NAME DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD
C0D7 C5D7 CVSS IVSS pins connected internally. DVDD, LADVDD, LDDVDD, GDDVDD, GADVDD pins connected internally. DVSS pins connected internally. VDDL pins connected internally. VSSL pins connected internally.
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
package assignments alphabetical listing (continued)
NAME EMU0 EMU1 GADVDD GADVDD GADVDD GADVDD GDDVDD GDDVDD GDDVDD GDDVDD IACK IIOF0 IIOF1 IIOF2 IIOF3 IVSS IVSS IVSS IVSS IVSS IVSS IVSS LA10 NAME LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LA26 LA27 LA28 LA29 LA30 LADVDD LADVDD LADVDD LADVDD LCE0 LCE1 LD10 LD11 LD12 NAME LD14 LD15 LD16 LD17 LD18 LD19 LD20 LD21 LD22 LD23 LD24 LD25 LD26 LD27 LD28 LD29 LD30 LD31 LDDVDD LDDVDD LDDVDD LDDVDD LLOCK LOCK LPAGE0 LPAGE1 LRDY0 LRDY1 LR/W0 LR/W1 LSTAT0 LSTAT1 LSTAT2 LSTAT3 LSTRB0 LSTRB1 PAGE0 NAME RDY0 RDY1 RESET RESETLOC0 RESETLOC1 ROMEN R/W0 R/W1 STAT0 STAT1 STAT2 STAT3 STRB0 STRB1 SUBS TCLK0 TCLK1 TRST VSSL# VSSL# VSSL# VSSL# X2/CLKIN
LA11 LD13 PAGE1 CVSS IVSS pins connected internally. DVDD, LADVDD, LDDVDD, GDDVDD, GADVDD pins connected internally. DVSS pins connected internally. VDDL pins connected internally. VSSL pins connected internally.
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
package assignments numerical listing
NAME GDDVDD CVSS CVSS IVSS GDDVDD GDDVDD GDDVDD NAME RDY1 CVSS CVSS LOCK VSSL# RDY0 TRST EMU0 EMU1 DVDD PAGE1 R/W1 STRB1 STAT0 STAT1 IVSS STAT2 STAT3 PAGE0 R/W0 STRB0 RESETLOC1 DVDD RESETLOC0 RESET NAME CSTRB5 CACK5 CREQ5 CRDY4 CSTRB4 CACK4 CREQ4 CVSS DVDD C5D7 C5D6 C5D5 C5D4 C5D3 C5D2 C5D1 C5D0 DVDD C4D7 C4D6 C4D5 C4D4 C4D3 C4D2 C4D1 C4D0 CVSS DVDD C3D7 C3D6 C3D5 C3D4 C3D3 C3D2 C3D1 NAME DVDD IVSS IVSS C2D7 C2D6 C2D5 C2D4 C2D3 C2D2 C2D1 C2D0 CVSS DVDD CRDY3 CSTRB3 CACK3 CREQ3 VSSL# CRDY2 CSTRB2 CACK2 CREQ2 DVDD CRDY1 CSTRB1 CACK1 CREQ1 CRDY0 CSTRB0 CACK0 CREQ0 CVSS CVSS IVSS DVDD NAME C1D7 C1D6 C1D5 C1D4 C1D3 C1D2 C1D1 C1D0 DVDD C0D7 C0D6 C0D5 C0D4 C0D3 C0D2 C0D1 C0D0 CVSS DVDD ROMEN IIOF0 IIOF1 IIOF2 IIOF3 LSTRB0 LR/W0 LPAGE0 LRDY0 LCE0 LSTRB1 LR/W1 DVDD CVSS LPAGE1 LRDY1 LCE1
CRDY5 C3D0 CVSS IVSS pins connected internally. DVDD, LADVDD, LDDVDD, GDDVDD, GADVDD pins connected internally. DVSS pins connected internally. VDDL pins connected internally. VSSL pins connected internally.
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
package assignments numerical listing (continued)
NAME TCLK0 TCLK1 IVSS LLOCK LSTAT0 LSTAT1 LSTAT2 LSTAT3 IACK VSSL# X2/CLKIN CVSS CVSS DVDD LA30 LA29 LA28 LA27 LADVDD LA26 LA25 LA24 LA23 LA22 LA21 LA20 LA19 LA18 LA17 LA16 LADVDD LADVDD NAME CVSS LA15 LA14 LA13 LA12 LA11 LA10 LADVDD CVSS LD31 LD30 LD29 LD28 LDDVDD LD27 LD26 LD25 LD24 LD23 LD22 LD21 LD20 LD19 LD18 LD17 NAME LDDVDD CVSS IVSS LD16 LD15 LD14 LD13 LD12 LD11 LD10 LDDVDD VSSL# CVSS CVSS GADVDD NAME GADVDD GADVDD CVSS CVSS GADVDD CVSS SUBS
CVSS LDDVDD CVSS IVSS pins connected internally. DVDD, LADVDD, LDDVDD, GDDVDD, GADVDD pins connected internally. DVSS pins connected internally. VDDL pins connected internally. VSSL pins connected internally.
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
Number
SMJ320C40 (Rev. Inner Lead Bond (ILB) Information Side Number XXXXX
Designator
Side Number
Side Number
Zero-Zero (Origin)
Side Number
Figure SMJ320C40 Numbering Format (See Table inner lead bond (ILB) pitch tape automated bonding (TAB) leadframe same bond pitch. Table provides reference following: lead numbers. lead numbers same bond numbers. 'C40 signal identities relation numbers There bond locations, leads, test locations. 'C40 X-,Y-coordinates, where bond serves origin, (0,0) inner lead bond pitch (ILB) same bond pitch. outer lead pitch 0.25 0.01 test pitch 0.40 0.01 tape width Outer lead bond (OLB) connect test
addition, following notes significant: coordinate data microns. Average pitch (4.96 mils). Smallest pitch value (4.96 mils). active silicon dimensions 12424.86 12035.52 (489.16 mils 473.83 mils). size approximately 12598.40 12192.00 (496.00 mils 480.00 mils). Distance from diced silicon polyimide support ring (35.0 mils). Bond dimensions 108.00 108.00 (4.25 mils 4.25 mils). Center bond edge minimum (without scribe) 107.80 (4.24 mils). nominal thickness 50.8 mils). polyimide encapsulant thickness approximately 304.8 mils).
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
Table SMJ320C40 Pad/TAB Lead Information Rev. (0,72
SIDE BOND LOCATIONS DIE/TAB BOND IDENTITY GDDVDD CVSS IVSS GDDVDD DVSS GDDVDD RDY1 DVSS CVSS 429.48 X-COORDINATE BOND (µm) Y-COORDINATE BOND (µm) 11368.44 11242.44 11116.44 10990.44 10864.44 10738.44 10612.44 10486.44 10360.44 10234.44 10108.44 9982.44 9856.44 9730.44 9604.44 9478.44 9352.44 9226.44 9100.44 8974.44 8848.44 8722.44 8596.44 8470.44 8344.44 8218.44 8092.44 7966.44 7840.44 7714.44 7588.44 7462.44 7336.44 7210.44 7084.44 6958.44 6832.44 6706.44 6550.02 6377.22 6225.12 6099.12 PITCH LEAD REFERENCES WHICH BOND PADS 126.00 126.00 126.00 126.00 126.00 126.00 126.00 126.00 126.00 126.00 (10, 126.00 (11, 126.00 (12, 126.00 (13, 126.00 (14, 126.00 (15, 126.00 (16, 126.00 (17, 126.00 (18, 126.00 (19, 126.00 (20, 126.00 (21, 126.00 (22, 126.00 (23, 126.00 (24, 126.00 (25, 126.00 (26, 126.00 (27, 126.00 (28, 126.00 (29, 126.00 (30, 126.00 (31, 126.00 (32, 126.00 (33, 126.00 (34, 126.00 (35, 126.00 (36, 126.00 (37, 156.42 (38, 172.80 (39, 152.10 (40, 126.00 (41, 126.00 (42,
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
Table SMJ320C40 Pad/TAB Lead Information Rev. (0,72 (Continued)
SIDE (CONTINUED) BOND LOCATIONS DIE/TAB BOND IDENTITY LOCK VDDL VSSL RDY0 TRST EMU0 EMU1 DVSS DVDD PAGE1 R/W1 STRB1 STAT0 STAT1 IVSS STAT2 STAT3 PAGE0 R/W0 STRB0 RESETLOC DVDD RESETLOC RESET CRDY5 CSTRB5 CACK5 CREQ5 CRDY4 CSTRB4 CACK4 CREQ4 429.48 X-COORDINATE BOND Y-COORDINATE BOND 5973.12 5847.12 5721.12 5564.70 5391.90 5219.10 5046.30 4894.20 4737.78 4564.98 4392.18 4240.08 4114.08 3988.08 3962.08 3736.08 3610.08 3484.08 3358.08 3232.08 3106.08 2980.08 2854.08 2726.64 2600.64 2474.64 2318.22 2143.98 1991.88 1835.46 1662.66 1510.56 1384.56 1258.56 1132.56 1006.56 880.56 754.56 628.56 PITCH LEAD REFERENCES WHICH BOND PADS 126.00 (43, 126.00 (44, 156.42 (45, 172.80 (46, 172.80 (47, 172.80 (48, 152.10 (49, 156.42 (50, 172.80 (51, 172.80 (52, 151.10 (53, 126.00 (54, 126.00 (55, 126.00 (56, 126.00 (57, 126.00 (58, 126.00 (59, 126.00 (60, 126.00 (61, 126.00 (62, 126.00 (63, 126.00 (64, 127.44 (65, 126.00 (66, 126.00 (67, 156.42 (68, 174.24 (69, 152.10 (70, 156.42 (71, 172.80 (72, 172.80 (73, 126.00 (74, 126.00 (75, 126.00 (76, 126.00 (77, 126.00 (78, 126.00 (79, 126.00 (80,
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
Table SMJ320C40 Pad/TAB Lead Information Rev. (0,72 (Continued)
SIDE BOND LOCATIONS DIE/TAB BOND IDENTITY CVSS DVSS DVDD C5D7 C5D6 C5D5 C5D4 C5D3 C5D2 C5D1 C5D0 DVDD C4D7 C4D6 C4D5 C4D4 C4D3 C4D2 C4D1 C4D0 CVSS DVSS DVDD C3D7 C3D6 C3D5 C3D4 C3D3 C3D2 C3D1 C3D0 DVDD IVSS C2D7 C2D6 C2D5 C2D4 C2D3 C2D2 C2D1 C2D0 CVSS X-COORDINATE BOND 0.00 1062.00 1188.00 1314.00 1440.00 1566.00 1692.00 1818.00 1944.00 2070.00 2196.00 2322.00 2448.00 2574.00 2700.00 2813.40 2952.00 3078.00 3204.00 3330.00 3456.00 3582.00 3708.00 3834.00 3960.00 4086.00 4212.00 4338.00 4464.00 4590.00 4716.00 4842.00 4968.00 5094.00 5220.00 5346.00 5472.00 5598.00 5724.00 5850.00 5976.00 6102.00 0.00 Y-COORDINATE BOND PITCH LEAD REFERENCES WHICH BOND PADS 1062.00 (82, 126.00 (83, 126.00 (84, 126.00 (85, 126.00 (86, 126.00 (87, 126.00 (88, 126.00 (89, 126.00 (90, 126.00 (91, 126.00 (92, 126.00 (93, 126.00 (94, 126.00 (95, 126.00 (96, 126.00 (97, 126.00 (98, 126.00 (99, 100) 126.00 (100, 101) 126.00 (101, 102) 126.00 (102, 103) 126.00 (103, 104) 126.00 (104, 105) 126.00 (105, 106) 126.00 (106, 107) 126.00 (107, 108) 126.00 (108, 109) 126.00 (109, 110) 126.00 (110, 111) 126.00 (111, 112) 126.00 (112, 113) 126.00 (113, 114) 126.00 (114, 115) 126.00 (115, 116) 126.00 (116, 117) 126.00 (117, 118) 126.00 (118, 119) 126.00 (119, 120) 126.00 (120, 121) 126.00 (121, 122) 126.00 (122, 123) 126.00 (123, 124)
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
Table SMJ320C40 Pad/TAB Lead Information Rev. (0,72 (Continued)
SIDE (CONTINUED) BOND LOCATIONS DIE/TAB BOND IDENTITY DVSS DVDD CRDY3 CSTRB3 CACK3 CREQ3 VDDL VSSL CRDY2 CSTRB2 CACK2 CREQ2 DVDD CRDY1 CSTRB1 CACK1 CREQ1 CRDY0 CSTRB0 CACK0 CREQ0 CVSS DVSS IVSS DVDD C1D7 C1D6 C1D5 C1D4 C1D3 C1D2 C1D1 C1D0 DVDD C0D7 C0D6 C0D5 C0D4 C0D3 X-COORDINATE BOND 6228.00 6354.00 6480.00 6606.00 6732.00 6858.00 6984.00 7110.00 7236.00 7362.00 7488.00 7614.00 7740.00 7866.00 7992.00 8118.00 8244.00 8370.00 8496.00 8622.00 8748.00 8874.00 9000.00 9126.00 9252.00 9378.00 9504.00 9630.00 9756.00 9882.00 10008.00 10134.00 10260.00 10386.00 10512.00 10638.00 10764.00 10890.00 11016.00 0.00 Y-COORDINATE BOND PITCH LEAD REFERENCES WHICH BOND PADS 126.00 (124, 125) 126.00 (125, 126) 126.00 (126, 127) 126.00 (127, 128) 126.00 (128, 129) 126.00 (129, 130) 126.00 (130, 131) 126.00 (131, 132) 126.00 (132, 133) 126.00 (133, 134) 126.00 (134, 135) 126.00 (135, 136) 126.00 (136, 137) 126.00 (137, 138) 126.00 (138, 139) 126.00 (139, 140) 126.00 (140, 141) 126.00 (141, 142) 126.00 (142, 143) 126.00 (143, 144) 126.00 (144, 145) 126.00 (145, 146) 126.00 (146, 147) 126.00 (147, 148) 126.00 (148, 149) 126.00 (149, 150) 126.00 (150, 151) 126.00 (151, 152) 126.00 (152, 153) 126.00 (153, 154) 126.00 (154, 155) 126.00 (155, 156) 126.00 (156, 157) 126.00 (157, 158) 126.00 (158, 159) 126.00 (159, 160) 126.00 (160, 161) 126.00 (161, 162)
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
Table SMJ320C40 Pad/TAB Lead Information Rev. (0,72 (Continued)
SIDE BOND LOCATIONS DIE/TAB BOND IDENTITY C0D2 C0D1 C0D0 CVSS DVDD ROMEN IIOF0 DVSS IIOF1 IIOF2 IIOF3 LSTRB0 LR/W0 LPAGE0 LRDY0 LCE0 LSTRB1 LR/W1 DVDD CVSS LPAGE1 LRDY1 LCE1 TCLK0 TCLK1 IVSS LLOCK LSTAT0 LSTAT1 LSTAT2 LSTAT3 IACK VDDL VSSL X2/CLKIN CVSS X-COORDINATE BOND Y-COORDINATE BOND 810.00 936.00 1062.00 1188.00 1314.00 1470.42 1622.88 1748.88 1874.88 2000.88 2126.88 2283.30 2435.40 2561.40 2687.40 2843.82 3016.62 3168.72 3294.72 3420.72 11779 11779.74 3546.72 3672.72 3829.14 4001.94 4174.74 4326.84 4452.84 4578.84 4704.84 4861.26 5013.36 5139.36 5265.36 5391.36 5517.36 5643.36 5770.80 5896.80 6022.80 6154.74 6326.28 6494.40 PITCH LEAD REFERENCES WHICH BOND PADS 126.00 (163, 164) 126.00 (164, 165) 126.00 (165, 166) 126.00 (166, 167) 156.42 (167, 168) 152.46 (168, 169) 126.00 (169, 170) 126.00 (170, 171) 126.00 (171, 172) 126.00 (172, 173) 156.42 (173, 174) 152.10 (174, 175) 126.00 (175, 176) 126.00 (176, 177) 156.42 (177, 178) 172.80 (178, 179) 152.10 (179, 180) 126.00 (180, 181) 126.00 (181, 182) 126.00 (182, 183) 126.00 (183, 184) 156.42 (184, 185) 172.80 (185, 186) 172.80 (186, 187) 152.10 (187, 188) 126.00 (188, 189) 126.00 (189, 190) 126.00 (190, 191) 156.42 (191, 192) 152.10 (192, 193) 126.00 (193, 194) 126.00 (194, 195) 126.00 (195, 196) 126.00 (196, 197) 126.00 (197, 198) 127.44 (198, 199) 126.00 (199, 200) 126.00 (200, 201) 131.94 (201, 202) 171.58 (202, 203) 168.12 (203, 204) 126.00 (204, 205)
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
Table SMJ320C40 Pad/TAB Lead Information Rev. (0,72 (Continued)
SIDE (CONTINUED) BOND LOCATIONS DIE/TAB BOND IDENTITY DVDD DVSS LA30 LA29 LA28 LA27 LADVDD LA26 LA25 LA24 LA23 LA22 LA21 LA20 LA19 LA18 LA17 LA16 LADVDD CVSS DVSS LA15 LA14 LA13 LA12 LA11 LA10 LADVDD DVSS 11779.74 X-COORDINATE BOND Y-COORDINATE BOND 6620.40 6746.40 6873.84 6999.84 7125.84 7251.84 7377.84 7503.84 7629.84 7755.84 7881.84 8007.84 8133.84 8259.84 8385.84 8511.84 8637.84 8763.84 8889.84 9015.84 9141.84 9267.84 9393.84 9519.84 9645.84 9771.84 9897.84 10023.84 10149.84 10275.84 10401.84 10527.84 10653.84 10779.84 10905.84 11031.84 11157.84 11283.84 11489.76 PITCH LEAD REFERENCES WHICH BOND PADS 126.00 (205, 206) 127.44 (206, 207) 126.00 (207, 208) 126.00 (208, 209) 126.00 (209, 210) 126.00 (210, 211) 126.00 (211, 212) 126.00 (212, 213) 126.00 (213, 214) 126.00 (214, 215) 126.00 (215, 216) 126.00 (216, 217) 126.00 (217, 218) 126.00 (218, 219) 126.00 (219, 220) 126.00 (220, 221) 126.00 (221, 222) 126.00 (222, 223) 126.00 (223, 224) 126.00 (224, 225) 126.00 (225, 226) 126.00 (226, 227) 126.00 (227, 228) 126.00 (228, 229) 126.00 (229, 230) 126.00 (230, 231) 126.00 (231, 232) 126.00 (232, 233) 126.00 (233, 234) 126.00 (234, 235) 126.00 (235, 236) 126.00 (236, 237) 126.00 (237, 238) 126.00 (238, 239) 126.00 (239, 240) 126.00 (240, 241) 126.00 (241, 242) 205.92 (242, 243)
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
Table SMJ320C40 Pad/TAB Lead Information Rev. (0,72 (Continued)
SIDE BOND LOCATIONS DIE/TAB BOND IDENTITY CVSS LD31 LD30 LD29 LD28 LDDVDD LD27 LD26 LD25 LD24 LD23 LD22 LD21 LD20 LD19 LD18 LD17 LDDVDD CVSS DVSS IVSS LD16 LD15 LD14 LD13 LD12 LD11 LD10 LDDVDD VDDL VSSL CVSS X-COORDINATE BOND 10953.72 10827.72 10701.72 10575.72 10449.72 10323.72 10197.72 10071.72 9945.72 9819.72 9693.72 9567.72 9441.72 9315.72 9189.72 9063.72 8937.72 8811.72 8685.72 8559.72 8433.72 8307.72 8181.72 8055.72 7929.72 7803.72 7677.72 7551.72 7425.72 7299.72 7173.72 7047.72 6921.72 6795.72 6669.72 6543.72 6417.72 6291.72 6165.72 6038.10 5912.10 5786.10 11819 11819.88 Y-COORDINATE BOND PITCH LEAD REFERENCES WHICH BOND PADS 126.00 (244, 245) 126.00 (245, 246) 126.00 (246, 247) 126.00 (247, 248) 126.00 (248, 249) 126.00 (249, 250) 126.00 (250, 251) 126.00 (251, 252) 126.00 (252, 253) 126.00 (253, 254) 126.00 (254, 255) 126.00 (255, 256) 126.00 (256, 257) 126.00 (257, 258) 126.00 (258, 259) 126.00 (259, 260) 126.00 (260, 261) 126.00 (261, 262) 126.00 (262, 263) 126.00 (263, 264) 126.00 (264, 265) 126.00 (265, 266) 126.00 (266, 267) 126.00 (267, 268) 126.00 (268, 269) 126.00 (269, 270) 126.00 (270, 271) 126.00 (271, 272) 126.00 (272, 273) 126.00 (273, 274) 126.00 (274, 275) 126.00 (275, 276) 126.00 (276, 277) 126.00 (277, 278) 126.00 (278, 279) 126.00 (279, 280) 126.00 (280, 281) 126.00 (281, 282) 127.62 (282, 283) 126.00 (283, 284) 126.00 (284, 285) 126.00 (285, 286)
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
Table SMJ320C40 Pad/TAB Lead Information Rev. (0,72 (Continued)
SIDE (CONTINUED) BOND LOCATIONS DIE/TAB BOND IDENTITY DVSS GADVDD GADVDD CVSS DVSS GADVDD CVSS DVSS SUBS X-COORDINATE BOND 5660.10 5534.10 5408.10 5282.10 5156.10 5030.10 4904.10 4778.10 4652.10 4526.10 4400.10 4274.10 4148.10 4022.10 3896.10 3770.10 3644.10 3518.10 3392.10 3266.10 3140.10 3014.10 2888.10 2762.10 2636.10 2510.10 2384.10 2258.10 2132.10 2006.10 1880.10 1754.10 1628.10 1502.10 1376.10 1250.10 1124.10 998.10 440.10 189.90 11819.88 11819 Y-COORDINATE BOND PITCH LEAD REFERENCES WHICH BOND PADS 126.00 (286, 287) 126.00 (287, 288) 126.00 (288, 289) 126.00 (289, 290) 126.00 (290, 291) 126.00 (291, 292) 126.00 (292, 293) 126.00 (293, 294) 126.00 (294, 295) 126.00 (295, 296) 126.00 (296, 297) 126.00 (297, 298) 126.00 (298, 299) 126.00 (299, 300) 126.00 (300, 301) 126.00 (301, 302) 126.00 (302, 303) 126.00 (303, 304) 126.00 (304, 305) 126.00 (305, 306) 126.00 (306, 307) 126.00 (307, 308) 126.00 (308, 309) 126.00 (309, 310) 126.00 (310, 311) 126.00 (311, 312) 126.00 (312, 313) 126.00 (313, 314) 126.00 (314, 315) 126.00 (315, 316) 126.00 (316, 317) 126.00 (317, 318) 126.00 (318, 319) 126.00 (319, 320) 126.00 (320, 321) 126.00 (321, 322) 126.00 (322, 323) 558.00 (323, 324) 630.00 (324, 325)
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
SMJ320C40 device nomenclature
PREFIX: MIL-PRF-38535 Standard Processing
SPEED RANGE: TEMPERATURE RANGE: -55°C 125°C -55°C 100°C PACKAGE TYPE: 325-Pin Ceramic Staggered 352-Lead Ceramic Quad Flat Pack (nonconductive tie-bar)
DEVICE FAMILY: SMJ320 Family TECHNOLOGY: CMOS DEVICE: '320C40
SOLDER LEAD FINISH SPEED RANGE: TEMPERATURE RANGE: -55°C 125°C -55°C 100°C 70°C
PREFIX: MIL-PRF-38535 Standard Processing Commercial Level DEVICE FAMILY: SMJ320 Family TECHNOLOGY: CMOS DEVICE: '320C40
PACKAGE TYPE: 324-Pad JEDEC Standard Tape With Polyimide Overcoat
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Supply voltage range, (see Note Input voltage range Output voltage range Operating case temperature range, version) 55°C 125°C version) 55°C 100°C version) 25°C 85°C version) 70°C Storage temperature range, Tstg 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE voltage values with respect VSS.
recommended operating conditions (see Note
SMJ320C40-40 Supply voltages (DVDD, etc.) Supply voltages (CVSS, etc.) X2/CLKIN High level input High-level voltage Low-level input voltage High-level output current Low-level output current version Operating case temperature (see Note version version CSTRBx, CREQx, CACKx other pins 0.3* SMJ320C40-50 SMJ320C40-60 4.75 4.75 4.75 0.3* 0.3* 0.3* 5.25 5.25 5.25 UNIT
version nominal values (ambient-air temperature)= 25°C. CRDYx minimum package only. products compliant MIL-PRF-38535, this parameter production tested. NOTES: input output voltage levels TTL-compatible. maximum rated operating conditions point case. initial (time zero) power-up.
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
electrical characteristics over specified case temperature range (see Note
PARAMETER IIPU IIPD High-level output voltage Low-level output voltage Three-state current Input current Input current (TDI, TCK, TMS) Input current (TRST) Input current, X2/CLKIN only Supply current Input capacitance TEST CONDITIONS MIN, MIN, (See Note (See Note MAX, (See Note 25°C -400 UNIT
Output capacitance nominal values 25°C. products compliant MIL-PRF-38535, this parameter production tested. NOTES: input output voltage levels TTL-compatible. Pins with internal pullup devices: TDI, TCK, TMS. with internal pulldown device: TRST. input clock frequency. maximum value MHz.
PARAMETER MEASUREMENT INFORMATION
Tester Electronics
VLoad
Output Under Test
Where: VLoad
(all outputs) (all outputs) 2.15 typical load circuit capacitance.
Figure Test Load Circuit
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
PARAMETER MEASUREMENT INFORMATION signal transition levels
TTL-level outputs driven minimum logic-high level maximum logic-low level Output transition times specified follows: high-to-low transition TTL-compatible output signal, level which output said longer high level which output said low-to-high transition, level which output said longer level which output said high Figure
Figure TTL-Level Outputs Transition times TTL-compatible inputs specified follows: high-to-low transition input signal, level which input said longer high level which input said low-to-high transition input signal, level which input said longer level which input said high Figure
Exceptions: 3.12 CSTRBx, CRDYx, CREQx CACKx 2.64 CLKIN
Figure TTL-Level Inputs Timing measurements, excluding disable (output going high impedance output becoming input), referenced from input trip point output trip point Timing measurements from referenced from rising falling edges. times referenced from below minimum above maximum. disable times referenced from input trip point below (TPHZ) above (TPLZ). load current increased reduce time constant during TPHZ TPLZ testing.
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
timing parameter symbology
Timing parameter symbols used herein were created accordance with JEDEC Standard 100-A.To shorten symbols, names that have both global local applications generally represented with immediately preceding basic signal name [for example, (L)RDY represents both global term local term LRDY]. Other names related terminology have been abbreviated follows, unless otherwise noted:
ASYNCH BYTE COMM CONTROL CRDY (L)A30-(L)A0 (L)Ax LAE, (L)AE asynchronous reset signals byte transfer CACK(0-5) CACKx C(0-5)D7-C(0-5)D0 CxDx (L)CE0, (L)CE1, (L)CEx X2/CLKIN asynchronous reset signals control signals CRDY(0-5) CRDYx CREQ(0-5) CREQx CSTRB(0-5) CSTRBx (L)D31-(L)D0 (L)Dx LDE, (L)DE IACK IIOF LOCK (L)RDY PAGE RESET WORD H1/H3 IACK IIOF(3-0) IIOFx LLOCK, LOCK, (L)LOCK (L)RDY0, (L)RDY1, (L)RDYx tc(H) (L)PAGE0, (L)PAGE1, (L)PAGEx RESET (L)R/W0, (L)R/W1, (L)R/Wx (L)STRB0, (L)STRB1, (L)STRBx (L)STAT3-(L)STAT0 (L)STATx TMS/TDI word transfer
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
timing parameters X2/CLKIN, (see Figure Figure
'320C40-40 tf(CI) tw(CIL) tw(CIH) tr(CI) tc(CI) tf(H) tw(HL) tw(HH) tr(H) td(HL-HH) Fall time, CLKIN Pulse duration, CLKIN low, tc(CI) Pulse duration, CLKIN high, tc(CI) Rise time, CLKIN Cycle time, CLKIN Fall time, H1/H3 Pulse duration, H1/H3 Pulse duration, H1/H3 high Rise time, H1/H3 Delay time, from high from high tc(Cl) tc(Cl) 242.5 tc(Cl) tc(Cl) tc(Cl) tc(Cl) 242.5 tc(Cl) tc(Cl) 33.3 tc(Cl) tc(Cl) 16.67 '320C40-50 242.5 tc(Cl) tc(Cl) '320C40-60 UNIT
tc(H) Cycle time, H1/H3 products compliant MIL-PRF-38535, this parameter production tested.
X2/CLKIN
Figure X2/CLKIN Timing
Figure H1/H3 Timings
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
timing parameters memory read/write [(L)STRBx (see Note Figure Figure
'320C40-40 td(H1L-SL) td(H1L-SH) td(H1H-RWL) td(H1L-A) tsu(D-H1L)R th(H1L-D)R tsu[(L)RDY-H1L] th[H1L-(L)RDY] td(H1L-ST) td(H1H-RWH)W tv(H1L-D)W th(H1H-D)W td(H1H-A) Delay time, (L)STRBx Delay time, (L)STRBx high Delay time, high (L)R/Wx Delay time, (L)Ax valid Setup time, (L)Dx valid before (read) Hold time, (L)Dx after (read) Setup time, (L)RDYx valid before Hold time, (L)RDYx after Delay time, (L)STAT3-(L)STAT0 valid Delay time, high (L)R/Wx high (write) Valid time, (L)Dx after (write) Hold time, (L)Dx after high (write) Delay time, high address valid back-to-back write cycles '320C40-50 '320C40-60 UNIT
products compliant MIL-PRF-38535, this parameter production tested. NOTE consecutive reads, (L)R/Wx stays high (L)STRBx stays low.
(L)STRBx
(L)R/Wx (L)Ax (L)Dx (L)RDYx (L)STAT3-(L)STAT0
Figure Memory-Read-Cycle Timing [(L)STRBx
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
PARAMETER MEASUREMENT INFORMATION
(L)STRBx (L)R/Wx (L)Ax (L)Dx (L)RDYx (L)STAT3-(L)STAT0
Figure Memory-Write-Cycle Timing [(L)STRBx
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
(L)DE, (L)AE, (L)CEx enable timings (see Figure
td(DEH-DZ) td(DEL-DV) td(AEH-AZ) td(AEL-AV) td(CEH-RWZ) td(CEL-RWV) td(CEH-SZ) td(CEL-SV) td(CEH-PAGEZ) Delay time, (L)DE high (L)D0-(L)D31 high-impedance state Delay time, (L)DE (L)D0-(L)D31 valid Delay time, (L)AE high (L)A0-(L)A30 high-impedance state Delay time, (L)AE (L)A0-(L)A30 valid Delay time, (L)CEx high (L)R/W0, (L)R/W1 high-impedance state Delay time, (L)CEx (L)R/W0, (L)R/W1 valid Delay time, (L)CEx high (L)STRB0, (L)STRB1 high-impedance state Delay time, (L)CEx (L)STRB0, (L)STRB1 valid Delay time, (L)CEx high (L)PAGE0, (L)PAGE1 high-impedance state '320C40-40 '320C40-50 MIN* '320C40-60 MIN* UNIT
td(CEL-PAGEV) Delay time, (L)CEx (L)PAGE0, (L)PAGE1 valid products compliant MIL-PRF-38535, this parameter production tested.
(L)DE (L)D31-(L)D0 Hi-Z
(L)AE (L)A30-(L)A0 Hi-Z
(L)CE0, (L)CE1 (L)R/W0, (L)R/W1 (L)STRB0, (L)STRB1 (L)PAGE0, (L)PAGE1 Hi-Z Hi-Z Hi-Z
Figure (L)DE, (L)AE, (L)CEx Enable Timings
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
timing parameters (L)LOCK when executing LDFI LDII (see Figure
'320C40-40 td(H1L-LOCKL) Delay time, (L)LOCK '320C40-50 '320C40-60 UNIT
LDFI LDII External Access
(L)STRBx
(L)R/Wx
(L)Ax
(L)Dx
(L)RDYx (L)LOCK
Figure Timing (L)LOCK When Executing LDFI LDII
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
timing parameters (L)LOCK when executing STFI STII (see Figure
'320C40-40 td(H1L-LOCKH) PARAMETER Delay time, (L)LOCK high '320C40-50 '320C40-60 UNIT
STFI STII External Access
(L)STRBx
(L)R/Wx
(L)Ax
(L)Dx
(L)RDYx (L)LOCK
Figure Timing (L)LOCK When Executing STFI STII
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
timing parameters (L)LOCK when executing SIGI (see Figure
'320C40-40 td(H1L-LOCKL) td(H1L-LOCKH) Delay time, (L)LOCK Delay time, (L)LOCK high '320C40-50 '320C40-60 UNIT
(L)LOCK
(L)R/Wx
(L)Ax
(L)Dx
(L)RDYx
(L)STAT3-(L)STAT0
Figure Timing (L)LOCK When Executing SIGI
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
timing parameters (L)PAGE0, (L)PAGE1 during memory access different page (see Figure
td(H1L-PAGEH) td(H1L-PAGEL) Delay time, (L)PAGEx high access different page Delay time, (L)PAGEx access different page '320C40-40 '320C40-50 '320C40-60 UNIT
(L)R/Wx
(L)STRBx
(L)RDYx (L)PAGEx
(L)Dx
(L)Ax
(L)STAT3-(L)STAT0
(L)STRB1 write different page
(L)STRB1 read from different page
Figure (L)PAGE0, (L)PAGE1 Timing Cycle, Memory Access Different Page
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
timing parameters loading register (IIOFx pins) when configured output (see Figure
'320C40-40 tv(H1L-IIOF) Valid time, IIOFx after '320C40-50 '320C40-60 UNIT
Fetch Load Instruction
Decode
Read
Execute
FLAG
IIOFx pins
Figure Timing Loading Register (IIOFx Pins) When Configured Output
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
timing parameters IIOFx changing from output input mode (see Figure
'320C40-40 '320C40-50 '320C40-60 th(H1L-IIOF) tsu(IIOF) Hold time, IIOFx after Setup time, IIOFx before UNIT
th(IIOF) Hold time, IIOFx after products compliant MIL-PRF-38535, this parameter production tested.
Execute Load IIOF
Buffers from Output Input
Synchronizer Delay
Value Seen IIOF
TYPE IIOFx pins Output
FLAG
Data Sampled Data Seen
Figure Change IIOFx From Output Input Mode
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
timing parameters IIOFx changing from input output mode (see Figure
td(H1L-IFIO) Delay time, IIOFx switching from input output Execution Load IIOF '320C40-40 '320C40-50 '320C40-60 UNIT
TYPE IIOFx pins
Figure Change IIOFx From Input Output Mode
timing parameters RESET (see Figure
'320C40-40 tsu(RESET-CIL) td(CIH-H1H) td(CIH-H1L) tsu(RESETH-H1L) td(CIH-H3L) td(CIH-H3H) tdis(H1H-DZ) tdis(H3H-AZ) td(H3H-CONTROLH) td(H1H-IACKH) tdis(RESETL-ASYNCHZ) td(RESETH-COMMH) Setup time, RESET before CLKIN Delay time, CLKIN high high Delay time, CLKIN high Setup time, RESET high before after clock cycles Delay time, CLKIN high Delay time, CLKIN high high Disable time, high (L)Dx high-impedance state Disable time, high (L)Ax high-impedance state Delay time, high control signals high [low (L)PAGEx] Delay time, high IACK high Disable time, RESET asynchronous reset signals high-impedance state Delay time, RESET high asynchronous reset signals high tc(CI) '320C40-50 tc(Cl)* '320C40-60 tc(Cl)* UNIT
products compliant MIL-PRF-38535, this parameter production tested.
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PARAMETER MEASUREMENT INFORMATION
X2/CLKIN RESET (see Notes (L)Dx (see Note (L)Ax (see Note
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Clock Cycles Hi-Z Hi-Z
Control Signals
Control Signals (see Note (L)PAGE0-(L)PAGE1 (see Note IACK Asynchronous Reset Signals (see Note Asynchronous Reset Signals (see Note Hi-Z Hi-Z
NOTES:
this figure, (L)Dx includes D31-D0, LD31-D0, CxD7-CxD0. (L)Ax includes A30-A0 LA30-LA0. Control signals LSTRB0, LSTRB1, STRB0, STRB1, (L)STAT3-(L)STAT0, (L)LOCK, (L)R/W0, (L)R/W1 high while (L)PAGE0 (L)PAGE1 low. Asynchronous reset signals that into high impedance after RESET goes include TCLK0, TCLK1, IIOF3-IIOF0, communication-port control signals CREQx, CACKy, CSTRBy, CRDYx (where reset, ports become outputs, ports become inputs.) Asynchronous reset signals that high-logic level after RESET goes include CREQy, CACKx, CSTRBx, CRDYy (where RESET asynchronous input asserted point during clock cycle. specified timings met, exact sequence shown will occur; otherwise, additional delay clock cycle occur.
SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
Figure RESET Timing
SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
timing parameters IIOF3-IIOF0 interrupt response tc(H)] (see Figure Note Note
tsu(IIOF-H1L) tw(IIOF) Setup time, IIOF3-IIOF0 before Interrupt pulse duration ensure interrupt seen (see Note '320C40-40 '320C40-50 1.5P '320C40-60 1.5P UNIT
products compliant MIL-PRF-38535, this parameter production tested. NOTES: IIOFx asynchronous input asserted point during clock cycle. specified timings met, exact sequence shown occurs; otherwise, additional delay clock cycle occur. Edge-triggered interrupts require setup time minimum duration maximum duration limit exists. Level-triggered interrupts require interrupt pulse duration least wide period) ensure that interrupt seen. must less than wide ensure that responded only once. Recommended pulse duration 1.5P. Fetch First Instruction Service Routine
Reset Interrupt Vector Read
(See Note IIOF3-IIOF0 Pins IIOF3-IIOF0 Flag First Instruction Address
ADDRESS Vector Address Data NOTE 'C40 accept interrupt from same source every clock cycles.
Figure IIOF3-IIOF0 Interrupt Response Timing [P=tc(H)]
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
timing parameters IACK (see Note Figure
td(H1H-IACKL) td(H1L-IACKH) Delay time, high IACK Delay time, IACK high during first cycle IACK instruction data read '320C40-40 '320C40-50 '320C40-60 UNIT
NOTE IACK output active entire duration cycle and, therefore, extended cycle utilizes wait states.
Fetch IACK Instruction
Decode IACK Instruction
IACK Data Read
Execute IACK Instruction
IACK
ADDRESS
DATA
Figure IACK Timing
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
communication-port word-transfer cycle timing [P=tc(H)] (see Note Figure
'320C40-40 '320C40-50 '320C40-60 tc(WORD) td(CRDYL-CSL)W* Cycle time, word transfer bytes word) Delay time, CRDYx CSTRBx between back-to-back write cycles 1.5P+7 1.5P+7 2.5P+17 2.5P+28 UNIT
these timing values, assumed that SMJ320C40 that receive data ready receive data. tc(WORD) 2.5P where boxed numbers refer values corresponding parameters communication-port byte timing table next page (for example, means value under parameter table value ns). This timing assumes that 'C40s connected. products compliant MIL-PRF-38535, this parameter production tested. NOTE These timings apply only communicating 'C4xs. When non-'C4x device communicates with 'C40, timings longer. restriction exists this case slow transfer could except when using early silicon ('C40 2.x). CSTRB width restriction Section 8.9.1 TMS320C4x User's Guide (literature number SPRU063).
CREQx
CACKx CSTRBx
CxD7-CxD0
Undef.
(see Note
CRDYx
when signal input (clear when signal output) NOTES: correct operation during token exchange, communicating SMJ320C40s must have CLKIN frequencies within factor each other other words, most, SMJ320C40s twice fast other). Begins byte next word
Figure Communication-Port Word-Transfer-Cycle Timing [P=tc(H)]
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
communication-port byte timing parameters (write read) (see Note Figure
'320C40-40 '320C40-50 '320C40-60 tsu(CD-CSL)W td(CRDYL-CSH)W th(CRDYL-CD)W td(CRDYH-CSL)W tc(BYTE) td(CSL-CRDYL)R tsu(CSH-CD)R th(CRDYL-CD)R td(CSH-CRDYH)R Setup time, CxDx data valid before CSTRBx (write) Delay time, CRDYx CSTRBx high (write) Hold time, CxDx after CRDYx (write) Delay time, CRDYx high CSTRBx subsequent bytes (write) Cycle time, byte transfer Delay time, CSTRBx CRDYx (read) Setup time, CxDx valid after CSTRBx high (read) Hold time, CxDx valid after CRDYx (read) Delay time, CSTRBx high CRDYx high (read) UNIT
tc(BYTE) where boxed numbers refer values corresponding parameters above table (for example, means value under parameter table value ns). This assumes that 'C40s connected. products compliant MIL-PRF-38535, this parameter production tested. NOTE Communication port timing does include line length delay.
CREQx
CACKx
CSTRBx CxDx Valid Data CRDYx WRITE TIMING when signal input (clear when signal output) READ TIMING Valid
Figure Communication-Port Byte Timing (Write Read)
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
timing parameters communication-token transfer sequence, input output port tc(H)] (see Figure
'320C40-40* '320C40-50* '320C40-60* td(CAL-CS)T td(CAL-CRQH)T td(CRQH-CRQ)T td(CRQH-CA)T td(CRQH-CD)T td(CRQH-CRDY)T td(CRQH-CSL)T Delay time, CACKx CSTRBx change from input high-level output Delay time, CACKx start CREQx going high token-request acknowledge Delay time, start CREQx going high CREQx change from output input Delay time, start CREQx going high CACKx change from input output level high Delay time, start CREQx going high CxD7-CxD0 change from inputs driven outputs driven Delay time, start CREQx going high CRDYx change from output input Delay time, start CREQx going high CSTRBx start word transfer 0.5P+ 0.5P 0.5P 0.5P 0.5P 1.5P 1.5P+ 0.5P+ 0.5P+13 0.5P+13 0.5P+13 1.5P+ UNIT
td(CRDYL-CSL)T Delay time, CRDYx word input CSTRBx word output 3.5P+12 5.5P+ These timing parameters result from synchronizer delays referenced from falling edge inputs (that cause output-signal pins change values) sampled falling. minimum delay occurs when input condition occurs just before falling, maximum delay occurs when input condition occurs just after falling. products compliant MIL-PRF-38535, this parameter production tested.
CREQx CACKx CSTRBx CxD7-CxD0 CRDYx when signal input (clear when signal output) NOTE Before token exchange, CREQx CRDYx output signals asserted SMJ320C40 that receiving data. CACKx, CSTRBx, CxD7-CxD0 input signals asserted device sending data 'C40; these asynchronous with respect clock receiving SMJ320C40. After token exchange, CACKx, CSTRBx, CxD7-CxD0 become output signals, CREQx CRDYx become inputs. Valid Data
Figure Communication-Token Transfer Sequence, Input Output Port [P=tc(H)]
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
timing parameters communication-token transfer sequence, output input port tc(H)] (see Figure
Delay time, CREQx start CACKx going token-request acknowledge Delay time, start CRDYx word transfer start CACKx going Delay time, start CACKx going CxD7-CxD0 change from outputs inputs Delay time, start CACKx going CRDYx change from input output, high level Delay time, CREQx high CREQx change from input output, high level Delay time, start CREQx high CACKx change from output input Delay time, start CREQx high CSTRBx change from output input Delay time, CREQx high CREQx next token request '320C40-40* '320C40-50* td(CRQL-CAL)T td(CRDYL-CAL)T td(CAL-CD)I td(CAL-CRDY)T td(CRQH-CRQ)T td(CRQH-CA)T td(CRQH-CS)T td(CRQH-CRQL)T 0.5P-8 0.5P-8 2P+26 2P+27 0.5P+8 0.5P+8 2P+8 '320C40-60* 0.5P-8 0.5P-8 2P+22 2P+27 0.5P+8 0.5P+8 2P+8 UNIT
These timing parameters result from synchronizer delays referenced from falling edge inputs (that cause output-signal pins change values) sampled falling. minimum delay occurs when input condition occurs just before falling, maximum delay occurs when input condition occurs just after falling. products compliant MIL-PRF-38535, this parameter production tested.
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
PARAMETER MEASUREMENT INFORMATION
CREQx CACKx CSTRBx CxD7-CxD0 Valid data Valid data CRDYx when signal input (clear when signal output) NOTE Before token exchange, CACKx, CSTRBx, CxD7-CxD0 asserted 'C40 sending data. CREQx CRDYx input signals asserted 'C40 receiving data asynchronous with respect clock sending 'C40. After token exchange, CREQx CRDYx become outputs, CSTRBx, CACKx, CxD7-CxD0 become inputs.
Figure Communication-Token Transfer Sequence, Output Input Port [P=tc(H)]
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
timing parameters timer (see Note Figure
'320C40-40 '320C40-50 '320C40-60 tsu(TCLK-H1L) th(H1L-TCLK) Setup time, TCLK before Hold time, TCLK after UNIT
td(H1H-TCLK) Delay time, TCLK valid after high NOTE Period polarity valid logic level specified contents internal control registers.
Peripheral (TCLK)
Figure Timer Timing Cycle
timing IEEE 1149.1 test-access port (see Figure
'320C40-40 '320C40-50 '320C40-60 tsu(TMS-TCKH) th(TCKH-TMS) td(TCKL-TDOV) Setup time, TMS/TDI before high Hold time, TMS/TDI after high Delay time, valid UNIT
TMS/TDI
Figure JTAG Emulation Timings
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
PRODUCT ORDERING INFORMATION SMJ320C40 standard package ordering information
DEVICE SMJ320C40GFM40 SM320C40GFM40 SMJ320C40GFM50 SM320C40GFM50 SMJ320C40HFHM40 SM320C40HFHM40 SMJ320C40HFHM50 SM320C40HFHM50 SMJ320C40GFS60 SM320C40GFS60 SMJ320C40HFHS60 SM320C40HFHS60 TEMPERATURE RANGE 55°C 125°C 55°C 125°C 55°C 125°C 55°C 125°C 55°C 125°C 55°C 125°C 55°C 125°C 55°C 125°C 55°C 100°C 55°C 100°C 55°C 100°C 55°C 100°C OPERATING FREQUENCY PACKAGE TYPE Ceramic 325-pin staggered (GF) Ceramic 325-pin staggered (GF) Ceramic 325-pin staggered Ceramic 325-pin staggered Ceramic 352-pin quad flatpack (HFH) Ceramic 352-pin quad flatpack (HFH) Ceramic 352-pin quad flatpack Ceramic 352-pin quad flatpack Ceramic 325-pin staggered Ceramic 325-pin staggered Ceramic 352-pin quad flatpack Ceramic 352-pin quad flatpack PROCESSING LEVEL Standard Standard Standard Standard Standard Standard
SMJ320C40 ordering information
DEVICE SMJ320C40TABM40/10 SM320C40TABM40/10 SMJ320C40TABM50/10 SM320C40TABM50/10 SM320C40TABS50/10 TMP320C40TABL50/10 SM320C40TABC50/10 SMJ320C40TABS60/10 SM320C40TABS60/10 TMP320C40TABL60/10 TEMPERATURE RANGE 55°C 125°C 55°C 125°C 55°C 125°C 55°C 125°C 55°C 100°C 70°C 25°C 85°C 55°C 100°C 55°C 100°C 70°C OPERATING FREQUENCY PACKAGE TYPE ILB/OLB tape (encapsulated) ILB/OLB tape (encapsulated) ILB/OLB tape (encapsulated) ILB/OLB tape (encapsulated) ILB/OLB tape (encapsulated) ILB/OLB tape (encapsulated) ILB/OLB tape (encapsulated) ILB/OLB tape (encapsulated) ILB/OLB tape (encapsulated) ILB/OLB tape (encapsulated) PROCESSING LEVEL Standard Standard Standard Commercial Burn-In) Commercial Burn-In) Standard Commercial Burn-In)
indicates solder-dip lead frame.
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
MECHANICAL DATA
(S-CPGA-P325)
1.717 (43,61) 1.683 (42,75) 0.100 (2,54)
CERAMIC GRID ARRAY
1.879 (47,73) 1.841 (46,76)
0.050 (1,27) 0.060 (1,52) 0.040 (1,02) 0.020 (0,51) 0.016 (0,41)
0.048 (1,22) Places 0.190 (4,83) 0.170 (4,32)
0.080 (2,03) 0.050 (1,27)
0.150 (3,81)
0.026 (0,660) 0.006 (0,152)
0.165 (4,19) 0.120 (3,05)
0.200 (5,08) 0.145 (3,68)
DETAIL 4040035-2/E 03/97
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. Index mark appear bottom, depending package vendor. Pins located within 0.010 (0,25) diameter true position relative each other maximum material condition within 0.030 (0,76) diameter relative edge ceramic. This package hermetically sealed with metal lids with ceramic lids using glass frit. pins gold-plated solder-dipped. Package thickness 0.165 (4,19) 0.120 (3,05) includes package body lid. Falls within JEDEC MO-128AK
Thermal Resistance Characteristics Parameter °C/W 10.9 Flow LFPM 1000
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
MECHANICAL DATA
(R-CQFP-F352)
76,40 74,85 75,40 74,60 57,00 55,60 48,48 47,52 43,50
CERAMIC QUAD FLATPACK WITH NCTB
1,55 1,45 Places
5,50 Width 4,50
DETAIL
70,00
3,60 3,50
DETAIL 2,60 Places 2,50
2,60 2,50 DETAIL
0,50
0,25 0,18 3,34
2,79 0,20 0,10 0,50 DETAIL NOTES: 0,35 0,05 DETAIL
1,05 0,75 DETAIL 4040232-5/F 12/98 THERMAL RESISTANCE CHARACTERISTICS Parameter 1.28 28.70
linear dimensions millimeters. This drawing subject change without notice. This package hermetically sealed with metal lid. terminals gold-plated. Leads shown clarity purposes Falls within JEDEC MO-134AE
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SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS
MECHANICAL DATA
WITH PROTECTIVE FILM) SMJ320C40 324-PIN FRAME SOCKET 5.x) OLB/ILB 0.25 PITCH
0,26 20,025 0,24 19,075
0,26 20,025 0,24 19,075
Face
2,25 Places)
0,26 20,025 0,24 19,075 24,00 Places)
4073433
NOTES:
linear dimensions millimeters. This drawing subject change without notice. lead width 0,10 0,02 lead width 0,05 0,01 tape width encapsulated with polyimide overcoat.
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0,26 20,025 0,24 19,075
Leads
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Customers responsible their applications using components. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 2000, Texas Instruments Incorporated

SMJ: Processing MIL-PRF-38535 Standard Processing TMP: Commercial Leve

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