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SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J SST34HF168116


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Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory
SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
SST34HF168116Mb (x8/x16) 2/4/8 SRAM (x16) ComboMemory
FEATURES:
Flash Organization: Dual-Bank Architecture Concurrent Read/Write Operation Bottom Sector Protection Mbit: Mbit Mbit (P)SRAM Organization: Mbit: 128K Mbit: 256K Mbit: 512K Single 2.7-3.3V Read Write Operations Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: Active Current: (typical) SRAM Standby Current: (typical) PSRAM Standby Current: (typical) Hardware Sector Protection (WP#) Protects outer most sectors KWord) larger bank holding unprotects holding high Hardware Reset (RST#) Resets internal state machine reading data array Byte Selection Flash (CIOF pin) Selects 8-bit 16-bit mode (56-ball package only) Sector-Erase Capability Uniform KWord sectors Block-Erase Capability Uniform KWord blocks Read Access Time Flash: (P)SRAM: Erase-Suspend Erase-Resume Capabilities Security Feature SST: bits User: bits Latched Address Data Fast Erase Program (typical): Sector-Erase Time: Block-Erase Time: Chip-Erase Time: Program Time: Automatic Write Timing Internal Generation End-of-Write Detection Toggle Data# Polling Ready/Busy# CMOS Compatibility JEDEC Standard Command Packages Available 56-ball LFBGA (8mm 10mm) 62-ball LFBGA (8mm 10mm) non-Pb (lead-free) devices RoHS compliant
PRODUCT DESCRIPTION
SST34HF16x1C/J ComboMemory devices integrate either CMOS flash memory bank with either 128K x16, 256K x16, 512K CMOS SRAM pseudo SRAM (PSRAM) memory bank multi-chip package (MCP). These devices fabricated using SST's proprietary, high-performance CMOS SuperFlash technology incorporating split-gate cell design thick-oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST34HF16x1C/J devices ideal applications such cellular phones, devices, PDAs, other portable electronic devices power small form factor system. SST34HF16x1C/J feature dual flash memory bank architecture allowing concurrent operations between flash memory banks (P)SRAM. devices read data from either bank while Erase Program
©2006 Silicon Storage Technology, Inc. S71252-02-000 2/06
operation progress opposite bank. flash memory banks partitioned into Mbit Mbit with bottom sector protection options storing boot code, program code, configuration/parameter data user data. SuperFlash technology provides fixed Erase Program times, independent number Erase/Program cycles that have occurred. Therefore, system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. SST34HF16x1C/J devices offer guaranteed endurance 10,000 cycles. Data retention rated greater than years. With high-performance Program operations, flash memory banks provide typical Program time µsec. entire flash memory bank erased programmed word-by-word typically seconds SST34HF16x1C/J, when using interface feaThe logo SuperFlash registered trademarks Silicon Storage Technology, Inc. ComboMemory trademarks Silicon Storage Technology, Inc. These specifications subject change without notice.
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Data Sheet tures such Toggle Bit, Data# Polling, RY/BY# indicate completion Program operation. protect against inadvertent flash write, SST34HF16x1C/J devices contain on-chip hardware software data protection schemes. flash (P)SRAM operate independent memory banks with respective bank enable signals. memory bank selection done bank enable signals. (P)SRAM bank enable signals, BES1# BES2, select (P)SRAM bank. flash memory bank enable signal, BEF#, used with Software Data Protection (SDP) command sequence when controlling Erase Program operations flash memory bank. memory banks superimposed same memory address space where they share common address lines, data lines, which minimize power consumption area. Designed, manufactured, tested applications requiring power small form factor, SST34HF16x1C/J offered extended temperatures small footprint package meet board space constraint requirements. Figures assignments.
Concurrent Read/Write Operation
Dual bank architecture SST34HF16x1C/J devices allows Concurrent Read/Write operation whereby user read from bank while programming erasing other bank. This operation used when user needs read system code bank while updating data other bank. Figures dualbank memory organization. Concurrent Read/Write States
Flash Bank Read Write Write Operation Write Operation Bank Write Read Operation Write Operation Write (P)SRAM Operation Operation Read Read Write Write
Note: purposes this table, Write means perform Block-/Sector-Erase Program operations applicable appropriate bank.
Device Operation
SST34HF16x1C/J uses BES1#, BES2 BEF# control operation either flash (P)SRAM memory bank. When BEF# low, flash bank activated Read, Program Erase operation. When BES1# low, BES2 high (P)SRAM activated Read Write operation. BEF# BES1# cannot level, BES2 cannot high level same time. bank enable signals asserted, contention will result device suffer permanent damage. address, data, control lines shared flash (P)SRAM memory banks which minimizes power consumption loading. device goes into standby when BEF# BES1# bank enables raised VIHC (Logic High) when BEF# high BES2 low.
Flash Read Operation
Read operation SST34HF16x1C/J controlled BEF# OE#, both have system obtain data from outputs. BEF# used device selection. When BEF# high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either BEF# high. Refer Read cycle timing diagram further details (Figure
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Flash Program Operation
These devices programmed word-by-word byte-by-byte basis depending state CIOF pin. Before programming, must ensure that sector which being programmed fully erased. Program operation accomplished three steps: Software Data Protection initiated using three-byte load sequence. Address data loaded. During Program operation, addresses latched falling edge either BEF# WE#, whichever occurs last. data latched rising edge either BEF# WE#, whichever occurs first. internal Program operation initiated after rising edge fourth BEF#, whichever occurs first. Program operation, once initiated, will completed typically within Figures BEF# controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands issued during internal Program operation ignored.
Flash Chip-Erase Operation
SST34HF16x1C/J provide Chip-Erase operation, which allows user erase sectors/blocks state. This useful when device must quickly erased. Chip-Erase operation initiated executing sixbyte command sequence with Chip-Erase command (10H) address 555H last byte sequence. Erase operation begins with rising edge sixth BEF#, whichever occurs first. During Erase operation, only valid read Toggle Bits Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands issued during Chip-Erase operation ignored. When low, attempt Chip-Erase will ignored.
Flash Erase-Suspend/-Resume Operations
Erase-Suspend operation temporarily suspends Sector- Block-Erase operation thus allowing data read from memory location, program data into sector/block that suspended Erase operation. operation executed issuing one-byte command sequence with Erase-Suspend command (B0H). device automatically enters read mode more than after Erase-Suspend command been issued. (TES maximum latency equals µs.) Valid data read from sector block that suspended from Erase operation. Reading address location within erasesuspended sectors/blocks will output toggling "1". While Erase-Suspend mode, Program operation allowed except sector block selected Erase-Suspend. resume Sector-Erase BlockErase operation which been suspended, system must issue Erase-Resume command. operation executed issuing one-byte command sequence with Erase Resume command (30H) address onebyte sequence.
Flash Sector- /Block-Erase Operation
These devices offer both Sector-Erase Block-Erase operations. These operations allow system erase devices sector-by-sector block-by-block) basis. sector architecture based uniform sector size KWord. Block-Erase mode based uniform block size KWord. Sector-Erase operation initiated executing six-byte command sequence with Sector-Erase command (30H) sector address (SA) last cycle. Block-Erase operation initiated executing six-byte command sequence with Block-Erase command (50H) block address (BA) last cycle. sector block address latched falling edge sixth pulse, while command (30H 50H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. commands issued during Block- SectorErase operation ignored except Erase-Suspend Erase-Resume. Figures timing waveforms.
Flash Write Operation Status Detection
SST34HF16x1C/J provide hardware software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. hardware detection uses Ready/Busy# (RY/BY#) pin. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode enabled after rising edge WE#, which initiates internal Program Erase operation.
©2006 Silicon Storage Technology, Inc.
S71252-02-000
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Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Data Sheet actual completion nonvolatile write asynchronous with system; therefore, either Ready/Busy# (RY/ BY#), Data# Polling (DQ7) Toggle (DQ6) read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid.
Flash Data# Polling (DQ7)
When devices internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth BEF#) pulse Program operation. Sector-, Block-, Chip-Erase, Data# Polling valid after rising edge sixth BEF#) pulse. Figure Data# Polling (DQ7) timing diagram Figure flowchart.
Ready/Busy# (RY/BY#)
SST34HF16x1C/J include Ready/Busy# (RY/BY#) output signal. RY/BY# open drain output that indicates whether Erase Program operation progress. Since RY/BY# open drain output, allows several devices tied parallel external pull-up resistor. After rising edge final pulse command sequence, RY/BY# status valid. When RY/BY# actively pulled low, indicates that Erase Program operation progress. When RY/BY# high (Ready), devices read left standby mode.
Toggle Bits (DQ6 DQ2)
During internal Program Erase operation, consecutive attempts read will produce alternating "1"s "0"s, i.e., toggling between When internal Program Erase operation completed, will stop toggling. device then ready next operation. toggle valid after rising edge fourth BEF#) pulse Program operations. Sector-, Block-, Chip-Erase, toggle (DQ6) valid after rising edge sixth BEF#) pulse. will Read operation attempted Erase-suspended Sector/Block. Program operation initiated sector/block selected Erase-Suspend mode, will toggle. additional Toggle available DQ2, which used conjunction with check whether particular sector being actively erased erase-suspended. Table shows detailed status information. Toggle (DQ2) valid after rising edge last BEF#) pulse Write operation. Figure Toggle timing diagram Figure flowchart.
Byte/Word (CIOF)
This function, found only 56-ball package, includes CIOF control whether device data pins operate x16. CIOF logic (VIH) device data configuration: data pins DQ0-DQ15 active controlled BEF# OE#. CIOF logic "0", device data configuration: only data pins DQ0-DQ7 active controlled BEF# OE#. remaining data pins DQ8DQ14 Hi-Z, while DQ15 used address input Least Significant address bus. TABLE Write Operation Status
Status Normal Operation Erase-Suspend Mode Standard Program Standard Erase Read From Erase Suspended Sector/Block Read From Non-Erase Suspended Sector/Block Program
DQ7# Data DQ7#
Toggle Toggle Data Toggle
Toggle Toggle Toggle Data Toggle
RY/BY#
T1.2 1252
Note: DQ7, DQ6, require valid address when reading status information. address must bank where operation progress order read operation status. address pointing different bank (not busy), device will output array data.
©2006 Silicon Storage Technology, Inc.
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Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Data Protection
SST34HF16x1C/J provide both hardware software features protect nonvolatile data from inadvertent writes.
Software Data Protection (SDP)
SST34HF16x1C/J provide JEDEC standard Software Data Protection scheme data alteration operations, i.e., Program Erase. Program operation requires inclusion three-byte sequence. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte sequence. SST34HF16x1C/J shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode within TRC. contents DQ15DQ8 "Don't Care" during command sequence.
Hardware Data Protection
Noise/Glitch Protection: BEF# pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, BEF# high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
Hardware Block Protection
SST34HF16x1C/J provide hardware block protection which protects outermost KWord Bank block protected when held low. Figures Block-Protection location. user disable block protection driving high thus allowing erase program data into protected sectors. must held high prior issuing write command remain stable until after entire Write operation completed. left floating, internally held high pull-up resistor, Boot Block unprotected, enabling Program Erase operations that block.
Common Flash Memory Interface (CFI)
These devices also contain information describe characteristics devices. order enter Query mode, system must write three-byte sequence same Software Entry command with (CFI Query command) address 555H last byte sequence. Entry Bead timing diagram, Figure Once device enters Query mode, system read data addresses given Tables system must write Exit command return Bead mode from Query mode.
Hardware Reset (RST#)
RST# provides hardware method resetting device read array data. When RST# held least TRP, in-progress operation will terminate return Read mode, Figure When internal Program/Erase operation progress, minimum period TRHR required after RST# driven high before valid Read take place, Figure Erase operation that been interrupted needs reinitiated after device resumes normal operation mode ensure data integrity. Figures timing diagrams.
Security
SST34HF16x1C/J devices offer 256-bit Security space. Secure space divided into 128-bit segments-one factory programmed segment user programmed segment. first segment programmed locked with unique, 128-bit number. user segment left un-programmed customer program desired. program user segment Security user must Security Program command. End-of-Write status checked reading toggle bits. Data# Polling used Security End-ofWrite detection. Once programming complete, should locked using User-Sec-ID-Program-LockOut. This disables future corruption this space. Note that regardless whether locked, neither segment erased. Secure space queried executing three-byte command sequence with Query-Sec-ID command (88H) address 555H last byte sequence. exit this mode, ExitSec-ID command should executed. Refer Table more details.
S71252-02-000 2/06
©2006 Silicon Storage Technology, Inc.
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Product Identification
Product Identification mode identifies device SST34HF16x1C/J manufacturer SST. This mode accessed software operations only. hardware device Read operation, which typically used programmers cannot used this device because shared lines between flash (P)SRAM multichip package. Therefore, application high voltage damage this device. Users software Product Identification operation identify part (i.e., using device when using multiple manufacturers same socket. details, Tables software operation, Figure Software Entry Read timing diagram Figure Entry command sequence flowchart. TABLE Product Identification
ADDRESS Manufacturer's Device SST34HF16x1C/J BK0001H 734BH
T2.1 1252
(P)SRAM Operation
With BES1# low, BES2 BEF# high, SST34HF16x1C/J operate either 128K x16, 256K x16, 512K CMOS (P)SRAM, with fully static operation requiring external clocks timing strobes. SST34HF16x1C/J (P)SRAM mapped into first KWord address space. When BES1#, BEF# high BES2 low, memory banks deselected device enters standby. Read Write cycle times equal. control signals UBS# LBS# provide access upper data byte lower data byte. (P)SRAM Read Write data byte control modes operation, Table
(P)SRAM Read
(P)SRAM Read operation SST34HF16x1C/J/S controlled BES1#, both have with BES2 high system obtain data from outputs. BES1# BES2 used (P)SRAM bank selection. output control used gate data from output pins. data high impedance state when high. Refer Read cycle timing diagram, Figure further details.
DATA 00BFH
BK0000H
Note: Bank Address (A19-A18)
Product Identification Mode Exit
order return standard Read mode, Software Product Identification mode must exited. Exit accomplished issuing Software Exit command sequence, which returns device Read mode. This command also used reset device Read mode after inadvertent transient condition that apparently causes device behave abnormally, e.g., read correctly. Note that Software Exit/CFI Exit command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform Figure flowchart.
(P)SRAM Write
(P)SRAM Write operation SST34HF16x1C/J/S controlled BES1#, both have low, BES2 must high system write (P)SRAM. During Word-Write operation, addresses data referenced rising edge either BES1#, WE#, falling edge BES2 whichever occurs first. write time measured from last falling edge BES#1 rising edge BES2 first rising edge BES1#, falling edge BES2. Refer Write cycle timing diagrams, Figures further details.
©2006 Silicon Storage Technology, Inc.
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Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
AMS1-
Address Buffers SuperFlash Memory (Bank CIOF RST# BEF# LBS# UBS# WE#2 OE#2 BES1# BES2 RY/BY#
SuperFlash Memory (Bank Control Logic Buffers DQ15/A-1
Address Buffers
Mbit SRAM PSRAM
Notes: Most significant address package only: WEF# and/or WES# OEF# and/or OES#
1252 B1.4
FIGURE Functional Block Diagram
©2006 Silicon Storage Technology, Inc.
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Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Bottom Sector Protection; KWord Blocks; KWord Sectors
FFFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H A7FFFH A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH 10000H 0FFFFH 08000H 07FFFH 02000H 01FFFH 00000H Block Block Block
Bank Bank
Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block
KWord Sector Protection (4-2 KWord Sectors)
Block
1252 F01.0
Note: address input range mode (COIF=VIH) A19-A0
FIGURE Concurrent SuperFlash Dual-Bank Memory Organization
©2006 Silicon Storage Technology, Inc. S71252-02-000 2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Bottom Sector Protection; KByte Blocks; KByte Sectors
1FFFFFH 1F0000H 1EFFFFH 1E0000H 1DFFFFH 1D0000H 1CFFFFH 1C0000H 1BFFFFH 1B0000H 1AFFFFH 1A0000H 19FFFFH 190000H 18FFFFH 180000H 17FFFFH 170000H 16FFFFH 160000H 15FFFFH 150000H 14FFFFH 140000H 13FFFFH 130000H 12FFFFH 120000H 11FFFFH 110000H 10FFFFH 100000H 0FFFFFH 0F0000H 0EFFFFH 0E0000H 0DFFFFH 0D0000H 0CFFFFH 0C0000H 0BFFFFH 0B0000H 0AFFFFH 0A0000H 09FFFFH 090000H 08FFFFH 080000H 07FFFFH 070000H 06FFFFH 060000H 05FFFFH 050000H 04FFFFH 040000H 03FFFFH 030000H 02FFFFH 020000H 01FFFFH 010000H 00FFFFH 004000H 003FFFH 000000H Block Block Block
Bank Bank
Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block
KByte Sector Protection (4-4 KByte Sectors)
Block
1252 F01b.0
Note: address input range mode (CIOF=VIL) A19-A-1
FIGURE Concurrent SuperFlash Dual-Bank Memory Organization
©2006 Silicon Storage Technology, Inc. S71252-02-000 2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
VIEW (balls facing down)
CIOF
NOTE* DQ14 DQ13 DQ12 VDDS VDDF DQ11
BES2 RST# RY/BY# LBS# UBS#
DQ10
BEF# BES1#
Note* DQ15/A-1
SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
FIGURE Assignments 56-ball LFBGA (8mm 10mm)
VIEW (balls facing down)
VSSF
DQ15 WES# DQ14 DQ13
WEF# RY/BY#
VSSS RST# DQ12 BES2 VDDS VDDF DQ11 DQ10 BES1#
1252 62-lfbga P2.1
LBS# UBS# OES#
BEF# VSSF OEF#
SST34HF16x1C/J
FIGURE Assignments 62-ball LFBGA (8mm 10mm)
©2006 Silicon Storage Technology, Inc.
1252 56-lfbga P1a.0
S71252-02-000
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Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Data Sheet TABLE Description
Symbol Name Functions provide flash address, A19-A0. provide (P)SRAM address, AMS-A0 output data during Read cycles receive input data during Write cycles. Data internally latched during flash Erase/Program cycle. outputs tri-state when high BES1# high BES2 BEF# high. DQ15 used data when mode (CIOF "1") used address when mode (CIOF "0") activate Flash memory bank when BEF# AMS1 Address Inputs DQ14-DQ0 Data Inputs/Outputs
DQ15/A-1 BEF# BES1# BES2 OEF#2 OES#2 WEF#2 WES#2 CIOF3 UBS# LBS# RST# RY/BY#
Data Input/Output Address Flash Memory Bank Enable
(P)SRAM Memory Bank Enable activate (P)SRAM memory bank when BES1# (P)SRAM Memory Bank Enable activate (P)SRAM memory bank when BES2 high Output Enable Output Enable Write Enable Write Enable Output Enable Write Enable Byte Selection Flash Upper Byte Control ((P)SRAM) Lower Byte Control ((P)SRAM) Write Protect Reset Ready/Busy# gate data output buffers Flash2 only gate data output buffers SRAM2 only control Write operations Flash2 only control Write operations SRAM2 only gate data output buffers control Write operations When low, select Byte mode. When high, select Word mode. enable DQ15-DQ8 enable DQ7-DQ0 protect unprotect bottom KWord sectors) from Erase Program operation Reset return device Read mode output status Program Erase Operation RY/BY# open drain output, 100K pull-up resistor required allow RY/BY# transition high indicating device ready read. Flash2 only SRAM2 only 2.7-3.3V Power Supply Flash only 2.7-3.3V Power Supply (P)SRAM only Unconnected pins
T3.1 1252
VSSF2 VSSS
Ground Ground Ground Power Supply (Flash) Power Supply ((P)SRAM) Connection
VDDF VDDS
Most Significant Address SST34HF1621C, SST34HF1641C/J, SST34HF1681J package only L1PE package only
©2006 Silicon Storage Technology, Inc.
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Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Data Sheet TABLE Operational Modes Selection
DQ15-8 Mode Full Standby Output Disable BEF#1 Flash Read Flash Write Flash Erase (P)SRAM Read BES1#1,2 BES21,2 (P)SRAM Write Product Identification4 DOUT HIGH-Z DOUT HIGH-Z DOUT DOUT HIGH-Z HIGH-Z DOUT DOUT HIGH-Z HIGH-Z DOUT DOUT DQ14-8 HIGH-Z DQ15 DQ14-8 HIGH-Z DQ15 OE#2,3 WE#2,3 LBS#2 UBS#2 HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z DQ7-0 HIGH-Z CIOF HIGH-Z CIOF HIGH-Z
Manufacturer's Device
T4.1 1252
apply BEF# VIL, BES1# BES2 same time VIH, other value. OEF# OES# WEF# WES# package only Software mode only With A19-A18 VIL; Manufacturer's BFH, read with A0=0, SST34HF16x1C/J Device 734BH, read with A0=1
©2006 Silicon Storage Technology, Inc.
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Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Data Sheet TABLE Software Command Sequence
Command Sequence Program Sector-Erase Block-Erase Chip-Erase Erase-Suspend Erase-Resume Query User Security Program User Security Program Lock-out7 Software Entry8 Query Entry Software Exit/ Exit Exit10,11 Software Exit/ Exit Exit10,11 Write Cycle Addr1
555H 555H 555H 555H XXXXH XXXXH 555H 555H 555H 555H 555H 555H
Write Cycle Addr1
2AAH 2AAH 2AAH 2AAH
Write Cycle Addr1
555H 555H 555H 555H
Write Cycle Addr1
555H 555H 555H
Write Cycle Addr1
2AAH 2AAH 2AAH
Write Cycle Addr1
SAX4
Data2
Data2
Data2
Data2
Data
Data2
Data2
555H
2AAH 2AAH 2AAH 2AAH 2AAH 2AAH
555H 555H 555H BKX9 555H BKX9 555H 555H
SIWA6 Data 0000H
T5.4 1252
Address format A10-A0 (Hex), Addresses A19-A11 VIH, other value, command sequence when mode. When mode, Addresses A19-A12, Address DQ14-DQ8 VIH, other value, command sequence. DQ15-DQ8 VIH, other value, command sequence Program word/byte address Sector-Erase; uses A19-A11 address lines Block-Erase; uses A19-A15 address lines SST34HF16x1C/J, read with (Address range 00000H 00007H), User read with (Address range 00010H 00017H). Lock Status read with A7-A0 000FFH. Unlocked: Locked: SIWA User Security Program word/byte address SST34HF16x1C/J, valid Word-Addresses User from 00010H-00017H. cycles User Security Program Program Lock-out must completed before going back Read-Array mode. User Security Program Lock-out command must executed mode (CIOF=VIH). device does remain Software Product Identification mode powered down. Both Software Exit operations equivalent users never lock after programming, User programmed over previously unprogrammed bits (data=1) using User mode again (the programmed bits cannot reversed "1"). SST34HF16x1C/J, valid Word-Addresses User from 00010H-00017H.
©2006 Silicon Storage Technology, Inc.
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Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Data Sheet TABLE QUERY IDENTIFICATION STRING1
Address Mode Address Mode Data2 0051H 0052H 0059H 001H 007H 0000H 0000H 0000H 0000H 0000H 0000H Description Query Unique ASCII string "QRY"
Primary command Address Primary Extended Table Alternate command (00H none exits) Address Alternate extended Table (00H none exits)
T6.0 1252
Refer publication more details. mode only lower byte data output.
TABLE SYSTEM INTERFACE INFORMATION
Address Mode Address Mode 3EHh Data1 0027H 0036H 0000H 0000H 0004H 0000H 0004H 0006H 0001H 0000H 0001H 0001H Description (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: Millivolts (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: Millivolts (00H pin) (00H pin) Typical time Program Typical time size buffer program (00H supported) Typical time individual Sector-/Block-Erase Typical time Chip-Erase Maximum time Program time typical Maximum time buffer program time typical Maximum time individual Sector-Block-Erase time typical Maximum time individual Chip-Erase time typical
T7.0 1252
mode, only lower byte data output.
©2006 Silicon Storage Technology, Inc.
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Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Data Sheet TABLE SYSTEM INTERFACE INFORMATION
Address Mode Address Mode Data1 0015H 0002H 0000H 00000H 0000H 0002H 00FFH 0001H 0010H 0000H 001FH 0000H 0000H 0001H Description Device size Bytes (15H MByte) Flash Device Interface description; 0002H x8/x16 asynchronous interface Maximum number bytes multi-byte write (00H supported) Number Erase Sector/Block sizes supported device Sector Information Number sectors; 256B sector size) sectors (01FFH 512) Bytes KByte/sector (0010H Block Information Number blocks; 256B block size) blocks (001FH Bytes KByte/block (0100H 256)
T8.0 1252
mode, only lower byte data output.
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Operating Temperature -20°C +85°C Storage Temperature -65°C +125°C Voltage Ground Potential .-0.5V VDD1+0.3V Transient Voltage (<20 Ground Potential -1.0V VDD1+1.0V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Solder Reflow Temperature 260°C seconds Output Short Circuit Current2
VDDF VDDS Outputs shorted more than second. more than output shorted time.
Operating Range
Range Extended Ambient Temp -20°C +85°C 2.7-3.3V
Conditions Test
Input Rise/Fall Time Output Load Figures
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Data Sheet TABLE Operating Characteristics (VDD VDDF VDDS 2.7-3.3V)
Limits Symbol IDD1 Parameter Active Current Read Flash (P)SRAM Concurrent Operation Write2 Flash (P)SRAM ILIW VILC VIHC Standby Current Reset Current Input Leakage Current Input Leakage Current RST# Output Leakage Current Input Voltage Input Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Flash Output Voltage Flash Output High Voltage SRAM PSRAM Units Test Conditions Address input VILT/VIHT, MHz, VDD=VDD Max, open OE#=VIL, WE#=VIH BEF#=VIL, BES1#=VIH, BES2=VIL BEF#=VIH, BES1#=VIL BES2=VIH BEF#=VIH, BES1#=VIL BES2=VIH WE#=VIL BEF#=VIL, BES1#=VIH, BES2=VIL, OE#=VIH BEF#=VIH, BES1#=VIL BES2=VIH Max, BEF#=BES1#=VIHC, BES2=VILC RST#=GND VIN=GND VDD, VDD=VDD WP#=GND VDD, VDD=VDD RST#=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD VDD=VDD VDD=VDD IOL=100 VDD=VDD IOH=-100 VDD=VDD
T9.1 1252
VDD-0.3 VDD-0.2
Address input VILT/VIHT, VDD=VDD (See Figure active while Erase Program progress.
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Data Sheet TABLE Recommended System Power-up Timings
Symbol TPU-READ1 TPU-WRITE
Parameter Power-up Read Operation Power-up Write Operation
Minimum
Units
T10.0 1252
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE Capacitance 25°C, Mhz, other pins open)
Parameter CI/O1
Description Capacitance Input Capacitance
Test Condition VI/O
Maximum
T11.0 1252
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE Flash Reliability Characteristics
Symbol NEND TDR1 ILTH1
Parameter Endurance Data Retention Latch
Minimum Specification 10,000
Units Cycles Years
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T12.0 1252
This parameter measured only initial qualification after design process change that could affect this parameter.
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
CHARACTERISTICS
TABLE (P)SRAM Read Cycle Timing Parameters
TRCS TAAS TBES TOES TBYES TBLZS1 TOLZS1 TBYLZS1 TBHZS
Units
Read Cycle Time Address Access Time Bank Enable Access Time Output Enable Access Time UBS#, LBS# Access Time BES# Active Output Output Enable Active Output UBS#, LBS# Active Output BES# High-Z Output Output Disable High-Z Output
T13.0 1252
TOHZS1 TBYHZS TOHS
UBS#, LBS# High-Z Output Output Hold from Address Change
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE (P)SRAM Write Cycle Timing Parameters
Symbol TWCS TBWS TAWS TASTS TWPS TWRS TBYWS TODWS TOEWS TDSS TDHS Parameter Write Cycle Time Bank Enable End-of-Write Address Valid End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time UBS#, LBS# End-of-Write Output Disable from Output Enable from High Data Set-up Time Data Hold from Write Time Units
T14.0 1252
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Data Sheet TABLE Flash Read Cycle Timing Parameters 2.7-3.3V
Symbol TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1
Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time BEF# Active Output Active Output BEF# High High-Z Output High High-Z Output Output Hold from Address Change RST# Pulse Width RST# High Before Read RST# Read
Units
T15.0 1252
TRHR1
This parameter measured only initial qualification after design process change that could affect this parameter. This parameter applies Sector-Erase, Block-Erase Program operations. This parameter does apply Chip-Erase.
TABLE Flash Program/Erase Cycle Timing Parameters
Symbol TOES TOEH TWPH1 TCPH1 TBY1,2 TBR1 TSCE
Parameter Program Time Address Setup Time Address Hold Time BEF# Setup Time BEF# Hold Time High Setup Time High Hold Time BEF# Pulse Width Pulse Width Pulse Width High BEF# Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time Erase-Suspend Latency RY/BY# Delay Time Bus# Recovery Time Sector-Erase Block-Erase Chip-Erase
Units
TIDA1
T16.1 1252
This parameter measured only initial qualification after design process change that could affect this parameter. This parameter applies Sector-Erase, Block-Erase, Program operations. This parameter does apply Chip-Erase operations.
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
TRCS ADDRESSES AMSS-0 TAAS BES1# TBES TOHS
BES2
TBES TBLZS TBHZS TOES TOLZS TOHZS TBYES TBYLZS TBYHZS DATA VALID
1252 F04.0
UBS#, LBS#
DQ15-0
Note: AMSS Most Significant Address AMSS SST34HF1621C, SST34HF1641C/J, SST34HF1681J
FIGURE (P)SRAM Read Cycle Timing Diagram
TWCS ADDRESSES AMSS3-0 TASTS
TAWS
TWPS
TWRS
TBWS
BES1# TBWS TBYWS TODWS DQ15-8, DQ7-0
NOTE
BES2 UBS#, LBS#
TDSS
TOEWS TDHS
NOTE
1252 F05.0
VALID DATA
Note: High during Write cycle, outputs will remain high impedance. BES1# goes BES2 goes high coincident with after goes Low, output will remain high impedance. BES1# goes High BES2 goes coincident with before goes High, output will remain high impedance. Because signals output state this time, input signals reverse polarity must applied. AMSS Most Significant SRAM Address AMSS SST34HF1621C, SST34HF1641C/J, SST34HF1681J
FIGURE (P)SRAM Write Cycle Timing Diagram (WE# Controlled)1
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
TWCS ADDRESSES AMSS3-0 TWPS TBWS BES1# BES2 TBWS TAWS TASTS UBS#, LBS# TDSS DQ15-8, DQ7-0
NOTE
TWRS
TBYWS
TDHS
NOTE
1252 F06.0
VALID DATA
Note: High during Write cycle, outputs will remain high impedance. Because signals output state this time, input signals reverse polarity must applied. AMSS Most Significant SRAM Address AMSS SST34HF1621C, SST34HF1641C/J, SST34HF1681J
FIGURE (P)SRAM Write Cycle Timing Diagram (UBS#, LBS# Controlled)1 (P)SRAM ONLY
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
ADDRESS A19-0 BEF# TCLZ DATA VALID TOLZ
TOHZ
TCHZ HIGH-Z DATA VALID
1252 F07.0
DQ15-0
HIGH-Z
FIGURE Flash Read Cycle Timing Diagram Word Mode (For Byte Mode Address Input)
ADDRESS A19-0 BEF# RY/BY# DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) Note: VIH, other value. VALID
1252 F08.1
ADDR
TWPH
FIGURE Flash Controlled Program Cycle Timing Diagram Word Mode (For Byte Mode Address Input)
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
ADDRESS A19-0 BEF# TCPH ADDR
RY/BY# DQ15-0
XXAA
XX55
XXA0
DATA WORD (ADDR/DATA)
VALID
1252 F09.1
Note: VIH, other value.
FIGURE Flash BEF# Controlled Program Cycle Timing Diagram Word Mode (For Byte Mode Address Input)
ADDRESS A19-0 BEF# TOEH RY/BY# TOES
DATA
DATA#
DATA#
DATA
1252 F10.0
FIGURE Flash Data# Polling Timing Diagram Word Mode (For Byte Mode Address Input)
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
ADDRESS A19-0 BEF# TOEH
READ CYCLES WITH SAME OUTPUTS
VALID DATA
1252 F11.0
FIGURE Flash Toggle Timing Diagram Word Mode (For Byte Mode Don't Care)
SIX-BYTE CODE CHIP-ERASE ADDRESS A19-0
TSCE
BEF#
RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10
VALID
Note: This device also supports BEF# controlled Chip-Erase operation. BEF# signals interchangeable long minimum timings met. (See Table 16.) VIH, other value.
1252 F12.1
FIGURE Flash Controlled Chip-Erase Timing Diagram Word Mode (For Byte Mode Don't Care)
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
SIX-BYTE CODE BLOCK-ERASE ADDRESS A19-0 BEF# RY/BY# XXAA DQ15-0 XX55 XX80 XXAA XX55 XX50
VALID
1252 F13.1
Note: This device also supports BEF# controlled Block-Erase operation. BEF# signals interchangeable long minimum timings met. (See Table 16.) Block Address VIH, other value.
FIGURE Flash Controlled Block-Erase Timing Diagram Word Mode (For Byte Mode Don't Care)
SIX-BYTE CODE SECTOR-ERASE ADDRESS A19-0 BEF# RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX30
VALID
1252 F14.1
Note: This device also supports BEF# controlled Sector-Erase operation. BEF# signals interchangeable long minimum timings met. (See Table 16.) Sector Address VIH, other value.
FIGURE Flash Controlled Sector-Erase Timing Diagram Word Mode (For Byte Mode Don't Care)
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Three-Byte Sequence Software Entry ADDRESS A14-0 0000 0001
BEF#
TWPH DQ15-0 XXAA XX55 XX90 00BF
Device
1252 F15.1
TIDA
Note: VIH, other value. Device 734BH SST34HF16x1C/J
FIGURE Flash Software Entry Read Word Mode (For Byte Mode
THREE-BYTE SEQUENCE QUERY ENTRY ADDRESSES
TWPH DQ15-0 XXAA XX55 XX98
1252 F26.0
TIDA
Note: VIH, other value.
FIGURE Entry Read
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Three-Byte Sequence Software Exit Reset
ADDRESS A14-0
DQ15-0
XXAA
XX55
XXF0 TIDA
BEF#
TWHP
1252 F16.1
Note: VIH, other value
FIGURE Flash Software Exit/CEI Exit Word Mode (For Byte Mode
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
RY/BY# RST#
BEF#/OE# TRHR
1252 F17.0
FIGURE Timing (when internal operations progress)
RY/BY#
RST# BEF#
1252 F18.0
FIGURE RST# Timing (during Sector- Block-Erase operation)
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
VIHT INPUT VILT
1252 F19.0
REFERENCE POINTS
OUTPUT
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD). Input rise fall times (10% 90%)
Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE Input/Output Reference Waveforms
TESTER
1252 F20.0
FIGURE Test Load Example
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Start
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XXA0H Address: 555H
Load Address/Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
1252 F21.2
Note: VIH, other value.
FIGURE Program Algorithm
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Internal Timer Program/Erase Initiated
Toggle Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE,
Read byte/word
Read
Program/Erase Completed
Read same byte/word
true data?
Does match? Program/Erase Completed
Program/Erase Completed
1252 F22.1
FIGURE Wait Options
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Software Product Entry Command Sequence Load data: XXAAH Address: 555H
Query Entry Command Sequence
Query Entry Command Sequence
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX90H Address: 555H
Load data: XX98H Address: 555H
Load data: XX88H Address: 555H
Wait TIDA
Wait TIDA
Wait TIDA
Read Software
Read data
Read
VIH, other value
1252 F23.2
FIGURE Software Product ID/CFI/Sec Command Flowcharts
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Software Exit/CFI Exit/Sec Exit Command Sequence
Load data: XXAAH Address: 555H
Load data: XXF0H Address:
Load data: XX55H Address: 2AAH
Wait TIDA
Load data: XXF0H Address: 555H
Return normal operation
1252 F24.2
Wait TIDA
Return normal operation
VIH, other value
FIGURE Software ID/CFI/ Exit/Sec Exit Command Flowcharts
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Chip-Erase Command Sequence Load data: XXAAH Address: 555H
Sector-Erase Command Sequence Load data: XXAAH Address: 555H
Block-Erase Command Sequence Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX80H Address: 555H
Load data: XX80H Address: 555H
Load data: XX80H Address: 555H
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX10H Address: 555H
Load data: XX30H Address:
Load data: XX50H Address:
Wait TSCE
Wait
Wait
Chip erased FFFFH
Sector erased FFFFH
Block erased FFFFH
1252 F25.1
Note: VIH, other value.
FIGURE Erase Command Sequence
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
PRODUCT ORDERING INFORMATION
Device Speed Suffix1 Suffix2 XXXX Package Attribute non-Pb Package Modifier balls balls Package Type LFBGA (8mm 10mm 1.4mm, 0.45mm ball size) LFBGA (8mm 10mm 1.4mm, 0.40mm ball size) Temperature Range Extended -20°C +85°C Minimum Endurance =10,000 cycles Read Access Speed Version Mbit SRAM Mbit PSRAM Boot Block Protection Bottom Boot Block (P)SRAM Density Mbit Mbit Mbit Flash Density Mbit Voltage 2.7-3.3V Product Series Concurrent SuperFlash (P)SRAM ComboMemory
SST34HF16x1X-
Environmental suffix denotes non-Pb solder. non-Pb solder devices "RoHS Compliant".
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Data Sheet Valid combinations SST34HF1621C SST34HF1621C-70-4E-L1PE SST34HF1621C-70-4E-LSE
Valid combinations SST34HF1641C SST34HF1641C-70-4E-L1PE SST34HF1641C-70-4E-LSE
Valid combinations SST34HF1641J SST34HF1641J-70-4E-L1PE SST34HF1641J-70-4E-LSE
Valid combinations SST34HF1681J SST34HF1681J-70-4E-L1PE SST34HF1681J-70-4E-LSE
Note: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
PACKAGING DIAGRAMS
VIEW
10.00 0.20
BOTTOM VIEW
5.60 0.80
0.80 CORNER 1.30 0.10 8.00 0.20 5.60
0.45 0.05 (56X) CORNER
SIDE VIEW
SEATING PLANE 0.35 0.05 Note:
0.12
Although many dimensions similar those JEDEC Publication MO-210, this specific package registered. linear dimensions millimeters. Coplanarity: 0.12 Ball opening size 0.38 0.05 56-lfbga-L1P-8x10-450mic-4
FIGURE 56-Ball Low-Profile, Fine-Pitch Ball Grid Array (LFBGA) 10mm Package Code: L1PE
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
VIEW
10.00 0.20
BOTTOM VIEW
7.20 0.80
0.80 CORNER 8.00 0.20 5.60
0.40 0.05 (62X) CORNER
SIDE VIEW
1.30 0.10
0.12 SEATING PLANE 0.32 0.05
Note:
Although many dimensions similar those JEDEC Publication MO-210, this specific package registered. linear dimensions millimeters. Coplanarity: 0.12 62-lfbga-LS-8x10-400mic-4 Ball opening size 0.32 0.05
FIGURE 62-Ball Low-Profile, Fine-Pitch Ball Grid Array (LFBGA) 10mm Package Code:
©2006 Silicon Storage Technology, Inc.
S71252-02-000
2/06
Mbit Concurrent SuperFlash 2/4/8 Mbit (P)SRAM ComboMemory SST34HF1621C SST34HF1641J SST34HF1641C SST34HF1681J
Data Sheet TABLE Revision History
Number Description Date 2004 2005
Initial Release Renamed devices previously released with version Removed Mbit PSRAM organization SST34HF1681J Changed references Word-Program Byte-Program Program Updated "Flash Erase-Suspend/-Resume Operations" page Added RoHS compliance information page "Product Ordering Information" page Removed references MPNs for, SST34HF1601C Data Sheet Removed references MPNs for, SST34HF1601S Moved references MPNs for, SST34HF1601S S71301 Updated software command sequence addresses Table page timing diagrams, flowcharts Added solder reflow temperature "Absolute Maximum Stress Ratings" page Corrected footnote Table "Software Command Sequence" page Added Table "CFI Query Identification String" page Added Table "System Interface Information" page Added Table "Device Geometry Information" page Changed test condition frequency specification from 1/TRC Table page Updated parameter from Table page Removed occurrences 256K Removed SRAM Read Write cross reference page Removed SRAM from Figure Functional Block Diagram page Removed SRAM Address from Table page Removed Table Operational Modes Selection SRAM Applied style formats throughout
2006
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2006 Silicon Storage Technology, Inc. S71252-02-000 2/06

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