Bluetooth® VREGA VREGD] VDDBAT VREF VREG_OFF Oscillator Powe
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XE1431
Bluetooth®
VREGA VREGD] VDDBAT VREF VREG_OFF
Oscillator Power Management Memory Boot Loader
Bluetooth Sequencer
MOSI NSS[4:0] MISO VMIC_P VMIC_N PA_OUTP PA_OUTN PA[7:0] PB[7:0]
RADIO Interface
radio inputs radio outputs
CODEC Bluetooth Controller Bluetooth Interface Bluetooth Interface
NRESET
WAKEUP clocks
GPIO/UART
XE1431
Ultra power Bluetooth® solution with Embedded Host data voice applications
GENERAL DESCRIPTION
XE1431 Bluetooth System-on-Chip based Semtech Bluetooth Sequencer, which includes fully programmable 8-bit application microcontroller, high speed UART, interface, oscillator, power management unit, on-chip voice CODEC. purpose XE1431 offer very high level integration requiring minimum external components build complete voice data applications while maintaining design flexibility. This product been designed ultra power consumption cheap solutions. combining XE1431 with power radio device such Semtech XE1413 CX72303, ultra power Bluetooth wireless headset consuming less than 23mW @2.2V (HV3) built.
PRODUCT FEATURES
System Chip Voice Data, including Bluetooth baseband, application host 15-bit audio linear Codec Fully integrated Bluetooth protocol stack HCI, compliant revision Embedded 8-bit host microcontroller On-chip preamplifier power amplifier Supports Class Class Class radio modules Minimum external components required Small form factor programmable GPIO's High speed UART chip power management unit oscillator Operating voltage range 3.6V Ultra power consumption, typically below 2.2V link, DM1, kbit/s.
APPLICATIONS
Bluetooth cellphone headset Handsfree VoRF Computer accessories Cable replacement Wireless games
ORDERING INFORMATION
Part Number XE1431IO77TR Description Bluetooth voice data applications
April 2006
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XE1431
Bluetooth®
Table Contents
Application Information XE1431-based System Level Block Diagram XE1431 Pinout description.
Detailed Functional Description Block Diagram Host Processor system 3.2.1 CoolRISC CPU. 3.2.2 Program memory. 3.2.3 Data memory. Power Management Unit. 3.3.1 Features 3.3.2 Register 3.3.3 Modes operation 3.3.4 Block diagram. 3.3.5 Regulators specifications, external components 3.3.6 Battery End-Of-Life (EOL). Reset controller 3.4.1 Features 3.4.2 Register 3.4.3 Power-On-Reset Brownout detector 3.4.4 Error 3.4.5 Watchdog 3.4.6 Analog reset specifications Clock Distribution Unit 3.5.1 Features 3.5.2 Register 3.5.3 oscillator 3.5.4 SLOW_CLOCK_IN. 3.5.5 SYS_CLOCK_IN 3.5.6 Clock source selection 3.5.7 RegSysMisc description. 3.5.8 Prescalers 3.5.9 Codec Bluetooth Sequencer clocks Interrupt controller 3.6.1 Features 3.6.2 Register 3.6.3 Operation. Event controller 3.7.1 Features 3.7.2 Register 3.7.3 Operation. Digital input port PA[7:0]. 3.8.1 Features 3.8.2 Register 3.8.3 Block diagram. 3.8.4 Debounce mode 3.8.5 Pull-ups/Snap-to-rail. 3.8.6 Interrupt sources 3.8.7 Event sources. 3.8.8 Clock sources. 3.8.9 Reset sources Digital input/output port PB[7:0] 3.9.1 Features
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Bluetooth®
3.9.2 Register 3.9.3 Multiplexing with other peripherals. 3.9.4 Port digital capabilities 3.10 Counters/Timers. 3.10.1 Features 3.10.2 Register 3.10.3 General Operation Overview. 3.10.4 Clock selection 3.10.5 Mode selection 3.10.6 Counter Timer mode 3.10.7 mode. 3.10.8 Counter capture function. 3.11 Serial Peripheral Interface (SPI) 3.11.1 Features 3.11.2 Register 3.11.3 Operation. 3.11.4 Software hints. 3.11.5 Pins 3.12 Application UART 3.12.1 Features 3.12.2 Registers 3.12.3 Block diagram. 3.12.4 Configuration 3.12.5 Baud rates 3.12.6 Transmission 3.12.7 Reception 3.12.8 Flow control 3.12.9 Software hints. 3.13 Bluetooth Sequencer Interface. 3.13.1 Features 3.13.2 Overview 3.13.3 Link Controller Features. 3.13.4 Link Manager Features 3.13.5 Standard Host Controller Interface (HCI) Commands 3.13.6 Vendor Specific Commands "EasyBlueCommands". 3.13.7 Radio Interface 3.13.8 UART 3.13.9 Bluetooth Sequencer clock source 3.14 Audio CODEC 3.14.1 Features 3.14.2 Register 3.14.3 Block diagram. 3.14.4 CODEC clock source 3.14.5 Specifications 3.14.6 Microphone input. 3.14.7 Speaker output 3.15 Debug Interface. 3.15.1 Description 3.15.2 Register 3.15.3 Pins mapping. 3.15.4 Configuration 3.15.5 Configuration Examples 3.16 Development Debug Chip Electrical Specifications Absolute Maximum Ratings Recommended Operating Conditions Supply configuration, power consumption
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XE1431
Bluetooth®
4.3.1 4.3.2 supply configuration, single crystal oscillator 1.8V supply configuration, single crystal oscillator
Application Schematics Bluetooth Headset Packaging Information 72-pin LFBGA Reference Documents Notice, Trademarks.
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XE1431
Bluetooth®
APPLICATION INFORMATION XE1431-BASED SYSTEM LEVEL BLOCK DIAGRAM
Semtech XE1431, member EasyBluefamily, based unique Embedded-Host architecture which enables data voice application enhanced with ultra power Bluetooth technology with risk short development time. core XE1431 Semtech ROM-based Bluetooth sequencer combined with embedded 8-bit RISC microcontroller several standard peripherals such GPIO, high speed UART, audio CODEC, power management unit. Bluetooth sequencer executes lower layers Bluetooth stack, while microcontroller runs application higher levels protocol. Since sequencer microcontroller independent, effort validation qualification Bluetooth protocol greatly decreased. typical wireless headset block diagram using XE1431 shown Figure on-chip CODEC connected with microphone speaker. Serial Peripheral Interface (SPI) directly interfaces external Flash memory. This memory stores application upper layers Bluetooth protocol stack which loaded boot-up time, then executed on-chip application processor. Fully programmable General Purpose Input/Output ports (GPIO) available interface push-buttons, LED's other peripherals. high speed UART supports hardware flow control data rates kbit/s. serial Flash
GPIO/UART
GPIO
on-chip host processor runs application software upper layer Bluetooth protocol stack software while Bluetooth sequencer handles level protocol without intervention application processor. This architecture guarantees that real time operations lower levels influenced application. Qualified upper layer Bluetooth protocol software from various party suppliers supplied XE1431. This system architecture definitely eases software development Bluetooth qualification processes guarantees highest flexibility. Bluetooth qualification process final application simplified fact that XE1431 uses qualified Bluetooth implementation.
CODEC
Application Processor
Bluetooth Sequencer
XE1431
Radio Interface
XEMICS XE1413 Bluetooth Radio
Figure Bluetooth Headset Application
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XE1431
Bluetooth®
XE1431 PINOUT
Bottom view
index
0.5mm
Figure LFBGA72, bottom view
DESCRIPTION Symbol PB[1] PB[3] PB[5] UA_RTS PB[7] UA_RX MOSI MISO NRESET Type/ capabilities connect connect Connect ground DIOu DIOu DIOu DIOu DIOu DIOu DIOu Reset connect connect Connect ground Description Test Test Test General purpose port General purpose port General purpose port UART handshaking General purpose port UART receive signal master slave master slave clock Master Reset VDDIO_DIG VDDIO_DIG VDDIO_DIG VDD_M
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Voltage level VDDIO_DIG VDDIO_DIG VDDIO_DIG VDDIO_DIG
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Bluetooth®
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Symbol VSS_DIG PB[0] PB[2] PB[4] UA_CTS PB[6] UA_TX VSSIO_DIG VDDIO_DIG NSS[0] NSS[1] VREG_OFF VDDBAT NSS[2] NSS[3] VMIC_P VDD_ANA DBG[4] DBG[7] PA[0] NSS[4] VMIC_N VREGA DBG[5] DBG[6] PA[2] PA[1] VREF VDD_M DBG[1] DBG[3] PA[4] PA[3] VSS_M VREGD
Type/ capabilities DIOu DIOu DIOu DIOu DIOu DIOu DIOu DIOu DIOk DIOk DIuk DIOu DIOk DIOk DIuk DIuk DIOk DIOk DIuk DIuk
Reset
Description Digital core ground General purpose port General purpose port General purpose port UART handshaking General purpose port UART transmit signal digital pads ground digital pads supply voltage First slave select Second slave select Internal regulators status Sensor input battery end-of-life detection Third slave select Fourth slave select Microphone positive input Analog core supply voltage Debug Interface Debug Interface General purpose port input Fifth slave select Microphone negative input Analog regulated voltage Debug Interface Debug Interface General purpose port input General purpose port input Reference voltage output Main supply voltage Debug Interface clock Debug Interface data General purpose port input General purpose port input Analog ground Digital regulated voltage
Voltage level VDDIO_DIG VDDIO_DIG VDDIO_DIG VDDIO_DIG VDDIO_DIG VDDIO_DIG VDDM VDDIO_DIG VDDIO_DIG VDDIO_DIG VDDIO_DIG VDDIO_DIG VDDIO_DIG VDDIO_DIG VDDIO_DIG VDDIO_DIG VDDIO_DIG VDDIO_DIG VDDIO_DIG VDDIO_DIG VDDIO_DIG www.semtech.com
XE1431
Bluetooth®
Symbol DBG[0] DBG[2] PA[6] PA[5] PA_OUTP VDD_PA VDD_DIG PA[7] PA_OUTN WAKEUP SPI_DATA_IN VDDIO VSSIO RX_EN SYNC_DETECT SYS_CLOCK_IN DOC_SDIO VSS_PA RX_DATA SLW_CLOCK_IN TX_DATA TX_EN SPI_DATA_OUT SPI_CLK_OUT SPI_EN_BAR DOC_SCK Type/ capabilities DIOk DIOk DIuk DIuk DIuk connect DIOu connect Analog Input Internal pull-up Internal keeper Reset connect connect Description Debug Interface fsync Debug Interface data General purpose port input General purpose port input Power amplifier positive output Power amplifier supply voltage Digital core supply voltage General purpose port input Power amplifier negative output Test Chip wake Radio input Radio pads supply voltage Radio pads ground Radio enable Radio sync detect Master clock input Monitor data Power amplifier ground Test Radio data clock input Radio data Radio enable Radio data Radio serial clock Radio select Monitor clock Digital Output Internal pull-down Power Voltage level VDDIO_DIG VDDIO_DIG VDDIO_DIG VDDIO_DIG VDD_PA VDDIO_DIG VDD_PA VDD_M VDDIO VDDIO VDDIO VDDIO VDDIO_DIG VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO_DIG
Table description
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XE1431
Bluetooth®
DETAILED FUNCTIONAL DESCRIPTION
BLOCK DIAGRAM Program Memory (ROM RAM)
RX_DATA SPI_DATA_IN
CoolRISC RISC
Data Memory
UART
uart
Bluetooth Sequencer
TX_DATA RX_EN SYNC_DETECT TX_EN SPI_DATA_OUT SPI_CLK_OUT SPI_EN_BAR
Event Controller
Codec
VMIC_P, VMIC_N PA_OUTP, PA_OUTN
NRESET
Reset Controller Interrupt Controller
GPIO
PB[7
Application UART
Counter/ Timer
SYS_CLOCK_IN
PA[7
Clock Controller
SLW_CLOCK_IN
MISO, MOSI, SCK,NSS[4
Oscillator
TP[4 DOC_SCK, DOC_SDIO DBG[7
Power Management
WAKEUP VDDBAT VREGA, VREGD VREF, VREG_OFF VDD_M, VDD_PA, VDD_DIG, VDDIO, VDD_ANA, VDDIO_DIG VSS_M, VSS_PA, VSS_DIG, VSSIO, VSSIO_DIG
Figure XE1431 block diagram
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Bluetooth®
high-level block diagram XE1431 shown Figure CoolRISC816 8-bit RISC processor optimized both computation power energy consumption efficiency. Every instruction executes clock cycle. system frequency selected between different possible clock signals SLW_CLOCK_IN, which typ. kHz, SYS_CLOCK_IN, which typ. MHz, internal programmable oscillator MHz. program memory consists first instructions boot code debug drivers, then instructions dedicated application upper layers Bluetooth protocol stack. data memory kbyte RAM. interrupt event controllers manage interrupts events from peripherals internal timers. reset controller takes care power-on phase. clock controller selects processor peripherals clocks between internal oscillator external clocks. GPIO's split into peripherals: port (PA) 8-bit wide input digital port with selectable pull-up debouncer. also programmed generate interrupts resets; port (PB) 8-bit wide input/output digital port with selectable pull-up open-drain capabilities. UART interfaces implement serial communication protocols. communicate with peripherals, them being serial non-volatile memory storing application code. UART 8-byte FIFO supports hardware flow control. integrated power management unit generates regulated supply voltages XE1431, thus reducing number external components. also monitors battery voltage detect end-of-life battery. codec compliant with Bluetooth Audio specifications integrates built-in CVSD coder/decoder. audio samples transferred directly from Bluetooth sequencer codec reduce processor load power consumption. interface allows transferring samples directly between memory codec. Bluetooth sequencer complete dedicated Bluetooth co-processor. implements lower layers Bluetooth protocol stack from radio interface HCI. runs independently from processor communicates with through dedicated internal UART link. This tremendously simplifies debugging final product Bluetooth qualification since application disturb time-critical part Bluetooth stack. Bluetooth sequencer supports modes operation (Active, Hold, Sniff, Park, Standby), packet types, simultaneous operation with (data) links (audio) link point-to-point, piconet, scatternet network configuration. debug-on-chip (DoC) peripheral interfaces chip with software debugger.
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XE1431
Bluetooth®
HOST PROCESSOR SYSTEM
3.2.1 CoolRISC XE1431 CoolRISC816, 8-bit power RISC core. instruction made generic instructions coded bits always executed clock cycle, including conditional jumps multiplications, thus providing MIPS/MHz. Instructions data memory separated (Harvard architecture). 8-bit registers enable compiler. complete hardware software description given document "CoolRISC 816, 8-bit Microprocesor Core, Hardware Software Reference Manual", version which found Semtech website http://www.semtech.com
0xBFFF 0x3FFF
instruction
0x3FF0 0x3FEF
Instruction memory
internal registers stat 0x0000 Peripheral registers data
0x2000 0x1FFF
0x2000 0h0FFF 0x0000
Figure Memory organization
3.2.2 Program memory instruction memory composed both RAM. size 4096 22-bit stores boot code Debug-On-Chip (DoC) driver. size instructions completely available application except last instructions between 0xBFB0 0xBFFF which used Debug-on-Chip. located from address 0x0000 address 0x0FFF. located 0x2000 0xBFFF range. Addresses 0x2000 0x2004 jump interrupt vectors. Address 0x2000 0x2001 0x2002 0x2003 0x2004 Usage start vector priority interrupt handler priority interrupt handler High priority interrupt handler RESERVED
Table Jump interrupt vectors address table
Comment Usually 0x2005. code actually begins 0x2005
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3.2.3 Data memory data memory space made kbytes RAM. last bytes between 0x3FF0 0x3FFF reserved Debug-On-Chip (DoC) interface. rest space from 0x2000 0x3FEF available application. peripheral registers located page data memory space. Block System registers (reset controller clock controller) Port registers Port registers Application UART registers Debug-On-Chip registers (reserved) Event controller registers Interrupt controller registers Power management unit registers UART (to/from Bluetooth Sequencer) registers Counter registers registers Debug-on-Chip registers (reserved) Codec registers Data Memory Debug-on-Chip memory (reserved) Address range 0x0010 0x001F 0x0020 0x0027 0x0028 0x002D 0x0030 0x0037 0x0038 0x003B 0x003C 0x003F 0x0040 0x0047 0x0048 0x004C 0x0050 0x0057 0x0058 0x005F 0x0068 0x006F 0x0080 0x009F 0x00E0 0x00FF 0x2000 0x3FEF 0x3FF0 0x3FFF
Table Data memory registers
3.3.1 3.3.2
POWER MANAGEMENT UNIT Features Wide power supply range, VDD_M from 3.6V. High current integrated 1.8V regulator supply digital core XE1431 external chips, VREGD output. Integrated 1.8V analog regulator supply analog blocks, VREGA output. Integrated temperature-compensated voltage reference. Battery end-of-life detection, VDDBAT input. Mode operation controller suppress need external power supply switch. Ultra power consumption mode. Register Address (Hex) 0x0048 0x0049 0x004A
Table Power management unit register mapping
Name RegPmgtVrega RegPmgtVregd RegPmgtEol
RegPmgtVrega DefaultVrega EnableVrega TuneVrega
Reset 0011
Function reserved force analog tuning default values VREGA voltage regulator switched VREGA voltage regulator switched adjust VREGA value
Table RegPmgtVrega register
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RegPmgtVregd WakeUp VregdStatus TuneVregd VregdLock
Reset
Function value wakeup reserved VREGD voltage regulator switched VREGD voltage regulator switched adjust VREGD value lock VREGD voltage regulator shut down VREGD voltage regulator reserved
Table RegPmgtVregd register
RegPmgtEol EolOk EnableEol EolThreshold
Reset 00000
Function VDDBAT voltage EolThreshold VDDBAT voltage EolThreshold reserved battery end-of-life switched battery end-of-life switched adjust battery end-of-life comparator threshold
Table RegPmgtEol register
3.3.3 Modes operation power management unit's role generate regulated voltages both internal external components such non-volatile serial memory radio chip. includes controller switch on/off voltage regulators when needed order reduce power consumption. Three modes operation defined (see Figure mode: internal power supplies shut down. Power consumption very low, typically microamps. mode: blocks except CODEC powered. application running Bluetooth connection active. chip enters this state when WAKEUP input high (see Figure leaves this mode under software control, when requested application. mode, VREGD outputs 1.8V VREGA floating. AUDIO mode: blocks powered. entered upon request from application. AUDIO mode, pins VREGA VREGD output 1.8V.
WAKEUP twakeup
Figure WAKEUP timing diagram
Software control (ex. link activated)
WAKEUP
AUDIO
Software control (for Timeout button)
Software control (for link closed)
Figure XE1431 power management modes
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3.3.4
Block diagram
VREF VDD_M Iref VDD_M Vref Bandga VDD_M
vreg_dig
VREGD
VDD_M VDDBAT
VDD_M
vreg_ana
VREG_OFF
VREGA
VDD_M
power_mngt controller
VDD_M
VDD_DIG VDDIO
levelshifters
VDD_ANA
VDD_ANA
VDD_DIG
analog core
digital core
VDDIO padring VDD_DIG VDDIO_DIG
VDD_PA Power Amplifier
VDDIO_DIG padring
Figure Power management unit block diagram
main power supply VDD_M. powers power management unit some pads. power management unit generates VREGD VREGA regulated voltages. VREGD usually used supply digital core, through VDD_DIG pin, external components such serial non-volatile memory radio chip. VREGA usually used supply internal analog blocks, through VDD_ANA. also used power external microphone. VDDIO power supply radio interface. radio chip powered VREGD, then VDDIO should connected VREGD well. VDDIO_DIG power supply most digital pads. Depending application, connected VREGD, VDD_M, other power supply which fulfills specifications.
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VDD_M should decoupled with capacitor CVDD_M best performances. VREGD connected external capacitor CVREGD insure stability performance voltage regulator. VREGA connected external capacitor CVREGA insure stability performance voltage regulator. VREF connected external capacitor CVREF. VDD_PA connected VREGD. 3.3.5 Regulators specifications, external components Symbol VREGA VREGD IREGA IREGD Description Analog regulated output voltage Digital regulated output voltage Output current VREGA Output current VREGD 1.62 1.62 Typ. 1.98 1.98 Unit Recommended max. load Recommended max. load Comments
Table On-chip voltage regulators specifications
Symbol CVREGD CVREGA CVREF CVDD_M
Value
Table Typical external components
Capacitors should added decouple VDD_PA, VDD_DIG, VDD_ANA, VDDIO, VDDIO_DIG, common practice. 3.3.6 Battery End-Of-Life (EOL)
VDDBAT EolOk Ieol 0.7V
Figure Battery end-of-life structure
battery end-of-life circuit structure described Figure voltage created drawing constant current Ieol from VDDBAT through internal resistor compared with voltage reference. EolOk register RegPmgtEol directly output comparator. EolOk whenever voltage VDDBAT higher equal threshold voltage VEOLThreshold. This threshold voltage comparator given Equation cThe start time end-of-life circuit TEOLstart. response time change VDDBAT TEOLres.
VEOLThreshold VEOLref VEOLstep EolThreshold
Equation Threshold voltage comparator
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Symbol VEOLref VEOLstep EOLThresho TEOLstart TEOLres
Parameter reference voltage Threshold tuning step EOLthreshold offset setting start-up time time response
0.710 0x00
0.725
0.740 0x14
Unit
Comment VDD_M=3V, 20°C VDD_M=3V, 20°C
Table End-of-life analog specifications
3.4.1 3.4.2
RESET CONTROLLER Features Handles different reset sources: power-on-reset, NRESET pin, BusError, Watchdog, port Power-on-reset/Brownout detector without external components Programmable watchdog timer Reset triggered NRESET Register Address (Hex) 0x0010 0x0014
Table Reset controller registers
Name RegSysCtrl RegSysWd
RegSysCtrl EnableBusError EnableResetWD
Reset 0000
Function reserved BusError reset enabled BusError reset disabled Watchdog reset enabled Watchdog reset disabled reserved
Table RegSysCtrl register
RegSysWd WDKey
Reset 0000 0000
Function reserved Watchdog
Table RegSysWd register
3.4.3 Power-On-Reset Brownout detector power-on-reset monitors both VDD_M VDD_DIG. Upon start-up, when both voltages reach level sufficient ensure correct circuit behavior, internal reset signal released. Then, during operations supply voltage drops below specified threshold (see Table 14), circuit goes into reset mode.
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Bluetooth®
VDD_M
POR_VDD_M
reset (general system reset)
NRESET
VDD_DIG resetfromportA buserrorreset watchdogreset
POR_VDD_DIG
Figure POR, NRESET, reset circuitry
output POR_VDD_M controls pull resistor NRESET pad. NRESET left unconnected (recommended) POR_VDD_M propagated into system. Otherwise, internal nreset_system signal activated connecting NRESET ground. NRESET active low. POR_VDD_M insures that VDD_M stable that power management unit operate safely. POR_VDD_DIG insures that VDD_DIG correct that digital core start. 3.4.4 Error address space assigned shown memory Table EnableBusError register RegSysCtrl unused address accessed processor, then reset generated. 3.4.5 Watchdog Once enabled setting EnableResetWD RegSysCtrl register, counter will started reset condition (watchdogreset, Figure will generated when counter reaches maximum value, unless counter cleared software. counter 3-bit wide clocked ck2Hz output prescaler. period typically around seconds will depend clock controller configuration. watchdog cleared writing consecutively values 0x0a 0x03 RegSysWd register. assembler, sequence will look like: move RegSysWd, #0x0a move RegSysWd, #0x03 Only writing 0x0a followed 0x03 will clear watchdog. some other writing done between, RegSysWd, then watchdog will cleared. status watchdog checked reading register RegSysWd. watchdog four counter with range reset generated when counter reaches value
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3.4.6 Analog reset specifications
VDD_M VDD_DIG
VrstT
VrstD
reset
trise tdrop
Figure Power-On Brownout reset conditions
VDD_M supervision
VDD_DIG supervision
Symbol VrstT VrstD trise tdrop VrstT VrstD trise tdrop
Description Start Voltage Drop Voltage Reset Time Rise Time Drop Time Start Voltage Drop Voltage Reset Time Rise Time Drop Time
Unit
Table specifications
3.5.1 3.5.2
CLOCK DISTRIBUTION UNIT Features On-chip oscillator Three available clock sources: oscillator, SYS_CLOCK_IN pin, SLW_CLOCK_IN divider chains: high-prescaler bits) low-prescaler bits). clock disabled halt mode. Register Address (Hex) 0x0012 0x0013 0x0015 0x001B 0x001C
Table Clock distribution registers addresses
Name RegSysClock RegSysMisc RegSysPre0 RegSysRcTrim1 RegSysRcTrim2
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RegSysClock CpuSel SysClockClk EnableSysClk ColdSlwClock ColdRC EnableSlwClock EnableRC
Reset
Function clock either SYS_CLOCK_IN SLW_CLOCK_IN clock ckRC SYS_CLOCK_IN clock detected SYS_CLOCK_IN clock detected enable SYS_CLOCK_IN clock disable SYS_CLOCK_IN clock reserved SLW_CLOCK_IN starting phase cycles) SLW_CLOCK_IN starting phase finished ckRC starting phase cycles) ckRC starting phase finished enable SLW_CLOCK_IN disable SLW_CLOCK_IN enable ckRC disable ckRC
Table RegSysClock register
RegSysMisc DebFast OutputCk32kHz OutputCkCpu
Reset 00000
Function reserved select high frequency debouncer (PA) clock select frequency debouncer (PA) clock output ck32kHz PB[3] output CkCpu pb[2]
Table RegSysMisc register
RegSysPre0 ResPre
Reset 0000000
Function reserved reset prescaler
Table RegSysPre0 register
RegSysRcTrim1 RCDivFactor RCCoarseMSB
Reset
Function reserved Divide frequency 2RcDivFactor coarse adjustment (MSB)
Table RegSysTrim1 register
RegSysRcTrim2 RCCoarseLSB RCFine
Reset 0000
Function reserved coarse adjustment (LSB) fine adjustment
Table RegSysTrim2 register
3.5.3 oscillator oscillator always turned selected system operation after power-on reset negative pulse NRESET. deselected after SYS_CLOCK_IN SLW_CLOCK_IN been started selected system clock.
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EnableRC register RegSysClock controls signal from oscillator. user disable oscillator clock signal resetting EnableRC. oscillator frequency trimmed with registers RegSysRcTrim1 RegSysRcTrim2. absolute value frequency given register content change from chip chip process tolerances. However, modification frequency function modification register content fairly precise. oscillator output frequency, fRC, obtained following trimming rule:
RCDivFactor
RCCoarse CoarseStep RCFine FineStep
Equation oscillator clock frequency
Table summarizes characteristics oscillator. Symbol FineStep CoarseStep Description Internal oscillator frequency Fine tuning step Coarse tuning step 8.25 Unit
Table oscillator specifications
Important note: system guaranteed operate properly with frequency greater than MHz. Setting oscillator over this limit produce unpredictable results. 3.5.4 SLOW_CLOCK_IN SLW_CLOCK_IN must present conform Bluetooth specifications Bluetooth sequencer deep-sleep mode used. typically generated XE1413 radio chip. frequency 32'000 32'768 3.5.5 SYS_CLOCK_IN used Bluetooth sequencer Codec. frequency must with tolerance ppm. SYS_CLOCK_IN typically generated XE1413 radio chip. 3.5.6 Clock source selection Different clock sources selected independently application processor reset system. clock Bluetooth sequencer hard-coded chosen user. clock always selected after power-up negative pulse NRESET pin. clock selection done with register RegSysClock according Table Switching from clock source another glitch free. also Figure Figure Figure
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Clock Sources EnableSysClock EnableSlwClock CpuCk EnableRC
Clock Targets
Mode name
CpuSel
CpuSel
High prescaler clock input
prescaler clock input
SlwClock SlwClock SysClock
SLW_CLOCK_IN ckRC ckRC SYS_CLOCK_IN
SLW_CLOCK_IN high prescaler output SLW_CLOCK_IN high prescaler output
ckRC ckRC SYS_CLOCK_IN
high prescaler output SLW_CLOCK_IN high prescaler output
Table XE1431 Clock configuration
Switching from clock other stopping unused clock must performed three MOVE instructions RegSysClock. First enable clock, then select clock, finally stop unused clock. Combining different operations instruction cause system malfunction. 3.5.7 RegSysMisc description DebFast selects debouncer clock between DebFast DebFast debouncer clock feeds port input debouncer. debouncer described paragraph 3.8.4 When OutputCk32kHz ck32kHz clock output port PB[3]. clock output port PB[2] when OutputCkCpu
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3.5.8 Prescalers Figure describes overall structure prescaler.
Oscillator SYS_CLOCK_IN
ckRC
ckRCext High Prescaler ckRCext/2 ckRCext/256 (EnableSlwClock) (NOT(EnableSysClock)) Prescaler RCDivFactor RCCoarse RCFine ck32kHz ck1Hz
EnableSysClock
SLW_CLOCK_IN
ck32kHz
ckcpu
CpuSel (EnableRC) (EnableSysClock)
Figure Prescaler Unit block diagram
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3.5.8.1 High Prescaler high prescaler made 8-stage dividing chain. driven with oscillator clock SYS_CLOCK pin, depending EnableSysClock parameter. ckRCext ckRCext/2 ckRCext/4 ckRCext/8 ckRCext/16 ckRCext/32 ckRCext/64 ckRCext/128 ckRCext/256
Figure High prescaler block diagram
Table summarizes which peripherals outputs high prescaler. Since each stage high prescaler divides frequency frequency outputs high prescaler proportional frequency ckRCext. High prescaler output ckRCext ckRCext/2 ckRCext/4 ckRCext/8 ckRCext/16 ckRCext/32 ckRCext/64 ckRCext/128 Peripherals application UART, Bluetooth UART, SPI, counter/timer, port application UART, Bluetooth UART application UART, Bluetooth UART, SPI, counter/timer application UART, Bluetooth UART, application UART, Bluetooth UART, application UART, Bluetooth UART application UART, Bluetooth UART application UART, Bluetooth UART
Table High prescaler outputs usage
3.5.8.2 prescaler prescaler driven from high prescaler outputs ckRCext/2 ckRCext/128 directly with SLW_CLOCK_OUT when EnableSlwClock EnableSysClock reseted ResPre register RegSysPre0 synchronously resets prescaler. prescaler also automatically cleared when EnableSlwClock ColdSlwClock value indicate that SLW_CLOCK_IN starting phase. automatically enters this phase when EnableSlwClock During this phase, SLW_CLOCK_IN available. becomes available after 32'768 cycles, when ColdSlwClock returns
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(EnableSlwClock) (NOT(EnableSysClock)) SLW_CLOCK_IN
Ck32kHz
Ck128Hz Ck64Hz Ck32Hz Ck16Hz Ck8Hz Ck4Hz Ck2Hz Ck1Hz
ckRCext/2 ckRCext/4 ckRCext/8 ckRCext/16 ckRCext/32 ckRCext/64 ckRCext/128 Decoder RCFine RCCoarse RCDivFactor
Ck16kHz Ck8kHz Ck4kHz Ck2kHz Ck1kHz Ck512Hz Ck256Hz
Figure prescaler block diagram
high prescaler output used prescaler input. decoder used select from high prescaler frequency that closest operate prescaler when SLW_CLOCK_IN running. this case, oscillator frequency will also valid prescaler frequency outputs. Table shows trimming values RegSysRcTrim1 RegSysRcTrim2 registers decoded select input frequency from high prescaler. least significant bits RCFine word ignored. order ensure correct frequency selection prescaler with external clock, proper value must trim registers. frequency correctly, timings derived from prescaler will shifted accordingly (e.g. watchdog interrupt frequencies). Table ckRCext stands either ckRC SYS_CLOCK_IN. RCDivFactor RCCoarseMSB RCCoarseLSB RCFine [0x0000]hex [0x0002]hex [0x0100]hex [0x0102]hex [0x010a]hex [0x0110]hex [0x0119]hex [0x0120]hex [0x0127]hex
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Selected high prescaler ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext
RCDivFactor RCCoarseMSB RCCoarseLSB RCFine [0x04c8]hex [0x04d0]hex [0x04d6]hex [0x04e0]hex [0x04e5]hex [0x04f0]hex [0x04f3]hex [0x0500]hex [0x0502]hex
Selected high prescaler ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext
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RCDivFactor RCCoarseMSB RCCoarseLSB RCFine [0x0130]hex [0x0135]hex [0x0140]hex [0x0144]hex [0x0150]hex [0x0152]hex [0x0160]hex [0x0161]hex [0x0200]hex [0x0202]hex [0x020a]hex [0x0210]hex [0x0219]hex [0x0220]hex [0x0227]hex [0x0230]hex [0x0235]hex [0x0240]hex [0x0244]hex [0x0250]hex [0x0252]hex [0x0260]hex [0x0261]hex [0x028e]hex [0x0290]hex [0x029d]hex [0x02a0]hex [0x02ab]hex [0x02b0]hex [0x02b9]hex [0x02c0]hex [0x02c8]hex [0x02d0]hex [0x02d6]hex [0x02e0]hex [0x02e5]hex [0x02f0]hex [0x02f3]hex [0x0300]hex [0x0302]hex [0x030a]hex [0x0310]hex [0x0319]hex [0x0320]hex [0x0327]hex [0x0330]hex [0x0335]hex [0x0340]hex [0x0344]hex [0x0350]hex [0x0352]hex
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Selected high prescaler ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext
RCDivFactor RCCoarseMSB RCCoarseLSB RCFine [0x050a]hex [0x0510]hex [0x0519]hex [0x0520]hex [0x0527]hex [0x0530]hex [0x0535]hex [0x0540]hex [0x0544]hex [0x0550]hex [0x0552]hex [0x0560]hex [0x0561]hex [0x058e]hex [0x0590]hex [0x059d]hex [0x05a0]hex [0x05ab]hex [0x05b0]hex [0x05b9]hex [0x05c0]hex [0x05c8]hex [0x05d0]hex [0x05d6]hex [0x05e0]hex [0x05e5]hex [0x05f0]hex [0x05f3]hex [0x0600]hex [0x0602]hex [0x060a]hex [0x0610]hex [0x0619]hex [0x0620]hex [0x0627]hex [0x0630]hex [0x0635]hex [0x0640]hex [0x0644]hex [0x0650]hex [0x0652]hex [0x0660]hex [0x0661]hex [0x068e]hex [0x0690]hex [0x069d]hex [0x06a0]hex [0x06ab]hex [0x06b0]hex [0x06b9]hex [0x06c0]hex
Selected high prescaler ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext
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RCDivFactor RCCoarseMSB RCCoarseLSB RCFine [0x0360]hex [0x0361]hex [0x038e]hex [0x0390]hex [0x039d]hex [0x03a0]hex [0x03ab]hex [0x03b0]hex [0x03b9]hex [0x03c0]hex [0x03c8]hex [0x03d0]hex [0x03d6]hex [0x03e0]hex [0x03e5]hex [0x03f0]hex [0x03f3]hex [0x0400]hex [0x0402]hex [0x040a]hex [0x0410]hex [0x0419]hex [0x0420]hex [0x0427]hex [0x0430]hex [0x0435]hex [0x0440]hex [0x0444]hex [0x0450]hex [0x0452]hex [0x0460]hex [0x0461]hex [0x048e]hex [0x0490]hex [0x049d]hex [0x04a0]hex [0x04ab]hex [0x04b0]hex [0x04b9]hex [0x04c0]hex Selected high prescaler ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext RCDivFactor RCCoarseMSB RCCoarseLSB RCFine [0x06c8]hex [0x06d0]hex [0x06d6]hex [0x06e0]hex [0x06e5]hex [0x06f0]hex [0x06f3]hex [0x0700]hex [0x0702]hex [0x070a]hex [0x0710]hex [0x0719]hex [0x0720]hex [0x0727]hex [0x0730]hex [0x0735]hex [0x0740]hex [0x0744]hex [0x0750]hex [0x0752]hex [0x0760]hex [0x0761]hex [0x078e]hex [0x0790]hex [0x079d]hex [0x07a0]hex [0x07ab]hex [0x07b0]hex [0x07b9]hex [0x07c0]hex [0x07c8]hex [0x07d0]hex [0x07d6]hex [0x07e0]hex [0x07e5]hex [0x07f0]hex [0x07f3]hex Selected high prescaler ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext ckRCext
Table ck32kHz frequency selector
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Table summarizes which peripherals outputs prescaler. frequencies outputs prescaler directly proportional frequency clock source prescaler. prescaler output ck32kHz ck2kHz ck1kHz ck128Hz ck2Hz ck1Hz Peripherals application UART, Bluetooth sequencer UART, counter/timer, port debouncer counter/timer counter/timer, port debouncer interrupt controller, event controller watchdog interrupt controller, event controller
Table prescaler outputs usage
3.5.9 Codec Bluetooth Sequencer clocks codec only SYS_CLOCK_IN since needs exactly frequency meet Bluetooth audio specifications. Bluetooth sequencer uses SYS_CLOCK_IN normal operations SLW_CLOCK_IN during power modes.
Oscillator
CLOCK
Application Processor Bluetooth Sequencer
SYS_CLOCK_IN
CODEC
Figure Codec Bluetooth Sequencer clocking sources
typical application where XE1431 used with companion chip, XE1413 radio, SYS_CLOCK_IN SLW_CLOCK_IN generated XE1413.
3.6.1 3.6.2
INTERRUPT CONTROLLER Features Supports sources interrupt Three levels priority Register Address (Hex) 0x0040 0x0041 0x0042 0x0043 0x0044 0x0045
Table Interrupt controller register
Name RegIrqHig RegIrqMid RegIrqLow RegIrqEnHig RegIrqEnMid RegIrqEnLow
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RegIrqHig 128Hz CntA CntC Codec UartHTx UartHRx
Reset
Function reserved interrupt from ck128Hz prescaler output interrupt from interrupt from counter interrupt from counter interrupt from Codec interrupt from Bluetooth Sequencer UART transmitter interrupt from Bluetooth Sequencer UART receiver
Table RegIrqHigh register
RegIrqMid UartTx UartRx WakeUp
Reset
Function interrupt from application UART transmitter interrupt from application UART receiver interrupt from port PA[5] interrupt from port PA[4] interrupt from ck1Hz prescaler output interrupt from WAKEUP interrupt from port PA[1] interrupt from port PA[0]
Table RegIrqMid register
RegIrqLow CntB CntD UartHFlowControl UartFlowControl
Reset
Function interrupt from port PA[7] interrupt from port PA[6] interrupt from counter interrupt from counter interrupt from port PA[3] interrupt from port PA[2] interrupt from Bluetooth Sequencer UART flow control interrupt from application UART flow control
Table RegIrqLow register
RegIrqEnHig En128Hz EnSpi EnCntA EnCntC EnCodec EnUartHTx EnUartHRx
Reset
Function reserved enable interrupt from ck128Hz prescaler output enable interrupt from enable interrupt from counter enable interrupt from counter enable interrupt from Codec enable interrupt from Bluetooth Sequencer UART transmitter enable interrupt from Bluetooth Sequencer UART receiver
Table RegIrqEnHig register
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RegIrqEnMid EnUartTx EnUartRx EnPa5 EnPa4 En1Hz EnWakeUp EnPa1 EnPa0
Reset
Function enable interrupt from application UART transmitter enable interrupt from application UART receiver enable interrupt from port PA[5] enable interrupt from port PA[4] enable interrupt from ck1Hz prescaler output enable interrupt from WAKEUP enable interrupt from port PA[1] enable interrupt from port PA[0]
Table RegIrqEnMid register
RegIrqEnLow EnPa7 EnPa6 EnCntB EnCntD EnPa3 EnPa2 EnUartHFlowControl EnUartFlowControl
Reset
Function interrupt from port PA[7] interrupt from port PA[6] interrupt from counter enable interrupt from counter enable interrupt from port PA[3] enable interrupt from port PA[2] enable interrupt from Bluetooth Sequencer UART flow control enable interrupt from application UART flow control
Table RegIrqEnLow register
RegIrqPriority IrqPriority
Reset 11111111
Function Number highest priority interrupt
Table RegIrqPriority register
RegIrqIrq HighIrqTriggered MidIrqTriggered LowIrqTriggered
Reset 00000
Function reserved more high priority interrupt have been triggered more priority interrupt have been triggered more priority interrupt have been triggered
Table RegIrqIrq
3.6.3 Operation XE1431 supports sources interrupt, divided into levels priority: high sources interrupt), middle sources interrupt), sources interrupt). sources interrupt sampled highest frequency available system. interrupt generated memorized when interrupt source triggered. three levels priority directly mapped those supported CoolRISC (IN0, IN2; CoolRISC documentation more information interrupt processing). RegIrqHig, RegIrqMid, RegIrqLow 8-bit registers containing flags interrupt sources. Those flags when interrupt enabled (i.e. corresponding registers RegIrqEnHig, RegIrqEnMid RegIrqEnLow set) rising edge detected corresponding interrupt source. Once memorized, interrupt flag cleared writing corresponding RegIrqHig, RegIrqMid RegIrqLow. Writing does modify flag. definitively clear interrupt, clear CoolRISC interrupt CoolRISC status register addition cleaning corresponding RegIrq register. interrupts automatically cleared after reset.
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registers provided facilitate writing interrupt service software. RegIrqPriority contains number highest priority (its value 0xFF when interrupt memorized). RegIrqIrq indicates priority level current interrupts.
3.7.1 3.7.2
EVENT CONTROLLER Features Supports sources events levels priority Register Address (Hex) 0x003C 0x003D 0x003E 0x003F
Table Event controller registers
Name RegEvn RegEvnEn RegEvnPriority RegEvnEvn
RegEvn CntA CntC CntB CntD
Reset
Function event from counter (high priority) event from counter (high priority) reserved event from port PA[1] (high priority) event from counter (low priority) event from counter (low priority) event from ck1Hz prescaler output event from port PA[0]
Table RegEvn register
RegEvnEn EnCntA EnCntC EnPa1 EnCntB EnCntD En1Hz EnPa0
Reset
Function enable event from counter (high priority) enable event from counter (high priority) reserved enable event from port PA[1] (high priority) enable event from counter (low priority) enable event from counter (low priority) enable event from ck1Hz prescaler output enable event from port PA[0]
Table RegEvnEn register
RegEvnPriority EvnPriority
Reset 00000000
Function number highest event triggered
Table RegEvnPriority register
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RegEvnEvn EvnHigh EvnLow
Reset 000000
Function reserved more high priority event have been triggered more priority event have been triggered
Table RegEvnEvn register
3.7.3 Operation XE1431 supports event sources, divided into levels priority. sources event sampled highest frequency available system. event generated memorized when event becomes source triggered. sources event divided into levels priority: High sources event) sources event). Those levels priority directly mapped those supported CoolRISC (EV0 EV1; CoolRISC documentation more information event processing). RegEvn 8-bit register containing flags sources event. Those flags when event enabled (i.e. corresponding registers RegEvnEn set) rising edge detected corresponding event source. Once memorized, writing corresponding RegEvn clears event flag. Writing does modify flag. events automatically cleared after reset. registers provided facilitate writing interrupt service software. RegEvnPriority contains number highest event (its value 0xFF when event memorized). RegEvnEvn indicates priority level current pending events.
3.8.1 3.8.2
DIGITAL INPUT PORT PA[7:0] Features Input port, 8-bit wide Each programmed individually debounced direct input, with pull-up Snap-to-rail option each input Each configured source interrupt rising falling edge system reset generated input pattern PA[0] PA[1] configured generate events PA[0] PA[3] used clock inputs counters/timers/PWM Register Address (Hex) 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027
Table registers
Name RegPAIn RegPADebounce RegPAEdge RegPAPullup RegPARes0 RegPARes1 RegPACtrl RegPASnapToRail
RegPAIn PAIn
Reset xxxxxxxx
Function value pads PA[7:0]
Table RegPAIn register
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RegPADebounce PADebounce
Reset 00000000
Function debouncer enabled (for each corresponding pad) =debouncer disabled (for each corresponding pad)
Table RegPADebounce register
RegPAEdge PAEdge
Reset 00000000
Function positive edge (for each corresponding pad) negative edge (for each corresponding pad)
Table RegPAEdge register
RegPAPullup PAPullup
Reset 11111111
Function pull-up enabled (for each corresponding pad) pull-up disabled (for each corresponding pad) Function each corresponding pad: reset configuration (see 3.8.9)
Table RegPAPullup register
RegPARes0 PARes0
Reset 00000000
Table RegPARes0 register
RegPARes1 PARes1
Reset 00000000
Function each corresponding pad: reset configuration (see 3.8.9)
Table RegPARes1 register
RegPACtrl DebounceSelect
Reset 0000000
Function reserved fast debounce clock selected slow debounce clock selected
Table RegPACtrl register
RegPASnapToRail SnapToRail
Reset 00000000
Function snap-to-rail mode enabled (for each corresp pad) =snap-to-rail mode disabled (for each corresp pad)
Table RegPASnapToRail register
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3.8.3 Block diagram Figure shows block diagram port
VDDIO_DIG
Port
logic debounce RegPASnapToRail RegPAPullup RegPADebounce DebFast (RegPACtrl(0)) RegPACtrl RegPAIn RegPAEdge interrupts events cntclocks Slow (1kHz) Fast (32kHz) RegPARes1 RegPARes0
resetfromporta
Figure Structure PA[7:0]
3.8.4 Debounce mode Each port individually debounced setting corresponding RegPADebounce. After reset, debounce function disabled. After enabling debouncer, change input value accepted only eight consecutive samples identical. Selection clock done DebounceSelect register RegPACtrl. DebounceSelect Debounce filter clock slow (ck1kHz prescaler output) Fast (ck32kHz prescaler output)
Table Debouncer clock selection
3.8.5 Pull-ups/Snap-to-rail Different functions possible depending value registers RegPAPullup RegPASnapToRail. When corresponding RegPAPullup cleared, inputs floating (pull-up pull-down resistors disconnected). When corresponding bits RegPAPullup cleared RegPASnapToRail pullup resistor connected input pin. Alternatively, when corresponding bits cleared RegPAPullup RegPASnapToRail, snap-to-rail function active. snap-to-rail function connects pull-up pull-down resistor input depending value last forced input pin. This function used instance when input port connected tri-state bus. When floating, pull-up pull-down maintains last impedance state before became floating until another impedance output drives bus. also reduces power consumption with respect classic pull-up since selects pull-up pull-down resistor that matches detected input state.
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state input summarized Table RegPAPullup[i] RegPASnapToRail[i] Last externally forced PA[i] value PA[i] pull none (floating) pull-up pull-down pull-up
Table state RegPAPullup RegPASnapToRail registers
port starts with pull-up resistor connected snap-to-rail function disabled. 3.8.6 Interrupt sources Every port input interrupt source which enabled rising falling edge with corresponding RegPAEdge. After reset, rising edge selected interrupt generation. interrupt source debounced setting register RegPADebounce. interrupt signals sampled fastest clock circuit. order guarantee that interrupt detected circuit, minimal pulse length should cycle this clock. Care must taken when modifying RegPAEdge because this register performs edge selection. change this register result transition which interpreted valid interruption corresponding interrupt sources temporarily disabled interrupt controller. 3.8.7 Event sources Pins PA[0] PA[1] also available events event controller. 3.8.8 Clock sources PA[0] PA[3] input ports (debounced not) available clock sources counter/timer/PWM peripherals.
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3.8.9 Reset sources port configured generate system reset when predetermined word detected PA[7:0]. reset built using logical PAReset[i] signals: resetfromportA PAReset[7] PAReset[6] PAReset[5] PAReset[0] PAReset[i] itself logical function corresponding PA[i]. four logical functions selected each writing into registers RegPARes0 RegPARes1 shown Table PARes1[i] PARes0[x]
Table PAReset generation
PAReset[i] PA[i] PA[i]
reset from port inhibited placing both PARes1[i] PARes0[i] least pin. Setting both RegPARes1[i] RegPARes0[i] makes reset independent value corresponding pin. Setting both registers 0xff, will reset circuit independently input value. This makes possible generate software reset. Depending value PA[0] PA[7], change RegPARes0 RegPARes1 cause reset. Therefore safe always have (RegPARes0[i], RegPARes1[i]) equal 0x00 during setting operations.
3.9.1 3.9.2
DIGITAL INPUT/OUTPUT PORT PB[7:0] Features 8-bit wide input/output port Each configured input output Each configured open-drain push-pull pull-up enabled each open-drain mode, pull-up active when corresponding zero internal freq. (ck32kHz CkCpu) output PB[2] PB[3] signals driven pads PB[0] PB[1] UART interface uses PB[7:4] UA_RX, UA_TX, UA_RTS UA_CTS respectively Register Address (Hex) 0x0028 0x0029 0x002A 0x002B 0x002C
Table port registers
Name RegPBOut RegPBIn RegPBDir RegPBOpen RegPBPullup
RegPBout PBOut
Reset 00000000
Function port output value
Table RegPBOut register
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RegPBIn PBIn Reset xxxxxxxx Function input value, read from pads PB[7:0]
Table RegPBIn register
RegPBDir PBDir
Reset 00000000
Function each corresponding pad: configured digital output configured digital input
Table RegPBDir register
RegPBOpen PBOpen
Reset 00000000
Function each corresponding pad: configured open drain configured push-pull
Table RegPBOpen register
RegPBPullup PBPullup
Reset 11111111
Function each corresponding pad: pull-up enabled pull-up disabled
Table RegPBPullup
3.9.3 Multiplexing with other peripherals Port acts GPIO port default. This functionality overridden other functions enabled shown Table Port number Priority Medium UA_RX UA_TX UA_RTS UA_CTS ck32k clock counter (C+D) PWM1 counter (A+B) PWM0
Table PB[7:0] usage
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
When counters used implement function (see 3.10), PB[0] PB[1] terminals used outputs (PB[0] used RegCntConfig1 PB[1] used RegCntConfig1 generated values override values written RegPBout. However, RegPBDir[0] RegPBDir[1] automatically overwritten have RegSysMisc, ck32kHz prescaler output output PB[3]. This overrides value contained RegPBOut[3]. However, RegPBDir[3] must frequency duty cycle clock signal given Figure
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1/fckRCext 1/fck32kHz
Figure ck32k output clock timing
Similarly, RegSysMisc, clock output PB[2] described Figure This overrides value contained RegPBOut[2]. However, RegPBDir[2] must
1/f1 1/f2
Figure output clock timing
timing clock depends selection CpuSel RegSysClock register given Table CpuSel fckRCext/4 fckRCext
Table clock PB[2] timing
fckRCext fck32kHz
3.9.4 Port digital capabilities direction each within PB[7:0] (input only input/output) individually using RegPBDir register. RegPBDir[i] both input output buffers active corresponding pin. RegPBDir[i] corresponding input only output buffer high impedance. After reset input only mode; RegPBDir[i] reset input values available RegPBIn (read only). Reading always direct there debounce function. case possible noise input signals, software debouncer with polling external hardware filter realized. input buffer also active when port defined output allows reading back effective value pin. Data stored RegPBOut output Port RegPBDir[x] default value after reset (0). When output mode (RegPBDir[i] set), output conventional CMOS (Push-Pull) Nchannel Open-drain, driving output low. default, after reset RegPBOpen cleared (push-pull). RegPBOpen[i] internal P-channel transistor output buffer electrically removed output only driven with RegPBOut[i] cleared, high-impedance when RegPBOut[i] set. internal pull-up external pull-up resistor used drive high. Because P-channel transistor actually exists (this real Open-drain output) pull-up range limited VDDIO_DIG 0.2V (avoid forward bias transistor diode). optional pull-up connected every configuring RegPBPullup. Input pulled when corresponding this register set. Default status after reset which means with pull-up. limit power consumption, pull-up resistors only enabled when associated either digital input N-channel opendrain output with (n-channel transistor disabled). other cases (push-pull output open-drain output driven low), pull resistors disabled independently from RegPBPullup. After power-on reset, Port configured input port with pull-up activated. input buffer always active. This means that input should valid digital value time. unused should configured input pull-up output. Violating this rule lead high power consumption.
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3.10 COUNTERS/TIMERS 3.10.1 3.10.2 Features 8-bits timer/counter modules 16-bits timers/counter modules, each with possible clock sources Up/down counter modes Interrupt event generation Capture function (internal external source) Rising, falling both edge capture signal (except ck32k, only rising edge) PA[3:0] used clock inputs (debounced direct, frequency divided not) bits bits resolution bits Complex mode combinations possible Register Address (Hex) 0x0058 0x0059 0x005A 0x005B 0x005C 0x005D 0x005E 0x005F
Table Counter Registers
Name RegCntA RegCntB RegCntC RegCntD RegCntCtrlCk RegCntConfig1 RegCntConfig2 RegCntOn
RegCntA CntA
Reset 00000000
Function counter
Table RegCntA register
RegCntB CntB
Reset 00000000
Function counter
Table RegCntB registers
RegCntC CntC
Reset 00000000
Function counter
Table RegCntC register
RegCntD CntD
Reset 00000000
Function counter
Table RegCntD register
RegCntCtrlCk CntDCkSel CntCCkSel CntBCkSel CntACkSel
Reset
Function counter clock selection counter clock selection counter clock selection counter clock selection
Table RegCntCtrlCk register
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RegCntConfig1 CntDDownUp CntCDownUp CntBDownUp CntADownUp CascadeCD CascadeAB CntPWM1 CntPWM0
Reset
Function counter counting counter counting down counter counting counter counting down counter counting counter counting down counter counting counter counting down cascade counters cascade counters cascade counter cascade counters counter enabled counter disabled counter enabled counter disabled
Table RegCntConfig1 register
RegCntConfig2 CapSel CaptFunc Pwm1Size Pwm0Size
Reset
Function capture source selection capture function selection PWM1 size selection PWM0 size selection
Table RegCntConfig2 register
RegCntOn CntDExtDiv CntCExtDiv CntBExtDiv CntAExtDiv CntDEnable CntCEnable CntBEnable CntAEnable
Reset
Function divide external clock PA[3] divide divide external clock PA[2] divide divide external clock PA[1] divide divide external clock PA[0] divide counter enabled counter disabled counter enabled counter disabled counter enabled counter disabled counter enabled counter disabled
When writing RegCntA RegCntB, processor writes counter comparison values. When reading these locations, processor reads back either actual counter value last captured value capture mode active. When writing RegCntC RegCntD, processor writes counter comparison values. When reading these locations, processor reads back actual counter value. Table RegCntOn register
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3.10.3 General Operation Overview Counter Counter 8-bit counters which cascaded form 16-bit counters. Counter Counter have same features. counters also used generate outputs PB[0] PB[1]. signals generated with 10-, 12-, 16-bit precision. Counters captured events internal external signal. capture performed both 8-bit counters running individually different clock sources both cascaded counters form 16-bit counter. case, same capture signal used both counters. When counters cascaded, they used several configurations: counters, captured counters, counter, captured counter. When counters cascaded, both used either counters counter counter counter. Counters enabled RegCntOn. When counters cascaded, CntBEnable controls counter CntDEnable controls counter counters have corresponding 8-bit read/write register: RegCntA, RegCntB, RegCntC, RegCntD. When read, these registers contain counter value captured counter value). When written, they modify counter comparison values. possible read counter time, even when counter running. value guaranteed correct when counter running internal clock source. correct acquisition counter value when running external clock source, three following methods: slow operating counters (typically least times slower than clock), over-sample counter content perform majority operation consecutive read results select correct actual content counter. Stop concerned counter, perform read operation restart counter. While stopped, counter content frozen counter does take into account clock edges delivered external pin. capture mechanism.
When value written into counter register while counter counter mode, both comparison value updated counter value modified. upcount mode, register value reset zero. downcount mode, comparison value loaded into counter. synchronization mechanism between processor clock domain external clock source domain, this modification counter value postponed until counter enabled receives first valid clock edge. mode capture mode, counter value modified write operation counter register. Changing counter mode does update counter value reset upcount, load downcount mode). 3.10.4 Clock selection clock source each counter individually selected writing appropriate value register RegCntCtrlCk. Table gives correspondence between binary codes used configuration bits RegCntCtrlCk[1:0], RegCntCtrlCk[3:2], RegCntCtrlCk[5:4] RegCntCtrlCk[7:6] clock source selected respectively counters RegCntCtrlCk[i:j] Clock source Counter Counter timer from clock controller ckRCext ckRCext PA[0] PA[1] Counter Counter
ck1kHz prescaler output ck32kHz prescaler output PA[2] PA[3]
Table Counter clock selection
chapter details about different clock sources. Four external clocks provided counters through pins PA[3:0]. Optionally, external clock sources debounced configuring port Additionally, external clocks divided configuring RegCntOn[7:4].
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Switching between internal external clock source only performed while counter stopped. Enabling disabling external clock frequency division only happen when counter using this clock stopped, when this counter running internal clock source. 3.10.5 Mode selection Each counter configured following modes: Counter Capture Captured counter mode writing registers RegCntConfig1 RegCntConfig2. RegCntConfig1 RegCntConfig1
RegCntConfig2 [5:4]
Counter mode
Counter mode
Counter source Counter Counter Capture Capture Capture Capture
Counter source Counter Counter Capture Capture Capture Capture
PB[0] function PB[0] PB[0] PB[0] PB[0]
Counter Counter Downup: Downup: Counter Downup: Counter Downup: Downup: Downup Captured Captured counter counter Downup: Downup: Captured counter Downup: Captured Captured counter Downup: Downup: Captured (captured value 16b) Downup:
Table Counters operation modes
Switching between different modes must done while concerned counters stopped. While switching capture mode off, unwanted interrupts appear interrupt channels concerned this mode change. Table shows operation modes counters function mode control bits. RegCntConfig1 Counter Counter mode mode Counter Counter Downup: Downup: Counter Downup: Counter Downup: Downup: Downup: Counter source Counter Counter Counter source Counter Counter PB[1] function PB(1) PB(1)
Table Counters C&D: operation modes
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3.10.6 Counter Timer mode counters counter timer mode used generate interrupts after predefined number clock periods applied counter clock input have elapsed. Each counter individually either upcount mode setting register RegCntConfig1 downcount mode resetting these bit. Counters cascaded behave 16-bit counter setting RegCntConfig1[2]. Counters also cascaded setting RegCntConfig1[3]. When cascaded, up/down count modes counters defined respectively up/down count modes counters When upcount mode, counter will start incrementing from zero target value which been written corresponding RegCntX register(s). When counter content equal target value, interrupt generated next counter clock pulse counter loaded again with zero value described Figure When downcount mode, counter will start counting down from initial load value which been written corresponding RegCntX register(s) down zero value. Once counter content equal zero, interrupt generated next counter clock pulse counter loaded again with load value described Figure counter must configured (capture, PWM, cascade, up/down counting mode) before writing target value RegCntX register(s). This ensures that counter will start from correct initial value. When counters cascaded, both counter registers must written ensure that both cascaded counters will start from correct initial values. Stopping restarting counter counter mode without reloading target load value write generate unwanted interrupt this counter been stopped zero value (downcount) target value (upcount). This interrupt already been generated when counter reached zero target value.
down counting
clock counter RegCntX_r RegCntX_w write RegCntX RegCntConfig1 (bit IrqX RegCntOn (bit
counting
clock counter RegCntX_r RegCntX_w write RegCntX RegCntConfig1 IrqX RegCntOn (bit (bit
Figure down count interrupt generation
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3.10.7 mode counters generate signals (Pulse Width Modulation) port outputs PB[0] PB[1]. mode selected setting RegCntConfig1[0] RegCntConfig1[1] bit. When RegCntConfig1[0] set, PWMA PWMAB output value overrides value RegPBOut[0]. When RegCntConfig1[1] enabled, PWMC PWMCD output value overrides value RegPBOut[1]. corresponding ports and/or must configured digital output. Counters mode count down according RegCntConfig1[7:4] setting. interrupts events generated counters which this mode. Counters count circularly: they restart zero maximal value (0xFF when cascaded 0xFFFF when cascaded) when respectively overflow underflow condition occurs. internal signals long counter contents higher than code values written RegCntX registers. They high when counter contents smaller equal these code values. order have glitch free outputs, outputs PB[0] PB[1] sampled versions these internal signals, therefore delayed counter clock cycle. resolution always bits when single counter used signal generation. RegCntConfig2 register used resolution counters respectively when they cascaded mode. different possible resolutions cascaded mode shown Table resolution. Choosing 16bit code which higher than maximum value results output always tied maximum value resolution RegCntConfig2[1:0] RegCntConfig2[3:2] Resolution bits bits bits bits
Table resolution
Small code Tlsmall Large code Tllarge Thlarge Tper Thsmall
Figure modulation examples
period Tper signal given formula:
duty cycle ratio signal defined
resolution ckcnt
where time during which output "high" within Tper
selected between
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function RegCntX content(s) given relation:
RegCntX ,100 resolution
3.10.8 Counter capture function 16-bit capture register provided facilitate frequency measurements. provides safe reading mechanism counters when they running. When capture function active, processor does read counters directly anymore, instead reads shadow registers located capture block. interrupt generated after capture condition been when shadow register content updated. capture condition user defined selecting either internal capture signal sources derived from prescaler from external PA[2] PA[3] ports. Both counters same capture condition. When capture function active, counters either upcount downcount. They count circularly: they restart zero maximal value (either 0xFF when cascaded 0xFFFF when cascaded) when respectively overflow underflow condition occurs counting. capture function also active counters when used generate signals. bits RegCntConfig2[5:4] determine capture function enabled selects which edges capture signal source valid capture operation. source capture signal selected setting RegCntConfig2[7:6] bits. sources; rising, falling both, edge sensitivity selected. Table shows capture condition function setting these configuration bits. RegCntConfig2[7:6] Selected capture signal RegCntConfig2[5:4]
Table Capture conditions
Selected condition Capture disabled Rising edge Falling edge Both edges Capture disabled Rising edge Falling edge Both edges Capture disabled Rising edge Falling edge Both edges Capture disabled Rising edge Falling edge Both edges
Capture condition rising edge falling edge rising edge falling edge PA[3] rising edge PA[3] falling edge PA[3] both edges PA[2] rising edge PA[2] falling edge PA[2] both edges
bits RegCntConfig2[7:6] RegCntConfig2[5:4] should modified only when counters stopped otherwise data corrupted during counter clock cycle. synchronization mechanism shadow registers depending frequency ratio between capture counter clocks, interrupts generated counter clock pulses after effective capture condition occurred. When counters cascaded operate same clock, counter counter interruptions which inform that capture condition met, appear different instants. this case, processor should read shadow register associated counter only interruption related this counter been detected. edge detected capture signals only minimal pulse widths these signals high states higher than period counter clock source.
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3.11 SERIAL PERIPHERAL INTERFACE (SPI) 3.11.1 3.11.2 Features Full duplex operating mode Master/slave configuration Separate transmit data, shift data, receive data registers order perform back-to-back transmissions. Four programmable baud rates Programmable serial clock polarity phase receive register full interrupt Overflow detection flag pads which configured GPIO. Support slaves devices Content serial memory connected NSS[0] automatically loaded upon reset Register Address (Hex) 0x0068 0x0069 0x006A 0x006B 0x006C 0x006D
Table registers
Name RegSpiControl RegSpiStatus RegSpiDataOut RegSpiDataIn RegSpiPullup RegSpiDir
RegSpiControl ClearCounter NotSlaveSelect SpiMaster SpiEnable ClockPhase ClockPolarity BaudRate
Reset
Function clear control counters master mode: drives NSS[0] pin. must during byte transfer. slave mode: unused master mode selected slave mode selected mode GPIO mode clock phase clock polarity master mode: baud rate selection ckRCext/2 ckRCext/8 ckRCext/16 ck4kHz slave mode: unused
Table RegSpiControl register
RegSpiStatus SpiOverflow SpiRxFull SpiTxEmpty
Reset 00000
Function reserved Overflow flag. Cleared when written byte been received available receive register. This flag cleared when reading RegSpiDataIn. transmit register empty transfer initiated. flag cleared when writing RegSpiDataOut.
Table RegSpiStatus register
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RegSpiDataOut SPIDataOut
Reset 00000000
Function mode: byte transmit GPIO mode: value forced pads configured digital outputs
Table RegSpiDataOut register
RegSpiDataIn SPIDataIn
Reset 00000000
Function mode: received byte GPIO mode: value read pads
Table RegSpiDataIn register
RegSpiPullup SPIPullup
Reset 11111111
Function pull-up enabled (for each corresponding pad) pull-up disabled (for each corresponding pad)
Table RegSpiPullup register
RegSpiDir SPIDir[7:4] SPIDir[3:0]
Reset 0000 0000
Function each corresponding pad: configured digital output configured digital input GPIO mode, each corresponding pad: configured digital output configured digital input
Table RegSpiDir register
3.11.3 Operation peripheral operates modes: GPIO. mode selected SpiEnable register RegSpiCtrl. Selecting mode only affects pins SCK, MOSI, MISO, NSS[0]. pins NSS[4:1] always configured GPIO. mode, serial clock. generated chip master mode frequency chosen field BaudRate RegSpiCtrl described Table master mode, SpiMaster XE1431 master. slave mode, SpiMaster master should always limit frequency ckRCext/2) Figure shows connect devices interface. slave connected NSS[0] boot device. program read from reset. Others slaves connected described Figure ClearCounter RegSpiCtrl used synchronization with slave lost, re-initialize communication. SpiRxFull flag RegSpiStatus used interrupt source interrupt controller block.
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XE1431
MOSI MISO NSS[0] NSS[1]
SS_n
Boot flash
SS_n
Other device
Figure Connecting devices
Figure shows timing diagrams transmission with clock phase equal (the active state serial clock signal occurs half cycle).
Figure transmission format with clock phase equal
Figure shows timing diagrams transmission with clock phase equal (the active state serial clock signal occurs half cycle).
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Figure transmission format with clock phase equal
3.11.4
Software hints
3.11.4.1 Master mode Initialization configured master mode reset. Clock phase, clock polarity, baud rate changed writing RegSpiControl. SpiMaster SpiEnable RegSpiControl. Byte transfer De-assert NSS[0] clearing NotSlaveSelect RegSpiControl Check that transmit buffer empty (SpiTxEmpty RegSpiStatus) Fetch with data transmitted. data written RegSpiDataOut Trigger transmission writing value RegSpiStatus Wait until receive buffer full (SpiRxFull RegSpiStatus) received data read from RegSpiDataIn Assert NSS[0] setting NotSlaveSelect RegSpiControl 3.11.4.2 Slave mode Initialization SpiEnable SpiMaster cleared RegSpiControl. Clock phase, clock polarity, baud rate changed writing RegSpiControl. Byte transfer Wait until receive buffer full (SpiRxFull RegSpiStatus) Read received data from RegSpiDataIn Fetch with data transmitted. data written RegSpiDataOut
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3.11.5 Pins Table summarizes pins usage either GPIO mode. name MISO MOSI NSS[0] NSS[1] NSS[2] NSS[3] NSS[4] Function serial clock master-in, slave-out master-out, slave-in slave select (active low) digital with selectable pull-up digital with selectable pull-up digital with selectable pull-up digital with selectable pull-up number registers
GPIO digital with selectable pull-up digital with selectable pull-up digital with selectable pull-up digital with selectable pull-up digital with selectable pull-up digital with selectable pull-up digital with selectable pull-up digital with selectable pull-up
Table pins
3.12 APPLICATION UART 3.12.1 Features Full duplex operation with buffered 8-byte FIFO receiver transmitter. Internal baud rate generator with programmable baud rates. bits word length. Even, odd, no-parity generation detection stop Error receive detection: Start, Parity, Frame Overrun Receiver echo mode Three interrupts (receive: data ready, FIFO threshold. Transmit: FIFO empty) Enable receive and/or transmit Invert and/or Flow control (RTS CTS)
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3.12.2
Registers Address (Hex) 0x0030 0x0031 0x0032 0x0033 0x0034 0x0035 0x0036
Table UART registers
Name RegUartFifoCtrl RegUartFifoBaud RegUartFifoTx RegUartFifoTxSta RegUartFifoRx RegUartFifoRxSta RegUartFifoMisc
RegUartFifoCtrl UartEcho UartEnRx UartEnTx UartXRx UartXTx UartPM UartPE UartWL
Reset
Function echo mode selected (UA_RX UA_TX internally connected) echo mode selected receiver enabled receiver disabled transmitter enabled transmitter disabled UA_RX inverted UA_RX inverted UA_TX inverted UA_TX inverted parity check selected even parity check selected parity check enabled parity check disabled 8-bit word selected 7-bit work selected
Table RegUartFifoCtrl register
RegUartFifoBaud UartRcSel UArtRcDiv
Reset 00000
Function prescaler selection baud rate selection
Table RegUartFifoBaud register
RegUartFifoTx UartTx
Reset 00000000
Function data sent
Table RegUartFifoTx
RegUartFifoTxSta UartTxFifoOerr UartTxFifoFull UartTxBusy UartTxFifoEmpty UartTxClear
Reset
Function reserved value transmitters overrun error flag. Cleared reading RegUartFifoTxSta transmit FIFO full flag transmitter busy transmitting data transmit FIFO empty flag. Cleared writing RegUartFifoTx. when transferring last data word from FIFO internal shift register. clear transmitter block when written
Table RegUartFifoTxSta register
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RegUartFifoRx UartRx
Reset 00000000
Function received data
Table RegUartFifoRx register
RegUartFifoRxSta UartRxFifoFull UartRxSErr UartRxPErr UartRxFErr UartRxFifoOErr UartRxBusy UartRxDataReady UartRxClear
Reset
Function reserved receive FIFO full flag start error flag parity error flag frame error flag overrun error flag. Cleared reading RegUartFifoRxSta uart receiver busy flag data available receive FIFO. Cleared reading data FIFO. clear receiver block when written
Table RegUartFifoRxSta
RegUartFifoMisc RtsMonitorMode RtsLevelMode
Reset
Sel32k UartFlowCtrl
Function reserved during monitor mode force during monitor mode rises when only bytes left FIFO falls when FIFO empty rises when only bytes left FIFO falls when more than bytes left FIFO. input clock ck32kHz prescaler output input clock ckRCext,. enable flow control disable flow control reserved
Table RegUartFifoMisc register
3.12.3 Block diagram UART Universal Asynchronous Receiver Transmitter interface with separated receive transmit 8-byte FIFO, fully automatic flow control.
Receiver FIFO
UA_RX Control Registers UART Prescaler UA_TX Transmitter FIFO
Figure UART block diagram
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3.12.4 Configuration configuration bits UART found registers RegUartFifoBaud, RegUartFifoCtrl RegUartFifoMisc. bits UartEnRx UartEnTx used enable disable reception transmission. word length data bits) chosen with UartWL. parity added during transmission checked during reception UartPE set. parity mode (odd even) chosen with UartPM. Setting bits UartXRx UartXTx respectively inverts UA_RX UA_TX signals. UartEcho automatically sends back received data. transmission function becomes then UA_TX UA_RX UartXRx UartXTx. UartEnRx UartEnTx must echo mode. bits UartFlowCtrl, RtsLevelMode RtsMonitorMode used control flow through pins described paragraph 3.12.8. 3.12.5 Baud rates UART interface clocked ckRCext when Sel32k cleared. UartRcSel UartRcDiv select baud rate. relation between baudrate ckRCext clock frequency given
Baudrate
ckRCext factorUartRcSel factorUartRcDiv
Equation Baudrate ckRCext
FactorUartRcSel prescaler selection bits UartRcSel RegUartFifoBaud factorUartRcDiv division bits UartRcDiv RegUartFifoBaud. values these factors given Table Table With frequency clock, highest baudrate kbit/s. clock dispersion, digital frequency lock loop (DFLL) must used calibrate before using clock source. UartRcSel factorUartRcSel
Table Division factor UartRcSel
UartRcDiv 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010
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UartRcDiv 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 factorUartRcDiv
Table Division factor UartRcDiv
ck32kHz prescaler output selected UART clock source Sel32k RegUartFifoCtrl set. baud rate selection follows Equation
Baudrate
factorUartRcDiv
Equation Baudrate ck32kHz
Ck32kHz generated from SLW_CLOCK_IN high prescaler input described 3.5.8.2. Table shows baud rate precision when SLW_CLOCK_IN selected. UartRcDiv 0000 0001 0011 0111 Baud rate (Bd/s) 2400 1200 SLW_CLOCK_IN frequency 32'000 32'768
Table Baud rate selection (Sel32k EnableSwClock
3.12.6 Transmission transmitter enabled setting UartEnTx. Data sent have written transmit FIFO through register RegUartFifoTx. transmitter loads sends data automatically, long transmission FIFO empty (bit UartTxFifoEmpty value When transmit FIFO empty, UartTxFifoEmpty returns interrupt generated. UartTxFifoFull RegUartFifoTxSta indicates that transmit FIFO full. data written FIFO while full, UartTxFifoOerr last data ignored. UartTxFifoOerr cleared when register RegUartFifoTxSta read. UartTxBusy RegUartFifoTxSta shows that transmitter busy transmitting word.
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Writing RegUartFifoTxSta resets transmitter block. Data FIFO that were transmitted lost. flags RegUartFifoTxSta reset. Figure Figure show UART transmission. figures drawn with FIFO depth simplification, although FIFO depth
write RegUartFifoTx TxFifo(1) TxFifo(0) CTSn shift enable UartTxFifoEmpty UartTxBusy IrqTxEmpty
word1
start
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
parity
stop
Figure Uart transmission timing diagram with FIFO depth
write RegUartFifoTx TxFifo(1) TxFifo(0) CTSn shift enable UartTxFifoEmpty UartTxFifoFull UartTxBusy IrqTxEmpty
word2 word1 word2
start
bit0
bit1
bit7
parity
stop start
bit0
bit1
bit7
parity stop
Figure Uart transmission timing diagram back back with FIFO depth
3.12.7 Reception detection start bit, UartRxBusy set. detection stop bit, received data flags transferred from internal shift register receive FIFO. same time, UartRxDataReady interrupts RxDataReady RxComp updated. UartRxDataReady long data present FIFO read software. interrupt RxDataReady generated each time when data written FIFO. interrupt RxComp generated when only free data words left reception FIFO. flags register RegUartFifoRxSta give status next word read reception FIFO. Therefore, order know status received data, RegUartFifoRxSta read before reading actual data RegUartFifoRx. Each data word reception FIFO three flags associated UartRxSErr, UartRxPErr UartRxFErr. UartRxSErr start error been detected. UartRxPErr parity error been detected, i.e. received parity equal calculated parity received data. UartRxFErr shows that frame error been detected: stop been detected. UartRxFifoFull when receive FIFO full. FIFO full data transferred from shift register FIFO, UartRxFifoOErr (overflow error) data lost. Reading RegUartFifoRxSta clears UartRxFifoOErr. Writing data RegUartFifoRxSta resets reception block: flags RegUartFifoRxSta reset data reception FIFO that were read software lost. used flow control. While reception FIFO reached threshold level, set. cleared soon software reads data reception FIFO depending RtsLevelMode.
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Figure shows timing diagram possible reception. this example, depth FIFO RTS1 shows functionality when RtsLevelMode RTS2 when RtsLevelMode actual depth FIFO
read RegUartFifoRx RxFifo(3) RxFifo(2) RxFifo(1) RxFifo(0) IrqRxComp shift enable UartRxFifoDataReady UartRxFifoFull UartRxBusy IrqRxDataReady
word2 word1 word2
start
bit0
bit1
bit7
parity
stop start
bit0
bit1
bit7
parity stop
start
Figure Uart reception timing diagram with FIFO depth
3.12.8 Flow control When automatic flow control activated (UartFlowCtrl transmission stops soon signal raised. transmits otherwise long data available transmission. receiver side, signal will automatically driven high antepenultimate byte receive FIFO filled. driven again receive FIFO emptied (RtsLevelMode only bytes left FIFO (RtsLevelMode connecting devices shown Figure transmission overruns avoided device will automatically stop transmitting other receive FIFO gets full. Device
UA_TX UA_RX
Device
UA_RX UA_TX
Figure Connecting devices with flow control
flow control disabled, pins used digital input/output ports. Setting RtsMonitorMode will automatically raise signal chip enters debug mode. This should default prevent loss data.
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3.12.9 Software hints transmission reception software driven interruption polling status bits. 3.12.9.1 Transmission with polling Initialize RegUartFifoBaud RegUartFifoCtrl with communication parameters (for example 8-bit word length, parity, 115200 bauds, enable UART transmission) Write bytes into transmit FIFO (RegUartFifoTx) Wait until UartTxFifoEmpty RegUartFifoTxSta Jump write next bytes message finished transmission 3.12.9.2 Transmission with interrupt Initialize RegUartFifoBaud RegUartFifoCtrl with communication parameters (for example 8-bit word length, parity, 115200 bauds, enable UART transmission) Write bytes into transmit FIFO (RegUartFifoTx) Jump after IrqTxEmpty been triggered, write next bytes message finished transmission 3.12.9.3 Reception with polling Initialize RegUartFifoBaud RegUartFifoCtrl with communication parameters (for example 8-bit word length, parity, 115200 bauds, enable UART reception) Wait until UartRxDataReady UartRxFifoFull RegUartFifoRxSta Check errors RegUartFifoRxSta Read data RegUartFifoRx Repeat until receive FIFO empty (UartRxDataReady Jump 3.12.9.4 Reception with interrupt Initialize RegUartFifoBaud RegUartFifoCtrl with communication parameters (for example 8-bit word length, parity, 115200 bauds, enable UART reception) Wait until IrqRxDataReady triggered Check errors RegUartFifoRxSta Read data RegUartFifoRx Repeat until receive FIFO empty (UartRxDataReady Jump
3.13 BLUETOOTH SEQUENCER INTERFACE 3.13.1 Features Fully embedded qualified ROM-based implementation lower layers Bluetooth protocol stack Compliant with Revision Bluetooth specification Embedded CVSD audio compression Direct interface with audio codec Direct interface with radio chip seven slaves audio-link Supports point-to-point, piconet, scatternet networks
3.13.2 Overview Bluetooth sequencer implements Bluetooth specific hardware lower layers protocol stack. lower layers handle time-critical hardware-dependant tasks that must disturbed application. qualified dedicated ROM-based coprocessor, Bluetooth sequencer isolates lower layers from application. consequence, debug qualification time dramatically decreased.
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Host Controller Interface (HCI) been specified into Bluetooth protocol standardized interface between lower upper layers. upper layers pieces software implemented host processor communicating with Bluetooth sequencer though HCI. commands carried internal UART link between host processor Bluetooth sequencer. Bluetooth specific commands usually embedded into abstraction layers upper layers Bluetooth stack, that programmer only deals with common services (e.g. serial port emulation, Full Bluetooth stacks from various vendors have been successfully ported XE1431.
Application
Upper layers (RFCom, L2CAP,
(hosted) CoolRISC
(embedded)
Link Manager
Link Controller
Radio chip XE1413
Radio Interface
Codec Interface
Bluetooth Sequencer XE1431
Figure XE1431 Bluetooth stack implementation
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3.13.3 Link Controller Features Link Controller supports features described Table Link Controller Feature links links Packet formatting Control packets (ID, NULL, POLL, FHS) Voice packets (HV1, HV2, HV3) Mixed voice-data packets (DV) Single-slot data packets (DM1, DH1, AUX1) Multi-slots data packets (DM3, DH3, DM5, DH5) Page page scan (mandatory page mode) Inquiry inquiry scan Broadcasting messages Sniff mode Hold mode Park mode Single piconet point-to-point operation (master slave) Single piconet operation (master with multiple slaves) Master-Slave switch Scatternet operation (master piconet slave another) CVSD compression support (linear) from CODEC (internal external) Voice channel channel) Bluetooth test mode (standard)
Table Link controller features
Supported
3.13.4 Link Manager Features Table shows supported Link Manager (LM) features. Link Manager Feature Encryption Encryption size Clock offset request Slot offset information Master-slave switch Hold mode Sniff mode Park mode Power control
Table Link manager features
Supported
3.13.5 Standard Host Controller Interface (HCI) Commands table contains messages understood Link Manager XE1431. detailed description command parameters found specification Bluetooth Specification [1]. following Host Controller Interface Commands (HCI) supported XE1431. command ChangeConnectionLinkKey
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Type Command Complete Event Status Event
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command ChangeLocalName ChangeLocalNameCompleteEvt CreateNewUnitKey CreateNewUnitKeyCompleteEvt DataBufferOverflowEvt DeleteStoredLinkKey DeleteStoredLinkKeyCompleteEvt EnableDeviceUnderTestMode ExitPeriodicInquiryMode HostBufferSize HostBufferSizeCompleteEvt Inquiry InquiryCancel InquiryCancelCompleteEvt InquiryCompleteEvt InquiryStatusEvt LinkKeyNotificationEvt LinkKeyRequestEvt LinkKeyRequestNegativeReply LinkKeyRequestReply LinkKeyRequestReplyCompleteEvt MaxSlotsChangeEvt PeriodicInquiryMode PeriodicInquiryModeCompleteEvt PINCodeRequestEvt PINCodeRequestNegativeReply PINCodeRequestReply PINCodeRequestReplyCompleteEvt ReadClassOfDevice ReadClassOfDeviceCompleteEvt ReadConnectionAcceptTimeout ReadCountryCode ReadCountryCodeCompleteEvt ReadCurrentIACLAP ReadCurrentIACLAPCompleteEvt ReadHoldModeActivity ReadHoldModeActivityCompleteEvt ReadInquiryScanActivity ReadLocalName ReadLocalNameCompleteEvt ReadLocalVersionInformation ReadLoopbackMode ReadLoopbackModeCompleteEvt ReadNumberOfSupportedIAC ReadNumBroadcastRetransmissions
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Type Command Complete Event Command Complete Event Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Command Complete Event Complete Event Status Event Event Event Command Complete Event Command Complete Event Event Command Complete Event Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command
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command ReadPageScanActivity ReadPageScanActivityCompleteEvt ReadPageScanMode ReadPageScanModeCompleteEvt ReadPageScanPeriodMode ReadPageTimeout ReadPageTimeoutCompleteEvt ReadPINType ReadPINTypeCompleteEvt ReadRemoteVersionInformation ReadStoredLinkKey ReadStoredLinkKeyCompleteEvt ReadTransmitPowerLevel ReadVoiceSetting ReadVoiceSettingCompleteEvt RemoteNameRequest RemoteNameRequestCompleteEvt RemoteNameRequestStatusEvt ReturnLinkKeyEvt SetEventFilter SetEventFilterCompleteEvt SetEventMask SetEventMaskCompleteEvt WriteClassOfDevice WriteClassOfDeviceCompleteEvt WriteConnectionAcceptTimeout WriteCurrentIACLAP WriteCurrentIACLAPCompleteEvt WriteHoldModeActivity WriteInquiryScanActivity WriteLoopbackMode WriteLoopbackModeCompleteEvt WritePageScanActivity WritePageScanMode WritePageScanModeCompleteEvt WritePageScanPeriodMode WritePageTimeout WritePageTimeoutCompleteEvt WritePINType WritePINTypeCompleteEvt WriteStoredLinkKey
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Type Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Status Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Status Event Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command Complete Event Command
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command WriteStoredLinkKeyCompleteEvt WriteVoiceSetting WriteVoiceSettingCompleteEvt Type Complete Event Command Complete Event
Table Host Controller Interface Commands
3.13.6 Vendor Specific Commands "EasyBlue Commands" addition standard commands, EasyBlue commands used access XE1431 specific features. Those commands allow reading/writing internal sequencer registers setting BdAddress. 3.13.6.1 Registers Writing Synopsis Command EasyBlue_WriteReg Parameters Parameter Address 0x08 Length Data Status Size bytes byte byte [Length] bytes byte Comment address register (MSB first) fixed Number bytes transfer data 0x00 command succeed 0x3F 0x02 Parameters Address, Length, Data Return parameters Status
Table EasyBlue_WriteReg synopsis
Table EasyBlue_WriteReg parameters
Description This command used write value Bluetooth sequencer registers. 3.13.6.2 Registers Reading Synopsis Command EasyBlue_ReadReg 0x3F 0x01 Parameters Address, Type, Length1 Return parameters Status, Length2, Data
Table EasyBlue_ReadReg synopsis
Parameters Parameter Address 0x08 Length1 Data Status Length2 Size bytes byte byte [Length] bytes byte byte Comment address register (MSB first) fixed Number bytes transfer. data 0x00 command succeed number bytes returned
Table EasyBlue_ReadReg parameters
Description This command used read value from Bluetooth sequencer registers.
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3.13.6.3 Setting Bluetooth Address Synopsis Command EasyBlue_SetBdAddr 0x3F 0x03 Parameters Reserved1, BdAddr, Reserved2 Return parameters Status
Table EasyBlue_SetBdAddr synopsis
Parameters Parameter Reserved1 BdAddr Reserved2 Status Size byte bytes bytes byte Comment 0x00 BdAddr 0x0000000000000000000000 0x00: command succeeded
Table EasyBlue_SetBdAddr parameters
Description This command sets 48-bit unique identifier Bluetooth device. 3.13.7 Radio Interface Table shows connect XE1413 radio chip XE1431. XE1431 name SYS_CLOCK_IN RX_DATA SPI_DATA_IN SLW_CLOCK_IN TX_DATA RX_EN SYNC_DETECT TX_EN SPI_DATA_OUT SPI_CLK_OUT SPI_EN_BAR Location XE1413 name SYS_CLK_OUT RX_DATA SPI_DATA_OUT SLW_CLK_OUT TX_DATA RX_EN SYNC_DETECT TX_EN SPI_DATA_IN SPI_CLK_IN SPI_EN_BAR
Table Connecting XE1431 XE1413
3.13.8 UART host processor communicates with Bluetooth Sequencer through UART identical described paragraph 3.12. register this peripheral given Table 103. Name RegHUartFifoCtrl RegHUartFifoBaud RegHUartFifoTx RegHUartFifoTxSta RegHUartFifoRx RegHUartFifoRxSta RegHUartFifoMisc Address (Hex) 0x0050 0x0051 0x0052 0x0053 0x0054 0x0055 0x0056
Table UART registers
Flow control enabled time UART. Upon start-up reset, UART configured 115'200 kbit/s, bits, parity.
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3.13.9 Bluetooth Sequencer clock source shown paragraph 3.5.9, Bluetooth sequencer clocked SYS_CLOCK_OUT SLW_CLOCK_OUT. Both must fulfill Bluetooth specifications. They usually generated radio chip. AUDIO CODEC 3.13.10 Features On-chip 15-bit audio linear codec, sampling rate, fully compliant with Bluetooth revision specifications Internal voltage references reduce external components count Single-ended differential microphone input Class output stage with simple passive filter Integrated preamplifier with configurable gain adapt various microphones Connected directly Bluetooth Sequencer Audio samples available host processor through direct memory access (DMA)
3.13.11 Register Name RegCodecCtrl RegDACSampleH RegDACSampleL RegADCSampleH RegADCSampleL RegDmaRdStartAddrH RegDmaRdStartAddrL RegDmaRdStopAddrH RegDmaRdStopAddrL RegDmaWrStartAddrH RegDmaWrStartAddrL RegDmaWrStopAddrH RegDmaWrStopAddrL RegDmaCtrl RegCodecDataFlow RegADCGain RegCodecPaMute Address (Hex) 0x00E0 0x00E2 0x00E3 0x00E4 0x00E5 0x00E6 0x00E7 0x00E8 0x00E9 0x00EA 0x00EB 0x00EC 0x00ED 0x00EE 0x00EF 0x00F1 0x00F9
Table Codec registers
RegCodecCtrl DmaIrqEnable SampleIrqEnable PcmEnable SerialLoopback ParallelLoopback DacEnable
Reset
Function generate interrupt when stop address reached interrupt generated generate interrupt when audio sample available interrupt generated reserved enable interface disable interface select loopback through interface select direct loopback enable disable
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RegCodecCtrl AdcEnable Reset Function enable disable
Table RegCodecCtrl register
RegDACSampleH DACSample[15:8]
Reset 00000000
Function audio sample sent
Table RegDACSampleHl register
RegDACSampleL DACSample[7:0]
Reset 00000000
Function audio sample sent
Table RegDACSampleL register
RegADCSampleH ADCSample[15:8]
Reset 00000000
Function audio sample read from
Table RegADCSampleH register
RegADCSampleL ADCSample[7:0]
Reset 00000000
Function audio sample read from
Table RegADCSampleL register
RegDmaRdStartAddrH DmaRdStartAddr[15:8]
Reset 00000000
Function start address read channel buffer
Table RegDmaRdStartAddrH register
RegDmaRdStartAddrL DmaRdStartAddr[7:0]
Reset 00000000
Function start address read channel buffer
Table RegDmaRdStartAddrL register
RegDmaRdStopAddrH DmaRdStopAddr[15:8]
Reset 00000000
Function address read channel buffer
Table RegDmaRdStopAddrH register
RegDmaRdStopAddrL DmaRdStopAddr[7:0]
Reset 00000000
Function address read channel buffer
Table RegDmaRdStopAddrL register
RegDmaWrStartAddrH
Reset
Function
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DmaWrStartAddr[15:8] 00000000 start address write channel buffer
Table RegDmaWrStartAddrH register
RegDmaWrStartAddrL DmaWrStartAddr[7:0]
Reset 00000000
Function start address write channel buffer
Table RegDmaWrStartAddrL register
RegDmaWrStopAddrH DmaWrStopAddr[15:8]
Reset 00000000
Function address write channel buffer
Table RegDmaWrStopAddrH register
RegDmaWrStopAddrL DmaWrStopAddr[7:0]
Reset 00000000
Function address write channel buffer
Table RegDmaWrStopAddrL register
RegDmaCtrl DmaRdCntLoad DmaWrCntLoad DmaRdFull DmaWrFull DmaRdEnable DmaWrEnable
Reset
Function reserved load DmaRdStartAddr[15:0] read channel address counter load DmaWrStartAddr[15:0] write channel address counter when read channel address counter reaches DmaRdStopAddr[15:0] when write channel address counter reaches DmaWrStopAddr[15:0] enable read channel disable read channel enable write channel disable write channel
Table RegDmaCtrl register
RegCodecDataFlow DmaWrSource PcmSource DacSource
Reset 0000
Function reserved select interface write channel source select write channel source select read channel interface source select interface source select read channel source select interface source reserved
Table RegCodecDataFlow register
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RegAdcGain PreampDisable PreampGain
Reset 00000
Function reserved disable preamplifier enable preamplifier Select preamplifier gain gain gain gain preamplifier bypassed
Table RegADCGain register
RegCodecPaMute PaMuteP PaMuteN
Reset 000000
Function reserved force PA_OUTP ground force PA_OUTN ground
Table RegCodecPaMute register
3.13.12 Block diagram
VMIC_P preamplifier VMIC_N Bluetooth Sequencer
CoolRISC data Current voltage references
Timing references
Configuration registers
PA_OUTP Power amplifier PA_OUTN
Figure Codec block diagram
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microphone input fully differential. signal from microphone between inputs VMIC_P VMIC_N first amplified variable gain amplifier. amplified signal then sampled digitized ADC. single output stream from then converted into 16-bit, kHz, linear data representing audio samples. These samples sent interface (connected Bluetooth Sequencer) host processor memory through interface depending settings RegCodecDataFlow configuration register. samples also directly read from RegADCSampleH/-L registers. 16-bit digital data from either Bluetooth Sequencer host processor memory through converted into stream DAC. host processor also write samples directly into RegDACSampleH/-L registers. This stream then amplified output power amplifier. signal available between PA_OUTP PA_OUTN outputs. output power amplifier class amplifier. requires only simple output filter. capable driving speaker directly impedance equal greater than Codec also includes Direct Memory Access host processor data memory (0x2000 0x3FEF) read write 16-bit audio samples, defined read channel write channel. area host processor data memory used write channel defined 16-bit pointers stored RegDmaWrStartAddrH/-L RegDmaWrStopAddrH/-L. Similarly, area host processor data memory used read channel defined 16-bit pointers stored RegDmaRdStartAddrH/-L RegDmaRdStopAddrH/-L. Software engineering should make sure these areas overlap with other application data otherwise this lead unpredictable behavior. strictly requires host processor clock same Codec input clock which SYS_CLOCK_IN (see 3.5.9). enable read and/or write channels, corresponding start stop addresses must loaded into internal address pointers from corresponding registers read and/or write channel must enabled. This performed setting appropriately RegDmaCtrl register. These pointers then automatically incremented sampling frequency defined audio samples, read and/or write samples after other from/to data memory. When read write pointer reach value defined RegDmaRdStopAddrH/-L RegDmaWrStopAddrH/-L interrupt host processor generated. interrupt service routine must stop access, write start stop addresses RegDmaRdStartAddrH/-L RegDmaRdStopAddrH/-L, RegDmaWrStartAddrH/-L RegDmaWrStopAddrH/-L, enable again read write channel. not, read write pointer will increment beyond stop addresses which means audio samples will read from application data memory, audio samples will overwrite application data memory. Note that settings lead unpredictable behavior: RegDmaWrStartAddr higher then RegDmaWrStopAddr then internal pointer counter will increment until reaches 0xFFFF address, then restarts 0x0000 increments until reaches RegDmaWrStopAddr; behavior similar RegDmaRdStartAddr RegDmaRdStopAddr; RegDmaWrStartAddr RegDmaWrStopAddr, and/or RegDmaRdStartAddr RegDmaRdStopAddr, then interrupt immediately generated. 3.13.13 CODEC clock source shown paragraph 3.5.9, codec clocked SYS_CLOCK_IN. frequency must order fulfill Bluetooth Audio specifications.
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3.13.14 Specifications Symbol VMIC Description input range Preamplifier gain Gain error Preamplifier Noise (x5) Preamplifier Noise (x10) Preamplifier Noise (x20) ZPreamp gain ZPreamp gain ZPreamp gain -0.5 Typ. Vrms Vrms Vrms gain gain gain Unit Comments Min/max levels VMIC_P VMIC_N Differential input VMIC_P VMIC_N x10, x20, under software control gain bandwidth bandwidth bandwidth
input noise level preamplifier gain input noise level preamplifier gain input noise level preamplifier gain Preamplifier high frequency roll-off Equivalent input impedance preamplifier Equivalent input impedance preamplifier Equivalent input impedance preamplifier equivalent input noise level Dynamic Range output rate Dynamic range Total harmonic distortion (relative full scale) Signal-to-Noise Ratio
Noise DRADC DRDAC
Vrms 1kHz, load, with direct loopback mode with direct loopback mode
Table Codec Specifications
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3.13.15 Microphone input
preamplifier
VREGA
Rpol
Rpol
Rmic
XE1431
CMIC VMIC_P CMIC CMIC VMIC_N
preamplifier
Figure Equivalent schematic gain calculation
Figure typical microphone configuration Figure Equivalent schematic CMIC calculation
Figure shows connect microphone. microphone powered VREGA, clean constant voltage through resistor Rpol. capacitors CMIC remove voltage level. Figure shows equivalent schematic gain dynamic range calculation. input impedance preamplifier, polarization resistor, internal resistor microphone considered parallel. input impedance preamplifier varies with preamplifier gain. Figure equivalent schematic CMIC frequency roll-off calculations. frequency given relation:
varies from depending gain preamplifier. CMIC typically about Rpol value usually about depends microphone. 3.13.16 Speaker output power amplifier operates class pins PA_OUTP PA_OUTN output complementary digital signals (see Figure high frequency whose cyclic ratio proportional amplitude audio signal. switching frequency filtered limit power consumption risk degradation speaker.
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VDD_PA
PA_OUTP PA_OUTN
VSS_PA
bitstream
Figure Power Amplifier (PA) structure
Figure shows typical configuration speaker power amplifier. VDD_PA connected VREGD voltage lesser equal 1.8V.
VREGD
VDD_PA PA_OUTP
XE143x
PA_OUTN VSSIO_DIG VSS_PA
Figure Typical output filter
output filter balanced 2-pole filter. Equation gives estimation values external inductors capacitors function speaker impedance cut-off frequency filter. usually kHz, defined Bluetooth audio specifications. very dependant speaker.
where
Equation Typical values speaker output filter
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Equation gives best estimation component values, since does take into account resistance inductor assumes that speaker impedance resistive constant over whole frequency range. However, estimation good starting point optimization components. Choosing filter cutoff frequency typical values, gives
3.14 DEBUG INTERFACE 3.14.1 Description debug interface used observe and/or force UART Codec signals. also used GPIO port. 3.14.2 Register Address (Hex) 0x0078 0x0079 0x007A 0x007B
Table Debug interface registers
Name RegDbgDir RegDbgOut RegDbgIn RegDbgMode
RegDbgDir DbgDir[7:0]
Reset 00000000
Function DBG[7:0] direction GPIO mode: output, input Debug mode: observation, force
Table RegDbgDir register
RegDbgOut DbgOut[7:0]
Reset 00000000
Function DBG[7:0] output value. Valid only GPIO mode
Table RegDbgOut register
RegDbgIn DbgIn[7:0]
Reset 00000000
Function DBG[7:0] input value. Valid only GPIO mode
Table RegDbgOut register
RegDbgMode DbgMode
Reset 00000000
Function GPIO Debug mode reserved
Table RegDbgMode register
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3.14.3
Pins mapping DBG[7] DBG[6] DBG[5] DBG[4] DBG[3] DBG[2] DBG[1] DBG[0] Signal (Bluetooth macro side) HCI_ DBG_ HCI_ DBG_RX HCI_ DBG_RTS HCI_ DBG_CTS PCM_ DBG_D_IN PCM_ DBG_D_OUT PCM_ DBG_CLK PCM_ DBG_FSYNC
Table Pins mapping
Bluetooth Sequencer RegDbgDir RegDbgDir
UART
HCI_DBG_TX HCI_DBG_CTS
Bluetooth Sequencer RegDbgDir RegDbgDir
UART
HCI_DBG_RX
Figure Debug Interface block schematics
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D_OUT FSYNC Bluetooth Sequencer
D_IN FSYNC CODEC
RegDbgDir RegDbgDir
PCM_D_OUT PCM_CLK PCM_FSYNC
D_OUT
D_IN
Bluetooth Sequencer RegDbgDir RegDbgDir
CODEC
PCM_D_IN
Figure Codec Debug Interface block schematics
3.14.4 Configuration debug interface modes, GPIO mode (default) Debug mode. 3.14.4.1 GPIO mode enter GPIO mode RegDbgMode register default value after reset (0). direction each within DBG[7:0] (input only input/output) individually using RegDbgDir register. RegDbgDir[i] both input output buffers active corresponding pin. RegDbgDir[i] corresponding input only output buffer high impedance. After reset input only mode; RegDbgDir[i] reset input values available RegDbgIn (read only). Reading always direct there debounce function. case possible noise input signals, software debouncer with polling external hardware filter implemented. input buffer also active when port defined output allows reading back effective value pin. Data stored RegDbgOut output RegDbgDir[i] default value after reset (0).
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3.14.4.2 Debug mode enter Debug mode RegDbgMode register Debug mode pins observed forced. RegDbgDir[i] corresponding observation mode. RegDbgDir[i] corresponding forced from outside. 3.14.5 Configuration Examples
3.14.5.1 XE1431 XE1401 Debug interface registers follows: RegDbgDir 0xAF RegDbgMode 0x80 3.14.5.2 Observe traffic Debug interface registers follows: RegDbgDir 0xFF RegDbgMode 0x80
3.15 DEVELOPMENT DEBUG CHIP This interface with XE1431 development tool. includes DOC_SCK DOC_SDIO pins. They powered VDDIO_DIG VSSIO_DIG. When normal operation applications, DOC_SCK DOC_SDIO should remain unconnected (N:C.) When operated development debug mode DOC_SCK DOC_SDIO, addition VDDIO_DIG VSSIO_DIG, connected XE1431 development tools through appropriate interface. (see
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ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS Stress above limits listed following table cause permanent failure. Exposure absolute ratings extended time periods affect device reliability. limiting values accordance with Absolute Maximum Rating System (IEC 134). voltages referenced ground (VSS_M). Symbol Parameter Supply voltage: VDD_M Codec power amplifier supply voltage: VDD_PA Storage temperature Electrostatic handling Conditions -0.3 -0.3 3.65 2000 Unit
Tstor
(*1) (*2)
Tested according MIL883C Method 3015.6 (Standardized Human Body Model: 1500, pulses, protection related substrate). Static dynamic latch-up values valid room temperature. Table Absolute maximum ratings
RECOMMENDED OPERATING CONDITIONS voltages referenced ground (VSS_M). Typical operating conditions typical configuration. Operating ranges define limits functional operation parametric characteristics device described this section. Functionality outside these limits implied.
Symbol Tamb VDD_M VDDBAT VDD_DIG VDD_PA VDD_ANA VDDIO VDDIO_DIG
Description Operating ambient temperature Main power supply Battery end-of-life sensor Digital core voltage Codec power amplifier supply voltage Analog core voltage Radio voltage level Digital voltage level
1.62 1.62 1.62 1.62
Typ.
1.98 1.98 1.98 1.98
Unit
Comments
VDD_M para. 3.3.6 usually connected VREGD usually VREGA connected
Table Operating supply ranges
Symbol
Description input logic level high input logic level output high voltage output voltage internal pull-up resistor input capacitance
0.7*VDDIO_DIG VSSIO_DIG VDDIO_DIG- VSSIO_DIG
VDDIO_DIG 0.3*VDDIO_DIG VDDIO_DIG VSSIO_DIG+0.2
Unit
Comments
IOH=-6mA, VDDIO_DIG=3.6V IOL=6mA, VDDIO_DIG=3.6V
Table Digital I/O's specifications
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SUPPLY CONFIGURATION, POWER C
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