Constant on-time fast dynamic response Programmable VOUT range VCCA VB

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Constant on-time fast dynamic response Programmable VOUT range VCCA VB

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Dual Synchronous Buck Pseudo Fixed Frequency Power Supply Controller
Constant on-time fast dynamic response Programmable VOUT range VCCA VBAT Range 1.8V current sense using low-side RDS(ON) sensing sense resistor Resistor programmable frequency Cycle-by-cycle current limit Digital soft-start Separate PSAVE option each switcher Over-voltage/Under-voltage fault protection 10µA Typical shutdown current quiescent power dissipation Power Good indicators Reference system accuracy) Integrated gate drivers with soft switching Separate enables Lead TSSOP Industrial temperature range Output soft discharge upon shutdown
SC483
SC483 dual output constant-on synchronous buck controller intended notebook computers other battery operated portable devices. Features include high efficiency fast dynamic response with minimum time. excellent transient response means that SC483 based solutions will require less output capacitance than competing fixed frequency converters. switching frequency constant until step load line voltage occurs which time pulse density frequency will increase decrease counter change output input voltage. After transient event, controller frequency will return steady state operation. light loads, Power-Save Mode enables SC483 skip pulses better efficiency. Each output voltage independently adjusted from 0.5V VCCA. frequency setting resistors on-time each buck controller. frequency thus tailored minimize crosstalk. integrated gate drivers feature adaptive shoot-through protection soft switching. Additional features include cycle-by-cycle current limit, digital soft-start, over-voltage undervoltage protection, PGOOD output each controller.
VBAT 5VSUS
Applications
Notebook computers supplies Handheld terminals PDAs monitors Network power supplies
5VSUS VBAT
RTON1 VOUT1 VSSA1 5VSUS RTON2 VOUT2 VSSA2 PGD2 VSSA2 VDDP2 PGND2 VSSA2 VCCA2 ILIM2 EN/PSV2 TON2 VOUT2 BST2 VOUT2 10uF 0.1uF PGD1 VSSA1 VDDP1 PGND1 VSSA1 VCCA1 ILIM1 EN/PSV1 TON1 VOUT1 SC483 BST1 VOUT1 10uF 0.1uF
PGOOD
VBAT
5VSUS
VBAT
PGOOD
Revision: March 2005
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SC483
POWER MANAGEMENT Absolute Maximum Ratings(1)
Exceeding specifications below result permanent damage device, device malfunction. Operation outside parameters specified Electrical Characteristics section implied. Exposure Absolute Maximum rated conditions extended periods time affect device reliability.
Parameter TONn VSSAn DHn, BSTn PGNDn PGNDn PGNDn VSSAn BSTn DLn, ILIMn, VDDPn PGNDn EN/PSVn, FBn, PGDn, VCCAn, VOUTn VSSAn VCCAn EN/PSVn, FBn, PGDn, VOUTn Thermal Resistance Junction Ambient Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) Sec.
Symbol
Maximum -0.3 +25.0 -0.3 +30.0 -2.0 +25.0 -0.3 +0.3 -0.3 +6.0 -0.3 +6.0 -0.3 +6.0 -0.3 +6.0
Units °C/W
TSTG TLEAD
+125 +150
Notes: This device sensitive. standard handling precautions required. Measured accordance with JESD51-1, JESD51-2 JESD51-7.
Electrical Characteristics
Test Conditions: VBAT 15V, EN/PSV1=EN/PSV2 VCCA1 VDDP1 VCCA2 VDDP2 VOUT1 VOUT2 =1.25V, RTON1 RTON2
Parameter
Conditions
25°C
-40°C 125°C
Units
Input Supplies VBAT Voltage Offtime 800ns 1100
VDDP1, VDDP2 Operating Current regulation point, ILOAD VCCA1, VCCA2 Operating Current regulation point, ILOAD TON1, TON2 Operating Current Shutdown Current RTON EN/PSV1, EN/PSV2 VDDP1, TON1, VDDP2, TON2
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SC483
POWER MANAGEMENT Electrical Characteristics (Cont.)
Test Conditions: VBAT 15V, EN/PSV1=EN/PSV2 VCCA1 VDDP1 VCCA2 VDDP2 VOUT1 VOUT2 =1.25V, RTON1 RTON2
Parameter
Conditions
25°C
-40°C 125°C
Units
Controller Error Comparator Threshold turn-on threshold)(1) Output Voltage Range On-Time, VBAT 2.5V RTON RTON 500k Minimum Time VOUT1, VOUT2 Input Resistance VOUT1, VOUT2 Shutdown Discharge Resistance FB1, Input Bias Current Over-Current Sensing ILIM Source Current Current Comparator Offset PSAVE Zero-Crossing Threshold Fault Protection Current Limit (Positive) (PGND LX), RILIM (PGND LX), RILIM (PGND LX), RILIM Current Limit (Negative) Output Under-Voltage Fault Output Over-Voltage Fault OUT1 Output Over-Voltage Fault OUT2 Over-Voltage Fault Delay Output Voltage Leakage Current Threshold (PGND With respect internal ref. With respect internal ref. With respect internal ref. forced above Threshold Sink regulation, With respect internal ref. -125 -160 (PGND LX), EN/PSV high PGND ILIM EN/PSV1, EN/PSV2 1761 -1.0 +1.0 VCCA 4.5V 5.5V 0.500 1497 2025 1076
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SC483
POWER MANAGEMENT Electrical Characteristics (Cont.)
Test Conditions: VBAT 15V, EN/PSV1=EN/PSV2 VCCA1 VDDP1 VCCA2 VDDP2 VOUT1 VOUT2 =1.25V, RTON1 RTON2
Parameter
Conditions
25°C
-40°C 125°C
Units
Fault Protection (Cont.) Fault Delay VCCA Undervoltage Threshold Over Temperature Lockout Inputs/Outputs Logic Input Voltage Logic Input High Voltage Logic Input High Voltage EN/PSV Input Resistance EN/PSV High, (Floating) EN/PSV high Pullup VCCA Pulldown VSSA Soft Start Soft-Start Ramp Time Under-Voltage Blank Time Gate Drivers Shoot-Through Delay Pull-Down Resistance Sink Current Pull-Up Resistance Source Current Pull-Down Resistance Pull-Up Resistance(5) Sink/Source Current rising 2.5V high 2.5V low, high, 2.5V EN/PSV high high EN/PSV high high clks(3) clks(3) forced outside window Falling (100mV Hysteresis 10°C Hysteresis
Notes: When inductor continuous discontinuous conduction mode, output voltage will have regulation level higher than error-comparator threshold ripple voltage. Using current sense resistor, this measurement relates PGND minus voltage source lowside MOSFET. These values guaranteed ILIM Source Current Current Comparator Offset tests. clks Switching cycles. Guaranteed design. Shoot-Through Delay Timing Diagram Page Semtech's SmartDriverFET drive first pulls high with pullup resistance (typ.) until 1.5V (typ.). this point, additional pullup device activated, reducing resistance (typ.). This negates need external gate boost resistor.
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SC483
POWER MANAGEMENT Configuration Ordering Information
Device SC483ITSTRT(2) Package(1) TSSOP-28
Notes: Only available tape reel packaging. reel contains 2500 devices. Lead free product. This product fully WEEE, RoHS J-STD-020B compliant.
TSSOP-28
Descriptions
Name PGND1 ILIM1 BST1 EN/PSV2 Function Power ground. Gate drive output side MOSFET switch. supply voltage input gate drivers. Decouple this with ceramic capacitor PGND1. Current limit input. Connect drain low-side MOSFET RDS(on) sensing source resistor sensing through threshold sensing resistor. Phase node (junction bottom MOSFETs output inductor) connection. Gate drive output high side MOSFET switch. Boost capacitor connection high side gate drive. Enable/Power Save input. Pull down VSSA2 shut down OUT2 discharge through (nom). Pull enable OUT2 activate PSAVE mode. Float enable OUT2 activate continuous conduction mode (CCM), which should used dynamic voltage transitioning. floated, bypass VSSA2 with 10nF ceramic capacitor. This used sense VBAT through pullup resistor, RTON2, MOSFET ontime. Bypass this with ceramic capacitor VSSA2. Output voltage sense input output Connect output load. Supply voltage input analog supply. filter from 5VSUS VSSA2. Feedback input. Connect resistor divider located from VOUT2 VSSA2 output voltage from 0.5V VCCA2. Power Good open drain NMOS output. Goes high after fixed clock cycle delay (440 cycles) following power Ground reference analog circuitry. Connect PGND2 bottom output capacitor.
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TON2 VOUT2 PGD2 VSSA2
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SC483
POWER MANAGEMENT Descriptions (Cont.)
Pin# Name PGND2 ILIM2 BST2 EN/PSV1 Function Power ground. Gate drive output side MOSFET switch. supply voltage input gate drivers. Decouple this with ceramic capacitor PGND2. Current limit input. Connect drain low-side MOSFET RDS(on) sensing source resistor sensing through threshold sensing resistor. Phase node (junction bottom MOSFETs output inductor) connection. Gate drive output high side MOSFET switch. Boost capacitor connection high side gate drive. Enable/Power Save input. Pull down VSSA1 shut down OUT1 discharge through (nom.). Pull enable OUT1 activate PSAVE mode. Float enable OUT1 activate continuous conduction mode (CCM). floated, bypass VSSA1 with 10nF ceramic capacitor. This used sense VBAT through pullup resistor, RTON1, MOSFET ontime. Bypass this with ceramic capacitor VSSA1. Output voltage sense input output Connect output load. Supply voltage input analog supply. filter from 5VSUS VSSA1. Feedback input. Connect resistor divider located from VOUT1 VSSA1 output voltage from 0.5V VCCA1. Power Good open drain NMOS output. Goes high after fixed clock cycle delay (440 cycles) following power Ground reference analog circuitry. Connect PGND1 bottom output capacitor.
TON1 VOUT1 PGD1 VSSA1
Shoot-Through Delay Timing Diagram
tplhDL tplhDH
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SC483
POWER MANAGEMENT Block Diagram
VCCA1 (25) EN/SPV1 (22) DSCHG1 BST1 TON1 (23) VOUT1 (24) DSCHG1 1.5V (26) ZERO ISENSE ILIM1 VDDP1 PGND1 VSSA1 (28) FAULT MONITOR VCCA2 (11) EN/SPV2 DSCHG2 BST2 (21) DSCHG2 TOFF CONTROL LOGIC (20) (19) TOFF CONTROL LOGIC
PGD1 (27)
TON2 VOUT2 (10)
1.5V (12) ZERO ISENSE ILIM2 (18) VDDP2 (17) (16) PGND2 (15) VSSA2 (14) FAULT MONITOR
PGD2 (13)
FIGURE
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SC483
POWER MANAGEMENT Applications Information
Bias Supplies SC483 requires external bias supply addition battery. stand-alone capability required, supply generated with external linear regulator such Semtech LP2951. avoid interference between outputs, each controller ground reference, VSSA, which should tied single trace PGND negative terminal that controller's output capacitor (see Layout Guidelines). external components referenced VSSA schematic should connected appropriate VSSA trace. supply decoupling capacitor controller should tied between VCCA1 VSSA1. Likewise, supply decoupling capacitor controller should tied between VCCA2 VSSA2. resistor should used decouple each VCCA supply from main VDDP supplies. PGND then separate plane which used routing traces. PGND connections connected directly ground plane with special attention given avoiding indirect connections which create ground loops. mentioned above, VSSA1 VSSA2 must connected PGND plane negative terminal their respective output capacitors only. VDDP1 VDDP2 inputs provide power upper lower gate drivers. decoupling capacitor each supply required. series resistor between VDDP required. layout guidelines more details. Pseudo-fixed Frequency Constant On-Time Controller control architecture consists constant ontime, pseudo fixed frequency controller (see Figure SC483 Block Diagram). output ripple voltage developed across output filter capacitor's provides ramp signal eliminating need current sense resistor. high-side switch on-time determined one-shot whose period directly proportional output voltage inversely proportional input voltage. second one-shot sets minimum off-time which typically 400ns. On-Time One-Shot (tON) on-time one-shot comparator inputs. input looks output voltage, while other input samples input voltage converts current.
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This input voltage-proportional current used charge internal on-time capacitor. on-time time required voltage this capacitor charge from zero volts VOUT, thereby making on-time high-side switch directly proportional output voltage inversely proportional input voltage. This implementation results nearly constant switching frequency without need clock generator. VOUT 3.3V:
50ns 3.3V VOUT
0.85 50ns RTON resistor connected from input supply (VBAT) pin. high impedance this resistor, should always bypassed VSSA using ceramic capacitor.
EN/PSV: Enable, Psave Soft Discharge EN/PSV enables supply. When EN/PSV tied VCCA controller enabled power save will also enabled. When EN/PSV tri-stated, internal pull-up will activate controller power save will disabled. PSAVE enabled, SC483 PSAVE comparator will look inductor current cross zero eight consecutive switching cycles comparing phase node (LX) PGND. Once observed, controller will enter power save turn side MOSFET when current crosses zero. improve light-load efficiency hysteresis, on-time increased power save. efficiency improvement light-loads more than offsets disadvantage slightly higher output ripple. inductor current does cross zero switching cycle, controller will immediately exit power save. Since controller counts zero crossings, converter sink current long current does cross zero eight consecutive cycles. This allows output voltage recover quickly response negative load steps even when psave enabled. EN/PSV pulled low, related output will shut down discharged using switch with nominal resistance Ohms. This will ensure that output defined state next time enabled also
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SC483
POWER MANAGEMENT
ensure, since this soft discharge, that there dangerous negative voltage excursions concerned about. order soft discharge circuitry function correctly, chip supply must present. Output Voltage Selection output voltage (OUT2 shown) feedback resistors Figure below. internal reference 1.5V, voltage feedback multiplied three match 1.5V reference. Therefore output minimum 0.5V. equation setting output voltage current sensing circuit actually regulates inductor valley current (see Figure This means that current limit 10A, peak current through inductor would plus peak-to-peak ripple current, average current through inductor would plus peak-to-peak ripple current. equations setting valley current calculating average current through inductor shown below: sense element (resistor MOSFET) falls below voltage across RILIM resistor. extreme overcurrent situation, MOSFET will never turn back eventually part will latch output undervoltage (see Output Undervoltage Protection).
VOUT
VOUT VOUT2 0402 20k0 0402 14k3 0402 EN/PSV2 TON2 VOUT2 VCCA2 PGD2 VSSA2 BST2 ILIM2 VDDP2 PGND2
INDUCTOR CURRENT
IPEAK ILOAD ILIMIT
SC483 OUT2
TIME Valley Current-Limit Threshold Point
VSSA2
Figure Valley Current Limiting Figure Setting Output Voltage Current Limit Circuit Current limiting SC483 accomplished ways. on-state resistance low-side MOSFET used current sensing element sense resistors series with low-side source used greater accuracy desired. RDS(ON) sensing more efficient less expensive. both cases, RILIM resistor between ILIM over current threshold. This resistor RILIM connected 10µA current source within SC483 which turned when side MOSFET turns When voltage drop across sense resistor side MOSFET equals voltage across RILIM resistor, positive current limit will activate. high side MOSFET will turned until voltage drop across
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equation current limit threshold follows:
ILIMIT
RILIM SENSE
Where (referring Figure Page RILIM RSENSE RDS(ON) resistor sensing, sense resistor placed between source PGND. current through source sense resistor develops voltage that opposes voltage developed across RILIM. When voltage developed across RSENSE resistor reaches voltage drop across RILIM, positive over-current exists high side MOSFET will allowed turn When using external sense resistor RSENSE resistance sense resistor.
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SC483
POWER MANAGEMENT
current limit circuitry also protects against negative over-current (i.e. when current flowing from load PGND through inductor bottom MOSFET). this case, when bottom MOSFET turned phase node, will higher than PGND initially. SC483 monitors voltage greater than threshold voltage 125mV (nom.) bottom MOSFET turned off. device then waits approximately 2.5µs then goes high 300ns (typ.) once more sense current. This repeats until either over-current condition goes away part latches output overvoltage (see Output Overvoltage Protection). Power Good Output power good output open-drain output requires pull-up resistor. When output voltage above below voltage, gets pulled low. held until output voltage returns within these tolerances once more. also held during start-up will allowed transition high until soft start over (440 switching cycles) output reaches voltage. There delay built into circuitry prevent false transitions. Output Overvoltage Protection When output exceeds voltage low-side MOSFET latched stays latched controller latched until reset (see below). There delay built into protection circuit prevent false transitions. Output Undervoltage Protection When output below voltage output latched tri-stated condition. stays latched controller latched until reset (see below). There delay built into protection circuit prevent false transitions. Note: reset from fault, VCCA EN/PSV must toggled. POR, UVLO Softstart internal power-on reset (POR) occurs when VCCA exceeds starting internal biasing. VCCA undervoltage lockout (UVLO) circuitry inhibits controller until VCCA rises above 4.2V. this time UVLO circuitry resets fault latch soft start timer, allows switching occur device enabled.
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Switching always starts with charge capacitor. With softstart circuit (automatically) enabled, will progressively limit output current limiting current ILIM pin) over predetermined time period switching cycles. ramp occurs four steps: cycles ILIM with double minimum off-time (for purposes on-time one-shot, there internal positive offset 120mV VOUT during this period startup) cycles ILIM with normal minimum off-time cycles ILIM with normal minimum off-time cycles 100% ILIM with normal minimum off-time. this point output undervoltage power good circuitry enabled. There 100mV hysteresis built into UVLO circuit when VCCA falls 4.1V (nom.) output drivers shut down tristated. MOSFET Gate Drivers drivers optimized driving moderate-sized high-side, larger low-side power MOSFETs. adaptive dead-time circuit monitors output prevents high-side MOSFET from turning until fully (below ~1V). Semtech's SmartDriverFET drive first pulls high with pull-up resistance (typ.) until 1.5V (typ.). this point, additional pull-up device activated, reducing resistance (typ.). This negates need external gate boost resistor. adaptive dead-time circuit also monitors phase node, determine state high side MOSFET, prevents lowside MOSFET from turning until fully below ~1V). sure have resistance inductance between outputs gate each MOSFET. Dropout Performance output voltage adjust range continuousconduction operation limited fixed 550ns (maximum) minimum off-time one-shot. best dropout performance, slowest on-time setting 200kHz. When working with input voltages, duty-factor limit must calculated using worst-case values times. duty-factor limitation given
DUTY
OFF(MAX
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SC483
POWER MANAGEMENT
sure include inductor resistance MOSFET onstate voltage drops when performing worst-case dropout duty-factor calculations. SC483 System Accuracy parameters affect system accuracy, error comparator threshold voltage variation switching frequency variation with line load. error comparator threshold does drift significantly with supply temperature. Thus, error comparator contributes less system inaccuracy. Board components layout also influence accuracy. feedback resistors contribute tighter accuracy required 0.1% feedback resistors. pulse SC483 calculated give pseudo fixed frequency. Nevertheless, some frequency variation with line load expected. This variation changes output ripple voltage. Because constant-on regulators regulate valley output ripple, output ripple appears regulation error. example, feedback resistors chosen divide down output factor five, valley output ripple will VOUT. example: VOUT 2.5V ripple 50mV with VBAT then measured output will 2.525V. ripple increases 80mV with VBAT 25V, then measured output will 2.540V. output inductor value change with current. This will change output ripple thus output voltage. will change frequency. Switching frequency variation with load minimized choosing MOSFETs with lower DS(ON). High DS(ON) MOSFETs will cause switching frequency increase load current increases. This will reduce ripple thus output voltage. Design Procedure Prior designing output making component selections, necessary determine input voltage range output voltage specifications. purposes demonstrating procedure output schematic Figure Page will designed.
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maximum input voltage (VBAT(MAX)) determined highest adaptor voltage. minimum input voltage BAT(MIN)) determined lowest battery voltage after accounting voltage drops connectors, fuses battery selector switches. purposes this design example will VBAT range design OUT2. design OUT1 employs same technique. Four parameters needed output: nominal output voltage, VOUT will 1.2V) static tolerance, TOLST will +/-4%) transient tolerance, TOLTR size transient will +/-8% purposes this demonstration). maximum output current, IOUT will design Switching frequency determines trade-off between size efficiency. Increased frequency increases switching losses MOSFETs, since losses function VIN2. Knowing maximum input voltage budget MOSFET switches usually dictates where design ends recommended that outputs designed operate frequencies approximately apart avoid possible interaction. also recommended that higher frequency output lower output voltage output, since this will tend have lower output ripple tighter specifications. default RtON values 715k suggested starting point, these stone. first thing calculate on-time, tON, VBAT(MIN) VBAT(MAX), since this depends only upon VBAT, VOUT tON. VOUT 3.3V:
VOUT VBAT(MIN) VBAT (MIN)
VOUT VBAT (MAX VBAT (MAX
From these values calculate nominal switching frequency follows:
VBAT (MIN
VOUT VBAT
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SC483
POWER MANAGEMENT
VBAT (MAX VOUT (VBAT(MAX VBAT(MAX
From this calculate minimum inductor current rating normal operation:
generated one-shot comparator that samples VBAT RtON, converting this current. This current used charge internal 3.3pF capacitor VOUT. equations above reflect this along with internal components delays that influence tON. example select RtON tON_VBAT(MIN) 563ns tON_VBAT(MAX) 255ns fSW_VBAT(MIN) 266kHz fSW_VBAT(MAX) 235kHz that know calculate suitable values inductor. this select acceptable inductor ripple current. calculations below assume IOUT which will give starting place.
IINDUCTOR (MIN) IOUT (MAX
example: IINDUCTOR(MIN) 7.1A(MIN)
IRIPPLE VBAT (MAX
(MIN)
Next will calculate maximum output capacitor equivalent series resistance (ESR). This determined calculating remaining static transient tolerance allowances. Then maximum smaller calculated static ESR_ST(MAX)) transient ESR_TR(MAX)):
RESR (MAX
(ERR
ERRDC
IRIPPLE VBAT (MAX
Ohms
VBAT (MIN) (VBAT (MIN) VOUT
VBAT (MIN)
(0.5
Where ERRST static output tolerance ERRDC error. error will plus tolerance feedback resistors, thus total feedback resistors. example: ERRST 48mV ERRDC 24mV, therefore RESR_ST(MAX)
VBAT (MAX (VBAT (MAX VOUT
example:
VBAT (MAX
(0.5
LVBAT(MIN) 1.3µH LVBAT(MAX) 1.6µH will select inductor value 2.2µH reduce ripple current, which calculated follows:
RESR (MAX
(ERR
IOUT
IRIPPLE VBAT (MIN) (VBAT (MIN) VOUT
VBAT (MIN)
Ohms IRIPPLE VBAT (MAX
IRIPPLE VBAT (MAX (VBAT (MAX VOUT
VBAT (MAX
Where ERRTR transient output tolerance. Note that this calculation assumes that worst case load transient full load. half full load, divide IOUT term example: ERRTR 96mV ERRDC 24mV, therefore RESR_TR(MAX) 10.2m full load transient
example: IRIPPLE_VBAT(MIN) 1.74AP-P IRIPPLE_VBAT(MAX) 2.18AP-P
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SC483
POWER MANAGEMENT
will select value 12.5m maximum design, which would achieved using output capacitors parallel. Note that constant-on converters there minimum requirement stability which calculated follows: example will 20.0k RBOT 14.3k, therefore: ZTOP 6.67k CTOP 60pF will select value CTOP 56pF. Calculating value based upon selected CTOP:
VRIPPLE VBAT(MIN) RBOT VBAT(MIN)
RESR (MIN
COUT
This criteria should checked once output capacitance been determined. that know output calculate output ripple voltage:
VBAT(MIN)
VRIPPLE VBAT(MAX) RESR IRIPPLE VBAT(MAX)
example: VFB_VBAT(MIN) 14.8mVP-P good Next need calculate minimum output capacitance required ensure that output voltage does exceed transient maximum limit, POSLIMTR, starting from actual static maximum, VOUT_ST_POS, when load release occurs:
VRIPPLE VBAT(MIN) RESR IRIPPLE VBAT(MIN)
example: VRIPPLE_VBAT(MAX) 27mVP-P VRIPPLE_VBAT(MIN) 22mVP-P Note that order device regulate controlled manner, ripple content feedback pin, VFB, should approximately 15mVP-P minimum worst case smaller than 10mV VRIPPLE_VBAT(MIN) less than 15mVP-P above component values should revisited order improve this. Quite often small capacitor, CTOP, required parallel with feedback resistor, RTOP, order ensure that large enough. should greater than 100pF. value CTOP calculated follows, where bottom feedback resistor. Firstly calculating value ZTOP required:
VOUT VOUT ERRDC
example: VOUT_ST_POS 1.224V
POSLIM VOUT
Where TOLTR transient tolerance. example: POSLIMTR 1.296V minimum output capacitance calculated follows:
IOUT RIPPLE VBAT (MAX POSLIM VOUT
(VRIPPLE VBAT (MIN) 0.015 Ohms 0.015
Secondly calculating value CTOP required achieve this:
VBAT (MIN)
(MIN)
This calculation assumes absolute worst case condition full-load load step transient occurring when inductor current highest. capacitance required smaller transient steps calculated substituting desired current IOUT term.
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SC483
POWER MANAGEMENT
example: COUT(MIN) 610µF. will select 440µF, using 220µF, capacitors parallel. smaller load release overshoot, 660µF used. Next calculate input ripple current, which largest minimum battery voltage: Thermal Considerations junction temperature device calculated follows:
IIN(RMS VOUT (VBAT (MIN) VOUT
example: IIN(RMS) 2.14ARMS
IOUT VBAT
Where: ambient temperature (°C) power dissipation thermal impedance junction ambient from absolute maximum ratings (°C/W) power dissipation calculated follows:
(VCCA IVCCA VDDP IVDDP VBST VBST
Input capacitors should selected with sufficient ripple current rating this current, example 10µF, 1210 size, ceramic capacitor handle approximately Refer manufacturer's data sheets derate appropriately. Finally, calculate current limit resistor value. described current limit section, current limit looks "valley current", which average output current minus half ripple current. maximum room temperature specification MOSFET RDS(ON) 4.5V purposes this calculation:
Where: VCCA chip supply voltage IVCCA operating current VDDP gate drive supply voltage IVDDP gate drive operating current gate drive voltage, typically gate charge, from datasheet switching frequency (kHz) VBST boost voltage during duty cycle Inserting following values VBAT(MIN) condition (since this worst case condition power dissipation controller) example (OUT1 1.5V, OUT2 1.2V): 85°C 84°C/W VCCA VDDP IVCCA 1100µA (data sheet maximum) IVDDP 150µA (data sheet maximum) 60nC 250kHz 300kHz VBAT(MIN) VBST(MIN) VBAT(MIN)+VDDP D1(MIN) 1.5/8 0.1875 D2(MIN) 1.2/8 0.15
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IVALLEY IOUT
IRIPPLE VBAT (MIN)
ripple battery voltage used because want make sure that current limit does occur under normal operating conditions.
RILIM (IVALLEY 1.2)
example:
RDS(
Ohms
IVALLEY 5.13A, RDS(ON) RILIM 7.76k select next lowest resistor value: 7.68k
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SC483
POWER MANAGEMENT
gives
1100 0.1875 0.15 0.182
and:
0.182
seen, heating effects internal power dissipation practically negligible, thus requiring special consideration thermally during layout.
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SC483
POWER MANAGEMENT
Layout Guidelines more) ground planes is/are recommended minimize effect switching noise copper losses, maximize heat dissipation. ground references, VSSA1 VSSA2, should kept separate from power ground. components that referenced them should connect them locally chip. VSSA1 VSSA2 should connect power ground their respective output capacitors only. Feedback traces must kept away from noise sources such switching nodes, inductors gate drives. Route feedback traces with their respective VSSAs differential pair from output capacitor back chip. them "quiet layer" possible. Chip decoupling capacitors (VDDP, VCCA) should located next pins connected directly them same side. Power sections should connect directly ground plane(s) using multiple vias required current handling (including chip power ground connections). Power components should placed minimize loops reduce losses. Make connections side using wide copper filled areas possible. "minimum" land patterns power components. Minimize trace lengths between gate drivers gates MOSFETs reduce parasitic impedances (and MOSFET switching losses), low-side MOSFET most critical. Maintain length width ratio <20:1 gate drive signals. multiple vias required current handling requirement (and reduce parasitics) routed more than layer Current sense connections must always made using Kelvin connections ensure accurate signal. will examine SC483 OUT2 reference design used Design Procedure section while explaining layout guidelines more detail, using same generic components OUT1.
5VSUS VBAT 5VSUS SOD323 0.1uF 0603
VBAT
0402
0402
EN/PSV1 TON1 VOUT1 VCCA1 PGD1 VSSA1
SC483 BST1 ILIM1 VDDP1 PGND1
0603
IRF7811AV
2n2/50V 0402
0u1/25V 0603
10u/25V 1210
VOUT1 VOUT 0402 20k0 0402
7k87 0402
VOUT1 FDS6676S 0402 220u/25m 7343 220u/25m 7343
PGOOD 20k0 0402
0402
0603
VSSA1
VSSA1 VBAT 5VSUS
5VSUS
VBAT
0402
0402
EN/PSV2 TON2 VOUT2 VCCA2 PGD2 VSSA2
BST2 ILIM2 VDDP2 PGND2
0603
SOD323 0.1uF 0603
IRF7811AV
2n2/50V 0402
0u1/25V 0603
10u/25V 1210
VOUT2 VOUT 0402 20k0 0402
7k87 0402
VOUT2 FDS6676S 0402 220u/25m 7343 220u/25m 7343
PGOOD 20k0 0402
0402
0603
VSSA2
VSSA2
OTES eeping VSSA1 VSSA2 eparate where ired out.
Figure Reference Design Layout Example
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SC483
POWER MANAGEMENT
layout considered parts, control section referenced VSSA1/2 power section. Looking control section first, locate components referenced VSSA1/2 schematic place these components chip. Connect VSSA1 VSSA2 using either wide (>0.020") trace. Very little current flows chip ground therefore large areas copper needed.
5VSUS VBAT 5VSUS
0402
0402
EN/PSV1 TON1 VOUT1 VCCA1 PGD1 VSSA1
SC483 BST1 ILIM1 VDDP1 PGND1
0603
VOUT1 VOUT 0402 0402
PGOOD 0402 0402 0603
VSSA1 VBAT 5VSUS
5VSUS
0402
0402
EN/PSV2 TON2 VOUT2 VCCA2 PGD2 VSSA2
BST2 ILIM2 VDDP2 PGND2
0603
VOUT VOUT2 0402 20k0 0402
PGOOD 20k0 0402
0402
0603
VSSA2
Figure Components Connected VSSA1 VSSA2
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SC483
POWER MANAGEMENT
Figure Example VSSA 0.020" Traces Figure components referenced VSSA1 VSSA2 have been placed have been connected using 0.020" traces. Note that there separate traces, VSSA1 VSSA2. Decoupling capacitors close possible their pins, VDDP decoupling capacitors C20. should connect ground plane using vias each.
2005 Semtech Corp.
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SC483
POWER MANAGEMENT
VOUT1 VSSA1
VOUT1 VOUT 0402 0402 0402 EN/PSV1 TON1 VOUT1 VCCA1 PGD1 VSSA1
SC483 BST1 ILIM1 VDDP1 PGND1 VSSA1 7343 0402 7343 VOUT1
VSSA1
VOUT2 VOUT 0402 20k0 0402 20k0 0402
EN/PSV2 TON2 VOUT2 VCCA2 PGD2 VSSA2
BST2 ILIM2 VDDP2 PGND2
0402 VSSA2 220u/25m 7343 220u/25m 7343 VOUT2
VSSA2 VOUT2 VSSA2
Figure Differential Routing Feedback Ground Reference Traces Figure VOUT1 VSSA1 routed differential pair from output capacitors back feedback components device. Similarly, VOUT2 VSSA2 routed differential pair from output capacitors back feedback components device.
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SC483
POWER MANAGEMENT
Next, looking power section, schematic Figure below shows power section input loop OUT2:
VBAT IRF7811AV
VOUT2 0402 220u/25m 7343 220u/25m 7343
10u/25V 1210
0u1/25V 0603
2n2/50V 0402 FDS6676S
Figure Power Section Input Loop schematic been redrawn emphasize input loop. highest di/dts occur input loops thus these should kept small possible. input capacitors should placed with highest frequency capacitors closest loop reduce EMI. large copper pours minimize losses parasitics. Exactly same philosophy applies OUT1 power section input loop. Figure below shows example layout power section using these guidelines.
Figure Power Component Placement Copper Pours
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SC483
POWER MANAGEMENT
points power section: there should very small input loop, well decoupled. phase node should large copper pour, compact since this noisiest node. input power ground output power ground should connect directly, through ground planes instead. outputs should share their input capacitors, these should have separate PWR_SRC PGND (component-side) copper pours. output inductors should placed adjacent each other avoid crosstalk. Notice Figure placement resistor bottom output capacitor connect VSSA1/2 each output. Connecting control power sections should accomplished follows (see Figure below): Route VSSA1/2 their related feedback traces differential pairs routed "quiet" layer away from noise sources. Route (low side gate drive, high side gate drive phase node) chip using wide traces with multiple vias using more than layer. These connections short possible loop minimization, with length width ratio less than 20:1 minimize impedance. most critical gate drive, with power ground return path. noisiest node circuit, switching between PWR_SRC ground high frequencies, thus should kept short practical. return path. also noisy node should kept short possible. Connect PGND pins chip directly VDDP decoupling capacitor then drop vias directly ground plane. Locate current limit sense resistors between ILIM pins device.
EN/PSV1 TON1 VOUT1 VCCA1 PGD1 VSSA1
SC483 BST1 ILIM1 VDDP1 PGND1
0402
EN/PSV2 TON2 VOUT2 VCCA2 PGD2 VSSA2
BST2 ILIM2 VDDP2 PGND2
7k87 0402
IRF7811AV
FDS6676S
Figure Connecting Control Power Sections Phase nodes (black) copper islands (preferred) wide copper traces. Gate drive traces (red) phase node traces (blue) wide copper traces (L:W 20:1) short possible, with most critical.
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SC483
POWER MANAGEMENT Typical Characteristics
1.2V Efficiency (Power Save Mode) Output Current Input Voltage
Efficiency IOUT Efficiency VBAT VBAT
1.2V Efficiency (Continuous Conduction Mode) Output Current Input Voltage
IOUT VBAT VBAT
1.2V Output Voltage (Power Save Mode) Output Current Input Voltage
1.220 1.216 1.212 1.208 VOUT 1.204 1.200 1.196 1.192 1.188 1.184 1.180 IOUT VBAT VBAT
1.2V Output Voltage (Continuous Conduction Mode) Output Current Input Voltage
1.220 1.216 1.212 1.208 VOUT 1.204 1.200 1.196 1.192 1.188 1.184 1.180 IOUT VBAT VBAT
1.2V Switching Frequency (Power Save Mode) Output Current Input Voltage
VBAT Frequency (kHz) IOUT
1.2V Switching Frequency (Continuous Conduction Mode) Output Current Input Voltage
VBAT Frequency (kHz)
VBAT
VBAT
IOUT
Please refer Figure Page test schematic (OUT2)
2005 Semtech Corp. www.semtech.com
SC483
POWER MANAGEMENT Typical Characteristics (Cont.)
Load Transient Response, Continuous Conduction Mode, Trace 1.2V, 50mV/div., coupled Trace 20V/div Trace connected Trace load current, 5A/div Timebase: 40µs/div.
Load Transient Response, Continuous Conduction Mode, Zoomed Trace 1.2V, 20mV/div., coupled Trace 10V/div Trace connected Trace load current, 5A/div Timebase: 10µs/div.
Load Transient Response, Continuous Conduction Mode, Zoomed Trace 1.2V, 50mV/div., coupled Trace 10V/div Trace connected Trace load current, 5A/div Timebase: 10µs/div.
Please refer Figure Page test schematic (OUT2)
2005 Semtech Corp. www.semtech.com
SC483
POWER MANAGEMENT Typical Characteristics (Cont.)
Load Transient Response, Power Save Mode, Trace 1.2V, 50mV/div., coupled Trace 20V/div Trace connected Trace load current, 5A/div Timebase: 40µs/div.
Load Transient Response, Power Save Mode, Zoomed Trace 1.2V, 20mV/div., coupled Trace 10V/div Trace connected Trace load current, 5A/div Timebase: 10µs/div.
Load Transient Response, Power Save Mode, Zoomed Trace 1.2V, 50mV/div., coupled Trace 10V/div Trace connected Trace load current, 5A/div Timebase: 10µs/div.
Please refer Figure Page test schematic (OUT2)
2005 Semtech Corp. www.semtech.com
SC483
POWER MANAGEMENT Typical Characteristics (Cont.)
Startup (PSV), EN/PSV Going High Trace 1.2V, 0.5V/div. Trace 10V/div Trace EN/PSV, 5V/div Trace PGD, 5V/div. Timebase: 1ms/div.
Startup (CCM), EN/PSV Floating Trace 1.2V, 0.5V/div. Trace 10V/div Trace EN/PSV, 5V/div Trace PGD, 5V/div. Timebase: 1ms/div.
Please refer Figure Page test schematic (OUT2)
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SC483
POWER MANAGEMENT Outline Drawing TSSOP-28
INDICATOR TIPS
DIMENSIONS INCHES MILLIMETERS
.047 .002 .006 .031 .042 .007 .012 .003 .007 .378 .382 .386 .169 .173 .177 .252 .026 .018 .024 .030 (.039) .004 .004 .008 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 9.60 9.70 9.80 4.30 4.40 4.50 6.40 0.65 0.45 0.60 0.75 (1.0) 0.10 0.10 0.20
SEATING PLANE
GAGE PLANE 0.25
(L1) DETAIL
SIDE VIEW
DETAIL
NOTES: CONTROLLING DIMENSIONS MILLIMETERS (ANGLES DEGREES). DATUMS DETERMINED DATUM PLANE -H3. DIMENSIONS "E1" INCLUDE MOLD FLASH, PROTRUSIONS GATE BURRS. REFERENCE JEDEC MO-153, VARIATION
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SC483
POWER MANAGEMENT Land Pattern TSSOP-28
DIMENSIONS INCHES MILLIMETERS
(.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20
NOTES: THIS LAND PATTERN REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES MET.
Contact Information
Semtech Corporation Power Management Products Division Flynn Road, Camarillo, 93012 Phone: (805)498-2111 (805)498-3804
2005 Semtech Corp. www.semtech.com

Constant on-time fast dynamic response Programmable VOUT range VCCA VB

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