PCF5083 signal processing Objective specification File under Inte
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PCF5083 signal processing
Objective specification File under Integrated Circuits, IC17 1996
Philips Semiconductors
Objective specification
signal processing
CONTENTS 8.2.1 8.2.2 8.2.3 8.3.1 8.3.2 8.3.3 8.4.1 8.4.2 8.4.3 8.4.4 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.5.7 8.5.8 8.6.1 8.6.2 8.8.1 9.1.1 9.1.2 FEATURES GENERAL DESCRIPTION APPLICATIONS ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pinning description OVERVIEW CHIP General role PCF5083 FUNCTIONAL DESCRIPTION TIMER CORE Clock generator ON/OFF Logic Mobile switch-on procedure Mobile switch-off procedure OFF/Watchdog Timer Timing Generator Quarterbit Counter Normal Mode Sleep Mode RF-IC Interface Frequency Setting Channel Gain Control Channel Immediate Control Channel Operation Modes Control Registers IOM®-2 Interface IOM®-2 Clock Generation IOM®-2 Master Unit Monitor Channel Transmitter Protocol Monitor Channel Receiver Protocol Command/Indication Channel Transmitter Command/Indication Channel Receiver Audio Interface External IOM®-2 Interface Interface RS232 Interface power-down Interface General purpose parallel I/O-port Real Time Clock Setting real time clock DESCRIPTION CORE Interface description Baseband Digitizer Interface GMSK Modulator Interface 9.1.3 9.1.4 9.1.5 9.1.6 9.1.7 9.1.8 9.1.9 9.2.1 9.2.2 9.2.3 9.2.4 9.3.1 9.3.2 9.4.1 9.4.2 9.4.3 9.4.4 10.1 10.2 19.1 19.2 19.3 19.4
PCF5083
Audio Data Interface Audio interface Terminal adaptor interface data services System controller interface Event Counter Clock Usage General Purpose Pins Power saving modes Message Interface System Controller Execution baseband procedures Operation (NOP) command Soft resetting Error handling baseband procedures Procedure description Performance baseband procedures Software applications Receiving block Transmitting block search timing synchronization Processing TCH/FS multiframe MICROCONTROLLER INTERFACE Register Timer Core Interrupt Logic RESET JTAG TEST INTERFACE TEST EMULATION MODES LIMITING VALUES CHARACTERISTICS CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS
1996
Philips Semiconductors
Objective specification
signal processing
FEATURES
PCF5083
RS232 interface machine interface controller machine interface power-down control Power supply control logic with Watchdog Timer Real time clock calendar running 32.768 6-bit general purpose port Reduced swing main clock input On-chip derive microcontroller clock 8-bit, 68000 compatible host interface with three interrupt lines Boundary scan interface accordance with "IEEE Standard 1149.1-1990". GENERAL DESCRIPTION
Fabricated CMOS process with 3-layer metal LQFP128 package (SOT420AA-2) operation power Embedded core specific signal processing tasks: 16-bit fixed point 19.5 external clock operation Flexible power-down modes kbyte on-chip program data kbyte on-chip data kbyte on-chip program Fully pre-programmed modules baseband tasks including data channels Dedicated signal processor with application specific hardware for: equalisation, channel encoding/decoding traffic control channels encryption/decryption (A5/1 A5/2 algorithms) Tone side-tone generation Hardware Timer Interface core: Power saving Sleep mode mobiles Programmable TDMA timing power-down signals with 0.25 resolution Three wire serial control fast programming synthesizers IOM®-2 interface external accessories, host software download support Digital Audio Interface (DAI) ORDERING INFORMATION
PCF5083 Signal Processing dedicated VLSI circuit; fabricated CMOS process. been designed baseband signal processing tasks European Global System Mobile telecommunication (GSM). PCF5083 part second generation Philips Semiconductors chip set. PCF5083 consists embedded 16-bit core specific signal processing tasks Timer Interface core which contains many peripheral functions simplify system design. APPLICATIONS
PCF5083 suitable mobile stations hand-helds.
PACKAGE TYPE NUMBER NAME PCF5083H/F2 PCF5083H/001/F2 PCF5083H/5V2/F3 LQFP128 LQFP128 LQFP128 DESCRIPTION plastic profile quad flat package; leads; (PCF5083-2B) plastic profile quad flat package; leads; (PCF5083-2C) plastic profile quad flat package; leads; (PCF5083-3A) VERSION SOT420-1 SOT420-1 SOT420-1
1996
Philips Semiconductors
Objective specification
signal processing
BLOCK DIAGRAM
PCF5083
handbook, full pagewidth
IO1/AEN IO3/IRQN2 IO4/DTX
I/O-PORT
EMBEDDED DSP-CORE
SERIAL X-PORT Y-PORT
HOST PORT
SIXCLK SIXEN SIXD SOXCLK SOXEN SOXD
HR/W HCEN_T HCEN_D DTACK
HOST INTERFACE
IOM-2 INTERFACE AUDIO INTERFACE
ACLK
FRAME_INT COMB_INT HIPR_INT
INTERRUPT LOGIC RXON TXON PDRX1 PDRX2 PDTX1 NPDTX1 NPDTX2 PDBIAS NPDBIAS PDSYN TXKEY1 TXKEY2 GPON1 GPON2 REFON NREFON
CLK13M CLK20M DCLK CLKSEL RSTP CLK32I CLK32O CLK32K
CLOCK GENERATOR
TIMING GENERATOR
ONKEY AUXON LOWVOLT POWON NPOWON RSTO
LOGIC
RF-IC INTERFACE RSTC REAL TIME CLOCK
RFCLK RFEN1 RFEN2 RFEN3 RFEN4 RFDI RFDO
TRSTN TCKIO TSCK1 TSCK2 DSPEN TIMEN
JTAG TEST
INTERFACE
MMIEN MMICLK MMIIREQ
PARALLEL PORT
MGE284
PIO1 PIO5
Fig.1 Block diagram.
1996
Philips Semiconductors
Objective specification
signal processing
PINNING INFORMATION Pinning
PCF5083
HIPR_INT COMB_INT
handbook, full pagewidth
FRAME_INT CLK20M
DTACK HCEN_D
VSS1 CLK13M
SOXCLK SIXD
SIXEN SIXCLK
TSCK2 TSCK1
VDD1
SOXD SOXEN
VSS2 VDD2
VDD1 VSS1
HR/W
ACLK
PIO1 PIO2 PIO3 PIO4 PIO5 TXON RXON VSS1 VDD1 PDRX1 PDRX2 PDTX1 NPDTX1 VDD2 VSS2 NPDTX2 PDBIAS NPDBIAS PDSYN TXKEY1 TXKEY2 DSPEN TIMEN RSTC RSTO VDD1 CLK32O CLK32I VSS1 ONKEY
PCF5083
IO4/DTX IO3/IRQN2 IO1/AEN HCEN_T VSS2 VDD2 TRSTN TCKIO VDDPLL VDD1 VSS1 VSSPLL CLKSEL RSTP DCLK REFON
AUXON LOWVOLT POWON NPOWON CLK32K MMIEN MMIIREQ MMICLK VSS2 VDD1 VSS1 VDD2 RFCLK RFEN1 RFEN2 RFEN3 RFEN4 VDD2 VSSPLL RFDI RFDO NREFON GPON1 GPON2
MGE282
Fig.2 configuration PCF5083-2B PCF5083-2C.
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
CLK13M HIPR_INT
handbook, full pagewidth
COMB_INT FRAME_INT
DTACK HCEN_D
SOXCLK SIXD
CLK20M SOXD
SIXEN SIXCLK
TSCK2 TSCK1
VDD1
SOXEN VSS2
VDD2
VDD1
HR/W
ACLK
VSS1
PIO1 PIO2 PIO3 PIO4 PIO5 TXON RXON VSS1 VDD1 PDRX1 PDRX2 PDTX1 NPDTX1 VDD2 VSS2 NPDTX2 PDBIAS NPDBIAS PDSYN TXKEY1 TXKEY2 DSPEN TIMEN RSTC RSTO VDD1 CLK32O CLK32I VSS1 ONKEY
VSS1
PCF5083
IO4/DTX IO3/IRQN2 IO1/AEN HCEN_T VSS2 VDD2 TRSTN TCKIO VDDPLL VDD1 VSS1 VSSPLL CLKSEL RSTP DCLK REFON
AUXON LOWVOLT POWON NPOWON CLK26M MMIEN MMIIREQ MMICLK VSS2 VDD1 VSS1 VDD2 RFCLK RFEN1 RFEN2 RFEN3 RFEN4 VDD2 VSSPLL RFDI RFDO NREFON GPON1 GPON2
MGD706
Fig.3 configuration PCF5083-3A.
1996
Philips Semiconductors
Objective specification
signal processing
Pinning description SYMBOL PIO1 PIO5 TXON RXON VSS1 VDD1 PDRX1 PDRX2 PDTX1 NPDTX1 VDD2 VSS2 NPDTX2 PDBIAS NPDBIAS PDSYN TXKEY1 TXKEY2 DSPEN TIMEN RSTC RSTO VDD1 CLK32O CLK32I VSS1 ONKEY DESCRIPTION
PCF5083
Test Clock Enable (active HIGH); tied during normal operation. General purpose parallel port (3-state output). Baseband Port Enable (active HIGH, 3-state). Modulator window enable (active HIGH, 3-state). Receiver window enable (active HIGH, 3-state). Ground pin. Supply pin. Receiver Power-down (active HIGH, 3-state). Receiver Power-down (active HIGH, 3-state). Transmitter Power-down (active HIGH, 3-state). Inverted output PDTX1 (active LOW, 3-state). Supply core. Ground core. Transmitter Power-down (active LOW, 3-state). Transmitter power supply Power-down (active HIGH, 3-state). Inverted output PDBIAS (active LOW, 3-state). Synthesizer Power-down (active HIGH, 3-state). Power ramping control (active HIGH, 3-state). Power module control (active HIGH, 3-state). Test Mode Enable (active HIGH). PCF5083-2B includes internal pull-down resistor. PCF5083-2C does include internal pull-down resistor. Timer Test Mode Enable (active HIGH). PCF5083-2B includes internal pull-down resistor. PCF5083-2C does include internal pull-down resistor. Asynchronous Reset real time clock (active LOW, CMOS level Schmitt trigger input). Asynchronous Reset ON/OFF logic (active LOW, CMOS level Schmitt trigger input). Supply pin. 32.768 crystal oscillator output. 32.768 crystal oscillator input. Ground pin. ON/OFF input (active HIGH, CMOS level Schmitt trigger input with internal pull-down resistor).
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
SYMBOL AUXON LOWVOLT POWON NPOWON CLK32K CLK26M MMIEN MMIREQ MMICLK VSS2 VDD1 VSS1 VDD2 RFCLK RFEN1 RFEN2 RFEN3 RFEN4 VDD2 VSSPLL RFDI RFDO NREFON
DESCRIPTION Auxiliary Switch input (active HIGH, CMOS level Schmitt trigger input). battery indication (active LOW, CMOS level Schmitt trigger input). Power Regulator (active HIGH). Power Regulator (active LOW). Asynchronous Reset timer section (active LOW, CMOS level Schmitt trigger input). 32.768 CMOS level output PCF5083-2B PCF5083-2C. CMOS level output PCF5083-3. RS232 transmit data output (open-drain output). RS232 receive data input. RS232 input buffer full indication (active LOW, open-drain output). clock request (active HIGH, CMOS level Schmitt trigger input). clock MHz. IOM®-2 frame pulse (3-state). IOM®-2 clock (3-state). IOM®-2 data input (CMOS level Schmitt trigger input). IOM®-2 data output (open drain output). Ground core. Supply pin. Ground pin. Supply core.
RF-IC interface shift clock (3-state). RF-IC Interface Enable 1(active LOW, 3-state). RF-IC Interface Enable (active LOW, 3-state). RF-IC Interface Enable (active LOW, 3-state). RF-IC Interface Enable (active LOW, 3-state). Supply core. Ground PLL.
RF-IC Interface data RF-IC Interface data (3-state). RF-IC Interface Enable (active HIGH, 3-state). Reference oscillator power-down (active LOW, 3-state).
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
SYMBOL GPON1 GPON2 REFON DCLK RSTP CLKSEL VSSPLL VSS1 VDD1 VDDPLL TCKIO TRSTN VDD2 VSS2 HCEN_T IO1/AEN
DESCRIPTION Sleep mode power-down (active HIGH, 3-state). Sleep mode power-down (active HIGH, open-drain output). Sleep mode power-down (active HIGH, 3-state). External clock input. reset (active with internal pull-down resistor). Timer clock source select. Ground PLL. swing input buffer output. Ground pin. Supply pin.
Reference clock input, swing input kHz. Supply PLL. JTAG port mode select (with internal pull-down resistor). JTAG port data input (with internal pull-down resistor). JTAG port data output. Auxiliary test signal tied during operation. JTAG port reset (with internal pull-down resistor). Supply core. Ground core.
JTAG port clock input (with internal pull-down resistor). Host Interface Enable Timer core (active LOW). general purpose used voice port control (CMOS level I/O). PCF5083-3 internal pull-up resistor however, both PCF5083-2B PCF5083-2C require pull-up resistor. general purpose used voice port control (CMOS level I/O). PCF5083-3 internal pull-up resistor however, both PCF5083-2B PCF5083-2C require pull-up resistor. general purpose Interrupt Request Input (CMOS level I/O). PCF5083-3 internal pull-up resistor however, both PCF5083-2B PCF5083-2C require pull-up resistor. general purpose (CMOS level I/O, external pull-up resistor required). Host Interface Address. Host Interface Data (3-state).
IO3/IRQN2
IO4/DTX
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
SYMBOL VSS1 VDD1 HR/W HCEN_D DTACK SIXCLK SIXEN SIXD SOXCLK VDD2 VSS2 SOXEN SOXD CLK20M FRAME_INT COMB_INT HIPR_INT CLK13M VSS1 VDD1 ACLK TSCK1 TSCK2
Ground pin. Supply pin. Host Interface data (3-state). Host Interface Write Enable.
DESCRIPTION
Host Interface Enable core (active LOW). Host port acknowledge used DTACK from core (active LOW, open-drain output). serial input port clock (CMOS level Schmitt trigger input). serial input port enable. serial input port data. serial output port clock (CMOS level Schmitt trigger input). Supply core. Ground core. serial output port enable. serial output port data (3-state). 19.5 CMOS level output. TDMA frame interrupt (active LOW, open drain output). Combined interrupt (active LOW, open drain output). High Priority Interrupt (active LOW, open drain output). CMOS level output. Ground pin. Supply pin. Audio Interface frame sync signal (3-state). Audio Interface Clock (3-state). Audio Interface Data RS232 clock enabled. Audio Interface Data (3-state). Test Clock tied during normal operation. Test Clock tied VDD2 during normal operation.
1996
Philips Semiconductors
Objective specification
signal processing
OVERVIEW CHIP General
PCF5083
After encryption burst builder generates either Normal Bursts (NB) Access Bursts (AB). bit-stream then modulated with GMSK modulator (Gaussian Minimum Shift Keying) upconverted quadrature mixer MHz. on-chip timer generates power-down control signals receiver, transmitter, P90CL301 System Controller PCF5072 baseband interface System Controller (P90CL301) services interfaces performs signalling software contained layer stack (with O&M, UAP, SIMAP etc). voiceband ADCs DACs PCF5072 perform conversion between analog audio signals digital domain. role PCF5083
chip set's high-level architectural modularity ensures that easily adapted meet various market requirements terms hardware software. Figure simplified block diagram terminal using Philips Semiconductors chip set. receiver converts antenna input signal from down into complex baseband signal consisting in-phase quadrature component (Q). order deal with high dynamic range from -104 dBm, receiver provides input controlled layer software System Controller. complex baseband signal connected input PCF5072 baseband interface This samples components clock (270 kHz) with accuracy approximately bits. equalizer responsible following tasks: Channel impulse response estimation synchronization means training sequence Adaptive channel equalization with modified Maximum Likelihood Sequence Estimation (MLSE) approach that produces bit-by-bit soft decision information (Channel Measurement Information (CMI) Channel impulse response adaption frequency offset estimation. After decryption channel decoder performs convolutional block decoding. Depending logical channel use, there decoding schemes TCH/F (FACCH/F), SACCH SDCCH. speech decoder synthesises audio signal from received stream. Updating comfort noise parameters occurs each time valid Silence Descriptor (SID) received. Comfort noise inserted during periods speech pauses. Substitution muting lost frames implemented. full rate speech encoder collects speech samples 13-bit uniform format (104 kbits/s) compresses them kbits/s according linear predictive coding, long term prediction, Regular Pulse Excitation (RPE-LTP). Discontinuous Transmission (DTX) available (voice activity detection, background acoustic noise). protect data from transmission errors, block convolutional coders form channel encoder. encoding modules relates logical channels (e.g. RACH, TCH/F (FACCH/F), SDCCH/SACCH).
PCF5083 dedicated VLSI circuit offering baseband signal processing tasks European Global System Mobile telecommunication (GSM). PCF5083 applied mobile stations hand-helds. embedded core optimized baseband functions contains on-chip program featuring following tasks: Full rate speech coding/decoding including VAD/DTX ("GSM series" Encryption/decryption according both A5/1 A5/2 algorithms ("GSM Rec. 3.20, 3.21" Burst building supporting access burst normal burst ("GSM Rec. 5.02" Frequency Correction Burst (FCB) detection evaluation Synchronization burst (SCH) detection BCCH monitoring neighbouring cells Channel coding/decoding interleaving/de-interleaving ("GSM Rec. 5.03") for: Broadcast Channels (BCH): SCH, BCCH Common Control Channels (CCCH): PCH, RACH, AGCH Dedicated Control Channels (DCH): SDCCH, SACCH Traffic Channels (TCH): TCH/FS, TCH/F2.4, TCH/F4.8, TCH/F9.6, TCH/H4.8 TCH/H2.4 Associated Control Channels (ACCH): FACCH SACCH
1996
Philips Semiconductors
Objective specification
signal processing
Equalization normal synchronization bursts Power measurement serving neighbouring cells Tone side-tone generation. kbytes free downloading additional software modules e.g. rate adaptation, handsfree, voice recognition. communicates serial ports baseband interface IOM®-2 Interface Voice Port speech data transmission. command data transfer connected microcontroller 8-bit Host Port 68000 compatible Host Interface. port core provides four general purpose lines. Some port lines used dedicated control signals. Timer Interface functions include specific hardware timer couple interface functions which simplify system design keep chip count minimum. Timing Generator provides TDMA burst timing power on/off signals transmitter, receiver, synthesizer, baseband interface timing signals programmed with accuracy quarterbit (1/500 TDMA frame). Their output polarity programmable. RF-IC Interface used program synthesizer. compatible with Philips `Three Wire Bus' other standards. consists clock, data several enable lines transfer data between PCF5083 connected devices. family share same enable line. Their unique address part data stream. different families separate enable lines. PCF5083 includes IOM®-2 Interface connect external accessories e.g. handsfree set. used software download interface provides access Digital Audio Interface during Type Approval. Audio Interface provides connection between local codec, IOM®-2 DSP. ON/OFF Logic performs basic power-up power-down switching function whole mobile. controls supply voltage switches terminal. on/off conditions controlled operators keyboard, voltage battery indication circuit, Watchdog Timer auxiliary switch input general purpose use.
PCF5083
man-machine interface section includes dedicated RS232 interface generates clock keyboard card reader controller. this controller inactive, clock stopped save power. controller requests service, clock switched again. PCF5083 includes 6-bit general purpose parallel port control system functions. port used on-chip provide reset signal core. PCF5083 accessed 8-bit, 68000 compatible Host Interface. Separate chip enable lines Timer core available. core provides signal used DTACK maximum speed operation. Three interrupt lines provided microcontroller. PCF5083 requires clock signals. main clock used internally generate TDMA timing reference clock on-chip PLL. second clock 32.768 used real time clock/calendar, Watchdog Timer provide timing power reducing Sleep mode. During this mode TDMA timing maintained with slow running, high accuracy counters, while timing signals kept inactive save power. on-chip generates three clocks (13, MHz) which manipulated generate internal clock (19.5 MHz), 19.5 output (CLK20M) output (CLK26M, only version used microcontroller other system components. output used Timing Generator addition being back PLL. nominal duty cycle outputs 50%, independent reference clock characteristics. clock outputs used system components requiring symmetric input clock therefore leading reduced tolerance requirements duty cycle reference clock. Other Philips second generation chipset are: P90CL301: 16-bit 68000 compatible microcontroller TDA8005: SIM/MMI-Controller PCF5072: Baseband Interface Audio Codec SA1638: processing SA1620: processing (900 MHz) UMA1019: Synthesizer PCF5075: Power amplifier controller BGY20x: Power Amplifier Module family.
1996
dbook, full pagewidth
1996
SA1620 SA1638
TRANSCEIVER INTERFACE codec GMSK MODULATOR
Philips Semiconductors
BGY20x
PCF5072
signal processing
DUPLEX FILTER
PCF5075 POWER AMPLIFIER CONTROLLER
transceiver control
system control
audio interface (IOM-2)
8-bit parallel port
TDA8005 TIMER CORE
BURST BUILDING ENCRYPTION A5/1 A5/2 SIM, DISPLAY, KEYBOARD SYNCHRONISATION MONITORING EQUALISER DECRYPTION A5/1 A5/2
PCF5083
MEMORY
P90CL301
CORE
CHANNEL ENCODER SPEECH ENCODER
SYSTEM CONTROLLER INTERFACE CHANNEL DECODER TONE SIDE TONE GENERATION SPEECH DECODER
SYSTEM
PERIPHERY
MGE283
Objective specification
PCF5083
Fig.4 Simplified block diagram terminal with PCF5083.
Philips Semiconductors
Objective specification
signal processing
FUNCTIONAL DESCRIPTION TIMER CORE Clock generator
PCF5083
Using output reduces tolerance requirements duty cycle reference clock. core will function with clock clock supplied from DCLK. clock source selected with flags SYSCON_REG; Tables Within core selected clock first halved before use. register selectable future applications should used current implementation this device inverting buffer stage between CLK32I CLK32O, together with external crystal network generates 32.768 clock Timer Core. This clock used real time clock, ON/OFF logic etc. internal MHz, 19.5 2b/2c: 32.768 kHz/ clocks externally available other system components, e.g. microcontroller. clock outputs disabled they used reduce power consumption.
Clock Generator consists swing input buffer reference clock, frequency multiplier 32.768 crystal oscillator. generates MHz, from reference clock. reset input RSTP used bring into low-power state when level. reference clock coupled input CKI. reduced swing input which requires signal range V(p-p) (worst case) operation. clock signal amplified used input clock PLL. Timer core either clocked with reference clock output. clock source selected with input CLKSEL shown Table Table Timer Core clock selection TIMER CORE CLOCK output buffered input
CLKSEL
Table
System Configuration Register (SYSCON); note FLAG LOCK RS232_CLK Reserved lock select. LOCK then lock. LOCK then lock. RS232 interface clock source. RS232_CLK then Timer clock used. RS232_CLK then RS232 clock supplied (pin 125). clock select. This bits select clock frequency; Table CLK32K output enable/disable. CLK32K then CLK32K output enabled. CLK32K then CLK32K output disabled. CLK26M output enable/disable. CLK26M then CLK26M output enabled. CLK26M then CLK26M output disabled. CLK20M output enable/disable. CLK20M then CLK20M output enabled. CLK20M then CLK20M output disabled. CLK13M output enable/disable. CLK13M then CLK13M output enabled. CLK13M then CLK13M output disabled. DESCRIPTION
DSP_CLK1 DSP_CLK0 CLK32K(2) CLK26M(3)
Note
CLK20M CLK13M
Default value after reset 0X00 0000b LOCK undefined). Versions PCF5083-2b PCF5083-2c only. PCF5083-3 only.
1996
Philips Semiconductors
Objective specification
signal processing
Table Selection clock DSP_CLK1 DSP_CLK0 CLOCK DCLK/2 19.5 Reserved
PCF5083
handbook, full pagewidth
CLKSEL SWING INPUT BUFFER RSTP RESET LOCK DCLK 32.768 clock timer core clock core clock timer core
CRYSTAL OSCILLATOR CLK32I CLK32O
CLK13M
CLK32K
CLK20M
SYSCON_REG
MGE287
Fig.5 Clock generator block diagram.
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
handbook, full pagewidth
CLKSEL SWING INPUT BUFFER RSTP RESET LOCK DCLK clock core clock timer core
CRYSTAL OSCILLATOR CLK32I CLK32O 32.768 clock timer core
CLK13M
CLK26M
CLK20M
SYSCON_REG
MGD705
Fig.6 Clock generator block diagram.
1996
Philips Semiconductors
Objective specification
signal processing
ON/OFF Logic 8.2.1 MOBILE SWITCH-ON PROCEDURE
PCF5083
ON/OFF logic performs main power switching function whole mobile. on/off conditions controlled operators keyboard, voltage battery indication circuit, hardware Watchdog Timer auxiliary switch input general purpose use. hardware control interrupt HWCTRL_INT, signalled COMB_INT output (refer Section 10.2), used signal status ON/OFF Logic. inputs DSPEN TIMEN used control Watchdog function. RSTO asynchronous reset lines. inputs ONKEY, AUXON LOWVOLT debounced with time constant 62.5 minimum pulse width safe detection signal transition therefore 62.5 these lines. ON/OFF Logic signals specified Table Table ON/OFF Logic signals DESCRIPTION Input (active HIGH) connected ON/OFF switch operators keyboard. Input (edge sensitive) general purpose use, e.g. used battery charger connect indication ignition sense mobile applications. Input (active LOW) connected external battery indication circuit. Output (active HIGH) connected terminal supply voltage switch. Inverted output signal POWON.
Switching mobile initiated PCF5083 according Table three conditions ONKEY, AUXON Alarm time match become true, corresponding flag register HWCTRL_REG. soon these flags set, signal POWON NPOWON reset. same time HWCTRL_INT interrupt activated. interrupt condition signalled COMB_INT line System Controller relevant COMBINT_REG register (refer Section 10.2). hardware reset clears enable bits COMB_INT interrupt lines. interrupt flags register HWCTRL_REG must cleared System Controller deactivate interrupt condition. flag cleared writing logic location. POWON output main power control signal. soon POWON goes HIGH, mobile powered supply voltage switch. LOWVOLT input asserted LOW, indicating voltage situation, RSTO asserted inhibits mobile switched PCF5083 switched AUXON (HWCTRL_REG[AUXON_LH] AUXON signal remains HIGH, flag HWCTRL_REG[AUXON_LH] must cleared, before PCF5083 enters Power-down mode.
SIGNAL ONKEY AUXON
LOWVOLT POWON
NPOWON Table RST0
Mobile switch-on conditions LOWVOLT ONKEY AUXON ALARM TIME MATCHES CURRENT TIME POWON COMB_INT 3-state 3-state
1996
Philips Semiconductors
Objective specification
signal processing
8.2.2 MOBILE SWITCH-OFF PROCEDURE should noted that:
PCF5083
switch-off request System Controller initiated LOW-to-HIGH transition hold ONKEY longer than second level LOWVOLT. HWCTRL_INT interrupt activated these conditions it's corresponding flag register HWCTRL_REG. next step deactivate POWON signal. Therefore flag HWCTRL_REG[SWOFF] set. SWOFF flag within seconds (see Section 8.2.3) Watchdog Timer expires, POWON deactivated without further interaction. SWOFF flag automatically cleared when mobile switched again. PCF5083 immediately under conditions forced into state with RSTO asserted LOW. Table Mobile switch-off request conditions LOWVOLT COMB_INT
POWON (switch-off state), outputs PCF5083 except POWON NPOWON their high-impedance state. hardware control interrupt (HWCTRL_INT) asserted externally stays internally pending during Sleep mode. timing generator unit forced into wake-up state hardware control interrupt asserted internally. Other interrupt conditions, caused power-down unit real time clock unit, also indicated with hardware control interrupt. These conditions mentioned appropriate sections. interrupt flags register HWCTRL_REG have cleared System Controller deactivate interrupt condition. flag cleared writing logic location.
ONKEY
Table
Mobile switch-off conditions OFF/WATCHDOG TIMER EXPIRES RSTO POWON
HWCTRL_REG[SWOFF]
1996
full pagewidth
1996
supply voltage HWCTRL_REG bits NPOWON POWON VOUT VOLTAGE REGULATORS
Philips Semiconductors
LOWVOLT
AUXON
signal processing
DEBOUNCING 62.5
ONKEY
VOUT
CURRENT TIME
ALARM TIME HWCTRL_INT
other sources
RSTO
POWON other interrupts
MGE288
HWCTRL[SWOFF]
COMB_INT MOBILE
TIMEN
WATCHDOG/OFF TIMER EXPIRY
enable
DSPEN
Wtg/OFF mode retrigger enable retrigger
read HWCTRL_REG
Objective specification
PCF5083
Fig.7 ON/OFF logic functional diagram.
Philips Semiconductors
Objective specification
signal processing
8.2.3 TIMER WATCHDOG TIMER
PCF5083
Timing Generator three modes operation control mobile: Normal mode: this mode mobile fully active. receive their operating voltage, power consumption reduced switching with their power-down inputs. Sleep Idle mode: this mode mobile switched call active. mobile will fully activated mobile originated call requested keyboard. Otherwise parts mobile activated from time time monitor incoming calls. Outside these intervals switched under control PCF5083. this mode main clock switched off. maintain TDMA timing alignment, PCF5083 running temporarily slower clock frequency. Reduced Sleep mode: this mode equal Sleep mode, except that TDMA timing alignment maintained main clock. this chapter following definitions used: (Bit) 3.692 TDMA 1250 13000000 frame) quarterbit (QB) 0.923 TDMA 5000 frame) timeslot (TS) 0.576 (1/8 TDMA frame) Burst term frame refers TDMA frame throughout this section unless otherwise stated. Timing Generator consists quarterbit counter (QBC) counting 5000 quarterbit steps TDMA frame running 1.0833 MHz. This clock switched during Sleep mode. Timing Generator (TG) with output polarity mask registers. sleep quarterbit counter (SQBC). Sleep mode timing generator.
hardware switch-off Watchdog Timer used power-down mobile System Controller lost control more than seconds.
8.2.3.1
Watchdog Timer
After reset signal deactivated, Watchdog Timer starts count. timer expires after seconds, POWON output LOW. prevent this occurring, System Controller must restart timer periodically, reading register HWCTRL_REG within seconds after previous read operation. Watchdog function enabled DSPEN TIMEN LOW. configuration DSPEN TIMEN HIGH disables Watchdog Timer. other settings debugging purposes.
8.2.3.2
Timer
After switch-off request (HWCTRL_INT activated LOWVOLT ONKEY conditions), OFF-Timer starts count. timer expires after seconds, System Controller sets HWCTRL_REG[SWOFF] logic POWON output LOW. OFF-Timer cannot restarted with read access register HWCTRL_REG. some special purposes, e.g. battery charging control handled from System Controller, OFF-Timer stopped after activated from ONKEY LOWVOLT. then resumes watchdog function. OFF-Timer stopped with write access register STOP_REG. data value written this register A5H. Other data values stop OFF-Timer. should noted that: OFF/Watchdog Timer restarted after stop operation either ONKEY LOWVOLT line stays active after stop operation, again recognized after second switch-off time-out 62.5 debouncing period, respectively. Timing Generator
Timing Generator provides TDMA timing power-down signals transmitter, receiver, synthesizer baseband interface
1996
Philips Semiconductors
Objective specification
signal processing
8.3.1 QUARTERBIT COUNTER
PCF5083
output polarity changed setting corresponding register POL_REG logic signals clamped level depending their flag POL_REG setting corresponding register MASK_REG logic After reset with RST, receiver, transmitter synthesizer control lines their inactive level. general timing assumed have receive timeslot (RX) timeslot transmit timeslot (TX) timeslot monitor timeslot (MON) timeslot within TDMA frame. Table Output signals DESCRIPTION
quarterbit counter (QBC) represents timebase mobile. consists 13-bit upcounter. counter directly counts quarterbit steps within TDMA frame. range therefore 4999. beginning every TDMA frame (quarterbit counter state signal FRAME_INT goes LOW, generating interrupt (frame interrupt) System Controller. interrupt line deactivated accessing register MODE0_REG. frame interrupt disabled with MODEx_REG[DISFRAMEINT]
8.3.1.1
Initial Quarterbit Counter Timing Alignment
timing offset between base station mobile station corrected presetting quarterbit counter with estimated correction value. Therefore register QBC_REG with this correction value frame flag QBRCTRL_REG[SYNC] set. frame quarterbit counter loaded from QBC_REG with zeros. duration frame 5000 [QBC_REG] mobile will synchronised beginning frame frame interrupt beginning frame disabled. timing generation disabled during frame SYNC flag cleared after synchronization. System Controller resulting timing looks like frame being extended synchronization being achieved with frame
SIGNAL
Signals receiver section RXON PDRX1 PDRX2 baseband interface receiver enable baseband interface enable receiver power-down receiver power-down
Signals transmitter section TXON TXKEY1 TXKEY2 PDTX1 NPDTX1 NPDTX2 PDPIAS NPDBIAS baseband interface transmitter enable baseband interface enable power amplifier power-down power ramping controller trigger signal transmitter power-down inverted output PDTX1 transmitter power-down power amplifier bias voltage power-down inverted output PDBIAS
8.3.1.2
Maintaining Quarterbit Counter Timing Alignment
Small timing corrections made inserting extracting quarterbit step beginning TDMA frame. Therefore INSERT EXTRACT flag register QBCCTRL_REG have set. These flags cleared after timing alignment performed. 8.3.2 NORMAL MODE
Signal synthesizer PDSYN synthesizer power-down
Normal mode Timing Generator provides output signals specified Table power-down signals NPDTX2, NPDTX1 NPDBIAS active default. other signals active HIGH default. Active HIGH this context means that signals high level during receive transmit burst.
1996
Philips Semiconductors
Objective specification
signal processing
8.3.2.1 Receiver Timing
PCF5083
Receiver Timing characterized Table start duration times defined loading mentioned registers. Table Receiver Timing (note START (QB)(2) DURATION (BIT)
BURST TYPE SIGNAL burst(3)(4) RXON PDRX1(5) PDRX2 PDSYN burst(6)(7)(8) RXON PDRX1(5) PDRX2 PDSYN Notes
RXSTART_REG 127) RXSTART_REG 127) RXSTART_REG 1024 PDRX1_REG 127) 1024 RXSTART_REG 1024 PDRX2_REG 127) 1024 RXSTART_REG 1024 PDSYN_REG 127) 1024
RXLENGTHx_REG 255) RXLENGTHx_REG 255) RXON RXON RXON
MONSTART_REG 4999) MONSTART_REG 4999) MONSTART_REG 1024 PDRX1_REG 4999) 1024 MONSTART_REG 1024 PDRX2_REG 4999) 1024 MONSTART_REG 1024 PDSYN_REG 4999) 1024
RXLENGTHx_REG 255) RXLENGTHx_REG 255) RXON RXON RXON
minimum delay quarterbit periods must programmed between monitor burst start next monitor burst, measured from falling edge RXON next rising edge RXON. (MONSTART_REG 929) 5000 then monitor burst ends next TDMA timeslot (MONSTART_REG 929) 5000. MODEx_REG[RECRX] enable generation burst timing. RXBURSTx_REG selected with flags register MODEx_REG. PDRX1 activated during monitor burst MODEx_REG[RXCAL] flag set. three level measurement mode, second monitor burst generated during timeslot. start position this burst then controlled with register TXSTART_REG. duration given from same register actual monitor burst. (MONSTART_REG +RXBURSTx_REG) 5000 then monitor burst ends next TDMA timeslot (MONSTART_REG RXBURSTx_REG) 5000. MODEx_REG[RECMON] enable/disable generation monitor burst timing.
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
handbook, full pagewidth
5000
FRAME_INT MONSTART_REG TXSTART_REG RXSTART_REG RXON (TX) MONBURSTx_REG
RXBURSTx_REG
MONBURSTx_REG
PDRX1 (PDRX1_REG level measurement (PDRX2_REG PDSYN (PDRX1_REG calibration timing
PDRX2
(PDRX2_REG
(PDSYN_REG
(PDSYN_REG
MGE290
Fig.8 Receiver timing.
1996
Philips Semiconductors
Objective specification
signal processing
8.3.2.2 Transmitter Timing
PCF5083
transmitter timing shown Table start duration times defined loading named registers. Table Transmitter Timing BURST TYPE SIGNAL burst TXON (N)PDTX1,2 (N)PDBIAS TXSTART_REG 2047) TXSTART_REG 2047) TXSTART_REG 1024 PDRX1,2_REG 2047) 1024 TXSTART_REG 1024 PDBIAS_REG 2047) 1024 PDBIAS_REG PDTX1_REG (note TXSTART_REG 1024 (PDTX1_REG 2047) 1024 TXKEY1 TXKEY2 PDSYN Notes timing advance adjusted with value TXSTART_REG. TXBURSTx_REG TXKEYx_REG selected with flag register MODEx_REG. Therefore (N)PDBIAS will always active least prior PDTX1. TXSTART_REG KEYON1_REG 2047) 511) TXSTART_REG KEYON2_REG 2047) 511) TXSTART_REG 1024 PDSYN_REG 2047) 1024 TXKEYx_REG 1023) TXKEYx KEYOFF_REG TXKEYx PDDELAY_REG TXLENGTHx_REG 255) TXON TXKEY PDDELAY_REG TXKEY PDDELAY_REG START (QB)(1) DURATION (QB)(2)
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
handbook, full pagewidth
5000
FRAME_INT TXSTART_REG TXON TXBURSTx_REG TXKEY1 TXKEYx_REG KEYON1_REG TXKEY2 KEYON2_REG PDTX1 (PDTX1_REG NPDTX2 (PDTX2_REG PDSYN (PDSYN_REG PDBIAS (PDBIAS_REG (PDTX1_REG (see text) PDDELAY_REG
MGE291
KEYOFF_REG
Fig.9 Transmit burst timing.
1996
Philips Semiconductors
Objective specification
signal processing
8.3.2.3 Timing Generation
PCF5083
generate burst types required fulfil timing, necessary combine and/or modify basic receive transmit burst sequences. this purpose registers MODE0_REG MODE1_REG exist, containing some flags control burst timing. Both mode registers registers RXSTART_REG, TXSTART_REG MONSTART_REG have additional pipeline stage.The first register stage read written second stage used timing generation. pipelining operation performed (together with frame interrupt generation). Some flags inside mode registers have third pipelining stage allow generation burst which overlaps into next frame. System Controller must registers within frame before programmed timing becomes active. Which register MODE0_REG MODE1_REG actually used described Table MODE0_REG MODE1_REG contain identical flags. Table Mode Registers (MODE0_REG MODE1_REG) FLAG USEMODE DISFRAMENT RXCAL TXLENGTH DESCRIPTION MODE_REGx select. USERMODE then switch MODE_REG0 after next frame. USERMODE then switch MODE_REG1 after next frame. Disable frame interrupt. DISFRAMENT then frame interrupt disabled. calibration timing. RXCAL then calibration timing generated. Register select. state this determines which registers used burst. TXLENGTH then registers TXBURST0_REG TXKEY0_REG used. TXLENGTH then registers TXBURST1_REG TXKEY1_REG used. RXBURSTx_REG select. state these bits determine which RXBURST register used burst; Table RXBURSTx_REG select. state these bits determine which RXBURST register used burst; Table timing enable. then timing enabled. burst timing. SEND burst timing generated. Receiver start-up. RECON receiver start-up sequence burst idle frame generated. burst timing. RECMON burst timing generated. Third level measurement. RECTX then burst timing during timeslot third level measurements generated. burst timing. RECRX burst timing generated.
MONLENGTH1 MONLENGTH0 RXLENGTH1 RXLENGTH0 SEND RECON RECMON RECTX RECRX
Table Register selection burst MONLENGTH1 MONLENGTH0 RXBURST0_REG used. RXBURST1_REG used. RXBURST2_REG used. Undefined during burst. REGISTER SELECTED
1996
Philips Semiconductors
Objective specification
signal processing
Table Register selection burst RXLENGTH1 RXLENGTH0 RXBURST0_REG used. RXBURST1_REG used. RXBURST2_REG used. Undefined during burst. REGISTER SELECTED
PCF5083
8.3.2.4
burst during idle frame
This burst special case burst. used search monitoring during idle frame. RECON set, timing equivalent burst timing generated, with exception that output lines (BEN, RXON, PDRXx etc.) kept active burst. output lines inactive again during first frame with RECMON time, they normally would deactivated burst. During frames between, either RECON RECRX RECTX RECMON RECON SEND must programmed.
8.3.2.5
Register mode switching
Which registers MODE0_REG MODE1_REG used timing generation determined using following rules: After write access MODE0_REG, MODE0_REG active during next frame. After every frame USEMODE flag currently active register determines which register used during next frame, unless there write access MODE0_REG during current frame. e.g. MODE0_REG: USEMODE MODE1_REG: USEMODE programmed during frame This causes following timing: MODE0_REG active during frame MODE1_REG active during frame MODE0_REG active during frame until MODE0_REG being written again.
8.3.2.6
Mode Processing
mode (Discontinuous Transmission) enabled with MODEx_REG[DTX] mode, makes decision whether burst should generated not. condition signalled (generate transmit burst: transmit burst: burst generated, power-down lines TXKEY1/2, (N)PDTX1/2 PDSYN kept inactive already asserted, they inactive again. (N)PDBIAS become inactive with their default delay after (N)PDTX1/2 respective PDSYN they were already asserted, otherwise they also remain inactive. TXON affected from mode.
8.3.2.7
Interface RF-IC
Timing Generator provides trigger signals frequency gain control channels RF-IC interface when quarterbit counter matches either RXSTART_REG, TXSTART_REG MONSTART_REG. Further trigger signals generated gain control channel after every receive burst send contents register DACOFF_REG prior receive burst quarterbit counter matches xxSTART_REG 1024 AGCSTART_REG MON) send contents register DACON_REG (refer Section 8.4). Note, generation trigger signal falls into active burst, trigger signal delayed until current burst.
1996
Philips Semiconductors
Objective specification
signal processing
8.3.2.8 Timing modes Application Examples
PCF5083
Table Timing mode applications FRAME SEND RECON RECMON RECTX RECRX BCCH Detection Receiver start timeslot (MONSTART_REG TDMA frame Receiver Keep receiver Receiver after number samples defined MONSTART_REG, RXLENGTHx_REG number TDMA frames Frequency Estimation Receive during TS0. Frame with Receive during MON, transmit during Frame before idle frame (monitoring) Receive during transmit during receiver defined MONSTART_REG. Idle frame (monitoring) Receiver defined MONSTART_REG RXLENGTHx_REG. Frame with or(1) or(1) Note SYNC burst location defined MONSTART_REG. timing required with MONSTART_REG 5000, MONSTART_REG programmed with 5000 second alternative used. Receive during MON, transmit during Receive during transmit during Idle frame (SYNC burst reading) operation. Receive during MON. Three level measurements Receive during slot. Send access burst Transmit during ASSIGNMENT; REGISTER MODE_REG ACTION
N+1+M
1996
Philips Semiconductors
Objective specification
signal processing
During three level measurement mode burst length receive burst during slot defined same register RXBURSTx_REG used burst. receive frequency must programming channel RF_IC interface. certain operation mode frame Timing Generator programmed with necessary parameters frame this purpose registers RXSTART_REG, TXSTART_REG, MONSTART_REG MODEx_REG have additional pipelining stage. pipelining takes place beginning every TDMA frame with frame interrupt generation. 8.3.3 SLEEP MODE
PCF5083
this mode also main oscillator switched off. maintain TDMA timing alignment, PCF5083 running temporarily slower clock frequency, derived from 32.768 real time clock oscillator. This clock called Sleep Clock (SLCLK). During Sleep mode PCF5083 controls signals specified Table timing these signals detailed Table Sleep mode activated with QBCCTRL_REG[SLEEP] QBCCTRL_REG[SLEEPRED] (the SLEEPRED flag used reduced Sleep mode, below). register SLEEPCNT_REG programmed with number TDMA frames mobile wants sleep minus one. Register FRAMECNT_REG automatically cleared when Sleep mode entered counts number TDMA frames actually slept. 9-bit registers SLEEPCNT_REG FRAMECNT_REG allow maximum Sleep mode period frames. Refer Fig.11 signal flow.
Sleep mode circuitry used reduce power consumption during Idle mode. During Sleep mode, mobile switched call active. mobile only activated read paging blocks neighbour cell monitoring. Outside these intervals, switched save power.
Table Signals controlled PCF5083 during Sleep mode SIGNAL REFON NREFON DSPON GPON1 GPON2 Inverted REFON output. power-down (connected chip). General purpose power-down radio part interface 3-state enable. Active HIGH output. General purpose power-down. Active HIGH output. DESCRIPTION Reference oscillator Active HIGH output.
Table Sleep mode signal timing SIGNAL (N)REFON DSPON GPON1 GPON2 Notes (N)REFON deactivated Sleep mode initiated while sleep clock calibration procedure running (see Section 8.3.3.3), while IOM®-2 interface enabled MMICLK flag register HWCTRL_REG set, indicating that controller requires clock. Maximum before Sleep mode terminates with resolution {[(0 ms}. FRAME NUMBER frame third positive SLCLK edge frame second positive SLCLK edge frame second positive SLCLK edge frame third positive SLCLK edge ACTIVATION SIGNAL SLEEPCNT_REG EQUALS REFON_REG (notes KISSON_REG (note GPON1_REG (note GPON2_REG (note
1996
Philips Semiconductors
Objective specification
signal processing
power-down line only deactivated during Sleep mode corresponding activation register programmed with higher value than register SLEEPCNT_REG. Otherwise power-down line stays active during Sleep mode. output polarity power-down lines changed setting their corresponding register POL_REG logic signals clamped level depending their flag POL_REG setting corresponding register MASK_REG logic Because clock also internally disabled during Sleep mode, PCF5083 cannot accessed with host port. During Sleep mode, burst timing frame interrupt generation stopped registers MODE0_REG MODE1_REG cleared.
PCF5083
signals driven into their high-impedance state independently actual polarity which GPON1 programmed, unless MASK_REG[GPON1] this case outputs driven during Sleep mode.
8.3.3.2
Sleep Quarterbit Counter
Sleep mode, reference oscillator switched reduce power consumption. TDMA timing maintained using sleep quarterbit counter (SQBC), which driven from sleep clock (SLCLK). sleep clock derived from 32.768 real time clock. Upon entering Sleep mode, contents quarterbit counter copied sleep quarterbit counter. After Sleep mode period, sleep quarterbit counter copied back quarterbit counter normal timing performed again. maintain correct timing over hundreds TDMA frames, sleep quarterbit counter incremented with value SQBC_INC equal clock ratio between quarterbit clock sleep clock. This value must very accurate derived using calibration method described Section 8.3.3.3.
8.3.3.1
Transceiver control lines
timing generator signals RXON, TXON, BEN, PDRX1, PDRX2, PDTX1, NPDTX1, NPDTX2, PDBIAS, NPDBIAS, PDSYN, TXKEY1, TXKEY2 device control signals RFCLK, RFDO, RFEN1 RFEN4, Voice Port signals ASF, ACLK 3-stated long signal GPON1 inactive during Sleep mode.
handbook, full pagewidth
1.08325
4999) TIMING GENERATOR NORMAL MODE
RXON TXON PDRX1,2 (N)PDTX1,2 SYNON (N)PDBIAS TXKEY1,2
QBCCTRL_REG[SLEEP] 32768
Enter sleep mode: Copy SQBC SLCLK 8192
Enter normal mode: Copy SQBC reduced sleep mode
SQBC
GPON1 TIMING GENERATOR SLEEP MODE GPON2 DSPON REFON NREFON
MGE289
QBCCTRL_REG[CAL]
1083 8.192
SQBC_INC 255) typ.
Fig.10 Quarterbit counters normal Sleep mode.
1996
Philips Semiconductors
Objective specification
signal processing
8.3.3.3 Sleep Clock Calibration 8.3.3.5
PCF5083
From Sleep mode Normal mode
Since ratio between quarterbit clock sleep clock vary, accurate value increment SQBC_INC obtained with following procedure: QBCCTRL_REG[CAL] enable calibration mode. calibration procedure lasts seconds. After calibration, flag QBCCTRL_REG automatically cleared. After register SQBCINC_REG holds lower bits increment value used verify calibration process. maximum allowed frequency deviation -23.8 +25.4 -63.6 +60.3 32.768 kHz. During calibration procedure, master clock switched off. Therefore, REFON stays active even Sleep mode enabled. calibration procedure repeated from time time, because exact frequency well clock change. After power calibration procedure must performed before Sleep mode activated.
PCF5083 forced into wake-up state hardware control interrupt HWCTRL_INT asserted internally (caused ON/OFF monitor, power-down unit real time clock). interrupt line COMB_INT asserted interrupt stays pending internally until Sleep mode finished. PCF5083 enters wake-up state SLEEPCNT_REG less than equal REFON_REG, Sleep mode terminates normally. Otherwise, SLEEPCNT_REG greater than REFON_REG, REFON_REG copied SLEEPCNT_REG instead SLEEPCNT_REG being decremented next frame boundary Sleep mode terminates with reduced duration. maximum delay from wake-up request wake-up procedure depends setting REFON_REG 294.4 After entering normal mode again FRAMECNT_REG shows number actually slept frames. Sleep mode terminated normally, this number equals number SLEEPCNT_REG previously programmed with. System Controller timing generator mode next frame. With beginning next frame PCF5083 enters normal operation again.
8.3.3.4
Reduced Sleep mode
During reduced Sleep mode mobile timing maintained with quarterbit counter. sleep quarterbit counter used. System Controller timings Sleep mode. signal REFON always active. other Sleep mode signals (GPON1 etc.) activated during Sleep mode. reduced Sleep mode invoked with QBCCTRL_REG[SLEEP] QBCCTRL_REG[SLEEPRED]
1996
handbook, full pagewidth
1996
N+10
Philips Semiconductors
TDMA FRAME
FRAME_INT
SLCLK
signal processing
QBCCTRL[SLEEP] SLEEPCNT_REG
SLEEPCNT_REG
FRAMECNT_REG
REFON_REG REFON_REG GPON1_REG
NREFON
REFON
DSPON DSPON_REG
GPON1
GPON2
GPON2_REG
MGE292
Objective specification
PCF5083
Fig.11 Sleep mode timing.
Philips Semiconductors
Objective specification
signal processing
RF-IC Interface
PCF5083
flag xxGAIN_REG selects either DAC0_REG DAC1_REG transmitted immediately after xxGAIN_REG. These registers hold static data have additional frame pipeline stage like xx_REG xxGAIN_REG. contents register RFCTRL2_REG functionally corresponds contents RFCTRL1_REG. further registers, DACON_REG DACOFF_REG exist. They used power-up power-down gain setting DAC. These registers also hold static data like DACx_REG. transmission three registers controlled from timing generator described Section 8.3.2.7. contents RFCTRL3_REG register functionally corresponds contents RFCTRL1_REG RFCTRL2_REG. (bit registers DAC0_REG, DAC1_REG, DACON_REG DACOFF_REG located register MSB_REG, because limited address space. 8.4.3 IMMEDIATE CONTROL CHANNEL
This block provides serial interface control devices like synthesizer, baseband interface etc. interface upward compatible with `Philips Three Wire Bus'. Compared with Philips extended bidirectional data transfer additional timing modes implemented. interface consists clock (RFCLK), data output (RFDO), data input (RFDI) enable lines (RFEN1 RFEN4 RFE). interface subdivided into three logical channels described below. 8.4.1 FREQUENCY SETTING CHANNEL
registers RX_REG, TX_REG MON_REG during frame with frequency information burst frame Therefore these three registers have pipeline stage. pipelining takes place beginning every TDMA frame together with frame interrupt generation. transmission three registers controlled from timing generator described Section 8.3.2.7. register TX_REG also used monitor burst during timeslot. register RFCTRL0_REG contains four address bits which transmitted with either three data registers. data structure function mode select (SEL0, SEL1) flags contained RFCTRL0_REG described Section 8.4.4. 8.4.2 GAIN CONTROL CHANNEL
registers RXGAIN_REG, TXGAIN_REG MONGAIN_REG during frame with gain control information burst burst frame Therefore these three registers have pipeline stage. pipelining takes place beginning every TDMA frame together with frame interrupt generation. transmission three registers controlled from timing generator described Section 8.3.2.7. gain information sent prior TX-burst. register TXGAIN_REG used monitor burst during timeslot. these registers transmitted used select between registers DAC0_REG DAC1_REG. register RFCTRL1_REG contains four address bits which transmitted with either three data registers. data structure function mode select (SEL0 SEL1) flags contained RFCTRL1_REG described Section 8.4.4.
Immediate Control Channel (IMC) consists registers IMCOUT_REG output direction IMCIN_REG input direction. contents IMCOUT_REG transmitted every time data word written flag SIINT_REG[IMC_OBE] after contents IMCOUT_REG copied shift register. corresponding mask flag SIMASK_REG[IMC_OBE_MASK] set, serial interface interrupt SI_INT activated. Together with IMCOUT_REG being transmitted, data RFDI read into register IMCIN_REG. flag SIINT_REG[IMC_IBF] shift operation. interrupt handling corresponds IMC_OBE flag. interrupt flags cleared when their corresponding register written respectively read. mode flags IMCOUT_REG have same function flags RFCTRLx_REG. four select flags (SEL0 SEL3) correspond enable lines RFEN1 RFEN4. Each enable line activated their corresponding select flag set. Therefore possible activate more than line time.
1996
Philips Semiconductors
Objective specification
signal processing
Table Select flags register IMCOUT_REG SEL0 SEL1 SEL2 SEL3 ACTIVE ENABLE LINE RFSEN1 RFSEN2 RFSEN3 RFSEN4 inhibit flag (INH) IMCOUT_REG controls whether operation inhibited during receive transmit burst indicated with PDRX2 NPDTX2 active. flag operation delayed until PDRX2 NPDTX2 become inactive. flag reset lines don't care. 8.4.4 OPERATION MODES CONTROL REGISTERS Note
PCF5083
Table Selection RC-IF Interface timing modes MODE BITS TRANSFERRED ASSERTED
Transmission corresponding data registers disabled.
data bits transmitted first according Table Table RF-IC Interface data structure MODE channel Note bits consist Table Selection enable lines RFEN1 RFEN4 SEL1 SEL0 ENABLE LINE ASSERTED RFEN1 RFEN2 RFEN3 RFEN4 BITS TRANSFERRED 21(1) LAST
characteristics each channel controlled using contents registers RFCTRL0_REG RFCTRL3_REG. interface programmable, three timing modes selected every data transfer. exact timing Chapter Mode transmission data registers associated with control register disabled. there conflict between different data channels, data transmission scheduled according Table Table RC-IF Interface Control Registers FLAG SEL1 SEL0 OPERATION These bits select timing mode, Table These bits used assert enable lines RFEN1 RFEN1, Table These four bits form address field.
Table Order priority PRIORITY Highest TRANSMISSION frequency setting gain control DACOFF_REG gain control DACON_REG gain control xxGAIN_REG then DACx_REG Lowest Immediate Control Channel
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
TRIGGER handbook, full pagewidth
RXSTART_REG
RX_REG
RFDO
TX_REG TXSTART_REG
MON_REG MONSTART_REG
RFCTRL0_REG SEL1 SEL0
frequency setting channel RXGAIN_REG RXSTART_REG
TXGAIN_REG TXSTART_REG
MONGAIN_REG MONSTART_REG
RFCTRL1_REG SEL1 SEL0 DAC0_REG MSB_REG SHIFT REGISTER
DAC1_REG
RFCTRL2_REG matches ACCSTART_REG condition SEL1 SEL0
DACON_REG
DACOFF_REG RXON inactive
RFCTRL3_REG SEL1 SEL0
gain control channel IMCOUT_REG SEL3 SEL0 SI_INT IMC_OBE flag IMCOUT_REG RFDI immediate control channel SI_INT IMC_IBF flag
MGE285
Fig.12 RF-IC interface register set.
1996
Philips Semiconductors
Objective specification
signal processing
IOM®-2 Interface
PCF5083
PCF5083 includes type Highway like digital Data Voice interface which also available external devices. configured compatible IOM®-2 standard. blocks connected this inside Y-Port core, IOM®-2 master Audio Interface. clock frame synchronization signals (DCL, FSC) either generated internally provided externally. Figure shows general structure IOM®-2 interface.
handbook, full pagewidth
MONITOR MASTER UNITS
IOM-2 CLOCK GENERATION UNIT
SOYD CORE IO1/AEN ACLK AUDIO INTERFACE ACON_REG B_IN A_IN B_OUT A_OUT SI_INT EXT_DVI flag SIYD SIYCLK SIYEN CLOCK_MODE
IOMEXT_EN
DETECT IOM-2 DEVICE
EXTERNAL IOM-2 INTERFACE
MGE286
Fig.13 IOM®-2 Interface structure.
1996
Philips Semiconductors
Objective specification
signal processing
8.5.1 IOM®-2 CLOCK GENERATION
PCF5083
Other clock modes derived from this mode subdividing 1.536 clock period changed. external clock mode IOM®-2 clock frame synchronization signal provided pins. clock this mode multiple with maximum frequency 2.048 4.096 respectively. both internal external clock modes, possible select between double clock cycle mode data single clock cycle mode data with IOMCON_REG[DATA_MODE] flag. double clock cycle mode data output gets valid with first rising edge data input sampled with second negative edge within period. single clock cycle mode data output gets valid with rising edge data input sampled with falling edge within period. Data organized 16-bit timeslots. maximum number timeslots supported internal external clock mode. Table lists possible clock modes.
IOM®-2 clock frame synchronization signals generated internally from reference clock, basis clock runs 1.536 illustrated Fig.14. period consists periods 191). periods 103, 116, 129, 142, 155, wide (high time time 4T), where clock period ns). other periods 8.5T wide (high time 4.5T, time 4T). possible extend reduce consecutive IOM®-2 frame periods each. This results total reduction extension quarterbit (12T ns), which required case timing alignment. This adjustment performed setting either FSCEXT flag extension, FSCRED flag reduction. Both these flags reside QCCTRL_REG. flags automatically reset after adjustment. length frame synchronization pulse (FSC) chosen 8.5T 268.5T. whole IOM®-2 signal generation disabled Clock mode (see Table default after reset). Sleep mode REFON output stays active keep oscillator running long IOM®-2 interface disabled (Clock mode Table IOM®-2 Clock Modes FREQUENCY IOM®-2 interface 1.536 1.536 external clock (2.084 max.) external clock (4.096 max.) 1996
SINGLE(1)/DOUBLE(2) NUMBER CLOCK CYCLE MODE 16-BIT TIMESLOTS
DIVISION RATIO
CLOCK_MODE DATA_MODE FLAGS (DEC.) FLAG
Philips Semiconductors
Objective specification
signal processing
PCF5083
handbook, full pagewidth
CLK13
268.5
periods
periods 103, 116, 129, 142, 155, 168(1), 181(1), 188(2), 189(2)
1.536 Basic Clock Scheme (CLOCK_MODE
timeslot
Double Clock Cycle Mode (DATA_MODE
Single Clock Cycle Mode (DATA_MODE
MGE293
Fig.14 IOM®-2 Interface timing diagrams.
1996
Philips Semiconductors
Objective specification
signal processing
8.5.2 IOM®-2 MASTER UNIT
PCF5083
full handshake implemented accordance with IOM®-2 specifications. transmitter delay data transmission case System Controller does provide data time. maintained until MONx_REG programmed with data. MONx_OBE flag cleared with data write access. receiver delays data transmission sends data acknowledge. this case maintained data byte repeated subsequent frames. request data from controller MONx_OBE flag soon data acknowledge from receiver detected except first byte reception. Here transition HIGH-to-LOW detected. This leaves controller approximately program MONx_REG with next byte without delay within handshake procedure except first byte. transmission sent TEOMx flag IOMCTRL_REG when MONx_OBE after last byte transmission. transmission sent least subsequent frames) after acknowledge last byte completely received. After transmission sent transmitter state machine idle state. TEOMx flags also used initialize transmitter state machine. flag state machine from state into idle state. TEOMx flag automatically cleared. abort request received, transmitter accordance with specifications, sends transmission sequence enters idle state. MONx_OBE flag set. abort request indicated with RABORTx flag IOMCTRL_REG. RABORTx also asserts IOM®-2 interrupt (MONx_OBE_EN used enable bit) indicate abort System Controller. flag reset with MONx_OBE flag.
IOM®-2 master unit implements monitor channels channel masters. handshake protocols implemented accordance with IOM®-2 standard with exception constraints mentioned below. data structure 16-bit monitor timeslot also implemented according IOM®-2 standard with exception that timeslot location fixed within IOM®-2 frame. data structured 16-bit timeslots (see Table timeslot master works selected with flags IOMCON_REG[MASTERx_TS0 MASTERx_TS3]. These bits binary encode timeslot number with timeslot being indicated with rising edge FSC. Both monitor masters independently enabled with flags IOMCON_REG[MASTERx_EN]. every serviced channel data register (MON0_REG, MON1_REG, CI0_REG CI1_REG) with input output buffer stage state machine receive transmit direction exists. every register IOMFLAG_REG holds flags indicate input data buffer full output buffer empty condition. flags xxx_IBF (input buffer full) xxx_OBE (output buffer empty) with equal register name. these flags together with corresponding enable flag IOMEN_REG IOM®-2 interrupt activated (refer Section 10.2). flags reset with read respectively write operations their corresponding data register. 8.5.3 MONITOR CHANNEL TRANSMITTER PROTOCOL
After IOMCON_REG[MASTERx_EN] logic transmitter state machine idle state. pattern sent output buffer empty flag MONx_OBE set. flag sent logic accordance with IOM®-2 specifications. initiate message transmission System Controller program MONx_REG with first byte message. MONx_OBE flag cleared with data write access.
Table Data structure 16-bit IOM®-2 monitor master timeslot C/IX
MONX
1996
Philips Semiconductors
Objective specification
signal processing
8.5.4 MONITOR CHANNEL RECEIVER PROTOCOL 8.5.6
PCF5083
COMMAND/INDICATION CHANNEL RECEIVER
After IOMCON_REG[MASTERx_EN] logic receiver state machine idle state waits first byte transmission. input buffer full flag MONx_IBF cleared. flag sent logic accordance with IOM®-2 specification. After reception data byte MONx_IBF flag System Controller read data from MONx_REG. full handshake implemented accordance with IOM®-2 specification. receiver delay data transmission input buffer full System Controller does read buffer time. this case maintained until MONx_REG read. MONx_IBF flag cleared with data read access. transmitter delay data transmission delays next byte valid indication. this case maintained subsequent frames. transmission detected receiver state machine gets into idle state. REOMx flag IOMCTRL_REG set. REOMx also asserts IOM®-2 interrupt (IOMx_IBF_EN used enable bit) indicate transmission System Controller. REOMx flag cleared with dummy read MONx_REG. send abort request TABORTx flag IOMCTRL_REG set. receiver state machine enters idle state. TABORTx flag reset after procedure. Time-outs detected. Collision detection maximum speed case supported. 8.5.5 COMMAND/INDICATION CHANNEL TRANSMITTER
received data different from data input buffer data pattern loaded into data input buffer. CI0(1)_IBF flag cleared set. during next frame received data identical data stored data input buffer buffer contents considered valid CI0(1)_IBF flag set. System Controller fetch data within next otherwise data might lost. 8.5.7 AUDIO INTERFACE
Audio Interface provides translation 16-bit IOM®-2 timeslot into timing according Chapter receive transmit direction. operation interface configurable with flags register ACON_REG. Audio Interface enabled disabled under control core with IO1/AEN Otherwise data word sent both directions. With ACON_REG[TRANS_EN] transparent mode selected. this mode internal IOM®-2 signals directly connected ACLK AFS. directly connected A_OUT B_OUT A_IN B_IN. following should noted: flags register ACON_REG should only changed when Audio Interface disabled with IO1/AEN Audio Interface only operate transparent mode timing mode selected which results only 16-bit timeslot IOM®-2 side frequency ACLK must chosen such that complete transmission 16-bit word Audio Interface does exceed duration timeslots, with equal number 16-bit timeslots IOM®-2 side Jitter allowed ACLK audio data might corrupted.
data words sent least subsequent frames. transmitter runs data last data word repeated. flags CI0(1)_IBF CI0(1)_OBE provided indicate input/output register status.
Table Audio Interface configuration register (ACON_REG) TX_EN TX_DEST RX_EN RX_SOURCE TX_SLOT0 TX_SLOT3 RX_SLOT0 RX_SLOT3 TRANS_EN FLAG OPERATION set) Enable transmit direction (ADI IOM®-2). Select output IOM®-2. logic selects A_OUT; logic selects B_OUT. Enable receive direction (IOM®-2 ADO). Select input from IOM®-2. logic selects A_IN; logic selects B_IN. IOM®-2 timeslot translated from transmit section 15). IOM®-2 timeslot translated from receive section 15). Enable transparent mode.
1996
Philips Semiconductors
Objective specification
signal processing
8.5.8 EXTERNAL IOM®-2 INTERFACE
PCF5083
8.6.1.2 Receive
This block provides IOM®-2 interface external devices accessories e.g. digital handsfree equipment data interfaces etc. used interface system simulator during type approval. external IOM®-2 interface (DCL, FSC, only enabled flag IOMCON_REG[IOMEXT_EN] set. Otherwise, unless external clock mode, outputs DCL, their high-impedance state input don't care (default after reset). external clock mode flag IOMCON_REG[IOMEXT_EN] flag only controls data lines inputs this mode independently from state flag. flag IOMCON_REG[IOMEXT_INV] set, I/Os external IOM®-2 interface inverted allow external inverting driver circuit. external IOM®-2 interface disabled with IOMCON_REG[IOMEXT_EN] input externally pulled-up will monitored level. external device pull-down this line register itself. detected, SI_INT interrupt activated with flag SIINT_REG[EXT_IOM] set. flag therefore interrupt condition automatically cleared after IOMCON_REG[IOMEXT_EN] set. Interface
incoming serial data stream clocked into register RXD_REG. SIINT_REG[RXD_IBF] after data byte received SI_INT interrupt generated. state RXD_IBF flag available MMIEN output used implement hardware handshake TDA8005. SIINT_REG[PAR_ERR] flag signals parity error will updated when RXD_IBF flag goes active. RXD_IBF flag therefore interrupt condition cleared automatically after reading register RXD_REG. Both interrupt conditions disabled with corresponding mask flags SIMASK_REG. flag handling remains same described. output MMIEN logic long HWCTRL_REG[MMICLK] Note that PAR_ERR used interrupt condition. 8.6.2 POWER-DOWN INTERFACE
power-down interface controls power consumption controller (MMIC) TDA8005 halting main clock. following signals used: MMICLK: clock output, main clock MMIC MMIREQ: clock request input. wake-up power-down procedures are: Force MMIC into power-down mode: HWCTRL_REG[MMICLK] stop clock. MMICLK output held output MMIEN RS232 interface HIGH. Wake-up MMIC System Controller: HWCTRL_REG[MMICLK] activate MMICLK. Wake-up MMIC after keyboard card reader activity: this case MMIC generates LOW-to-HIGH transition MMIREQ. flags MMIREQ MMICLK register HWCTRL_REG will MMICLK output activated. timing generator unit (SGU) Sleep mode, wake-up request issued force into wake-up state. wake-up state HWCTRL_INT MMICLK activated. MMIREQ flag explicitly cleared System Controller.
PCF5083 provides RS232 Power-down interface fully support controller TDA8005. 8.6.1 RS232 INTERFACE
This block provides full RS232 interface with fixed protocol configuration. shift clock derived from clock normal operation. test purposes clock applied input used SYSCON_REG[RS232_CLK] set. clock divided derive shift clock. This results baud rate 22569.44 Baud MHz. receiver works with oversampling
8.6.1.1
Transmit
After writing register TXD_REG, register content serially clocked out. SIINT_REG[TXD_OBE] flag SI_INT interrupt generated (refer Section 10.2). flag therefore interrupt condition cleared after writing next data byte register TXD_REG.
1996
Philips Semiconductors
Objective specification
signal processing
should noted that: LOW-to-HIGH transition MMIREQ detected independent HWCTRL_REG[MMICLK] respectively. long HWCTRL_REG[MMICLK] REFON output stays active even enters Sleep mode. During power-up reset indicated with active LOW, HWCTRL_REG[MMICLK] MMICLK activated. General purpose parallel port
PCF5083
flag HWCTRL_REG[SECINT] reset, hardware control interrupt (HWCTRL_INT, refer Section 10.2) asserted with HWCTRL_REG[CLOCK] flag every time MIN_REG incremented. Otherwise flag set, interrupt asserted every time SEC_REG incremented. 8.8.1 SETTING REAL TIME CLOCK
PCF5083 includes 6-bit general purpose parallel port. Every line, except PIO0, corresponding data PORTDATA_REG data direction PORTDDIR_REG. bits PORTDATA_REG directly represent state pins port configured input. Otherwise port configured output, data written PORTDATA_REG directly represents state port line. logic PORTDDIR_REG configures port line output, logic input. PIO0 configured output only. used internally drive reset input core. Real Time Clock
real time clock, SETCLOCK HWCTRL_REG must logic flag then polled until read logic again. This action last After SETCLOCK detected, clock registers written. After write operation SETCLOCK reset again. register setting takes place immediately after hardware control interrupt asserted, clock registers written without polling SETCLOCK flag (SETCLOCK still prior reset after register write operation). following should noted: Sleep mode invoked, wake-up request generated every time hardware control interrupt asserted. increase performance recommended interrupt facility rate second during Sleep mode. alarm function implemented using registers SEC_A_REG, MIN_A_REG, HOUR_A_REG, DAY_A_REG, DATE_A_REG, MONTH_A_REG YEAR_A_REG. contents these registers equals corresponding counters, hardware control interrupt asserted with flag HWCTRL_REG[ALARM] set. bits registers (07H case DAY_A_REG) don't care comparison. alarm function activated while switched off, powered described Section 8.2.1. RSTC activated clock counters reset 00H, except date month which 01H. MONTH_A_REG avoid alarm condition. other alarm registers undefined.
real time/alarm time clock unit included timer core. clock unit driven from 32.768 crystal oscillator. leap year function included. clock function utilizes registers/counters specified Table Table Clock function registers/counters REGISTERS/ COUNTERS SEC_REG MIN_REG HOUR_REG DAY_REG DATE_REG MONTH_REG YEAR_REG CLOCK FUNCTION seconds, 4-bit digits encoded minutes, 4-bit digits encoded hours, 4-bit digits encoded day, Monday Sunday date, 4-bit digits encoded month, 4-bit digits encoded year, 4-bit digits encoded
1996
Philips Semiconductors
Objective specification
signal processing
9.1.1 DESCRIPTION CORE Interface description BASEBAND DIGITIZER INTERFACE
PCF5083
Time slots numbered from whereby slot defined receive time slot mobile station (see Section 8.3.2.1). Each component pair represented 16-bit two's complement numbers, shown Table with sign (I15 Q15) fractional bits. range components specified below. Range: -1.0 +1.0 should noted that limited PCF5072 only MSBs contain meaningful data. components defined follows: f(A) f(A) where magnitude phase antenna input signal. function f(A) describes characteristic applied (see Fig.16).
PCF5083 serial input port used reception off-air data from baseband digitizer PCF5072 (BBD). port consists Serial Input Data signal (SIXD), containing data bits, first Serial Input Clock signal (SIXCLK), running Serial Input Enable signal (SIXEN), active LOW. Regularly spaced samples sent with periodicity 1/(2 270.833 kHz); (twice period). number incoming samples expected depends upon current status which operating (see Table 27). column START SAMPLING indicates which time slot time slot TDMA frame sampling pairs start. Table Time window output data OPERATION STATUS Reception normal burst Reception synchronization burst Reception normal burst Level measurement neighbouring BCCH offset measurement search Note
START SAMPLING
NUMBER PAIRS 1404(1) 156)
value 1404 search default value after reset. changed FB_search_fcb_init procedure. Table component format
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
handbook, full pagewidth
SIXCLK MHz)
SIXEN (2.27 kHz)
SIXD
MGE294
Fig.15 Baseband Timing diagram.
handbook, full pagewidth
MGE295
output (dB)
-120 -100 absolute input level (dBm)
Fig.16 characteristic.
1996
Philips Semiconductors
Objective specification
signal processing
9.1.2 GMSK MODULATOR INTERFACE Table Access burst format BITS 9.1.3 NUMBER BITS
PCF5083
PCF5083 serial output port used transmit coded, interleaved formatted bits GMSK modulator PCF5072 baseband interface port consists Serial Output Data signal (SOXD) Serial Output Clock signal (SOXCLK), running 270.83 Serial Output Enable signal (SOXEN), active LOW. clock directly used external shift clock, therefore external buffering transmission data necessary. PCF5083 general purpose used enable disable transmitter during DTX. transmitter enabled. transmitter disabled. sampled TDMA timer beginning transmit burst period.
DESCRIPTION dummy bits (set logic BN87 accordance with "GSM Rec. 05.02" dummy bits (set logic
AUDIO DATA INTERFACE
PCF5083 serial port connected on-chip IOM®-2 interface Timer Core. used connection following devices: codec PCF5072 Digital Audio Interface (DAI), used during type approval Terminal adaptor data services External digital answering machine. physical transfer order IOM®-2 16-bit, first. following signals used: Serial data input SIYD Serial data output SOYD Serial shift clock SIYCLK Frame synchronization input SIYEN. default reads writes first 16-bit timeslot IOM®-2 interface. This changed with appropriate software command 16-bit timeslot. Input output from/to IOM®-2 performed FIFOs named audio input audio output FIFO. These FIFOs implemented firmware. Each FIFO able store 16-bit samples.
9.1.2.1
Burst format
Tables show format normal access burst produced DSP. period leading bits allows power amplifier ramp-down ramp-up. Table Normal burst format BITS NUMBER BITS DESCRIPTION dummy bits (set logic BN147 accordance with "GSM Rec. 05.02"
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
handbook, full pagewidth
SOXCLK
SOXD
b(0)
b(1)
b(2)
b(154)
b(155)
SOXEN (DTX) valid
MGE296
setup time: hold time: 3.69
Fig.17 GMSK modulator timing diagram.
handbook, full pagewidth
SIYCLK
SIYEN
SIYD SOYD
MGE297
Fig.18 Audio Interface timing (default).
1996
Philips Semiconductors
Objective specification
signal processing
9.1.4 AUDIO INTERFACE
PCF5083
9.1.4.1
Downlink speech frame format
Every speech decoder outputs speech frame consisting 16-bit words. These speech frames transmitted codec. speech frame format described Table Table Field descriptions FIELD SAMPLE PARM DESCRIPTION This field contains 13-bit linear audio samples two's complement (MSB sign bit) representation defined "GSM recommendation 06.01". Whenever speech decoder active PARM field used transfer speech parameters D260) together with some frame classification information (see Table currently selected test mode (see Table DSP. terms (speech flag), (silence descriptor) (muting flag) defined "GSM Rec. 06.31" (DTX full-rate speech TCH). indicates, whether speech codec operating handsfree mode not. bits intended evaluated external Digital Audio Interface (DAI). They determine currently selected test mode during type approval described "GSM Rec. 11.10, Section III.1.2.4.7". passed TMODE file operation_mode parameter speech decoder procedure. Refer Section 9.3.1 more information. Synchronization signal external (test) equipment. Marks speech frames. Each falling edge SYNC marks beginning output speech frame with constant offset internal module processing time rising edge SYNC marks input speech frame. soon audio output data available this always reflects internal speech frame timing independently other processing tasks DSP.
SYNC
Table Downlink speech frame format SAMPLE FIELD OFFSET used D258 D260 D257 D259 audio sample audio sample audio sample audio samples audio sample audio sample audio sample audio sample audio samples audio sample audio sample PARM FIELD SYNC FIELD
1996
Philips Semiconductors
Objective specification
signal processing
Table Frame classification FRAME TYPE Speech frame Transmitted Repeated Silence frame Reserved Table Test mode selection DESCRIPTION Normal operation tested divide DAI) Test speech decoder/DTX functions (downlink) Test speech encoder/DTX functions (uplink) Test acoustic devices ADCs DACs Reserved SID2
PCF5083
other codes
other codes
1996
Philips Semiconductors
Objective specification
signal processing
9.1.4.2 Uplink Speech Frame Format
PCF5083
Every speech encoder requires speech frame consisting 16-bit words. speech frame format described Table Each word consists three fields shown Table Table Field descriptions FIELD SAMPLE PARM DESCRIPTION This field contains 13-bit linear audio samples two's complement (MSB sign bit) representation defined "GSM recommendation 06.01". bypass_flag SP_encoder_TCHFS procedure (see Section 9.3.1) speech encoder bypassed bits D260 used coded speech frame. bypass_flag speech encoder only bypassed, control flag SP_R flag indicates, either speech frame (SP_R silence frame (SP_R transmitted. Before external device could send meaningful information, synchronize rising edge SYNC (see Table 43). RESet Decoder, RESet Encoder. test mode (see Section 9.3.1 speech coding procedures) these bits behave reset signal speech decoder/encoder LOW-to-HIGH transition, RESD/RESE must remain least
RESD, RESE
Table Uplink speech frame format SAMPLE FIELD OFFSET RESE used RESD RESD audio sample audio sample audio samples audio sample audio sample audio sample audio sample audio samples audio sample audio sample D258 D260 PARM FIELD RESD FIELD
used SP_R D257 D259
1996
Philips Semiconductors
Objective specification
signal processing
9.1.5 TERMINAL ADAPTOR INTERFACE DATA SERVICES
PCF5083
Data transfer IOM®-2 done form data frames. Each data frame contains 16-bit samples consists user data block containing user data to/from channel codec control data block containing control data to/from System Controller. firmware (the procedures MP_read_data_frame MP_write_data_frame, Section 9.3.1) performs multiplexing demultiplexing user control data. Control data forwarded System Controller terminal adaptor, respectively without modification interpretation DSP. fully integrated solution architecture data services preparation, which rate adaptation realised additional software module, Hayes command interpretation part P90CL301 software data communications done RS-232 port P90CL301.
9.1.5.1
General description
Fig.19 block diagram data service architecture using PCF5083 shown. terminal connected external terminal adaptor IOM®-2 interface (serial port PCF5083. Channel coding accordance with "GSM recommendation 05.03" done DSP, rate adaptation e.g. Hayes command handling done terminal adaptor. There types information that have exchanged between terminal adaptor terminal: User data that transmitted interface. This input output channel codec PCF5083 Control data which exchanged between System Controller terminal adaptor.
handbook, full pagewidth
P90CL301
LAYER MMI,
PCF5083 DEVICE DRIVER
control data
PCF5083
CHANNEL CODEC user data DEMUX IOM-2 user control data TERMINAL ADAPTOR
MGE317
TERMINAL
Fig.19 Block diagram Data Services with PCF5083.
1996
Philips Semiconductors
Objective specification
signal processing
9.1.5.2 Format downlink data frames
PCF5083
downlink data frame format described Table Each word consists four fields; these described Table Table Field descriptions FIELD DATA SYNC DESCRIPTION Depending contents field (see Table 38), this field contains data byte belonging user control data block auxiliary control information terminal adaptor. This field classifies 16-bit samples described Table Synchronization signal external (test) equipment. Marks speech frames. Each falling edge SYNC marks beginning output speech frame with constant offset internal module processing time rising edge SYNC marks input speech frame. soon audio output data available this always reflects internal speech frame timing independently other processing tasks DSP. This field used external devices distinguish between audio data frames. INFO field word#2 contains called frame identification (FID); Table
INFO
Table Classification 16-bit samples FIELD DESCRIPTION data field contains valid data byte belonging either user control data block. data field contains auxiliary control information that used terminal adaptor synchronization purposes. Indicates that data field contains invalid data, which should ignored. Reserved future expansion. used DSP.
Other combinations
Table Valid values FID(1) Note Binary value; don't care. audio frame data frame reserved FRAME TYPE
1996
Philips Semiconductors
Objective specification
signal processing
Table Downlink data frame format DATA FIELD OFFSET 0XFF 0XFF 0XFF 0XFF 0X01 0XFF 0XFF 0X00 0XFF 0XFF 0XFF 0XFF 0XFF U[1] 0XFF 0XFF U[2] 0XFF U(LU 0XFF 0XFF U(LU) 0XFF 0XFF 0XFF 0XFF C[0] 0XFF 0XFF C[1] 0XFF C(LC 0XFF 0XFF C(LC 0XFF FIELD INFO FIELD SYNC FIELD
PCF5083
DESCRIPTION Header: used terminal adaptor synchronization purposes
User data block. block length. Valid range:
Control data block; block length. Valid range:
1996
Philips Semiconductors
Objective specification
signal processing
9.1.5.3 Format uplink data frames
PCF5083
uplink data frame format described Table Each word consists four fields; these described Table Table Field descriptions FIELD DATA SYNC, INFO DESCRIPTION This field contains data bytes user data block control data block. Only words with 00001 contain valid data fields (see Table 42). This field classifies 16-bit samples described Table uplink direction, these fields without meaning.
Table Classification 16-bit samples FIELD DESCRIPTION data field contains valid data byte belonging either user control data block. data field contains auxiliary control information that used terminal adaptor synchronization purposes; note Indicates that data field contains invalid data, which should ignored. Reserved future expansion. used DSP.
Other combinations Note
external terminal adaptor insert position arbitrary number fill words with 11111. Table Uplink data frame format DATA FIELD(1) OFFSET U[0] U[1] U(LU U(LU C[0] C[1] C(LC C(LC Notes don't care. FIELD INFO FIELD SYNC FIELD User data block; this block contains modified CCITT frame accordance with "GSM Rec. 05.03". used input data channel encoder. block length Valid range: Control data block; first byte block length. also zero. This block forwarded System Controller. Valid range:
DESCRIPTION
1996
Philips Semiconductors
Objective specification
signal processing
9.1.5.4 User data block formats
PCF5083
Error Rate calculated using following equation: rxqual_ber_low rxqual_ber_high -4096 Tables show user data block format full-rate half-rate data channels running different baud rates. Note that TCH/H4.8 format used half-rate data channels kbits/s. equivalent format used TCH/F9.6 (see Table 46).
following sections user data block formats data channels defined "GSM Rec. 05.03" explained. formats uplink downlink directions identical with exception that three additional bytes transmitted downlink direction: first byte contains facch_flag. This flag indicates whether channel decoder decoded FACCH (facch_flag (facch_flag other bytes, rxqual_ber_low rxqual_ber_high, indicate estimated Error Rate (BER) channel decoder input.
Table TCH/F2.4 following table shows user data block full rate data channel kbit/s (and less). data bits shown correspond modified CCITT V.110 36-bit frames. DESCRIPTION Block size Valid flag Modified CCITT frame OFFSET Modified CCITT frame FACCH flag rxqual_ber DOWNLINK DATA rb16 rb24 rb17 rb32 rb25 rb36 rb33 rb16 rb24 rb17 rb32 rb25 rb36 rb33 facch_flag rxqual_ber_low rxqual_ber_high UPLINK DATA rb16 rb24 rb17 rb32 rb25 rb36 rb33 rb16 rb24 rb17 rb32 rb25 rb36 rb33
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
Table TCH/F4.8 following table shows user block data format full rate data channel kbit/s. data bits shown correspond modified CCITT V.110 60-bit frames according "GSM 21". DESCRIPTION Block size Valid flag Modified CCITT frame OFFSET Modified CCITT frame FACCH flag rxqual_ber DOWNLINK DATA rb16 rb24 rb17 rb32 rb25 rb40 rb33 rb48 rb41 rb56 rb49 rb60 rb57 rb16 rb24 rb17 rb32 rb25 rb40 rb33 rb48 rb41 rb56 rb49 rb60 rb57 facch_flag rxqual_ber_low rxqual_ber_high UPLINK DATA rb16 rb24 rb17 rb32 rb25 rb40 rb33 rb48 rb41 rb56 rb49 rb60 rb57 rb16 rb24 rb17 rb32 rb25 rb40 rb33 rb48 rb41 rb56 rb49 rb60 rb57
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
Table TCH/F9.6 following table shows full rate data channel kbit/s. data bits shown correspond modified CCITT V.110 60-bit frames accordance with "GSM 04.21". non-transparent services those four blocks shall align with 240-bit frame. valid_flag indicates, whether data block contains valid data (valid_flag (valid_flag used DTX. DESCRIPTION Block size Valid flag; note Modified CCITT frame OFFSET Modified CCITT frame Modified CCITT frame Modified CCITT frame DOWNLINK DATA rb16 rb24 rb17 rb32 rb25 rb40 rb33 rb48 rb41 rb56 rb49 rb60 rb57 rb16 rb24 rb17 rb32 rb25 rb40 rb33 rb48 rb41 rb56 rb49 rb60 rb57 rb16 rb24 rb17 rb32 rb25 rb40 rb33 rb48 rb41 rb56 rb49 rb60 rb57 rb16 rb24 rb17 rb32 rb25 rb40 rb33 rb48 rb41 rb56 rb49 rb60 rb57 UPLINK DATA valid flag rb16 rb24 rb17 rb32 rb25 rb40 rb33 rb48 rb41 rb56 rb49 rb60 rb57 rb16 rb24 rb17 rb32 rb25 rb40 rb33 rb48 rb41 rb56 rb49 rb60 rb57 rb16 rb24 rb17 rb32 rb25 rb40 rb33 rb48 rb41 rb56 rb49 rb60 rb57 rb16 rb24 rb17 rb32 rb25 rb40 rb33 rb48 rb41 rb56 rb49 rb60 rb57
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
DESCRIPTION FACCH flag Rxqual_ber
OFFSET
DOWNLINK DATA facch_flag rxqual_ber_low rxqual_ber_high
UPLINK DATA
Table TCH/H2.4 following table shows user data block half rate data channel kbit/s (and less). data bits shown correspond modified CCITT V.110 36-bit frames according DESCRIPTION Block size Valid flag Modified CCITT frame OFFSET Modified CCITT frame Modified CCITT frame Modified CCITT frame FACCH flag Rxqual_ber DOWNLINK DATA rb16 rb24 rb17 rb32 rb25 rb36 rb33 rb16 rb24 rb17 rb32 rb25 rb36 rb33 rb16 rb24 rb17 rb32 rb25 rb36 rb33 rb16 rb24 rb17 rb32 rb25 rb36 rb33 facch_flag rxqual_ber_low rxqual_ber_high UPLINK DATA rb16 rb24 rb17 rb32 rb25 rb36 rb33 rb16 rb24 rb17 rb32 rb25 rb36 rb33 rb16 rb24 rb17 rb32 rb25 rb36 rb33 rb16 rb24 rb17 rb32 rb25 rb36 rb33
1996
Philips Semiconductors
Objective specification
signal processing
9.1.6 SYSTEM CONTROLLER INTERFACE
PCF5083
PCF5083 parallel port used communication with P90CL301 System Controller (SC) which compatible with 68000 family microcontrollers. Details about interfacing described Chapter host port three internal registers: 16-bit parallel input register (write-only) 16-bit parallel output register (read-only) PIOS; 5-bit parallel Status/Control register (see Table 50). 16-bit words registers transferred access cycles 8-bits. byte/HIGH byte selection controlled with with PIOS register, PLSB. correct interrupt generation transfer order should then (see Table 48). Table Host port register addressing PLSB DESCRIPTION access PI/PO HIGH (LOW) byte access PI/PO (HIGH) byte reserved read status register PIOS STATUS REGISTER PIOS CHANGE change PISE POSF change change
Table Status/Control Register (PIOS) PLSB PORQEN PIRQEN POSF PISE
Table Description PIOS bits NAME PLSB PORQEN PIRQEN POSF PISE DIRECTION read read/write read/write read read This controls parallel transfer order. When PLSB transferred first. reset value logic When PORQEN PORQN enabled. reset value logic When PIRQEN PIRQN enabled. reset value logic When POSF Output Register (PO) full. reset value logic When PISE Input Register (PI) empty. reset value logic DESCRIPTION These three bits used.
1996
Philips Semiconductors
Objective specification
signal processing
host used three modes: Acknowledge mode: this mode PCF5083 provides open drain output DTACK, that acknowledges data read write accesses host port registers PIOS. This signal connected 90CL301 DTACK input. Using hardware handshake DTACK, 90CL301 write data register time. necessary poll PISE status register PIOS. 90CL301 writes still full, write access automatically extended until read Under worst case conditions this will last (see formula below). Before reading message however, System Controller check once message available from DSP. This done polling POSE flag PIOS register. POSE logic System Controller read first word message. After determination message length, rest message read without further polling. Polling mode: this mode hardware handshake DTACK used. Before writing word 90CL301 must wait until PISE flag Status Register PIOS set. Correspondingly, 90CL301 must wait until POSE flag PIOS set, before reading Interrupt mode: this mode PCF5083 provides internal interrupt request signals PIRQN PORQN. Signal PIRQN (active LOW) corresponds status register PISE (active HIGH) PORQN (active LOW) POSF (active HIGH). soon status PISE POSF set, PIRQN/PORQN going LOW, generating interrupt host. interrupt service routines should handle 8-bit transfers. After first transfer PIRQN/PORQN goes HIGH, removing interrupt source. After second transfer interrupt will generated. PIRQN PORQN enabled setting PIOS PIRQ_EN PIRQ_EN HIGH. After reset both signals disabled. PIRQN PORQN interrupt condition signalled HIPR_INT interrupt line (see Section 10.2). Command indication messages buffered queues, each words. working acknowledge mode layer software 90CL301 ensure that queue overflow occurs (this will never happen during normal operation).
PCF5083
times required receive transmit message consisting words calculated according following formulas: Data transfer acknowledge mode produces least overhead 90CL301 layer software. therefore recommended acknowledge mode communication with DSP. 9.1.7 EVENT COUNTER CLOCK
event counter used firmware time-out detection.The 32.768 clock internally connected ECLK input DSP. 9.1.8 GENERAL PURPOSE PINS
Table Usage General Purpose Pins RESET DEFAULT DESCRIPTION Audio interface timer core select pin. logic enables interface; logic disables interface. used procedure trace used procedure trace select pin. logic enables transmitter; logic disables transmitter.
Note that changed automatically firmware (e.g. procedure MP_iom2_enable). Whenever audio data should transmitted audio interface, explicitly calling procedure DB_write_register: DB_write_register(11, 0x0100, sets register SIOC DB_write_register(11, 0x0100, resets register SIOC.
1996
Philips Semiconductors
Objective specification
signal processing
9.1.9 POWER SAVING MODES
PCF5083
Message Interface System Controller
9.1.9.1
Idle mode
When operating Idle mode enters dormant state requires only fraction power normally needed supply device full operating mode. processor core switched whereas section processor fully functional. Idle mode invoked on-chip firmware whenever waiting event. automatically leaves Idle mode soon input output operation been completed.
controlled with commands joining 16-bits parameters from System Controller host port register first word always contains command OPCODE length. second word arbitrary code which useful debugging purposes. following words command parameters. also generate indications giving status information requested data. These indication messages read host port register message used download data into program/data RAM. Download always done into data address space. parameters mc_before mc_after indicate value Memory Configuration Register before after download. Thus, possible switch bank into data address space, download program switch back afterwards. more information about Register PCF5083 memory mapping please refer "Information Manual Digital Signal Processors PCF508x, Philips Semiconductors, 1995".
9.1.9.2
Power-down mode
Power-down mode initiated when signal DSPON deactivated during Sleep mode (see Section 8.3.3). will stop operation synchronously after maximum CLKI cycles delay. parts which operate with main processor clock static state. Only blocks running with serial interface clocks affected Power-down mode. minimum power consumption external serial shift clocks should therefore switched off. remains power-down state long signal DSPON held inactive. processor continues operation maximum clock cycles after signal DSPON active again.
Table Commands/indications to/from PCF5083 MNEMONIC DIRECTION write OPCODE(1) LENGTH msg_id DATA mc_before n_words; address data data words]; mc_after proc_id; parameter_1 parameter_N proc_id; return_value return value_N cmd_1 cmd_N reset_parm data_1 data_N error_code
0X0000
EXEC_PROC PROC_RETUR PACKET RESET ERROR Note don't care.
write read write write write read
0X01 0X11 0X02 0X03 0X05 0X12
npar n_retvals
msg_id msg_id
(cmd_len) msg_id msg_id msg_id msg_id
1996
Philips Semiconductors
Objective specification
signal processing
9.2.1 EXECUTION BASEBAND PROCEDURES 9.2.3 SOFT RESETTING
PCF5083
EXEC_PROC commands initiate execution internal procedures. procedure specified proc_id executed within DSP. input parameters procedure part message. return values any) procedure msg_id parameter packed PROC_RETURN indication. Several commands combined with PACKET command reduce overhead especially when sending commands polling mode. 9.2.2 OPERATION (NOP) COMMAND
RESET command causes perform soft reset. executed immediately after current running procedure completed. Depending reset parameter (see Table input and/or output command queues cleared. possible reset more than FIFO queue, setting appropriate bits.
This command used debugging purposes. ignored DSP. length data field least word. Table Parameter RESET message MNEMONIC RESET_ALL OUTPUT_MESSAGE_QUEUE INPUT_MESSAGE_QUEUE BBD_IN_FIFO MOD_OUT_FIFO Note don't care. VALUE(1) 0X0000 0X0001 0X0002 0X0004 0X0008 DESCRIPTION Restart main program (soft reset), clear buffers queues external memory. Clear output message queue. Clear input message queue. Clear baseband digitizer input FIFO. Clear GMSK modulator output FIFO.
1996
Philips Semiconductors
Objective specification
signal processing
9.2.4 ERROR HANDLING
PCF5083
ERROR indication notifies that error occurred previously submitted EXEC PROC commands with msg_id. Table shows possible error codes. After detection error, current command aborted continues execution next command input queue. Table Error codes MNEMONIC RESET_OCCURRED MSG_TYP_UNKNOWN WRONG_PARAMETER MSG_IN_FIFO_OVERFLOW MSG_OUT_FIFO_OVERFLOW BBD_IN_FIFO_OVERFLOW MOD_FIFO_FULL AUDIO_IN_IFO_OVERFLOW AUDIO_OUT_FIFO_UNDERFLOW AUDIO_OUT_FIFO_FULL TIMEOUT_BBD_IN_FIFO TIMEOUT_AUDIO_IN_FIFO AUDIO_SYNC_FAILED AUDIO_SYNC_TIMEOUT FSC_TIMEOUT AUDIO_SAMPLES_INSERTED AUDIO_SAMPLES_REMOVED SPEECH_ENCODER_RESET SPEECH_DECODER_RESET Note These error codes notify real error; they indicate occurrence special event. CODE 28(1) 29(1) 31(1) 32(1) DESCRIPTION main program restarted undefined command received procedure parameters valid range input queue overflow occurred output queue overflow occurred FIFO overflow occurred modulator FIFO empty enough receive data audio input FIFO overflow occurred audio output FIFO underflow occurred audio output FIFO empty enough receive data time-out occurred waiting samples timeout occurred waiting audio input samples audio synchronization successful MP_audio_sync waited long first sample MP_iom2_enable waited long frame sync interrupt MP_audio_sync inserted audio samples into audio FIFO MP_audio_sync removed audio samples from audio FIFO speech encoder reset occurred speech decoder reset occurred
1996
Philips Semiconductors
Objective specification
signal processing
baseband procedures
PCF5083
baseband procedures with optional input parameters called EXEC_PROC command described Section 9.2. Return values packed PROC_RETURN indication. Every procedure deals with following types data: Input parameters which directly supplied System Controller Return values which automatically sent System Controller soon procedure completed Input output data buffers located data RAM. They used communication with other procedures. Most procedures common buffer SCRATCH_BUFF their input output data. Only small number procedures need specific buffer input output. this case there additional parameters in_buff_id out_buff_id which determine buffers where input output data located. Table list available buffers given. trailing parameters procedure which transmitted with EXEC_PROC command default value zero used. Table Data buffers baseband procedures MNEMONIC VERSION_BUFF ID(1) 0X8000 SIZE DESCRIPTION Contains coded version numbers software packages (order: TP). version number 0Xmm.ss means version mm.ss. Scratch buffer communication between arbitrary modules. combination buffers; TCH_CMI_BUFF1 TCH_CMI_BUFF4. Used store values consecutive bursts belonging block.
SCRATCH_BUFF TCH_CMI_BUFF TCH_CMI_BUFF1 TCH_CMI_BUFF2 TCH_CMI_BUFF3 TCH_CMI_BUFF4 CCH_CMI_BUFF CCH_CMI_BUFF1 CCH_CMI_BUFF2 CCH_CMI_BUFF3 CCH_CMI_BUFF4 CCH_INFO_BUFF CCH_INFO_BUFF1 CCH_INFO_BUFF2 CCH_INFO_BUFF3 CCH_INFO_BUFF4 TCH_LOOP_BUFF
0X8001 0X8002 0X8003 0X8004 0X8005 0X8006 0X8007 0X8008 0X8009 0X800A 0X800B 0X800C 0X800D 0X800E 0X800F 0X8010 0X8011
combination buffers; CCH_CMI_BUFF1 CCH_CMI_BUFF4. Used store values consecutive bursts belonging block.
combination buffers; CCH_INFO_BUFF1 CCH_INFO_BUFF4. Used store information bits bursts belonging block.
Used store four normal bursts during loop-back operation. Note this buffer also used speech encoder. Used control several features firmware; Table Used store components from PCF5072. This buffer overlaid with SCRATCH_BUFF.
MP_CONTROL_BUFF 0X8013 IQ_BUFF Notes don't care. 0X8018
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
MP_CONTROL_BUFF used control several features DSP. consists parameter fields given Tables Table Contents MP_CONTROL_BUFF OFFSET DESCRIPTION time-out_freq: ECLK input frequency divided kHz. After reset time-out_freq (32.768 clock). eclk_cycle_count: contains number ECLK cycles spent most recently called procedure. Required test purposes only. proc_trace_buff[2]: debugging purposes provides procedure trace facility. procedures traced must stored proc_trace_buff. these procedures executing, corresponding (see Table logic
Table Associated pins LOCATION proc_trace_buff[0] proc_trace_buff[1] Note proc_trace_buff[1] then errors. DEFAULT AFTER RESET CP_rx_normal_burst trace errors; note
1996
Philips Semiconductors
Objective specification
signal processing
9.3.1 PROCEDURE DESCRIPTION
PCF5083
this section baseband procedures offered listed alphabetical order. following naming conventions used throughout description: Value: this 16-bit integer parameter (call value) return value (e.g. training sequence code, flag) Value [SIZE]: this array consisting SIZE 16-bit words. array transmitted word word between System Controller (e.g. FACCH msg[12]) Parameter names ending with buff_id identify buffer data where input output data procedure stored. Table Procedure description DESCRIPTION BB_access_burst Burst building random access burst accordance with "GSM Rec. 05.02". burst information bits must located SCRATCH_BUFF. result returned SCRATCH_BUFF. BB_normal_burst Burst building n_bursts normal bursts accordance with "GSM Rec. 05.02". burst information bits must located buffer determined info_buff_id. result returned buffer burst_buff_id. `tsc' training sequence code (range: CI_decrypt (note Decryption values n_bursts bursts stored buffer cmi_buff_id. Note that n_bursts range from n_bursts cmi_buff_id must other than TCH_CMI_BUFF CCH_CMI_BUFF cmi_buff_id n_bursts info_buff_id burst_buff_id n_bursts PARAMETERS RETURN VALUES
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
DESCRIPTION CI_decrypt_init (note Initialization CI_decrypt. decrypt_flag enables disables decryption. decrypt_flag means decryption. decrypt_flag decryption according A5/1. decrypt_flag decryption according A5/2 absolute Frame Number (FN) divisor 2047,11 bits). absolute Frame Number (FN) modulo bits) absolute Frame Number (FN) modulo bits) key[0 contains bits ciphering accordance with "GSM Rec. 03.20". bits loaded algorithm first order (first {key[0]}, last {key[3]}). algorithm delivers bytes kc[0] kc[7]. mapping between follows: key[0] kc[6] kc[7] key[1] kc[4] kc[5] key[2] kc[2] kc[3] key[3] kc[0] kc[1] CI_encrypt Encryption n_bursts normal bursts, info_buff_id determines buffer where information bits first burst stored. CI_encrypt_init Initialization CI_encrypt. encrypt_flag enables disables encryption. decrypt_flag means encryption. decrypt_flag encryption according A5/1. decrypt_flag encryption according A5/2. absolute Frame Number (FN) divisor 2047,11 bits). absolute Frame Number (FN) modulo bits) absolute Frame Number (FN) modulo bits) Key[0 contains bits ciphering accordance with "GSM Rec. 03.20". bits loaded algorithm first order (first {key[0]}, last {key[3]}). algorithm delivers bytes kc[0] kc[7]. mapping between follows: key[0] kc[6] kc[7] key[1] kc[4] kc[5] key[2] kc[2] kc[3] key[3] kc[0] kc[1]
PARAMETERS decrypt_flag key[4]
RETURN VALUES
info_buff_id n_bursts
encrypt_flag key[4]
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
DESCRIPTION CM_convert_TCHFS_data This routine used TCH/FS loop-back. converts output data CM_decoder_TCHFS into format which required CM_encoder_TCHS. bfi_sig_flag logic then decoded speech parameters zero frame been detected. CM_decoder_CCH Channel decoder control channels. accordance with "GSM Rec. 05.03" this procedure used following channels: BCCH: Broadcast Control Channel PCH: Paging Channel SACCH: Slow Associated Control Channel AGCH: Access Grant Channel SDCCH: Stand-alone Dedicated Control Channel. four bursts containing information which stored CCH_CMI_BUFF decoded rxqual_ber reflects estimated error rate input channel decoder (hard decision assumed) multiplied 4096. bfi_cch frame indication: bfi_cch decoded message bfi_cch parity error been detected bfi_cch metric error been detected bfi_cch both parity metric errors have been detected. cch_msg[12] contains message consisting bits. bits stored packed format with 16-bits word first order. Unused MSBs zero. CM_decoder_SCH Channel decoder synchronization channel. bfi_sch frame indication: bfi_sch decoded message bfi_sch parity error been detected bfi_sch metric error been detected bfi_sch both parity metric errors have been detected. sch_msg[2] contains decoded message consisting bits. bits stored packed format with 16-bits word first order. Unused bits zero.
PARAMETERS bfi_sig_flag
RETURN VALUES
rxqual_ber bfi_cch cch_msg[12]
bfi_sch sch_msg[2]
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
DESCRIPTION CM_decoder_TCHDATA Channel decoder de-interleaver data channels FACCH accordance with "GSM Rec. 05.03". values located TCH_CMI_BUFF decoded. decoded bits stored SCRATCH_BUFF. data channel decoder selected call CM_DECODER_TCHDATA_INIT. rxqual_ber (format 16-bit integer) reflects estimated error rate input channel decoder (hard decision assumed) multiplied 4096. bfi_facch frame indication: bfi_facch decoded FACCH message bfi_facch parity error been detected bfi_facch metric error been detected bfi_facch both parity metric errors have been detected. facch_flag indications: facch_flag indicates that FACCH message been received. this case facch_msg[12] contains zeros. facch_flag indicates that FACCH message been decoded returned into facch_msg[12]. facch_msg[12] contains bits decoded FACCH message. bits stored packed format with 16-bits word first order. Unused MSBs zero. CM_decoder_TCHDATA_init Initialization CM_decoder_TCHDATA. parameter data_service following values: data_service full-rate kbits/s data_service full-rate kbits/s data_service full-rate kbits/s data_service half-rate kbits/s data_service half-rate kbits/s.
PARAMETERS
RETURN VALUES rxqual_ber bfi_facch facch_flag facch_msg[12]
data_service
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
DESCRIPTION CM_decoder_TCHFS Channel decoder de-interleaver full-rate speech traffic channel FACCH accordance with "GSM Rec. 05.03". values located TCH_CMI_BUFF decoded. decoded bits stored SCRATCH_BUFF. rxqual_ber (format 16-bit integer) reflects estimated error rate input channel decoder (hard decision assumed) multiplied 4096. bfi_facch frame indication: bfi_facch decoded FACCH message bfi_facch parity error been detected bfi_facch metric error been detected bfi_facch both parity metric errors have been detected. facch_flag indications: facch_flag indicates that FACCH message been received. this event facch_msg[12] contains zeros facch_flag indicates that FACCH message been decoded returned into facch_msg[12]. facch_msg[12] contains bits decoded FACCH message. bits stored packed format with 16-bits word first order. Unused MSB's zero. CM_decoder_TCHFS_init Initialization CM_decoder_TCHFS. CM_encoder_CCH Channel decoder control channels. accordance with "GSM Rec. 05.03" this procedure used following channels: SACCH: Slow Associated Control Channel SDCCH: Stand-alone Dedicated Control Channel. encoded data stored CCH_INFO_BUFF. cch_msg[12] contains bits decoded message. bits stored packed format with 16-bits word first order. Unused MSB's zero.
PARAMETERS
RETURN VALUES rxqual_ber bfi_facch facch_flag facch_msg[12]
cch_msg[12]
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
DESCRIPTION CM_encoder_RACH Channel encoder random access channel. encoded RACH message stored SCRATCH_BUFF. bsic contains bits B(0) B(5) base station identity code accordance with "GSM Rec. 05.03". B(0) stored (bit bsic, B(5) bsic. B(0) PLMN colour code, B(5) colour code. rach_msg[1] contains RACH message consisting bits. bits stored first order. Unused MSBs zero. CM_encoder_TCHDATA Channel encoder interleaver data channels, FACCH uplink control. dtx_flag determines whether discontinuous transmission (DTX) applied: dtx_flag applied dtx_flag applied. valid only encoder full-rate kbits/s half-rate kbits/s. facch_flag indications: facch_flag indicates that FACCH data must encoded facch_flag indicates that FACCH message must encoded. facch_msg[12] contains bits FACCH message. bits stored packed format with 16-bits word first order. return value txen only useful applied. indicates whether block will transmitted over interface. txen block will transmitted over interface txen block will transmitted over interface. data services other than full-rate kbits/s half-rate kbits/s txen will logic CM_encoder_TCHDATA_init Initialization CM_ENCODER_TCHDATA. parameter data_service following values: data_service full-rate kbits/s data_service full-rate kbits/s data_service full-rate kbits/s data_service half-rate kbits/s data_service half-rate kbits/s.
PARAMETERS bsic rach_msg[1]
RETURN VALUES
dtx_flag facch_flag facch_msg[12]
txen
data_service
1996
Philips Semiconductors
Objective specification
signal processing
PCF5083
DESCRIPTION CM_encoder_TCHFS Channel encoder interleaver traffic channel full-rate speech FACCH uplink c
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