Channel, Cost Converter Power Consumption Description C

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Channel, Cost Converter Power Consumption Description C

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CS5550
Channel, Cost Converter
Power Consumption
Description
CS5550 combines ADCs serial interface single chip. CS5550 with on-chip functionality facilitate offset gain Adjustable Input Range AIN1± GND-Referenced Signals with Single Supply calibration. CS5550 features bi-directional serial interface communication with On-chip Reference ppm/°C typ) microcontroller.
Simple Three-Wire Digital Serial Interface Power Supply Configurations
AGND +3.3
ORDERING INFORMATION: CS5550-IS -40°C +85°C
24-pin SSOP
RESET
AIN1+ AIN1-
10x,50x
Order Modulator
Digital Filter
Calibration Registers Config Register Serial Interface
SCLK
AIN2+ AIN2-
Order Modulator
Digital Filter
Output Registers
VREFIN
VREFOUT
Voltage Reference
Clock Generator
AGND
XOUT CPUCLK
DGND
Preliminary Product Information
http://www.cirrus.com
This document contains information product. Cirrus Logic reserves right modify this product without notice.
Copyright Cirrus Logic, Inc. 2004 (All Rights Reserved)
DS630PP2
CS5550
TABLE CONTENTS
DESCRIPTION CHARACTERISTICS/SPECIFICATIONS ANALOG CHARACTERISTICS VOLTAGE REFERENCE. DIGITAL CHARACTERISTICS. DIGITAL CHARACTERISTICS. RECOMMENDED OPERATING CONDITIONS SWITCHING CHARACTERISTICS Theory Operation 2.1.1 High-Rate Digital Low-Pass Filters 2.1.2 Digital Compensation Filters 2.1.3 Gain Offset Adjustment Performing Measurements CS5550 Linearity Performance FUNCTIONAL DESCRIPTION Analog Inputs Voltage Reference Oscillator Characteristics Calibration 3.4.1 Overview Calibration Process 3.4.2 Calibration Sequence 3.4.3 Calibration Signal Input Level 3.4.4 Input Configurations Calibrations 3.4.5 Description Calibration Algorithms 3.4.5.1 Offset Calibration Sequence 3.4.5.2 Gain Calibration Sequence 3.4.6 Duration Calibration Sequence Interrupt 3.5.1 Typical 3.5.2 Active State Layout SERIAL PORT OVERVIEW Commands Serial Port Interface Serial Read Write 4.3.1 Register Write 4.3.2 Register Read System Initialization Serial Port Initialization CS5550 Power States REGISTER DESCRIPTION Configuration Register Offset Registers Gain Registers Cycle Count Register OUT1 OUT2 Output Registers. FILT1, FILT2 Unsigned Output Register. Status Register Mask Register Control Register PACKAGE DIMENSIONS
DS630PP2
CS5550
LIST FIGURES
Figure CS5550 Read Write Timing Diagrams. Figure Oscillator Connection. Figure System Calibration Gain. Figure System Calibration Offset. Figure Example Gain Calibration
Table Change History Revision Date October 2003 August 2004 Initial release Update AIN1. Update Noise AIN2. Update PSRR AIN2. Delete Calibration references. Changes
Contacting Cirrus Logic Support
complete listing Direct Sales, Distributor, Sales Representative contacts, visit Cirrus Logic site http://www.cirrus.com/
IMPORTANT NOTICE "Preliminary" product information describes products that production, which full characterization data available. Cirrus Logic, Inc. subsidiaries ("Cirrus") believe that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). Customers advised obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, patent infringement, limitation liability. responsibility assumed Cirrus this information, including this information basis manufacture sale items, infringement patents other rights third parties. This document property Cirrus furnishing this information, Cirrus grants license, express implied under patents, mask work rights, copyrights, trademarks, trade secrets other intellectual property rights. Cirrus owns copyrights associated with information contained herein gives consent copies made information only within your organization with respect Cirrus integrated circuits other products Cirrus. This consent does extend other copying such copying general distribution, advertising promotional purposes, creating work resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS DESIGNED, AUTHORIZED WARRANTED AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO BODY, LIFE SUPPORT PRODUCTS OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS COMPONENTS PERSONAL AUTOMOTIVE SAFETY SECURITY DEVICES). INCLUSION CIRRUS PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK CIRRUS DISCLAIMS MAKES WARRANTY, EXPRESS, STATUTORY IMPLIED, INCLUDING IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE, WITH REGARD CIRRUS PRODUCT THAT USED SUCH MANNER. CUSTOMER CUSTOMER'S CUSTOMER USES PERMITS CIRRUS PRODUCTS CRITICAL APPLICATIONS, CUSTOMER AGREES, SUCH USE, FULLY INDEMNIFY CIRRUS, OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS OTHER AGENTS FROM LIABILITY, INCLUDING ATTORNEYS' FEES COSTS, THAT RESULT FROM ARISE CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, Cirrus Logic logo designs trademarks Cirrus Logic, Inc. other brand product names this document trademarks service marks their respective owners. Microwire trademark National Semiconductor Corporation.
DS630PP2
CS5550
DESCRIPTION
Crystal Clock Output Positive Power Supply Digital Ground Serial Clock Serial Data Ouput Chip Select Test Output Differential Analog Input Differential Analog Input Voltage Reference Output Voltage Reference Input XOUT CPUCLK DGND SCLK TSTO AIN2+ AIN2VREFOUT VREFIN TSTO TSTO RESET TSTO TSTO AIN1+ AIN1VA+ AGND Crystal Serial Data Input Test Output Test Output Interrupt Reset Test Output Test Output Differential Analog Input Differential Analog Input Positive Analog Supply Analog Ground
Clock Generator
Crystal Crystal Clock Output
1,24
XOUT, gate inside chip connected these pins used with crystal provide system clock device. Alternatively, external (CMOS compatible) clock supplied into provide system clock device. CPUCLK Output on-chip oscillator which drive standard CMOS load.
Control Pins Serial Data
Serial Clock Input Serial Data Output Chip Select Reset Interrupt Serial Data Input
SCLK clock signal this determines input output rate data pins respectively. SCLK will recognize clocks only when low. -The serial data port output pin. output high impedance state when high. When low, port will recognize SCLK. active high this forces high impedance state. should changed when SCLK low. RESET When reset taken low, internal registers their default states. When goes signals that enabled event occurred. serial data port input pin. Data will input rate determined SCLK.
Measurement Reference Input
Differential Analog Inputs Voltage Reference Output Voltage Reference Input
9,10,15,16
AIN1+, AIN1-, AIN2+, AIN2- Differential analog input pins. VREFOUT on-chip voltage reference output. voltage reference nominal magnitude referenced AGND converter. VREFIN input establishes voltage reference on-chip modulator.
Power Supply Connections
Positive Digital Supply Digital Ground Positive Analog Supply Analog Ground Test Output
4,9,10
positive digital supply relative DGND. DGND common-mode potential digital ground must equal above common-mode potential AGND. positive analog supply relative AGND. AGND analog ground must lowest potential.
8,17,18,21,22 TSTO These pins used factory testing must left floating.
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CS5550
CHARACTERISTICS/SPECIFICATIONS
characteristics specifications guaranteed over Operating Conditions. Typical characteristics specifications measured nominal supply voltages 25°C. DGND voltages with respect
ANALOG CHARACTERISTICS
Parameter Symbol (DC, CMRR (Gain (Gain Both Gain Ranges (50, (Gain (Gain (Gain (Gain (Gain (Gain (Note (Note {(AIN2+) (AIN2-)} EII1 AIN1 THD1 -0.25 -0.25 (50, (Gain (Gain (Gain (Note (Note EII2 -115 22.5 ±0.001 ±0.001 ±0.01 ±0.01 Unit nV/°C
mVP-P mVP-P
Accuracy (Both Channels)
Common Mode Rejection Offset Drift
Analog Inputs (AIN1±)
Differential Input Voltage Range {(AIN1+) (AIN1-)} Total Harmonic Distortion Common Mode Signal Crosstalk with AIN2± Full Scale Input Capacitance Effective Input Impedance (Note Noise (Referred Input)
µVrms µVrms
Accuracy Bipolar Offset Error
Full-Scale Error
AIN2 THD2
%F.S. %F.S.
mVP-P
Analog Inputs (AIN2±)
Differential Input Voltage Range Total Harmonic Distortion Common Mode Signal Crosstalk with AIN1± Full Scale Input Capacitance Effective Input Impedance (Note Noise (Referred Input)
µVrms
Accuracy
Bipolar Offset Error Full-Scale Error Notes: Applies after system calibration Effective Input Impedance (EII) determined clock frequency (DCLK) Input Capacitance (IC). 1/(IC*DCLK/4). Note that DCLK MCLK %F.S. %F.S.
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CS5550
ANALOG CHARACTERISTICS (Continued)
Parameter Dynamic Characteristics High Rate Filter Output Word Rate Input Sampling Rate Full Scale Calibration Range High Pass Filter Pole Frequency DCLK MCLK/K (Note (VD+ (VD+ PSCA PSCD PSCD FSCR Symbol DCLK/1024 DCLK/8 11.6 6.75 Unit %F.S.
Power Supplies Power Supply Currents (Active State)
Power Consumption (Note
Active State (VD+ Active State (VD+ Stand-by State Sleep State (Gain (Gain (Gain
Power Supply Rejection Ratio (AIN1±) (50, Hz)(Note Power Supply Rejection Ratio (AIN2±) (50, Hz)(Note
PSRR1 PSRR1 PSRR2
Notes: minimum FSCR limited maximum allowed gain register value. outputs unloaded. inputs CMOS level. Definition PSRR: VREFIN tied VREFOUT, (zero-to-peak) sinewave imposed onto supply
voltage pins. input pins both input channels shorted AGND. Then CS5550 commanded continuous conversion acquisition mode, digital output data collected channel under test. (zero-to-peak) value digital sinusoidal output signal determined, this value converted into (zero-to-peak) value sinusoidal voltage (measured that would need applied channel's inputs, order cause same digital sinusoidal output. This voltage then defined PSRR then dB):
VOLTAGE REFERENCE
Parameter Symbol REFOUT (Note VREFIN (Output Current Source Sink) Unit ppm/°C
Reference Output
Output Voltage Temperature Coefficient Load Regulation
Reference Input
Input Voltage Range Input Capacitance Input Current
Notes: voltage VREFOUT measured across temperature range. From these measurements following formula used calculate VREFOUT Temperature Coefficient:.
TCVREF
MIN)
AMAX
TAMIN
(VREFOUT VREFOUT VREFOUT
PSRR
DS630PP2
CS5550
DIGITAL CHARACTERISTICS
Parameter High-Level Input Voltage Pins Except SCLK RESET SCLK RESET Low-Level Input Voltage Pins Except SCLK RESET SCLK RESET High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Capacitance Iout Iout Symbol (VD+) Cout (VD+) Unit
DIGITAL CHARACTERISTICS
Parameter High-Level Input Voltage Pins Except SCLK RESET SCLK RESET Low-Level Input Voltage Pins Except SCLK RESET SCLK RESET High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Capacitance Iout Iout Symbol (VD+) Cout (VD+) 0.48 Unit
RECOMMENDED OPERATING CONDITIONS
Parameter Positive Digital Power Supply Positive Analog Power Supply Negative Analog Power Supply Voltage Reference Specified Temperature Range Symbol AGND VREF 3.135 4.75 -0.25 5.25 5.25 0.25 Unit
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CS5550
SWITCHING CHARACTERISTICS
Master Clock Frequency Master Clock Duty Cycle CPUCLK Duty Cycle Rise Times (Note Fall Times (Note Parameter Internal Gate Oscillator (Note (Note Digital Input Except SCLK SCLK Digital Output Digital Input Except SCLK SCLK Digital Output XTAL 4.096 (Note Symbol MCLK 4.096 Unit
trise
tfall
Start-up Oscillator Start-Up Time Serial Port Timing Serial Clock Frequency Serial Clock Timing Falling SCLK Rising
tost SCLK
Pulse Width High Pulse Width
Data Set-up Time Prior SCLK Rising Data Hold Time After SCLK Rising SCLK Falling Prior Disable
Timing Falling Driving
SCLK Falling Data (hold time) Rising Hi-Z
Notes: Device parameters specified with 4.096 clock. crystal used, then frequency must remain between MHz. external MCLK used, then duty cycle must between maintain this spec. Specified using points wave-form interest. Output loaded with Oscillator start-up time varies with crystal parameters. This specification does apply when using external clock source.
DS630PP2
DS630PP2
SCLK
Command Time SCLKs High Byte Byte
Byte
Write Timing (Not Scale)
High Byte
Byte
Byte
SCLK
Figure CS5550 Read Write Timing Diagrams
Command Time SCLKs
Must strobe "SYNC0" command when reading each byte data from SDO.
Read Timing (Not Scale)
CS5550
CS5550
Theory Operation
analog signals analog inputs subject gains input PGAs. These signals then sampled delta-sigma modulators rate (MCLK/K) resent normalized value between unsigned data CS5550 output registers represent normalized values between register value represents maximum possible value. Note that value never actually obtained, true maximum register value [(2^23 (2^23)] 0.999999880791. After each conversion, CRDY will asserted Status Register, will also become active CRDY unmasked Mask Register). assertion CRDY indicates that instantaneous samples have been collected. unsigned FILT1 FILT2 calculations updated every conversions (which known "computation cycle") where value Cycle Count Register. each computation cycle, DRDY Mask Register will set, will become active DRDY unmasked. DRDY only after each computation cycle completed, whereas CRDY asserted after each individual conversion. When these bits asserted, they must cleared before they asserted again. Cycle Count Register value output calculations instantaneous, DRDY will indicate when instantaneous calculations finished, just like CRDY bit. FILT results valid, Cycle-Count Register must value greater than computation cycle derived from master clock frequency (MCLK/K)/(1024*N). Under default conditions with 4.096 clock XIN, instantaneous conversions performed 4000 rate, whereas FILT calculations performed rate.
2.1.1 High-Rate Digital Low-Pass Filters
data then low-pass filtered, remove high-frequency noise from modulator output. high rate filters both channels implemented fixed Sinc3 filters.
2.1.2 Digital Compensation Filters
data from both channels then passed through 4th-order "compensation" filters, whose purpose correct (compensate) magnitude roll-off low-pass filtering operation. These filters "re-flatten" magnitude response AIN1 AIN2 channels over relevant frequency range, correcting magnitude roll-off effects that induced Sinc3 low-pass filter stages.
2.1.3 Gain Offset Adjustment
After filtering, digital codes subjected value adjustments, based values Offset Registers (additive) Gain Registers (multiplicative). These registers used calibration device (see Section 3.4, Calibration). After offset gain, data available user reading appropriate registers.
Performing Measurements
CS5550 performs measurements output word rate (sampling rate) (MCLK/K) 1024. From these instantaneous samples, FILT1 FILT2 computed, using most recent instantaneous samples that were acquired. measurements/results available percentage full scale. signed output format two's complement format, output data words rep-
DS630PP2
CS5550
CS5550 Linearity Performance
FILT1 FILT2
100%
voltage signal that placed across inputs, with saturation
500mV ~176.78mV
Range Linearity
0.2% 100%
0.1% reading
0.1% reading
Table Available range ±0.1% output linearity, with default settings gain/offset registers.
which ~70.7% full-scale. sinusoidal inputs full scale peak-to-peak level full scale registration ~.707.
Table lists range input levels percentage full-scale registration FILT Registers) over which output linearity FILT Register measurements guaranteed within ±0.1%. This linearity guaranteed available full-scale input voltage ranges. Note that until CS5550 calibrated (see Calibration) accuracy CS5550 guaranteed within ±0.1%. linearity given sample CS5550, before calibration, will within ±0.1% reading over ranges specified, with respect input voltage levels required cause full-scale readings FILT Registers. Table describes linearity variation specs after completion each successive computation cycle.
Voltage Reference
CS5550 specified operation with +2.5 reference between VREFIN AGND pins. converter includes internal reference ppm/°C drift) that used connecting VREFOUT VREFIN device. higher accuracy/stability required, external reference used.
Oscillator Characteristics
XOUT input output inverting amplifier provide oscillation configured on-chip oscillator, shown Figure oscillator circuit designed work with quartz crystal ceramic resonator. reduce circuit cost, load capacitors integrated device. With these load capacitors, oscillator circuit capable oscillation MHz. drive device from external clock source, XOUT should left unconnected while driven external circuitry. There amplifier between digital section which provides CMOS level signals. This amplifier works with sinusoidal inputs there problems with slow edge times. CS5550 driven external oscillator ranging from MHz, divider value must such that internal DCLK will somewhere between MHz. divider value with K[3:0] bits Configuration Register. example, MCLK MHz, then DCLK MHz, which valid value DCLK.
FUNCTIONAL DESCRIPTION Analog Inputs
CS5550 available full-scale differential input voltage ranges AIN1±. input ranges maximum sinusoidal signals that applied analog inputs, theses values will result full scale registration. analog inputs mVP-P, only mVRMS signal will register full scale. would practical inject sinusoidal signal with value mVRMS. When such sine wave enters higher levels positive crest region (over each cycle), voltage level this signal exceeds maximum differential input voltage range input channels. largest sine wave
DS630PP2
CS5550
quence complete. results calibration available appropriate gain/offset registers.
Oscillator Circuit
XOUT
3.4.3 Calibration Signal Input Level
gain calibrations, there absolute limit voltage levels that selected gain calibration input signals. maximum value that gain register attain Therefore, either channel, voltage level gain calibration input signal enough that causes CS5550 attempt either gain register higher than gain calibration result will invalid CS5550 results obtained while performing conversions will invalid.
DGND
Figure Oscillator Connection
Calibration 3.4.1 Overview Calibration Process
CS5550 offers digital calibration offset gain. Since both channels have separate offset gain registers associated with them, system offset system gain performed either channel without calibration results from channel affecting other.
3.4.4 Input Configurations Calibrations
Figure shows basic setup gain calibration. When performing gain calibration positive voltage level must applied inputs AIN1 and/or AIN2 channels. This voltage should level that represents absolute maximum instantaneous voltage level that needs measured across inputs (including maximum over-range level that must accurately measured). offset calibrations, pins AIN± channels should connected their ground reference level. (See Figure Calibrating both offset gain same time will cause undesirable calibration results.
External nections Scale
3.4.2 Calibration Sequence
Before Calibration CS5550 must operating active state, ready accept valid commands. `DRDY' Status Register should also cleared. Apply appropriate calibration signals inputs AIN1 AIN2 channels (discussed next Sections 3.4.3 3.4.4.) Send 8-bit calibration command CS5550 serial interface. Various bits within this command specify exact type calibration. calibration command should sent device while performing conversions. After CS5550 finishes desired internal calibration sequence, DRDY Status Register indicate that calibration
AIN-
Figure System Calibration Gain.
DS630PP2
CS5550
Before Gain Calibration (Vgain Register
External Connections AIN+ AINXGAIN -250 -1.0000.
Signal
0.9999. 0.92 Output Register Values
INPUT SIGNAL
FILT Register 230/250 0.92
Figure System Calibration Offset.
3.4.5 Description Calibration Algorithms
Note: proper calibration, value AIN1/AIN2 Gain Registers must default (1.0) before running gain calibration(s), value Offset Registers must default before running offset calibrations. This accomplished software hardware reset device. values calibration registers affect results calibration sequences.
After Gain Calibration (Vgain Register changed 1.0870)
Signal
0.9999. Ouptut Register Values
INPUT SIGNAL FILT Register 0.9999.
Figure Example Gain Calibration
3.4.5.1 Offset Calibration Sequence
Offset Registers hold negative simple average samples taken while offset calibration executed. inputs should grounded during offset calibration. offset value added signal path nullify offset system.
CS5550 during given calibration sequence. offset/gain calibrations, calibration sequence takes least conversion cycles complete. increased, accuracy calibration results will increase.
Interrupt
used indicate that event taken place converter that needs attention. These events inform system about operation conditions internal error conditions. signal created combining Status Register with Mask Register. Whenever Status Register becomes active, corresponding Mask Register logic signal becomes active. interrupt condition cleared when bits Status Register returned their inactive state.
3.4.5.2 Gain Calibration Sequence
Based level positive calibration voltage applied across inputs, CS5550 determines Gain Register value averaging Digital Output Register's output signal values over computation cycle samples) then dividing this average into Therefore, after gain calibration, Instantaneous Register will read full-scale whenever level input signal equal level calibration signal applied inputs during gain calibration (see Figure
3.4.6 Duration Calibration Sequence
value Cycle Count Register determines number conversions performed
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CS5550
3.5.1 Typical
steps below show interrupts handled. Initialization: Step Status bits cleared writing FFFFFF (Hex) into Status Register. Step conditional bits which will used generate interrupts then logic Mask Register. Step Enable interrupts. Interrupt Handler Routine: Step Read Status Register. Step Disable interrupts. Step Branch proper interrupt service routine. Step Clear Status Register writing back read value step Step Re-enable interrupts. Step Return from interrupt service routine. This handshaking procedure insures that interrupts activated between steps lost (cleared) step
3.5.2 Active State
behavior controlled IMODE IINV bits Configuration Register. active (default), active high, active return logic (pulse-low), active return logic (pulse-high). interrupt output signal format either pulse-high pulse-low, duration pulse will least DCLK cycle (DCLK MCLK
Layout
CS5550 should placed entirely over analog ground plane with both AGND DGND pins device connected analog plane. Place analog-digital plane split immediately adjacent digital portion chip.
DS630PP2
CS5550
SERIAL PORT OVERVIEW
CS5550's serial port incorporates state machine with transmit/receive buffers. state machine interprets 8-bit command words rising edge SCLK. Upon decoding command word, state machine performs requested command prepares data transfer addressed register. Request read requires internal register transfer transmit buffer, while write waits until completion SCLKs before performing transfer. internal registers used control ADC's functions. registers 24-bits length. CS5550 initialized fully operational active state upon power-on. After power-on, device will wait receive valid command (the first 8-bits clocked into serial port). Upon receiving decoding valid command word, state machine instructs converter either perform system operation, transfer data from internal register. user should refer "Commands" section decode valid commands.
Commands
command words byte length. 8-bit word that listed this section should considered illegal command word, issuing such illegal command word serial interface result unpredictable operation CS5550. Commands that write register must followed bytes register data. Commands that read data chained with other commands (e.g., while reading data, command sent which execute before original read completed). This allows "chaining" commands.
4.1.1 Start Conversions
This command indicates state machine begin acquiring measurements calculating results. device modes acquisition. Modes acquisition/measurement Perform single computation cycle Perform continuous computation cycles
4.1.2 SYNC0 Command
This command serial port re-initialization sequence. command also used command. serial port resynchronized byte boundaries sending three more consecutive SYNC1 commands followed SYNC0 command.
4.1.3 SYNC1 Command
This command part serial port re-initialization sequence. command also serves command.
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CS5550
4.1.4 Power-Up/Halt
device powered-down, this command will power-up device. When powered-on, computations will running. part already powered-on, computations will halted.
4.1.5 Power-Down Software Reset
device power-down states conserve power. chip stand-by state, circuitry except analog/digital clock generators turned off. sleep state, circuitry except digital clock generator instruction decoder turned off. Waking CS5550 sleep state requires more time than stand-by state, because extra time needed re-start re-stabilize analog clock signal. S1,S0 Power-down state Software Reset Halt enter stand-by power saving state. This state allows quick power-on time Halt enter sleep power saving state. This state requires slow power-on time Reserved
4.1.6 Calibration
device capability performing system offset calibration gain calibration. Offset gain calibrations should performed same time (must after other). Proper inputs must supplied device before initiating calibration. A2,A1 Designates calibration channel allowed Calibrate AIN1 channel Calibrate AIN2 channel Calibrate AIN1 channel AIN2 channel simultaneously Designates gain calibration Normal operation Perform gain calibration Designates offset calibration Normal operation Perform offset calibration
DS630PP2
CS5550
4.1.7 Register Read/Write
Read/Write command informs state machine that register access required. During read operation, addressed register loaded into device's output buffer clocked SCLK. During write operation, data clocked into input buffer and, bits transferred addressed register 24th SCLK. Write/Read control Read register Write register Register address bits (bits through read/write command. RA[4-0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Abbreviation Config AIN1DCoff AIN1gn AIN2DCoff AIN2gn Cycle Count OUT1 OUT2 FILT1 FILT2 Status Mask Ctrl Name/Description Configuration Register AIN1 Offset Register AIN1 Gain Register AIN2 Offset Register AIN2 Gain Register Number conversions used computation cycle (N)). Reserved AIN1 Output Register AIN2 Output Register Reserved Reserved Computed Filtered value AIN1 Computed Filtered value AIN2 Reserved Reserved Status Register Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Mask Register Reserved Control Register Reserved Reserved Reserved
RA[4:0] Address
These registers internal only. proper device operation, user must attempt write these registers.
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CS5550
Serial Port Interface
CS5550's serial interface consists four control lines, which have following pin-names: SDI, SDO, SCLK. Chip Select, control line which enables access serial port. tied logic port function three wire interface. SDI, Serial Data data signal used transfer data converters. SDO, Serial Data Out, data signal used transfer output data from converters. output will held high impedance time logic SCLK, Serial Clock, serial bit-clock which controls shifting data from ADC's serial port. must held logic before SCLK transitions recognized port logic. accommodate opto-isolators SCLK designed with Schmitt-trigger input allow opto-isolator with slower rise fall times directly drive pin. Additionally, capable sinking sourcing directly drive opto-isolator LED. will have less than loss drive voltage when sinking sourcing must followed bits data. write Configuration Register, user would transmit command (0x40) initiate write Configuration Register. CS5550 will then acquire serial data input from (SDI) when user pulses serial clock (SCLK) times. Once data received, state machine writes data Configuration Register then waits receive another valid command.
4.3.2 Register Read
When read command initiated, serial port will start transferring register content bits serial (MSB first) next SCLK cycles. Command words instructing register read terminated 8-bit boundaries (e.g., read transfers bits length). Also data register reads allow "command chaining". This means that micro-controller allowed send command while reading register data. command will acted upon immediately could possibly terminate first register read. example, user only interested acquiring most significant bits data from first read, then user begin strobe second read command after first data bits have been read from SDO. During read cycle, SYNC0 command (NOP) should strobed port while clocking data from port.
Serial Read Write
state machine decodes command word received. Data written read from CS5550 using Register Read/Write command. Figure illustrates serial sequence necessary write read from serial port's buffers. shown Figure transfer data always initiated sending appropriate 8-bit command (MSB first) serial port (SDI pin).
System Initialization
software hardware reset initiated time. software reset initiated sending command 0x80. hardware reset initiated when RESET forced with minimum pulse width RESET signal asynchronous, requiring MCLKs part detect store reset event. RESET Schmitt Trigger input, which allows accept slow rise times and/or noisy control signals. Once RESET inacDS630PP2
4.3.1 Register Write
When command involves write operation, serial port will continue clock data bits (MSB first) next SCLK cycles. Command words instructing register write
CS5550
tive, internal reset circuitry remains active MCLK cycles insure resetting synchronous circuitry device. modulators held reset MCLK cycles after RESET becomes inactive. After hardware software reset, internal registers (some which drive output pins) will reset their default values first MCLK received after detecting reset event. internal register values also their default values after initial power-on device. CS5550 will then assume active state. (The term active state, well other defined power states CS5550, described Section 4.6). Refer Section data sheet default register values particular device register. Hardware Reset (drive RESET low, least then drive back high). Issue Serial Port Initialization Sequence, which performed clocking more) SYNC1 command bytes (0xFF) followed SYNC0 command byte (0xFE).
CS5550 Power States
Active state denotes operation CS5550 when device fully powered (not sleep state stand-by state). Performing either following actions will insure that CS5550 operating active state: Power CS5550. device already powered recycle power.) Software Reset Hardware Reset addition actions listed above, note that device sleep state stand-by state, action waking device sleep state stand-by state issuing Power-Up/Halt command) will also insure that device into active state. order send Power-Up/Halt command device, serial port must initialized. Therefore, after applying power CS5550, hardware reset should always performed.
Serial Port Initialization
possible serial interface become unsynchronized, with respect SCLK input. this occurs, attempt clock valid CS5550 commands into serial interface will result either operation unexpected operation, because CS5550 will interpret input command bits correctly. CS5550's serial port must then re-initialized. initialize serial port, following actions performed: Drive (assert) already low, drive high, then back low].
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REGISTER DESCRIPTION
"Default**" status after power-on reset labeled Reserved. zero should always used when writing these bits.
Configuration Register
Address:
2HPF 1HPF IMODE iCPU IINV
gain
Default** 0x000001 gain Sets gain AIN1 gain gain
[IMODE IINV] Soft interrupt configuration bits. Select desired behavior indication interrupt. active level (default) active high level falling edge (INT normally high) rising edge (INT normally low) 1HPF Control High Pass Filter AIN1 Channel. disabled enabled Control High Pass Filter AIN2 Channel. disabled enabled Inverts CPUCLK clock. order reduce level noise present when analog signals sampled, logic driven CPUCLK should active during sample edge. normal operation (default) minimize noise when CPUCLK driving rising edge logic Clock divider. 4-bit binary number used divide value MCLK generate internal clock DCLK. internal clock frequency DCLK MCLK/K. value range between Note that value "0000" will (not zero).
2HPF
iCPU
K[3:0]
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Offset Registers
Address: (Offset Register AIN1) (Offset Register AIN2)
2-23
Default** 0.000 Offset Registers initialized zero reset, allowing device function perform measurements. register loaded after computation cycle with offset when proper input applied Calibration Command received. DRDY will asserted calibration. register read stored register restored with desired system offset compensation. value range full scale. numeric format this register two's complement notation.
Gain Registers
Address: (Gain Register AIN1) (Gain Register AIN2)
2-16
2-17
2-18
2-19
2-20
2-21
2-22
Default** 1.000 Gain registers initialized reset, allowing device function perform measurements. Gain registers hold result gain calibrations. calibration performed, register loaded after computation cycle with system gain when proper input applied Calibration Command received. DRDY will asserted calibration. register read stored register restored with desired system offset compensation. value range Gain 3.9999.
Cycle Count Register
Address:
Default** 4000 Cycle Count Register value (denoted `N') determines length computation cycle. During continuous conversions, computation cycle frequency (MCLK/K)/(1024N) where MCLK master clock input frequency (into XIN/XOUT pins), clock divider value specified Configuration Register), Cycle Count Register Value.
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CS5550
OUT1 OUT2 Output Registers
Address:
(AIN1 Output Register) (AIN2 Output Register)
2-23
These signed registers contain last value measured results AIN1 AIN2. results will within range -1.0 AIN1,AIN2 1.0. value represented two's complement notation, with binary point place right (MSB negative weighting). These values bits length. least significant bits, (located right-side) have meaning, will always have value "0".
FILT1, FILT2 Unsigned Output Register
Address:
(AIN1 Filtered Output Register) (AIN2 Filtered Output Register)
2-18
2-19
2-20
2-21
2-22
2-23
2-24
These unsigned registers contain last values FILT1 FILT2. results range FILT1,FILT2 1.0. value represented (unsigned) binary notation, with binary point place left MSB. These results updated after each computation cycle.
Status Register Mask Register
Address: Address:
DRDY
(Status [Clear] Register) (Mask Register)
FOR1 FOR2 CRDY
Default** 0x000000 (Status [Clear] Register 0x000000 (Mask Register) Status [Clear] Register indicates condition chip. normal operation writing will cause state. Writing will maintain status current state. With this feature user simply write back Status [Clear] Register clear bits that have been seen, without concern clearing newly bits. Even status masked prevent interrupt time that status asserted), status will still (both Status Registers user poll status. Mask Register used control activation pin. Placing logic Mask Register will allow corresponding Status Register activate when status becomes active. DRDY Data Ready. When running single continuous conversion acquisition mode, this will indicate computation cycles. When running calibrations, this indicates that calibration sequence completed, results have been stored offset gain Output Range. when magnitude calibrated output large
OR1,
DS630PP2
CS5550
small Output Register. CRDY OD1, Conversion Ready. Indicates conversion ready. Modulator oscillation detect. when modulator oscillates input above Full Scale. Note that level which modulator oscillates significantly higher than Input Voltage Range. FILT range. when calibrated voltage value large FILT register. Invalid Command. Normally logic logic host interface strobed with 8-bit word that recognized valid commands (see Section 4.1, Commands).
FOR1, FOR2
Control Register
Register Address:
INTOD NOCPU NOOSC
Default** 0x000000 INTOD NOCPU NOOSC Converts output open drain configuration. saves power disabling CPUCLK external drive pin. saves power disabling crystal oscillator circuit.
DS630PP2
CS5550
PACKAGE DIMENSIONS
SSOP PACKAGE DRAWING
SIDE VIEW
VIEW
SEATING PLANE
VIEW
-0.002 0.064 0.009 0.311 0.291 0.197 0.022 0.025
INCHES -0.006 0.068 -0.323 0.307 0.209 0.026 0.03
0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.030 0.041
-0.05 1.62 0.22 7.90 7.40 5.00 0.55 0.63
MILLIMETERS -0.13 1.73 -8.20 7.80 5.30 0.65 0.75
NOTE 2.13 0.25 1.88 0.38 8.50 8.20 5.60 0.75 1.03
JEDEC MO-150
Controlling Dimension Millimeters. Notes: "E1" reference datums included mold flash protrusions, include mold mismatch measured parting line, mold flash protrusions shall exceed 0.20 side. Dimension does include dambar protrusion/intrusion. Allowable dambar protrusion shall 0.13 total excess dimension maximum material condition. Dambar intrusion shall reduce dimension more than 0.07 least material condition. These dimensions apply flat section lead between 0.10 0.25 from lead tips.
DS630PP2

Channel, Cost Converter Power Consumption Description C

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