Highest-Performance Fixed-Point Digital Signal Processors (DSPs)
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SMJ320C6414, SMJ320C6415, SMJ320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
Highest-Performance Fixed-Point Digital
Signal Processors (DSPs) 1.67-, 1.39-ns Instruction Cycle Time 600-MHz Clock Rate Eight 32-Bit Instructions/Cycle Twenty-Eight Operations/Cycle 4800 MIPS Fully Software-Compatible With C62x C6414/15/16 Devices Pin-Compatible VelociTI.2 Extensions VelociTI Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x Core Eight Highly Independent Functional Units With VelociTI.2 Extensions: ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, Quad 8-Bit Arithmetic Clock Cycle Multipliers Support Four 16-Bit Multiplies (32-Bit Results) Clock Cycle Eight 8-Bit Multiplies (16-Bit Results) Clock Cycle Non-Aligned Load-Store Architecture 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size Instructions Conditional Instruction Features Byte-Addressable (8-/16-/32-/64-Bit Data) 8-Bit Overflow Protection Bit-Field Extract, Set, Clear Normalization, Saturation, Bit-Counting VelociTI.2 Increased Orthogonality Viterbi Decoder Coprocessor (VCP) [C6416] Supports Over 7.95-Kbps Programmable Code Parameters Turbo Decoder Coprocessor (TCP) [C6416] Supports 2-Mbps 3GPP Iterations) Programmable Turbo Code Decoding Parameters L1/L2 Memory Architecture 128K-Bit (16K-Byte) Program Cache (Direct Mapped) 128K-Bit (16K-Byte) Data Cache (2-Way Set-Associative) 8M-Bit (1024K-Byte) Unified Mapped RAM/Cache (Flexible Allocation)
External Memory Interfaces (EMIFs)
64-Bit (EMIFA), 16-Bit (EMIFB) Glueless Interface Asynchronous Memories (SRAM EPROM) Synchronous Memories (SDRAM, SBSRAM, SRAM, FIFO) 1280M-Byte Total Addressable External Memory Space Enhanced Direct-Memory-Access (EDMA) Controller Independent Channels) Host-Port Interface (HPI) User-Configurable Width (32-/16-Bit) 32-Bit/33-MHz, 3.3-V Master/Slave Interface Conforms Specification [C6415/C6416 Three Address Registers: Prefetchable Memory Non-Prefetchable Memory Four-Wire Serial EEPROM Interface Interrupt Request Under Program Control Interrupt Cycle Three Multichannel Buffered Serial Ports Direct Interface T1/E1, MVIP, SCSA Framers Channels Each ST-Bus-Switching-, AC97-Compatible Serial Peripheral Interface (SPI) Compatible (Motorola) Three 32-Bit General-Purpose Timers Universal Test Operations Interface A(UTOPIA) [C6415/C6416] UTOPIA Level Slave AController 8-Bit Transmit Receive Operations Direction User-Defined Cell Format Bytes Sixteen General-Purpose (GPIO) Pins Flexible Clock Generator IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 570-Pin Grid Array (PGA) Package (GAD Suffix) 0.13-µm/6-Level Metal Process (CMOS) 3.3-V I/Os, 1.4-V Internal
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. C62x, VelociTI.2, VelociTI, TMS320C64x trademarks Texas Instruments. Motorola trademark Motorola, Inc. IEEE Standard 1149.1-1990 Standard-Test-Access Port Boundary Scan Architecture.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters. products compliant 38535, parameters tested unless otherwise noted. other products, production processing does necessarily include testing parameters.
Copyright 2004, Texas Instruments Incorporated
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SMJ320C6414, SMJ320C6415, SMJ320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
Table Contents
revision history package (bottom view) description device characteristics device compatibility functional block (DSP core) diagram (DSP core) description memory summary peripheral register descriptions EDMA channel synchronization events interrupt sources interrupt selector signal groups description device configurations multiplexed pins debugging considerations terminal functions development support documentation support clock general-purpose input/output (GPIO) power-down mode logic power-supply sequencing power-supply decoupling IEEE 1149.1 JTAG compatibility statement EMIF device speed bootmode absolute maximum ratings over operating case temperature range recommended operating conditions electrical characteristics over recommended ranges supply voltage operating case temperature
recommended clock control signal transition behavior parameter measurement information input output clocks asynchronous memory timing programmable synchronous interface timing synchronous DRAM timing HOLD/HOLDA timing BUSREQ timing reset timing external interrupt timing host-port interface (HPI) timing peripheral component interconnect (PCI) timing [C6415 C6416 only] multichannel buffered serial port (McBSP) timing UTOPIA slave timing [C6415 C6416 only] timer timing general-purpose input/output (GPIO) port timing JTAG test-port timing mechanical data
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SMJ320C6414, SMJ320C6415, SMJ320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
REVISION HISTORY
This data sheet revision history highlights technical changes made SMJ320C6414, SMJ320C6415, SMJ320C6416 device-specific data sheet. Scope: Applicable updates C64x device family, specifically relating C6414, C6415, C6416 devices, have been incorporated.
PAGE(S) Original release Removed A24, changed Cycle-to-cycle jitter Period jitter.
ADDITIONS/CHANGES/DELETIONS
Ceramic package (bottom view)
CERAMIC 570-PIN GRID ARRAY (PGA) PACKAGE BOTTOM VIEW
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description
TMS320C64x DSPs (including SMJ320C6414, SMJ320C6415, SMJ320C6416 devices) highest-performance fixed-point generation TMS320C6000 platform. TMS320C64x (C64x) device based second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture (VelociTI.2) developed Texas Instruments (TI), making these DSPs excellent choice multichannel multifunctional applications. C64x code-compatible member C6000 platform. With performance 5760 million instructions second (MIPS) clock rate MHz, C64x devices offer cost-effective solutions high-performance programming challenges. C64x DSPs possess operational flexibility high-speed controllers numerical capability array processors. C64x core processor general-purpose registers 32-bit word length eight highly independent functional units-two multipliers 32-bit result arithmetic logic units (ALUs)- with VelociTI.2 extensions. VelociTI.2 extensions eight functional units include instructions accelerate performance applications extend parallelism VelociTI architecture. C64x produce four 32-bit multiply-accumulates (MACs) cycle total 2400 million MACs second (MMACS), eight 8-bit MACs cycle total 4800 MMACS. C64x also application-specific hardware logic, on-chip memory, additional on-chip peripherals similar other C6000 platform devices. C6416 device high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP) Turbo Decoder Coprocessor (TCP)] that significantly speed channel-decoding operations on-chip. operating clock divided-by-4 decode over 7.95-Kbps adaptive multi-rate (AMR) 1/3] voice channels. supports constraint lengths rates 1/2, 1/3, 1/4, flexible polynomials, while generating hard decisions soft decisions. operating clock divided-by-2 decode thirty-six 384-Kbps 2-Mbps turbo encoded channels (assuming iterations). implements max*log-map algorithm designed support polynomials rates required Third-Generation Partnership Projects (3GPP 3GPP2), with fully programmable frame length turbo interleaver. Decoding parameters such number iterations stopping criteria also programmable. Communications between VCP/TCP carried through EDMA controller. C64x uses two-level cache-based architecture powerful diverse peripherals. Level program cache (L1P) 128K-bit direct mapped cache Level data cache (L1D) 128K-bit 2-way set-associative cache. Level memory/cache (L2) consists 8M-bit memory space that shared between program data space. memory configured mapped memory combinations cache 256K bytes) mapped memory. peripheral includes three multichannel buffered serial ports (McBSPs); 8-bit Universal Test Operations Interface Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port (C6415/C6416 only); three 32-bit general-purpose timers; user-configurable 16-bit 32-bit host-port interface (HPI16/HPI32); peripheral component interconnect (PCI) [C6415/C6416 only]; general-purpose input/output port (GPIO) with GPIO pins; glueless external memory interfaces (64-bit EMIFA 16-bit EMIFB), both which capable interfacing synchronous asynchronous memories peripherals. C64x complete development tools which includes: advanced compiler with C64x-specific enhancements, assembly optimizer simplify programming scheduling, Windows debugger interface visibility into source code execution.
TMS320C6000, C64x, C6000 trademarks Texas Instruments. Windows registered trademark Microsoft Corporation. trademarks property their respective owners. Throughout remainder this document, SMJ320C6414, SMJ320C6415, SMJ320C6416 shall referred SMJ320C64x C64x where generic, where specific, their individual full device part numbers will used abbreviated C6414, C6415, C6416. These C64x devices have EMIFs (64-bit EMIFA 16-bit EMIFB). prefix front signal name indicates EMIFA signal whereas prefix front signal name indicates EMIFB signal. Throughout rest this document, generic EMIF areas discussion, prefix omitted from signal name.
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device characteristics
Table provides overview C6414, C6415, C6416 DSPs. table shows significant features C64x devices, including capacity on-chip RAM, peripherals, frequency, package type with count. Table Characteristics C6414, C6415, C6416 Processors
HARDWARE FEATURES EMIFA (64-bit width) (default clock source AECLKIN) Peripherals peripherals pins available same time. (For more details, Device Configuration section.) Peripheral performance dependent chip-level configuration. EMIFB (16-bit width) (default clock source BECLKIN) EDMA independent channels) (32- 16-bit user selectable) (32-bit) [DeviceID Register value 0xA106] McBSPs (default internal clock source CPU/4 clock frequency) UTOPIA (8-bit mode) 32-Bit Timers (default internal clock source CPU/8 clock frequency) General-Purpose Input/Output (GP0) Decoder Coprocessors Size (Bytes) On-Chip Memory Organization Control Status Register (CSR.[31:16]) Silicon Revision Identification Register (DEVICE_REV [19:16]) Address: 0x01B0 0200 Core Voltage Options Package Process Technology Product Status CLKIN frequency multiplier Product Preview (PP) Advance Information (AI) Production Data (PD) DEVICE_REV[19:16] 1111 0001 0010 0000 C6414, C6415, C6416 (HPI16 HPI32) [C6415/C6416 only] [C6415/C6416 only] (C6416 only) (C6416 only) 1056K 16K-Byte (16KB) Program (L1P) Cache 16KB Data (L1D) Cache 1024KB Unified Mapped RAM/Cache (L2) 0x0C01 Silicon Revision 1.03 earlier 1.03 1.67 (C6414, C6415, C6416) (C6414A, C6415A, C6416A) [600-MHz CPU, 133-MHz EMIFA] Bypass (x1), 570-Pin (GAD) 0.13
Device_ID
Frequency Cycle Time
these C64x devices, rated EMIF speed affects only SDRAM interface EMIFA. more detailed information, EMIF Device Speed section this data sheet.
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device compatibility
C64x generation devices diverse powerful peripherals. common peripheral pin-compatibility that C6414, C6415, C6416 devices offer lead easier system designs faster time market. Table identifies peripherals coprocessors that available C6414, C6415, C6416 devices. C6414, C6415, C6416 devices pin-for-pin compatible, provided following conditions met:
devices using same peripherals.
C6414 pin-for-pin compatible with C6415/C6416 when UTOPIA peripherals C6415/C6416 disabled. C6415 pin-for-pin compatible with C6416 when they same peripheral selection mode. [For more information peripheral selection, Device Configurations section this data sheet.]
BEA[9:7] pins properly pulled up/down.
[For more details device-specific BEA[9:7] configurations, Terminal Functions table this data sheet.] Table Peripherals Coprocessors Available C6414, C6415, C6416 Devices
PERIPHERALS/COPROCESSORS EMIFA (64-bit width) EMIFB (16-bit width) EDMA independent channels) (32- 16-bit user selectable) (32-bit) [Specification v2.2] McBSPs (McBSP0, McBSP1, McBSP2) UTOPIA (8-bit mode) [Specification v1.0] Timers (32-bit) [TIMER0, TIMER1, TIMER2] GPIOs (GP[15:0]) VCP/TCP Coprocessors C6414 C6415 C6416
denotes peripheral/coprocessor available this device. peripherals pins available same time. (For more details, Device Configuration section.)
more detailed information device compatibility similarities/differences among C6414, C6415, C6416 devices, Begin Development Today With TMS320C6414, TMS320C6415, TMS320C6416 DSPs application report (literature number SPRA718).
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functional block (DSP core) diagram
C64x Digital Signal Processor
SDRAM SBSRAM SRAM FIFO SRAM ROM/FLASH Devices Timer Timer
Cache Direct-Mapped Bytes Total
EMIF EMIF C64x Core Instruction Fetch Instruction Dispatch Advanced Instruction Packet Instruction Decode Data Path Register File A31-A16 A15-A0 Data Path Register File B31-B16 B15-B0 Control Registers Control Logic Test Advanced In-Circuit Emulation Interrupt Control
Timer
McBSP2
UTOPIA: Mbps Master ATMC McBSPs: Framing Chips: H.100, MVIP, SCSA, AC97 Devices, Devices, Codecs UTOPIA Enhanced Controller (64-channel) Memory 1024K Bytes
McBSP1
McBSP0
Cache 2-Way Set-Associative Bytes Total
GPIO[8:0] GPIO[15:9]
(x1, x12) Power-Down Logic
Boot Configuration
Interrupt Selector
decoder coprocessors applicable C6416 device only. C6415 C6416 devices, UTOPIA peripheral MUXed with McBSP1, peripheral MUXed with peripheral GPIO[15:9] port. more details multiplexed pins these peripherals, Device Configurations section this data sheet.
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(DSP core) description
fetches VelociTI advanced very-long instruction words (VLIWs) (256 bits wide) supply eight 32-bit instructions eight functional units during every clock cycle. VelociTI VLIW architecture features controls which eight units have supplied with instructions they ready execute. first every 32-bit instruction determines next instruction belongs same execute packet previous instruction, whether should executed following clock part next execute packet. Fetch packets always bits wide; however, execute packets vary size. variable-length execute packets memory-saving feature, distinguishing C64x CPUs from other VLIW architectures. C64x VelociTI.2 extensions enhancements TMS320C62x VelociTI architecture. These enhancements include:
Register file enhancements Data path extensions Quad 8-bit dual 16-bit extensions with data flow enhancements Additional functional unit hardware Increased orthogonality instruction Additional instructions that reduce code size increase register flexibility
features sets functional units. Each contains four units register file. contains functional units .L1, .S1, .M1, .D1; other contains units .D2, .M2, .S2, .L2. register files each contain 32-bit registers total general-purpose registers. addition supporting packed 16-bit 32-/40-bit fixed-point data types found C62x VelociTI VLIW architecture, C64x register files also support packed 8-bit data 64-bit fixed-point data types. sets functional units, along with register files, compose sides [see functional block (DSP core) diagram, Figure four functional units each side freely share registers belonging that side. Additionally, each side features "data cross path"-a single data connected registers other side, which sets functional units access data from register files opposite side. C64x pipelines data-cross-path accesses over multiple clock cycles. This allows same register used data-cross-path operand multiple functional units same execute packet. functional units C64x access operands data cross path. Register access functional units same side register file service units single clock cycle. C64x CPU, delay clock introduced whenever instruction attempts read register data cross path that register updated previous clock cycle. addition C62x fixed-point instructions, C64x includes comprehensive collection quad 8-bit dual 16-bit instruction extensions. These VelociTI.2 extensions allow C64x operate directly packed data streamline data flow increase instruction efficiency. Another feature C64x load/store architecture, where instructions operate registers opposed data memory). sets data-addressing units (.D1 .D2) responsible data transfers between register files memory. data address driven units allows data addresses generated from register file used load store data from other register file. C64x units load store bytes bits), half-words bits), words bits) with single instruction. with data path extensions, C64x unit load store doublewords bits) with single instruction. Furthermore, non-aligned load store instructions allow units access words doublewords byte boundary. C64x supports variety indirect addressing modes using either linear- circular-addressing with 15-bit offsets. instructions conditional, most access registers. Some registers, however, singled support specific addressing modes hold condition conditional instructions condition automatically "true").
TMS320C62x trademark Texas Instruments.
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(DSP core) description (continued)
functional units perform multiplication operations. Each C64x units perform 16-bit multiplies four 8-bit multiplies clock cycle. unit also perform 32-bit multiply operations, dual 16-bit multiplies with add/subtract operations, quad 8-bit multiplies with operations. addition standard multiplies, C64x units include bit-count, rotate, Galois field multiplies, bidirectional variable shift hardware. functional units perform general arithmetic, logical, branch functions with results available every clock cycle. arithmetic logical functions C64x include single 32-bit, dual 16-bit, quad 8-bit operations. processing flow begins when 256-bit-wide instruction fetch packet fetched from program memory. 32-bit instructions destined individual functional units "linked" together bits least significant (LSB) position instructions. instructions that "chained" together simultaneous execution eight total) compose execute packet. instruction breaks chain, effectively placing instructions that follow next execute packet. C64x device enhancement allows execute packets cross fetch-packet boundaries. TMS320C62x/TMS320C67x devices, execute packet crosses fetch-packet boundary (256 bits wide), assembler places next fetch packet, while remainder current fetch packet padded with instructions. C64x device, execute boundary restrictions have been removed, thereby, eliminating NOPs added fetch packet, thus, decreasing overall code size. number execute packets within fetch packet vary from eight. Execute packets dispatched their respective functional units rate clock cycle next 256-bit fetch packet fetched until execute packets from current fetch packet have been dispatched. After decoding, instructions simultaneously drive active functional units maximum execution rate eight instructions every clock cycle. While most results stored 32-bit registers, they subsequently moved memory bytes, half-words, words, doublewords. load store instructions byte-, half-word-, word-, doubleword-addressable. more details C64x functional units enhancements, following documents: TMS320C6000 Instruction Reference Guide (literature number SPRU189) TMS320C64x Technical Overview (literature number SPRU395) Begin Development Today With TMS320C6414, TMS320C6415, TMS320C6416 DSPs application report (literature number SPRA718)
TMS320C67x trademark Texas Instruments.
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(DSP core) description (continued)
src1 src2
long long ST1b (Store Data) ST1a (Store Data) MSBs LSBs long long src1 Data Path src2 long src1 src2 LD1b (Load Data) LD1a (Load Data) (Address) MSBs LSBs src1 src2
Register File (A0-A31)
Note Note
src2 (Address) LD2a (Load Data) LD2b (Load Data) LSBs MSBs src2 src1 long src2 Data Path src1 long long Note Note Register File (B0- B31) src1
ST2a (Store Data) ST2b (Store Data)
MSBs LSBs long long src2 src1 Control Register File
NOTE functional units, long MSBs LSBs.
Figure SMJ320C64x (DSP Core) Data Paths
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memory summary
Table shows memory address ranges SMJ320C64x device. Internal memory always located address used both program data memory. external memory address ranges C64x device begin address locations 0x6000 0000 EMIFB 0x8000 0000 EMIFA.
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memory summary (continued)
Table SMJ320C64x Memory Summary
MEMORY BLOCK DESCRIPTION Internal (L2) Reserved External Memory Interface (EMIFA) Registers Registers Registers McBSP Registers McBSP Registers Timer Registers Timer Registers Interrupt Selector Registers EDMA EDMA Registers McBSP Registers EMIFB Registers Timer Registers GPIO Registers UTOPIA Registers (C6415 C6416 only) TCP/VCP Registers (C6416 only) Reserved Registers (C6415 C6416 only) Reserved QDMA Registers Reserved McBSP Data McBSP Data McBSP Data UTOPIA Queues (C6415 C6416 only) Reserved TCP/VCP (C6416 only) EMIFB EMIFB EMIFB EMIFB Reserved EMIFA EMIFA EMIFA EMIFA Reserved BLOCK SIZE (BYTES) 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 736M 256M 256M 256M 256M 256M 256M 256M ADDRESS RANGE
0000 0010 0180 0184 0188 018C 0190 0194 0198 019C 01A0 01A4 01A8 01AC 01B0 01B4 01B8 01BC 01C0 01C4 0200 0200 3000 3400 3800 3C00 4000 5000 6000 6400 6800 6C00 7000 8000 9000 A000 B000 C000
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0034 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
000F 017F 0183 0187 018B 018F 0193 0197 019B 019F 01A3 01A7 01AB 01AF 01B3 01B7 01BB 01BF 01C3 01FF 0200 2FFF 33FF 37FF 3BFF 3FFF 4FFF 5FFF 63FF 67FF 6BFF 6FFF 7FFF 8FFF 9FFF AFFF BFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 0033 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
C6414 device, these memory address locations reserved. C6414 device does support UTOPIA peripherals. Only C6416 device supports VCP/TCP Coprocessors. C6414 C6415 devices, these memory address locations reserved.
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peripheral register descriptions
Table through Table identify peripheral registers C6414, C6415, C6416 devices their register names, acronyms, address address range. more detailed information register contents, names their descriptions, specific peripheral reference guide listed TMS320C6000 Peripherals Overview Reference Guide (literature number SPRU190). Table EMIFA Registers
ADDRESS RANGE 0180 0000 0180 0004 0180 0008 0180 000C 0180 0010 0180 0014 0180 0018 0180 001C 0180 0020 0180 0024 0180 003C 0180 0040 0180 0044 0180 0048 0180 004C 0180 0050 0180 0054 0180 0058 0183 FFFF ACRONYM GBLCTL CECTL1 CECTL0 CECTL2 CECTL3 SDCTL SDTIM SDEXT PDTCTL CESEC1 CESEC0 CESEC2 CESEC3 EMIFA global control EMIFA space control EMIFA space control Reserved EMIFA space control EMIFA space control EMIFA SDRAM control EMIFA SDRAM refresh control EMIFA SDRAM extension Reserved Peripheral device transfer (PDT) control EMIFA space secondary control EMIFA space secondary control Reserved EMIFA space secondary control EMIFA space secondary control Reserved REGISTER NAME
Table EMIFB Registers
ADDRESS RANGE 01A8 0000 01A8 0004 01A8 0008 01A8 000C 01A8 0010 01A8 0014 01A8 0018 01A8 001C 01A8 0020 01A8 0024 01A8 003C 01A8 0040 01A8 0044 01A8 0048 01A8 004C 01A8 0050 01A8 0054 01A8 0058 01AB FFFF ACRONYM GBLCTL CECTL1 CECTL0 CECTL2 CECTL3 SDCTL SDTIM SDEXT PDTCTL CESEC1 CESEC0 CESEC2 CESEC3 EMIFB global control EMIFB space control EMIFB space control Reserved EMIFB space control EMIFB space control EMIFB SDRAM control EMIFB SDRAM refresh control EMIFB SDRAM extension Reserved Peripheral device transfer (PDT) control EMIFB space secondary control EMIFB space secondary control Reserved EMIFB space secondary control EMIFB space secondary control Reserved REGISTER NAME
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peripheral register descriptions (continued)
Table Cache Registers
ADDRESS RANGE 0184 0000 0184 0004 0184 0FFC 0184 1000 0184 1004 0184 1FFC 0184 2000 0184 2004 0184 2008 0184 200C 0184 2010 0184 3FFC 0184 4000 0184 4004 0184 4010 0184 4014 0184 4020 0184 4024 0184 4030 0184 4034 0184 4038 0184 4FFC 0184 5000 0184 5004 0184 5008 0184 7FFC 0184 8000 0184 817C 0184 8180 0184 8184 0184 8188 0184 818C 0184 8190 0184 8194 0184 8198 0184 819C 0184 81A0 0184 81A4 0184 81A8 0184 81AC 0184 81B0 0184 81B4 0184 81B8 0184 81BC 0184 81C0 0184 81FC 0184 8200 0184 8204 ACRONYM CCFG EDMAWEIGHT L2ALLOC0 L2ALLOC1 L2ALLOC2 L2ALLOC3 L2FBAR L2FWC L2CBAR L2CWC L1PFBAR L1PFWC L1DFBAR L1DFWC L2FLUSH L2CLEAN MAR0 MAR95 MAR96 MAR97 MAR98 MAR99 MAR100 MAR101 MAR102 MAR103 MAR104 MAR105 MAR106 MAR107 MAR108 MAR109 MAR110 MAR111 MAR112 MAR127 MAR128 MAR129 Reserved EDMA access control register Reserved allocation register allocation register allocation register allocation register Reserved flush base address register flush word count register clean base address register clean word count register flush base address register flush word count register flush base address register flush word count register Reserved flush register clean register Reserved Reserved Controls EMIFB range 6000 0000 60FF FFFF Controls EMIFB range 6100 0000 61FF FFFF Controls EMIFB range 6200 0000 62FF FFFF Controls EMIFB range 6300 0000 63FF FFFF Controls EMIFB range 6400 0000 64FF FFFF Controls EMIFB range 6500 0000 65FF FFFF Controls EMIFB range 6600 0000 66FF FFFF Controls EMIFB range 6700 0000 67FF FFFF Controls EMIFB range 6800 0000 68FF FFFF Controls EMIFB range 6900 0000 69FF FFFF Controls EMIFB range 6A00 0000 6AFF FFFF Controls EMIFB range 6B00 0000 6BFF FFFF Controls EMIFB range 6C00 0000 6CFF FFFF Controls EMIFB range 6D00 0000 6DFF FFFF Controls EMIFB range 6E00 0000 6EFF FFFF Controls EMIFB range 6F00 0000 6FFF FFFF Reserved Controls EMIFA range 8000 0000 80FF FFFF Controls EMIFA range 8100 0000 81FF FFFF REGISTER NAME Cache configuration register COMMENTS
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SMJ320C6414, SMJ320C6415, SMJ320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
Table Cache Registers (Continued)
ADDRESS RANGE 0184 8208 0184 820C 0184 8210 0184 8214 0184 8218 0184 821C 0184 8220 0184 8224 0184 8228 0184 822C 0184 8230 0184 8234 0184 8238 0184 823C 0184 8240 0184 8244 0184 8248 0184 824C 0184 8250 0184 8254 0184 8258 0184 825C 0184 8260 0184 8264 0184 8268 0184 826C 0184 8270 0184 8274 0184 8278 0184 827C 0184 8280 0184 8284 0184 8288 0184 828C 0184 8290 0184 8294 0184 8298 0184 829C 0184 82A0 0184 82A4 0184 82A8 0184 82AC 0184 82B0 0184 82B4 ACRONYM MAR130 MAR131 MAR132 MAR133 MAR134 MAR135 MAR136 MAR137 MAR138 MAR139 MAR140 MAR141 MAR142 MAR143 MAR144 MAR145 MAR146 MAR147 MAR148 MAR149 MAR150 MAR151 MAR152 MAR153 MAR154 MAR155 MAR156 MAR157 MAR158 MAR159 MAR160 MAR161 MAR162 MAR163 MAR164 MAR165 MAR166 MAR167 MAR168 MAR169 MAR170 MAR171 MAR172 MAR173 REGISTER NAME Controls EMIFA range 8200 0000 82FF FFFF Controls EMIFA range 8300 0000 83FF FFFF Controls EMIFA range 8400 0000 84FF FFFF Controls EMIFA range 8500 0000 85FF FFFF Controls EMIFA range 8600 0000 86FF FFFF Controls EMIFA range 8700 0000 87FF FFFF Controls EMIFA range 8800 0000 88FF FFFF Controls EMIFA range 8900 0000 89FF FFFF Controls EMIFA range 8A00 0000 8AFF FFFF Controls EMIFA range 8B00 0000 8BFF FFFF Controls EMIFA range 8C00 0000 8CFF FFFF Controls EMIFA range 8D00 0000 8DFF FFFF Controls EMIFA range 8E00 0000 8EFF FFFF Controls EMIFA range 8F00 0000 8FFF FFFF Controls EMIFA range 9000 0000 90FF FFFF Controls EMIFA range 9100 0000 91FF FFFF Controls EMIFA range 9200 0000 92FF FFFF Controls EMIFA range 9300 0000 93FF FFFF Controls EMIFA range 9400 0000 94FF FFFF Controls EMIFA range 9500 0000 95FF FFFF Controls EMIFA range 9600 0000 96FF FFFF Controls EMIFA range 9700 0000 97FF FFFF Controls EMIFA range 9800 0000 98FF FFFF Controls EMIFA range 9900 0000 99FF FFFF Controls EMIFA range 9A00 0000 9AFF FFFF Controls EMIFA range 9B00 0000 9BFF FFFF Controls EMIFA range 9C00 0000 9CFF FFFF Controls EMIFA range 9D00 0000 9DFF FFFF Controls EMIFA range 9E00 0000 9EFF FFFF Controls EMIFA range 9F00 0000 9FFF FFFF Controls EMIFA range A000 0000 A0FF FFFF Controls EMIFA range A100 0000 A1FF FFFF Controls EMIFA range A200 0000 A2FF FFFF Controls EMIFA range A300 0000 A3FF FFFF Controls EMIFA range A400 0000 A4FF FFFF Controls EMIFA range A500 0000 A5FF FFFF Controls EMIFA range A600 0000 A6FF FFFF Controls EMIFA range A700 0000 A7FF FFFF Controls EMIFA range A800 0000 A8FF FFFF Controls EMIFA range A900 0000 A9FF FFFF Controls EMIFA range AA00 0000 AAFF FFFF Controls EMIFA range AB00 0000 ABFF FFFF Controls EMIFA range AC00 0000 ACFF FFFF Controls EMIFA range AD00 0000 ADFF FFFF COMMENTS
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Table Cache Registers (Continued)
ADDRESS RANGE 0184 82B8 0184 82BC 0184 82C0 0184 82C4 0184 82C8 0184 82CC 0184 82D0 0184 82D4 0184 82D8 0184 82DC 0184 82E0 0184 82E4 0184 82E8 0184 82EC 0184 82F0 0184 82F4 0184 82F8 0184 82FC 0184 8300 0184 83FC 0184 8400 0187 FFFF ACRONYM MAR174 MAR175 MAR176 MAR177 MAR178 MAR179 MAR180 MAR181 MAR182 MAR183 MAR184 MAR185 MAR186 MAR187 MAR188 MAR189 MAR190 MAR191 MAR192 MAR255 REGISTER NAME Controls EMIFA range AE00 0000 AEFF FFFF Controls EMIFA range AF00 0000 AFFF FFFF Controls EMIFA range B000 0000 B0FF FFFF Controls EMIFA range B100 0000 B1FF FFFF Controls EMIFA range B200 0000 B2FF FFFF Controls EMIFA range B300 0000 B3FF FFFF Controls EMIFA range B400 0000 B4FF FFFF Controls EMIFA range B500 0000 B5FF FFFF Controls EMIFA range B600 0000 B6FF FFFF Controls EMIFA range B700 0000 B7FF FFFF Controls EMIFA range B800 0000 B8FF FFFF Controls EMIFA range B900 0000 B9FF FFFF Controls EMIFA range BA00 0000 BAFF FFFF Controls EMIFA range BB00 0000 BBFF FFFF Controls EMIFA range BC00 0000 BCFF FFFF Controls EMIFA range BD00 0000 BDFF FFFF Controls EMIFA range BE00 0000 BEFF FFFF Controls EMIFA range BF00 0000 BFFF FFFF Reserved Reserved COMMENTS
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peripheral register descriptions (continued)
Table EDMA Registers
ADDRESS RANGE 01A0 FF9C 01A0 FFA4 01A0 FFA8 01A0 FFAC 01A0 FFB0 01A0 FFB4 01A0 FFB8 01A0 FFBC 01A0 FFC0 01A0 FFC4 01A0 FFC8 01A0 FFCC 01A0 FFDC 01A0 FFE0 01A0 FFE4 01A0 FFE8 01A0 FFEC 01A0 FFF0 01A0 FFF4 01A0 FFF8 01A0 FFFC 01A1 0000 01A3 FFFF ACRONYM EPRH CIPRH CIERH CCERH EERH ECRH ESRH PQAR0 PQAR1 PQAR2 PQAR3 EPRL PQSR CIPRL CIERL CCERL EERL ECRL ESRL REGISTER NAME Event polarity high register Channel interrupt pending high register Channel interrupt enable high register Channel chain enable high register Event high register Event enable high register Event clear high register Event high register Priority queue allocation register Priority queue allocation register Priority queue allocation register Priority queue allocation register Event polarity register Priority queue status register Channel interrupt pending register Channel interrupt enable register Channel chain enable register Event register Event enable register Event clear register Event register Reserved
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peripheral register descriptions (continued)
Table EDMA Parameter
ADDRESS RANGE 01A0 0000 01A0 0017 01A0 0018 01A0 002F 01A0 0030 01A0 0047 01A0 0048 01A0 005F 01A0 0060 01A0 0077 01A0 0078 01A0 008F 01A0 0090 01A0 00A7 01A0 00A8 01A0 00BF 01A0 00C0 01A0 00D7 01A0 00D8 01A0 00EF 01A0 00F0 01A0 00107 01A0 0108 01A0 011F 01A0 0120 01A0 0137 01A0 0138 01A0 014F 01A0 0150 01A0 0167 01A0 0168 01A0 017F 01A0 0150 01A0 0167 01A0 0168 01A0 017F 01A0 05D0 01A0 05E7 01A0 05E8 01A0 05FF 01A0 0600 01A0 0617 01A0 0618 01A0 062F 01A0 07E0 01A0 07F7 01A0 07F8 01A0 07FF ACRONYM REGISTER NAME Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Reload/link parameters Event words) Reload/link parameters Event words) Reload/link parameters Event words) COMMENTS
Scratch area words) C64x device twenty-one parameter sets [six words each] that used reload/link EDMA transfers.
Table Quick (QDMA) Pseudo Registers
ADDRESS RANGE 0200 0000 0200 0004 0200 0008 0200 000C 0200 0010 0200 0014 0200 001C 0200 0020 0200 0024 0200 0028 0200 002C 0200 0030 QSOPT QSSRC QSCNT QSDST QSIDX ACRONYM QOPT QSRC QCNT QDST QIDX REGISTER NAME QDMA options parameter register QDMA source address register QDMA frame count register QDMA destination address register QDMA index register Reserved QDMA pseudo options register QDMA pseudo source address register QDMA pseudo frame count register QDMA pseudo destination address register QDMA pseudo index register
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peripheral register descriptions (continued)
Table Interrupt Selector Registers
ADDRESS RANGE 019C 0000 019C 0004 019C 0008 019C 000C 019C 01FF ACRONYM MUXH MUXL EXTPOL REGISTER NAME Interrupt multiplexer high Interrupt multiplexer External interrupt polarity Reserved COMMENTS Selects which interrupts drive interrupts 10-15 (INT10-INT15) Selects which interrupts drive interrupts (INT04-INT09) Sets polarity external interrupts (EXT_INT4-EXT_INT7)
Table McBSP Registers
ADDRESS RANGE 018C 0000 0x3000 0000 0x33FF FFFF 018C 0004 0x3000 0000 0x33FF FFFF 018C 0008 018C 000C 018C 0010 018C 0014 018C 0018 018C 001C 018C 0020 018C 0024 018C 0028 018C 002C 018C 0030 018C 0034 018C 0038 018C 003C 018C 0040 018F FFFF ACRONYM DRR0 DRR0 DXR0 DXR0 SPCR0 RCR0 XCR0 SRGR0 MCR0 RCERE00 XCERE00 PCR0 RCERE10 XCERE10 RCERE20 XCERE20 RCERE30 XCERE30 REGISTER NAME McBSP0 data receive register Configuration McBSP0 data receive register Peripheral McBSP0 data transmit register Configuration McBSP0 data transmit register Peripheral McBSP0 serial port control register McBSP0 receive control register McBSP0 transmit control register McBSP0 sample rate generator register McBSP0 multichannel control register McBSP0 enhanced receive channel enable register McBSP0 enhanced transmit channel enable register McBSP0 control register McBSP0 enhanced receive channel enable register McBSP0 enhanced transmit channel enable register McBSP0 enhanced receive channel enable register McBSP0 enhanced transmit channel enable register McBSP0 enhanced receive channel enable register McBSP0 enhanced transmit channel enable register Reserved COMMENTS EDMA controller only read this register; they cannot write
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peripheral register descriptions (continued)
Table McBSP Registers
ADDRESS RANGE 0190 0000 0x3400 0000 0x37FF FFFF 0190 0004 0x3400 0000 0x37FF FFFF 0190 0008 0190 000C 0190 0010 0190 0014 0190 0018 0190 001C 0190 0020 0190 0024 0190 0028 0190 002C 0190 0030 0190 0034 0190 0038 0190 003C 0190 0040 0193 FFFF ACRONYM DRR1 DRR1 DXR1 DXR1 SPCR1 RCR1 XCR1 SRGR1 MCR1 RCERE01 XCERE01 PCR1 RCERE11 XCERE11 RCERE21 XCERE21 RCERE31 XCERE31 REGISTER NAME McBSP1 data receive register Configuration McBSP1 data receive register Peripheral McBSP1 data transmit register Configuration McBSP1 data transmit register Peripheral McBSP1 serial port control register McBSP1 receive control register McBSP1 transmit control register McBSP1 sample rate generator register McBSP1 multichannel control register McBSP1 enhanced receive channel enable register McBSP1 enhanced transmit channel enable register McBSP1 control register McBSP1 enhanced receive channel enable register McBSP1 enhanced transmit channel enable register McBSP1 enhanced receive channel enable register McBSP1 enhanced transmit channel enable register McBSP1 enhanced receive channel enable register McBSP1 enhanced transmit channel enable register Reserved COMMENTS EDMA controller only read this register; they cannot write
Table McBSP Registers
ADDRESS RANGE 01A4 0000 0x3800 0000 0x3BFF FFFF 01A4 0004 0x3800 0000 0x3BFF FFFF 01A4 0008 01A4 000C 01A4 0010 01A4 0014 01A4 0018 01A4 001C 01A4 0020 01A4 0024 01A4 0028 01A4 002C 01A4 0030 01A4 0034 01A4 0038 01A4 003C 01A4 0040 01A7 FFFF ACRONYM DRR2 DRR2 DXR2 DXR2 SPCR2 RCR2 XCR2 SRGR2 MCR2 RCERE02 XCERE02 PCR2 RCERE12 XCERE12 RCERE22 XCERE22 RCERE32 XCERE32 REGISTER NAME McBSP2 data receive register Configuration McBSP2 data receive register Peripheral McBSP2 data transmit register Configuration McBSP2 data transmit register Peripheral McBSP2 serial port control register McBSP2 receive control register McBSP2 transmit control register McBSP2 sample rate generator register McBSP2 multichannel control register McBSP2 enhanced receive channel enable register McBSP2 enhanced transmit channel enable register McBSP2 control register McBSP2 enhanced receive channel enable register McBSP2 enhanced transmit channel enable register McBSP2 enhanced receive channel enable register McBSP2 enhanced transmit channel enable register McBSP2 enhanced receive channel enable register McBSP2 enhanced transmit channel enable register Reserved COMMENTS EDMA controller only read this register; they cannot write
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peripheral register descriptions (continued)
Table Timer Registers
ADDRESS RANGE 0194 0000 ACRONYM CTL0 REGISTER NAME Timer control register COMMENTS Determines operating mode timer, monitors timer status, controls function TOUT pin. Contains number timer input clock cycles count. This number controls TSTAT signal frequency. Contains current value incrementing counter.
0194 0004
PRD0
Timer period register
0194 0008 0194 000C 0197 FFFF
CNT0
Timer counter register Reserved
Table Timer Registers
ADDRESS RANGE 0198 0000 ACRONYM CTL1 REGISTER NAME Timer control register COMMENTS Determines operating mode timer, monitors timer status, controls function TOUT pin. Contains number timer input clock cycles count. This number controls TSTAT signal frequency. Contains current value incrementing counter.
0198 0004
PRD1
Timer period register
0198 0008 0198 000C 019B FFFF
CNT1
Timer counter register Reserved
Table Timer Registers
ADDRESS RANGE 01AC 0000 ACRONYM CTL2 REGISTER NAME Timer control register COMMENTS Determines operating mode timer, monitors timer status, controls function TOUT pin. Contains number timer input clock cycles count. This number controls TSTAT signal frequency. Contains current value incrementing counter.
01AC 0004
PRD2
Timer period register
01AC 0008 01AC 000C 01AF FFFF
CNT2
Timer counter register Reserved
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peripheral register descriptions (continued)
Table Registers
ADDRESS RANGE 0188 0000 0188 0004 0188 0008 0188 000C 0189 FFFF 018A 0000 018A 0004 018B FFFF ACRONYM HPID HPIC HPIA (HPIAW) HPIA (HPIAR) TRCTL data register control register address register (Write) address register (Read) Reserved transfer request control register REGISTER NAME COMMENTS Host read/write access only HPIC both Host/CPU read/write access HPIA both Host/CPU read/write access
Reserved Host access HPIA register updates both HPIAW HPIAR registers. access HPIAW HPIAR independently.
Table GPIO Registers
ADDRESS RANGE 01B0 0000 01B0 0004 01B0 0008 01B0 000C 01B0 0010 01B0 0014 01B0 0018 01B0 001C 01B0 0020 01B0 0024 01B0 0028 01B0 01FF 01B0 0200 01B0 0204 01B3 FFFF ACRONYM GPEN GPDIR GPVAL GPDH GPHM GPDL GPLM GPGC GPPOL DEVICE_REV REGISTER NAME GPIO enable register GPIO direction register GPIO value register Reserved GPIO delta high register GPIO high mask register GPIO delta register GPIO mask register GPIO global control register GPIO interrupt polarity register Reserved Silicon Revision Identification Register (For more details, device characteristics listed Table Reserved
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peripheral register descriptions (continued)
Table Peripheral Registers (C6415 C6416 Only)
ADDRESS RANGE 01C0 0000 01C0 0004 01C0 0008 01C0 000C 01C0 0010 01C0 0014 01C0 0018 01C0 001C 01C0 0020 01C0 0024 01C0 0028 01C0 002C 01C1 FFEF 0x01C1 FFF0 0x01C1 FFF4 0x01C1 FFF8 0x01C1 FFFC 01C2 0000 01C2 0004 01C2 0008 01C2 000C 01C2 FFFF 01C3 0000 01C3 0004 01C3 FFFF ACRONYM RSTSRC PCIIS PCIIEN DSPMA PCIMA PCIMC CDSPA CPCIA CCNT HDCR DSPP EEADD EEDAT EECTL TRCTL Reserved interrupt source register interrupt enable register master address register master address register master control register Current address register Current address register Current byte count register Reserved Reserved Host status register Host-to-DSP control register page register Reserved EEPROM address register EEPROM data register EEPROM control register Reserved transfer request control register REGISTER NAME Reset source/status register
Reserved These registers supported C6414 device.
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peripheral register descriptions (continued)
Table UTOPIA (C6415 C6416 Only)
ADDRESS RANGE 01B4 0000 01B4 0004 01B4 0008 01B4 000C 01B4 0010 01B4 0014 01B4 0018 01B4 001C 01B4 0020 01B7 FFFF ACRONYM UIER UIPR EIER EIPR Reserved Reserved UTOPIA interrupt enable register UTOPIA interrupt pending register Clock detect register Error interrupt enable register Error interrupt pending register REGISTER NAME UTOPIA control register
Reserved These UTOPIA registers supported C6414 device.
Table UTOPIA QUEUES (C6415 C6416 Only)
ADDRESS RANGE 3C00 0000 3D00 0000 3D00 0004 3FFF FFFF ACRONYM REGISTER NAME UTOPIA receive queue UTOPIA transmit queue
Reserved These UTOPIA registers supported C6414 device.
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peripheral register descriptions (continued)
Table Registers (C6416 Only)
EDMA ADDRESS RANGE 5000 0000 5000 0004 5000 0008 5000 000C 5000 0010 5000 0014 5000 0040 5000 0044 5000 0080 5000 0088 PERIPHERAL ADDRESS RANGE 01B8 0000 01B8 0004 01B8 0008 01B8 000C 01B8 0010 01B8 0014 01B8 0024 01B8 0028 01B8 0018 01B8 0020 01B8 0040 01B8 0044 01B8 0050 ACRONYM VCPIC0 VCPIC1 VCPIC2 VCPIC3 VCPIC4 VCPIC5 VCPOUT0 VCPOUT1 VCPWBM VCPRDECS VCPEXE VCPEND VCPSTAT0 VCPSTAT1 VCPERR REGISTER NAME input configuration register input configuration register input configuration register input configuration register input configuration register input configuration register output register output register branch metrics write register decisions read register execution register endian register status register status register error register
These registers supported C6416 device only.
Table Registers (C6416 Only)
EDMA ADDRESS RANGE 5800 0000 5800 0004 5800 0008 5800 000C 5800 0010 5800 0014 5800 0018 5800 001C 5800 0020 5800 0024 5800 0028 5800 002C 5800 0030 5802 0000 5804 0000 5806 0000 5808 0000 580A 0000 PERIPHERAL ADDRESS RANGE 01BA 0000 01BA 0004 01BA 0008 01BA 000C 01BA 0010 01BA 0014 01BA 0018 01BA 001C 01BA 0020 01BA 0024 01BA 0028 01BA 002C 01BA 0030 01BA 0038 01BA 0040 01BA 0050 01BA 0058 ACRONYM TCPIC0 TCPIC1 TCPIC2 TCPIC3 TCPIC4 TCPIC5 TCPIC6 TCPIC7 TCPIC8 TCPIC9 TCPIC10 TCPIC11 TCPOUT TCPSP TCPEXT TCPAP TCPINTER TCPHD TCPEXE TCPEND TCPERR TCPSTAT REGISTER NAME input configuration register input configuration register input configuration register input configuration register input configuration register input configuration register input configuration register input configuration register input configuration register input configuration register input configuration register input configuration register output parameters register systematics parities memory extrinsic memory apriori memory interleaver memory hard decisions memory execution register endian register error register status register
These registers supported C6416 device only.
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EDMA channel synchronization events
C64x EDMA supports EDMA channels which service peripheral devices external memory. Table lists source C64x EDMA synchronization events associated with each programmable EDMA channels. C64x device, association event channel fixed; each EDMA channels specific event associated with These specific events captured EDMA event registers (ERL, ERH) even events disabled EDMA event enable registers (EERL, EERH). priority each event specified independently transfer parameters stored EDMA parameter RAM. more detailed information EDMA module EDMA events enabled, captured, processed, linked, chained, cleared, etc., TMS320C6000 Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234).
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EDMA channel synchronization events (continued)
Table SMJ320C64x EDMA Channel Synchronization Events
EDMA CHANNEL
22-27 33-39 41-47 56-63
EVENT NAME
DSP_INT TINT0 TINT1 SD_INTA GPINT4/EXT_INT4 GPINT5/EXT_INT5 GPINT6/EXT_INT6 GPINT7/EXT_INT7 GPINT0 GPINT1 GPINT2 GPINT3 XEVT0 REVT0 XEVT1 REVT1 XEVT2 REVT2 TINT2 SD_INTB VCPREVT VCPXEVT TCPREVT TCPXEVT UREVT UXEVT GPINT8 GPINT9 GPINT10 GPINT11 GPINT12 GPINT13 GPINT14 GPINT15
EVENT DESCRIPTION
HPI/PCI-to-DSP interrupt (PCI peripheral supported C6415 C6416 only) Timer interrupt Timer interrupt EMIFA SDRAM timer interrupt GPIO event 4/External interrupt GPIO event 5/External interrupt GPIO event 6/External interrupt GPIO event 7/External interrupt GPIO event GPIO event GPIO event GPIO event McBSP0 transmit event McBSP0 receive event McBSP1 transmit event McBSP1 receive event None McBSP2 transmit event McBSP2 receive event Timer interrupt EMIFB SDRAM timer interrupt Reserved, future expansion None receive event (C6416 transmit event (C6416 receive event (C6416 transmit event (C6416 UTOPIA receive event (C6415 C6416 only) None UTOPIA transmit event (C6415 C6416 only) None GPIO event GPIO event GPIO event GPIO event GPIO event GPIO event GPIO event GPIO event None
addition events shown this table, each channels also synchronized with transfer completion alternate transfer completion events. more detailed information EDMA event-transfer chaining, TMS320C6000 Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234). UTOPIA peripherals supported C6414 device; therefore, these EDMA synchronization events reserved. VCP/TCP EDMA synchronization events supported C6416 only. C6414 C6415 devices, these events reserved.
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interrupt sources interrupt selector
C64x core supports prioritized interrupts, which listed Table highest-priority interrupt INT_00 (dedicated RESET) while lowest-priority interrupt INT_15. first four interrupts (INT_00-INT_03) non-maskable fixed. remaining interrupts (INT_04-INT_15) maskable default interrupt source specified Table interrupt source interrupts 4-15 programmed modifying selector value (binary value) corresponding fields Interrupt Selector Control registers: MUXH (address 0x019C0000) MUXL (address 0x019C0004).
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interrupt sources interrupt selector (continued)
Table C64x Interrupts
INTERRUPT NUMBER INT_00 INT_01 INT_02 INT_03 INT_04 INT_05 INT_06 INT_07 INT_08 INT_09 INT_10 INT_11 INT_12 INT_13 INT_14 INT_15 INTERRUPT SELECTOR CONTROL REGISTER MUXL[4:0] MUXL[9:5] MUXL[14:10] MUXL[20:16] MUXL[25:21] MUXL[30:26] MUXH[4:0] MUXH[9:5] MUXH[14:10] MUXH[20:16] MUXH[25:21] MUXH[30:26] SELECTOR VALUE (BINARY) 00100 00101 00110 00111 01000 01001 00011 01010 01011 00000 00001 00010 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11101 11110 11111 INTERRUPT EVENT RESET Reserved Reserved GPINT4/EXT_INT4 GPINT5/EXT_INT5 GPINT6/EXT_INT6 GPINT7/EXT_INT7 EDMA_INT EMU_DTDMA SD_INTA EMU_RTDXRX EMU_RTDXTX DSP_INT TINT0 TINT1 XINT0 RINT0 XINT1 RINT1 GPINT0 XINT2 RINT2 TINT2 SD_INTB Reserved Reserved UINT Reserved VCPINT TCPINT Reserved. use. Reserved. use. GPIO interrupt 4/External interrupt GPIO interrupt 5/External interrupt GPIO interrupt 6/External interrupt GPIO interrupt 7/External interrupt EDMA channel through interrupt DTDMA EMIFA SDRAM timer interrupt real-time data exchange (RTDX) receive RTDX transmit HPI/PCI-to-DSP interrupt (PCI supported C6415 C6416 only) Timer interrupt Timer interrupt McBSP0 transmit interrupt McBSP0 receive interrupt McBSP1 transmit interrupt McBSP1 receive interrupt GPIO interrupt McBSP2 transmit interrupt McBSP2 receive interrupt Timer interrupt EMIFB SDRAM timer interrupt Reserved. use. Reserved. use. UTOPIA interrupt (C6415/C6416 only) Reserved. use. interrupt (C6416 only) interrupt (C6416 only) INTERRUPT SOURCE
Interrupts INT_00 through INT_03 non-maskable fixed. Interrupts INT_04 through INT_15 programmable modifying binary selector values Interrupt Selector Control registers fields. Table shows default interrupt sources Interrupts INT_04 through INT_15. more detailed information interrupt sources selection, TMS320C6000 Interrupt Selector Reference Guide (literature number SPRU646).
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signal groups description
CLKIN CLKOUT4/GP1 CLKOUT6/GP2 CLKMODE1 CLKMODE0 PLLV
Clock/PLL
Reset Interrupts
RESET GP7/EXT_INT7 GP6/EXT_INT6 GP5/EXT_INT5 GP4/EXT_INT4
TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5 EMU6 EMU7 EMU8 EMU9 EMU10 EMU11
Reserved
IEEE Standard 1149.1 (JTAG) Emulation
Peripheral Control/Status
PCI_EN MCBSP2_EN
Control/Status
CLKS2/GP8
GPIO
GP7/EXT_INT7 GP6/EXT_INT6 GP5/EXT_INT5 GP4/EXT_INT4 CLKOUT6/GP2 CLKOUT4/GP1
General-Purpose Input/Output (GPIO) Port These pins MUXed with GPIO port pins default these signals function clocks (CLKOUT4 CLKOUT6) McBSP2 clock source (CLKS2). these MUXed pins GPIO signals, appropriate GPIO register bits (GPxEN GPxDIR) must properly enabled configured. more details, Device Configurations section this data sheet. These pins GPIO pins that also function external interrupt sources (EXT_INT[7:4]). Default after reset EXT_INTx GPIO input-only. C6415 C6416 devices, these GPIO pins MUXed with peripheral pins. default, these signals function with both GPIO functions disabled. more details these MUXed pins, Device Configurations section this data sheet. C6414 device, GPIO peripheral pins MUXed; C6414 device does support peripheral.
Figure Peripheral Signals
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signal groups description (continued)
AED[63:0] ACE3 ACE2 ACE1 ACE0 AEA[22:3] ABE7 ABE6 ABE5 ABE4 ABE3 ABE2 ABE1 ABE0 Byte Enables Memory Space Select External Memory Control Data AECLKIN AECLKOUT1 AECLKOUT2 ASDCKE AARE/ASDCAS/ASADS/ASRE AAOE/ASDRAS/ASOE AAWE/ASDWE/ASWE AARDY ASOE3 APDT
Address
Arbitration
AHOLD AHOLDA ABUSREQ
EMIFA (64-bit)
BED[15:0] Data BECLKIN BECLKOUT1 BECLKOUT2 Memory Space Select External Memory Control BARE/BSDCAS/BSADS/BSRE BAOE/BSDRAS/BSOE BAWE/BSDWE/BSWE BARDY BSOE3 BPDT
BCE3 BCE2 BCE1 BCE0 BEA[20:1]
Address
BBE1 BBE0
Byte Enables Arbitration EMIFB (16-bit)
BHOLD BHOLDA BBUSREQ
These C64x devices have EMIFs (64-bit EMIFA 16-bit EMIFB). prefix front signal name indicates EMIFA signal whereas prefix front signal name indicates EMIFB signal. Throughout rest this document, generic EMIF areas discussion, prefix omitted from signal name.
Figure Peripheral Signals
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signal groups description (continued)
(Host-Port Interface) HAS/PPAR HR/W/PCBE2 HCS/PPERR HDS1/PSERR HDS2/PCBE1 HRDY/PIRDY HINT/PFRAME
HD[31:0]/AD[31:0]
Data
HCNTL0/PSTOP HCNTL1/PDEVSEL
Register Select Control Half-Word Select
HHWIL/PTRDY (HPI16 ONLY)
HD[31:0]/AD[31:0] Data/Address Clock GP14/PCLK
GP10/PCBE3 HR/W/PCBE2 HDS2/PCBE1
Command Byte Enable
Control
GP9/PIDSEL HCNTL1/PDEVSEL HINT/PFRAME GP13/PINTA HAS/PPAR GP15/PRST HRDY/PIRDY HCNTL0/PSTOP HHWIL/PTRDY
GP12/PGNT GP11/PREQ
Arbitration Error
HDS1/PSERR HCS/PPERR
Serial EEPROM Interface (C6415 C6416 Only)
DX2/XSP_DO CLKX2/XSP_CLK DR2/XSP_DI
C6415 C6416 devices, these pins MUXed with peripheral. default, these signals function HPI. more details these MUXed pins, Device Configurations section this data sheet. C6414 device, these pins MUXed; C6414 device does support peripheral. C6415 C6416 devices, these pins (excluding PCBE0 XSP_CS) MUXed with HPI, McBSP2, GPIO peripherals. default, these signals function HPI, McBSP2, function, respectively. more details these MUXed pins, Device Configurations section this data sheet. C6414 device, HPI, McBSP2, GPIO peripheral pins MUXed; C6414 device does support peripheral. C6414 device, these pins "Reserved (leave unconnected, connect power ground)."
Figure Peripheral Signals (Continued)
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signal groups description (continued)
McBSP1 CLKX1/URADDR4 FSX1/UXADDR3 DX1/UXADDR4 CLKR1/URADDR2 FSR1/UXADDR2 DR1/UXADDR1 CLKS1/URADDR3 Transmit McBSP0 Transmit CLKX0 FSX0 CLKR0 FSR0 Clock Clock CLKS0
Receive
Receive
McBSP2 CLKX2/XSP_CLK FSX2 DX2/XSP_DO CLKR2 FSR2 DR2/XSP_DI CLKS2/GP8 Transmit
Receive
Clock
McBSPs (Multichannel Buffered Serial Ports)
C6415 C6416 devices, these McBSP2 McBSP1 pins MUXed with UTOPIA peripherals, respectively. default, these signals function McBSP2 McBSP1, respectively. more details these MUXed pins, Device Configurations section this data sheet. C6414 device, these McBSP2 McBSP1 peripheral pins MUXed; C6414 device does support UTOPIA peripherals. McBSP2 clock source (CLKS2, default) MUXed with pin. this MUXed signal, appropriate GPIO register bits (GP8EN GP8DIR) must properly enabled configured. more details, Device Configurations section this data sheet.
Figure Peripheral Signals (Continued)
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signal groups description (continued)
UTOPIA (SLAVE) [C6415 C6416 Only]
URDATA7 URDATA6 URDATA5 URDATA4 URDATA3 URDATA2 URDATA1 URDATA0
Receive
Transmit
UXDATA7 UXDATA6 UXDATA5 UXDATA4 UXDATA3 UXDATA2 UXDATA1 UXDATA0
URENB CLKX1/URADDR4 CLKS1/URADDR3 CLKR1/URADDR2 URADDR1 URADDR0 URCLAV URSOC
Control/Status
Control/Status
UXENB DX1/UXADDR4 FSX1/UXADDR3 FSR1/UXADDR2 DR1/UXADDR1 UXADDR0 UXCLAV UXSOC
URCLK
Clock
Clock
UXCLK
TOUT1 TINP1 TOUT2 TINP2
Timer
Timer
TOUT0 TINP0
Timer Timers
C6415 C6416 devices, these UTOPIA pins MUXed with McBSP1 peripheral. default, these signals function McBSP1. more details these MUXed pins, Device Configurations section this data sheet. C6414 device, these McBSP1 peripheral pins MUXed; C6414 does support UTOPIA peripheral.
Figure Peripheral Signals (Continued)
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DEVICE CONFIGURATIONS
C6414, C6415, C6416 peripheral selections other device configurations determined external pullup/pulldown resistors following pins (all which latched during device reset):
peripherals selection (C6415 C6416 devices)
BEA11 (UTOPIA_EN) PCI_EN (for C6415 C6416, Table footnotes) MCBSP2_EN (for C6414 C6416, Table footnotes)
C6414 device does support UTOPIA peripherals; proper operation C6414 device, oppose internal pulldowns (IPDs) BEA11, PCI_EN, MCBSP2_EN pins. (For IPUs/IPDs pins, Terminal Functions table this data sheet.)
other device configurations (C64x)
BEA[20:13,
peripherals selection
Some C6415/C6416 peripherals share same pins (internally MUXed) mutually exclusive (i.e., HPI, general-purpose input/output pins GP[15:9], internal EEPROM, McBSP1, McBSP2, UTOPIA). VCP/TCP coprocessors (C6416 only) other C64x peripherals (i.e., Timers, McBSP0, GP[8:0] pins), always available.
UTOPIA McBSP1 peripherals
UTOPIA_EN (BEA11) latched reset. C6415 C6416 devices, this selects whether UTOPIA peripheral McBSP1 peripheral functionally enabled (see Table 26). C6414 device does support UTOPIA peripheral; proper device operation, oppose internal pulldown (IPD) BEA11 pin. Table UTOPIA_EN Peripheral Selection (McBSP1 UTOPIA) (C6415/C6416 Only)
PERIPHERAL SELECTION UTOPIA_EN (BEA11) [F14] PERIPHERALS SELECTED UTOPIA McBSP1 DESCRIPTION McBSP1 enabled UTOPIA disabled [default]. This means multiplexed McBSP1/UTOPIA pins function McBSP1 other standalone UTOPIA pins tied-off (Hi-Z). UTOPIA enabled McBSP1 disabled. This means multiplexed McBSP1/UTOPIA pins function UTOPIA other standalone McBSP1 pins tied-off (Hi-Z).
HPI, GP[15:9], PCI, EEPROM (internal PCI), McBSP2 peripherals
PCI_EN MCBSP2_EN pins latched reset. They determine specific peripheral selection C6415 C6416 devices, summarized Table C6414 device does support peripheral; proper device operation, oppose internal pulldowns (IPDs) PCI_EN MCBSP2_EN pins.
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DEVICE CONFIGURATIONS (CONTINUED)
Table PCI_EN MCBSP2_EN Peripheral Selection (HPI, GP[15:9], PCI, McBSP2)
PERIPHERAL SELECTION PCI_EN [T8] MCBSP2_EN [AB4] GP[15:9] PERIPHERALS SELECTED EEPROM (Internal PCI) McBSP2
PCI_EN must driven valid times user must switch values throughout device operation. MCBSP2_EN must driven valid times user switch values throughout device operation. only time McBSP2 disabled when both PCI_EN MCBSP2_EN This configuration enables, reset, auto-initialization peripheral through internal EEPROM [provided EEPROM Auto-Initialization (BEA13) pulled (EEAI 1)]. user then enable McBSP2 peripheral (disabling EEPROM) dynamically changing MCBSP2_EN after device initialized (out reset).
disabled (PCI_EN peripheral enabled GP[15:9] pins programmed GPIO, provided GPxEN GPxDIR bits properly configured. This means multiplexed HPI/PCI pins function standalone pins (PCBE0 XSP_CS) tied-off (Hi-Z). Also, multiplexed GPIO/PCI pins used GPIO with proper software configuration GPIO enable direction registers (for more details, Table 29).
enabled (PCI_EN peripheral disabled. This means multiplexed HPI/PCI pins function PCI. Also, multiplexed GPIO/PCI pins function pins (for more details, Table 29).
MCBSP2_EN pin, combination with PCI_EN pin, controls selection McBSP2 peripheral internal EEPROM (for more details, Table footnotes).
other device configurations
Table describes C6414, C6415, C6416 devices configuration pins, which external pullup/pulldown resistors through specified EMIFB address pins (BEA[20:13, 9:7]) pin. more details these device configuration pins, Terminal Functions table Debugging Considerations section.
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DEVICE CONFIGURATIONS (CONTINUED)
Table Device Configuration Pins (BEA[20:13, 9:7], HD5, BEA11)
CONFIGURATION BEA20 FUNCTIONAL DESCRIPTION Device Endian mode (LEND) System operates Endian mode System operates Little Endian mode (default) Bootmode [1:0] boot boot EMIFB 8-bit boot with default timings (default mode) Reserved EMIFA input clock select Clock mode select EMIFA (AECLKIN_SEL[1:0]) AECLKIN (default mode) CPU/4 Clock Rate CPU/6 Clock Rate Reserved EMIFB input clock select Clock mode select EMIFB (BECLKIN_SEL[1:0]) BECLKIN (default mode) CPU/4 Clock Rate CPU/6 Clock Rate Reserved EEPROM Auto-Initialization (EEAI) [C6415 C6416 devices only] [The C6414 device does support peripheral; proper device operation, oppose internal pulldown (IPD) BEA13 pin.] auto-initialization external EEPROM auto-initialization through EEPROM disabled; peripheral uses specified default values (default). auto-initialization through EEPROM enabled; peripheral configured through EEPROM provided peripheral enabled (PCI_EN McBSP2 peripheral disabled (MCBSP2_EN Note: peripheral disabled (PCI_EN this must pulled more information EEPROM default values, TMS320C6000 Peripheral Component Interconnect (PCI) Reference Guide (literature number SPRU581). UTOPIA Enable (UTOPIA_EN) [C6415 C6416 devices only] [The C6414 device does support UTOPIA peripheral; proper device operation, oppose internal pulldown (IPD) BEA11 pin.] UTOPIA peripheral enable (functional) BEA11 UTOPIA peripheral disabled (McBSP1 functions enabled). [default] This means multiplexed McBSP1/UTOPIA pins function McBSP1 other standalone UTOPIA pins tied-off (Hi-Z). UTOPIA peripheral enabled (McBSP1 functions disabled). This means multiplexed McBSP1/UTOPIA pins function UTOPIA other standalone McBSP1 pins tied-off (Hi-Z).
BEA[19:18]
[D17, J14]
BEA[17:16]
[E16, G15]
BEA[15:14]
[C18, F15]
BEA13
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DEVICE CONFIGURATIONS (CONTINUED)
Table Device Configuration Pins (BEA[20:13, 9:7], HD5, BEA11) (Continued)
CONFIGURATION C6414 Devices BEA7 BEA8 BEA9 FUNCTIONAL DESCRIPTION C6415 Devices C6416 Devices oppose Pullup Pullup
oppose internal pulldown (IPD) Pullup oppose oppose oppose oppose
proper device operation, this must externally pulled with resistor. peripheral width (HPI_WIDTH) operates HPI16. (HPI bits wide. HD[15:0] pins used remaining HD[31:16] pins reserved pins Hi-Z state.) operates HPI32. (HPI bits wide. HD[31:0] pins used host-port operations.)
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DEVICE CONFIGURATIONS (CONTINUED) multiplexed pins
Multiplexed pins pins that shared more than peripheral internally multiplexed. Some these pins configured software, others configured external pullup/pulldown resistors only reset. Those MUXed pins that configured software programmed switch functionalities time. Those MUXed pins that configured external pullup/pulldown resistors mutually exclusive; only peripheral primary control function these pins after reset. Table identifies multiplexed pins C6414, C6415, C6416 devices; shows default (primary) function default settings after reset; describes pins, registers, etc. necessary configure specific multiplexed functions.
debugging considerations
recommended that external connections provided device configuration pins, including CLKMODE[1:0], BEA[20:13, 9:7], HD5/AD5, PCI_EN, MCBSP2_EN. Although internal pullup/pulldown resistors exist these pins (except HD5/AD5), providing external connectivity adds convenience user debugging flexibility switching operating modes. Internal pullup/pulldown resistors also exist non-configuration pins (BEA[12, 6:1]). oppose internal pullup/pulldown resistors these non-configuration pins with external pullup/pulldown resistors. external controller provides signals these non-configuration pins, these signals must driven default state pins reset, driven all. internal pullup/pulldown resistors C6414, C6415, C6416 device pins, terminal functions table.
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DEVICE CONFIGURATIONS (CONTINUED)
Table C6414, C6415, C6416 Device Multiplexed Pins
MULTIPLEXED PINS NAME CLKOUT4/GP1 DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION These pins software-configurable. these pins GPIO pins, GPxEN bits GPIO Enable Register GPxDIR bits GPIO Direction Register must properly configured. GPxEN enabled GPxDIR input GPxDIR output GP[15:9] GPIO pins, needs disabled (PCI_EN GPxEN bits GPIO Enable Register GPxDIR bits GPIO Direction Register must properly configured. GPxEN enabled GPxDIR input GPxDIR output
CLKOUT4
GP1EN (disabled)
CLKOUT6/GP2
CLKOUT6
GP2EN (disabled)
CLKS2/GP8 GP9/PIDSEL GP10/PCBE3 GP11/PREQ GP12/PGNT GP13/PINTA GP14/PCLK GP15/PRST DX1/UXADDR4 FSX1/UXADDR3 FSR1/UXADDR2 DR1/UXADDR1 CLKX1/URADDR4 CLKS1/URADDR3 CLKR1/URADDR2 CLKX2/XSP_CLK DR2/XSP_DI DX2/XSP_DO HD[31:0]/AD[31:0] HAS/PPAR HCNTL1/PDEVSEL HCNTL0/PSTOP HDS1/PSERR HDS2/PCBE1 HR/W/PCBE2 HWWIL/PTRDY HINT/PFRAME HCS/PPERR
AA11
CLKS2
GP8EN (disabled)
None
GPxEN (disabled) PCI_EN (disabled)
FSX1 FSR1 CLKX1 CLKS1 CLKR1 CLKX2 HD[31:0] HCNTL1 HCNTL0 HDS1 HDS2 HR/W HHWIL (HPI16 only) HINT PCI_EN (disabled) default, enabled upon reset (PCI disabled). enable peripheral external pullup resistor must provided PCI_EN (setting PCI_EN reset). UTOPIA_EN (BEA11) (disabled) default, McBSP1 enabled upon reset (UTOPIA disabled). enable UTOPIA peripheral, external pullup resistor must provided BEA11 (setting UTOPIA_EN reset).
HRDY/PIRDY HRDY C6415 C6416 devices, other standalone UTOPIA pins tied-off internally (pins Hi-Z) when peripheral disabled [UTOPIA_EN (BEA11) PCI_EN C6414 device does support UTOPIA peripherals. These only multiplexed pins C6414 device, other pins standalone peripheral functions MUXed. HD[31:0]/AD[31:0] multiplexed pins numbers, Terminal Functions table.
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Terminal Functions
SIGNAL NAME TYPE IPD/ CLOCK/PLL CONFIGURATION CLKIN CLKMODE1 CLKMODE0 TRST EMU11 EMU10 EMU9 EMU8 EMU7 EMU6 EMU5 EMU4 EMU3 EMU2 AA17 AB18 AA16 AB17 AA15 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Clock Input. This clock input on-chip PLL. Clock output device speed (O/Z) [default] this programmed GPIO (I/O/Z). Clock output device speed (O/Z) [default] this programmed GPIO (I/O/Z). Clock mode select Selects whether clock frequency input clock frequency (Bypass), x12. more details CLKMODE pins multiply factors, Clock section this data sheet. voltage supply JTAG EMULATION JTAG test-port mode select JTAG test-port data JTAG test-port data JTAG test-port clock JTAG test-port reset. IEEE 1149.1 JTAG compatibility, IEEE 1149.1 JTAG Compatibility Statement section this data sheet. Emulation Reserved future use, leave unconnected. Emulation Reserved future use, leave unconnected. Emulation Reserved future use, leave unconnected. Emulation Reserved future use, leave unconnected. Emulation Reserved future use, leave unconnected. Emulation Reserved future use, leave unconnected. Emulation Reserved future use, leave unconnected. Emulation Reserved future use, leave unconnected. Emulation Reserved future use, leave unconnected. Emulation Reserved future use, leave unconnected. Emulation [1:0] pins Select device functional mode operation Operation EMU[1:0] Boundary Scan/Normal Mode (see Note) Reserved Reserved Emulation/Normal Mode [default] (see IEEE 1149.1 JTAG Compatibility Statement section this data sheet) Normal mode refers DSPs normal operational mode, when free running. placed normal operational mode when EMU[1:0] pins configured either Boundary Scan Emulation. Note: When EMU[1:0] pins configured Boundary Scan mode, internal pulldown (IPD) TRST signal must opposed order operate Normal mode. Boundary Scan mode pulldown EMU[1:0] pins with dedicated resister. Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.) These pins multiplexed pins. more details, Device Configurations section this data sheet. PLLV part external voltage supply. Clock section information connect this pin. Analog signal (PLL Filter) DESCRIPTION
EMU1 EMU0
I/O/Z
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Terminal Functions (Continued)
SIGNAL NAME RESET GP7/EXT_INT7 GP6/EXT_INT6 GP5/EXT_INT5 GP4/EXT_INT4 I/O/Z I/O/Z TYPE IPD/ DESCRIPTION
RESETS, INTERRUPTS, GENERAL-PURPOSE INPUT/OUTPUTS Device reset Nonmaskable interrupt, edge-driven (rising edge) General-purpose input/output (GPIO) pins (I/O/Z) external interrupts (input only). default after reset setting GPIO enabled input-only. When these pins function External Interrupts selecting corresponding interrupt enable register (IER.[7:4])], they edge-driven polarity independently selected External Interrupt Polarity Register bits (EXTPOL.[3:0]). General-purpose input/output (GPIO) (I/O/Z) reset (I). function default. GPIO (I/O/Z) clock (I). function default. GPIO (I/O/Z) interrupt (O/Z). function default. GPIO (I/O/Z) grant (I). function default. GPIO (I/O/Z) request (O/Z). function default. GPIO (I/O/Z) command/byte enable (I/O/Z). function default. GPIO (I/O/Z) initialization device select (I). function default. GPIO (I/O/Z). default after reset setting GPIO enabled input-only. GPIO pin. general-purpose (GPIO (I/O/Z) programmed GPIO (input only) [default] GPIO (output only) output general-purpose interrupt (GP0INT) signal (output only). McBSP2 external clock source (CLKS2) [input only] [default] this programmed GPIO (I/O/Z). Clock output device speed (O/Z) [default] this programmed GPIO (I/O/Z). Clock output device speed (O/Z) [default] this programmed GPIO (I/O/Z).
I/O/Z I/O/Z I/O/Z
HOST-PORT INTERFACE (HPI) [C64x] PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415 C6416 devices only] enable pin. This controls selection (enable/disable) GP[15:9], peripherals (for C6415 C6416 devices). This works conjunction with MCBSP2_EN enable/disable other peripherals (for more details, Device Configurations section this data sheet). C6414 device does support peripheral; proper device operation, oppose internal pulldown (IPD) this pin. HCNTL1/ HCNTL0/ I/O/Z I/O/Z I/O/Z I/O/Z Host interrupt from host [default] frame (I/O/Z) Host control selects between control, address, data registers [default] device select (I/O/Z). Host control selects between control, address, data registers [default] stop (I/O/Z) Host half-word select first second half-word (not necessarily high order) [For HPI16 width selection only] [default] target ready (I/O/Z)
PCI_EN
I/O/Z Host read write select [default] command/byte enable (I/O/Z) Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.) C6415 C6416 devices, these pins multiplexed pins. more details, Device Configurations section this data sheet. C6414 device does support UTOPIA peripherals; therefore, these MUXed peripheral pins standalone peripheral functions this device. C6414 device, only these pins multiplexed pins.
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Terminal Functions (Continued)
SIGNAL NAME TYPE IPD/ DESCRIPTION
HOST-PORT INTERFACE (HPI) [C64x] PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415 C6416 devices only] (CONTINUED) I/O/Z Host-port data (I/O/Z) [default] (C64x) data-address (I/O/Z) [C6415 C6416] data (PCI_EN Used transfer data, address, control Host-Port width user-configurable device reset 10-k resistor pullup/pulldown resistor pin: operates HPI16. (HPI bits wide. HD[15:0] pins used remaining HD[31:16] pins reserved pins high-impedance state.) operates HPI32. (HPI bits wide. HD[31:0] pins used host-port operations.) data-address (PCI_EN [C6415 C6416 devices only] Used transfer data address C6414 device does support peripheral; therefore, peripheral pins standalone peripheral functions, MUXed. I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Host address strobe [default] parity (I/O/Z) Host chip select [default] parity error (I/O/Z) Host data strobe [default] system error (I/O/Z) Host data strobe [default] command/byte enable (I/O/Z) Host ready from host [default] initiator ready (I/O/Z).
Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.) C6415 C6416 devices, these pins multiplexed pins. more details, Device Configurations section this data sheet. C6414 device does support UTOPIA peripherals; therefore, these MUXed peripheral pins standalone peripheral functions this device.
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Terminal Functions (Continued)
SIGNAL NAME TYPE IPD/ DESCRIPTION
HOST-PORT INTERFACE (HPI) [C64x] PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415 C6416 devices only] (CONTINUED) PCBE0 I/O/Z command/byte enable (I/O/Z). When disabled (PCI_EN this tied-off. C6414 device this "Reserved (leave unconnected, connect power ground)." serial interface chip select (O). When disabled (PCI_EN this tied-off. C6414 device this "Reserved (leave unconnected, connect power ground)." McBSP2 transmit clock (I/O/Z) [default] serial interface clock (O). McBSP2 receive data [default] serial interface data (I). mode, this connected output data serial PROM. McBSP2 transmit data (O/Z) [default] serial interface data (O). mode, this connected input data serial PROM. General-purpose input/output (GPIO) (I/O/Z) reset (I). function default. GPIO (I/O/Z) clock (I). function default. GPIO (I/O/Z) interrupt (O/Z). function default. I/O/Z GPIO (I/O/Z) grant (I). function default. GPIO (I/O/Z) request (O/Z). function default. GPIO (I/O/Z) command/byte enable (I/O/Z). function default. GPIO (I/O/Z) initialization device select (I). function default. EMIFA (64-bit) CONTROL SIGNALS COMMON TYPES MEMORY||k EMIFA byte-enable control Decoded from low-order address bits. number address bits byte enables used depends width external memory. Byte-write enables most types memory directly connected SDRAM read write mask signal (SDQM) EMIFA memory space enables Enabled bits through word address Only asserted during external data access
XSP_CS CLKX2/ ACE3 ACE2 ACE1 ACE0 ABE7 ABE6 ABE5 ABE4 ABE3 ABE2 ABE1 ABE0
I/O/Z
APDT EMIFA peripheral data transfer, allows direct transfer between external peripherals Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.) C6415 C6416 devices, these pins multiplexed pins. more details, Device Configurations section this data sheet. C6414 device does support UTOPIA peripherals; therefore, these MUXed peripheral pins standalone peripheral functions this device. These C64x devices have EMIFs (64-bit EMIFA 16-bit EMIFB). prefix front signal name indicates EMIFA signal whereas prefix front signal name indicates EMIFB signal. Throughout rest this document, generic EMIF areas discussion, prefix omitted from signal name. maintain signal integrity EMIF signals, serial termination resistors should inserted into EMIF output signal lines.
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Terminal Functions (Continued)
SIGNAL NAME AHOLDA AHOLD ABUSREQ TYPE IPD/ DESCRIPTION EMIFA (64-BIT) ARBITRATION||k EMIFA hold-request-acknowledge host EMIFA hold request from host EMIFA request output EMIFA external input clock. EMIFA input clock (AECLKIN, CPU/4 clock, CPU/6 clock) selected reset pullup/pulldown resistors BEA[17:16] pins. AECLKIN default EMIFA input clock. EMIFA output clock Programmable EMIFA input clock (AECLKIN, CPU/4 clock, CPU/6 clock) frequency divided-by-1, EMIFA output clock EMIFA input clock (AECLKIN, CPU/4 clock, CPU/6 clock) frequency]. EMIFA asynchronous memory read-enable/SDRAM column-address strobe/programmable synchronous interface-address strobe read-enable programmable synchronous interface, RENEN field Space Secondary Control Register (CExSEC) selects between ASADS ASRE: RENEN then ASADS/ASRE signal functions ASADS signal. RENEN then ASADS/ASRE signal functions ASRE signal. EMIFA asynchronous memory output-enable/SDRAM row-address strobe/programmable synchronous interface output-enable EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable synchronous interface write-enable EMIFA SDRAM clock-enable (used self-refresh mode). [EMIFA module only.] SDRAM system, ASDCKE used general-purpose output. EMIFA synchronous memory output-enable ACE3 (for glueless FIFO interface) Asynchronous memory ready input EMIFA (64-BIT) ADDRESS||k
EMIFA (64-BIT) ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL||k AECLKIN
AECLKOUT2 AECLKOUT1
AARE/ ASDCAS/ ASADS/ASRE
AAOE/ ASDRAS/ ASOE AAWE/ ASDWE/ ASWE ASDCKE ASOE3 AARDY AEA22 AEA21 AEA20 AEA19 AEA18 AEA17 AEA16 AEA15 AEA14 AEA13 AEA12
EMIFA external address (doubleword address)
AEA11 Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.) These C64x devices have EMIFs (64-bit EMIFA 16-bit EMIFB). prefix front signal name indicates EMIFA signal whereas prefix front signal name indicates EMIFB signal. Throughout rest this document, generic EMIF areas discussion, prefix omitted from signal name. maintain signal integrity EMIF signals, serial termination resistors should inserted into EMIF output signal lines.
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Terminal Functions (Continued)
SIGNAL NAME AEA10 AEA9 AEA8 AEA7 AEA6 AEA5 AEA4 AEA3 AED63 AED62 AED61 AED60 AED59 AED58 AED57 AED56 AED55 AED54 AED53 AED52 AED51 AED50 AED49 AED48 AED47 AED46 AED45 AED44 AED43 AED42 AED41 AED40 AED39 AED38 EMIFA (64-bit) DATA||k AB21 AA20 AA19 AB20 AA18 AB19 I/O/Z EMIFA external data EMIFA external address (doubleword address) TYPE IPD/ DESCRIPTION EMIFA (64-BIT) ADDRESS||k (CONTINUED)
AED37 Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.) These C64x devices have EMIFs (64-bit EMIFA 16-bit EMIFB). prefix front signal name indicates EMIFA signal whereas prefix front signal name indicates EMIFB signal. Throughout rest this document, generic EMIF areas discussion, prefix omitted from signal name. maintain signal integrity EMIF signals, serial termination resistors should inserted into EMIF output signal lines.
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Terminal Functions (Continued)
SIGNAL NAME AED36 AED35 AED34 AED33 AED32 AED31 AED30 AED29 AED28 AED27 AED26 AED25 AED24 AED23 AED22 AED21 AED20 AED19 AED18 AED17 AED16 AED15 AED14 AED13 AED12 AED11 AED10 AED9 AED8 AED7 AED6 AED5 AED4 AED3 AED2 AED1 AA22 I/O/Z EMIFA external data TYPE IPD/ DESCRIPTION EMIFA (64-bit) DATA||k (CONTINUED)
AED0 Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.) These C64x devices have EMIFs (64-bit EMIFA 16-bit EMIFB). prefix front signal name indicates EMIFA signal whereas prefix front signal name indicates EMIFB signal. Throughout rest this document, generic EMIF areas discussion, prefix omitted from signal name. maintain signal integrity EMIF signals, serial termination resistors should inserted into EMIF output signal lines.
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Terminal Functions (Continued)
SIGNAL NAME BCE3 BCE2 BCE1 BCE0 BBE1 BBE0 BPDT BHOLDA BHOLD BBUSREQ TYPE IPD/ DESCRIPTION
EMIFB (16-bit) CONTROL SIGNALS COMMON TYPES MEMORY||k EMIFB byte-enable control Decoded from low-order address bits. number address bits byte enables used depends width external memory. Byte-write enables most types memory directly connected SDRAM read write mask signal (SDQM) EMIFB peripheral data transfer, allows direct transfer between external peripherals EMIFB (16-BIT) ARBITRATION||k EMIFB hold-request-acknowledge host EMIFB hold request from host EMIFB request output EMIFB external input clock. EMIFB input clock (BECLKIN, CPU/4 clock, CPU/6 clock) selected reset pullup/pulldown resistors BEA[15:14] pins. BECLKIN default EMIFB input clock. EMIFB output clock Programmable EMIFB input clock (BECLKIN, CPU/4 clock, CPU/6 clock) frequency divided EMIFB output clock EMIFB input clock (BECLKIN, CPU/4 clock, CPU/6 clock) frequency]. EMIFB asynchronous memory read-enable/SDRAM column-address strobe/programmable synchronous interface-address strobe read-enable programmable synchronous interface, RENEN field Space Secondary Control Register (CExSEC) selects between BSADS BSRE: RENEN then BSADS/BSRE signal functions BSADS signal. RENEN then BSADS/BSRE signal functions BSRE signal. EMIFB asynchronous memory output-enable/SDRAM row-address strobe/programmable synchronous interface output-enable EMIFB asynchronous memory write-enable/SDRAM write-enable/programmable synchronous interface write-enable EMIFB synchronous memory output enable BCE3 (for glueless FIFO interface) EMIFB memory space enables Enabled bits through word address Only asserted during external data access
EMIFB (16-BIT) ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL||k BECLKIN
BECLKOUT2 BECLKOUT1
BARE/ BSDCAS/ BSADS/BSRE
BAOE/ BSDRAS/ BSOE BAWE/BSDWE/ BSWE BSOE3
BARDY EMIFB asynchronous memory ready input Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.) These C64x devices have EMIFs (64-bit EMIFA 16-bit EMIFB). prefix front signal name indicates EMIFA signal whereas prefix front signal name indicates EMIFB signal. Throughout rest this document, generic EMIF areas discussion, prefix omitted from signal name. maintain signal integrity EMIF signals, serial termination resistors should inserted into EMIF output signal lines.
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Terminal Functions (Continued)
SIGNAL NAME TYPE IPD/ EMIFB (16-BIT) ADDRESS||k BEA20 BEA19 BEA18 BEA17 BEA16 BEA15 BEA14 BEA13 BEA12 BEA11 BEA10 BEA9 BEA8 BEA7 BEA6 BEA5 BEA4 BEA3 BEA2 BEA1 I/O/Z Also proper C6414 device operation, oppose IPDs BEA7, BEA8, BEA9 pins. proper C6415 device operation, BEA7 must externally pulled with resistor. proper C6416 device operation, BEA8 BEA9 pins must externally pulled with resistor. EMIFB external address (half-word address) (O/Z) Also controls initialization modes reset pullup/pulldown resistors Device Endian mode BEA20: Endian Little Endian (default mode) Boot mode BEA[19:18]: boot boot EMIFB 8-bit boot with default timings (default mode) Reserved EMIF clock select BEA[17:16]: Clock mode select EMIFA (AECLKIN_SEL[1:0]) AECLKIN (default mode) CPU/4 Clock Rate CPU/6 Clock Rate Reserved BEA[15:14]: Clock mode select EMIFB (BECLKIN_SEL[1:0]) BECLKIN (default mode) CPU/4 Clock Rate CPU/6 Clock Rate Reserved EEPROM Auto-Initialization (EEAI) [C6415 C6416 devices only] BEA13: auto-initialization external EEPROM peripheral disabled (PCI_EN this must pulled auto-initialization through EEPROM disabled (default). auto-initialization through EEPROM enabled. UTOPIA Enable (UTOPIA_EN) [C6415 C6416 devices only] BEA11: UTOPIA peripheral enable (functional) UTOPIA disabled (McBSP1 enabled) [default] UTOPIA enabled (McBSP1 disabled) C6414 device does support UTOPIA peripherals; proper device operation, oppose internal pulldowns (IPDs) BEA13 BEA11 pins. DESCRIPTION
more details, Device Configurations section this data sheet. Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.) These C64x devices have EMIFs (64-bit EMIFA 16-bit EMIFB). prefix front signal name indicates EMIFA signal whereas prefix front signal name indicates EMIFB signal. Throughout rest this document, generic EMIF areas discussion, prefix omitted from signal name. maintain signal integrity EMIF signals, serial termination resistors should inserted into EMIF output signal lines.
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Terminal Functions (Continued)
SIGNAL NAME BED15 BED14 BED13 BED12 BED11 BED10 BED9 BED8 BED7 BED6 BED5 BED4 BED3 BED2 BED1 BED0 MULTICHANNEL BUFFERED SERIAL PORT (McBSP2) MCBSP2_EN CLKR2 CLKX2/ FSR2 FSX2 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z McBSP2 enable pin. This works conjunction with PCI_EN enable/disable other peripherals (for more details, Device Configurations section this data sheet). McBSP2 external clock source (CLKS2) [input only] [default] this also programmed GPIO (I/O/Z). McBSP2 receive clock. When McBSP2 disabled (PCI_EN MCBSP2_EN this tied-off. McBSP2 transmit clock (I/O/Z) [default] serial interface clock (O). McBSP2 receive data [default] serial interface data (I). mode, this connected output data serial PROM. McBSP2 transmit data (O/Z) [default] serial interface data (O). mode, this connected input data serial PROM. McBSP2 receive frame sync. When McBSP2 disabled (PCI_EN MCBSP2_EN this tied-off. McBSP2 transmit frame sync. When McBSP2 disabled (PCI_EN MCBSP2_EN this tied-off. I/O/Z EMIFB external data TYPE IPD/ EMIFB (16-bit) DATA||k DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.) C6415 C6416 devices, these pins multiplexed pins. more details, Device Configurations section this data sheet. C6414 device does support UTOPIA peripherals; therefore, these MUXed peripheral pins except CLKS2/GP8 standalone peripheral functions this device. These C64x devices have EMIFs (64-bit EMIFA 16-bit EMIFB). prefix front signal name indicates EMIFA signal whereas prefix front signal name indicates EMIFB signal. Throughout rest this document, generic EMIF areas discussion, prefix omitted from signal name. maintain signal integrity EMIF signals, serial termination resistors should inserted into EMIF output signal lines.
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Terminal Functions (Continued)
SIGNAL NAME CLKS1/ CLKR1/ CLKX1/ DR1/ DX1/ FSR1/ FSX1/ TYPE IPD/ DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT (McBSP1) AA11 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z McBSP1 external clock source opposed internal) [default] UTOPIA receive address McBSP1 receive clock (I/O/Z) [default] UTOPIA receive address McBSP1 transmit clock (I/O/Z) [default] UTOPIA receive address McBSP1 receive data [default] UTOPIA transmit address McBSP1 transmit data (O/Z) [default] UTOPIA transmit address McBSP1 receive frame sync (I/O/Z) [default] UTOPIA transmit address McBSP1 transmit frame sync (I/O/Z) [default] UTOPIA transmit address MULTICHANNEL BUFFERED SERIAL PORT (McBSP0) CLKS0 CLKR0 CLKX0 FSR0 FSX0 TOUT2 TINP2 TOUT1 TINP1 TOUT0 I/O/Z I/O/Z I/O/Z I/O/Z McBSP0 external clock source opposed internal) McBSP0 receive clock McBSP0 transmit clock McBSP0 receive data McBSP0 transmit data McBSP0 receive frame sync McBSP0 transmit frame sync TIMER Timer general-purpose output Timer general-purpose input TIMER Timer general-purpose output Timer general-purpose input TIMER Timer general-purpose output TINP0 Timer general-purpose input Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.) C6415 C6416 devices, these pins multiplexed pins. more details, Device Configurations section this data sheet. C6414 device does support UTOPIA peripherals; therefore, these MUXed peripheral pins standalone peripheral functions this device.
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Terminal Functions (Continued)
SIGNAL NAME TYPE IPD/ DESCRIPTION
UNIVERSAL TEST OPERATIONS INTERFACE ASYNCHRONOUS TRANSFER MODE (ATM) [UTOPIA SLAVE] [C6415 C6416 devices only] UTOPIA SLAVE (ACONTROLLER) TRANSMIT INTERFACE UXCLKY Source clock UTOPIA transmit driven Master AController. When UTOPIA peripheral disabled (UTOPIA_EN [BEA11 pin] this tied-off. Transmit cell available status output signal from UTOPIA Slave. indicates complete cell available transmit indicates complete cell available transmit When UTOPIA peripheral disabled (UTOPIA_EN [BEA11 pin] this tied-off. UXENBY UTOPIA transmit interface enable input signal. Asserted Master AController indicate that UTOPIA Slave should Transmit Data first byte valid data UXSOC signal next clock cycle. When UTOPIA peripheral disabled (UTOPIA_EN [BEA11 pin] this tied-off. Transmit Start-of-Cell signal. This signal output UTOPIA Slave rising edge UXCLK, indicating that first valid byte cell available 8-bit Transmit Data (UXDATA[7:0]). When UTOPIA peripheral disabled (UTOPIA_EN [BEA11 pin] this tied-off. McBSP1 [default] UTOPIA transmit address pins UTOPIA transmit address pins UXADDR[4:0] (I), UTOPIA_EN (BEA11 pin) 5-bit Slave transmit address input pins driven Master AController identify select Slave devices possible) ASystem. I/O/Z UXADDR0 tied when UTOPIA peripheral disabled [UTOPIA_EN (BEA11 pin)
UXCLAVY
AA13
UXSOCY
DX1/
McBSP1 functions (UTOPIA_EN (BEA11 pin) [default]), MULTICHANNEL BUFFERED SERIAL PORT (McBSP1) section this table. FSX1/ FSR1/ DR1/ UXADDR0Y AA11 I/O/Z McBSP1 [default] UTOPIA transmit address pins UTOPIA transmit address pins UXADDR[4:0] (I), UTOPIA_EN (BEA11 pin) 5-bit Slave transmit address input pins driven Master AController identify select Slave devices possible) ASystem. UXADDR0 tied when UTOPIA peripheral disabled [UTOPIA_EN (BEA11 pin)
I/O/Z
McBSP1 functions (UTOPIA_EN (BEA11 pin) [default]), MULTICHANNEL BUFFERED SERIAL PORT (McBSP1) section this table. Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.) C6415 C6416 devices, these pins multiplexed pins. more details, Device Configurations section this data sheet. C6414 device does support UTOPIA peripherals; therefore, these MUXed peripheral pins standalone peripheral functions this device. C6415 C6416 devices, external pulldowns required: UTOPIA selected (BEA11 these pins connected other devices, then 10-k resistor must used externally pull down each these pins. these pins connects", then only UXCLK URCLK need pulled down other pulldowns necessary. C6415 C6416 devices, external pullups required: UTOPIA selected (BEA11 these pins connected other devices, then 10-k resistor must used externally pull each these pins. these pins connects", then pullups necessary. C6414 device does support UTOPIA peripheral; therefore, these standalone UTOPIA pins Reserved (leave unconnected, connect power ground) with exception UXCLK URCLK which should connected 10-k pulldown resistor (see square footnote).
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Terminal Functions (Continued)
SIGNAL NAME UXDATA7Y UXDATA6Y UXDATA5Y UXDATA4Y UXDATA3Y UXDATA2Y UXDATA1Y UXDATA0Y UTOPIA SLAVE (ACONTROLLER) RECEIVE INTERFACE URCLKY Source clock UTOPIA receive driven Master AController. When UTOPIA peripheral disabled (UTOPIA_EN [BEA11 pin] this tied-off. Receive cell available status output signal from UTOPIA Slave. indicates space available receive cell from Master AController indicates space available receive cell from Master AController When UTOPIA peripheral disabled (UTOPIA_EN [BEA11 pin] this tied-off. URENBY UTOPIA receive interface enable input signal. Asserted Master AController indicate UTOPIA Slave sample Receive Data (URDATA[7:0]) URSOC signal next clock cycle thereafter. When UTOPIA peripheral disabled (UTOPIA_EN [BEA11 pin] this tied-off. Receive Start-of-Cell signal. This signal output Master AController indicate UTOPIA Slave that first valid byte cell available sample 8-bit Receive Data (URDATA[7:0]). When UTOPIA peripheral disabled (UTOPIA_EN [BEA11 pin] this tied-off. McBSP1 [default] UTOPIA receive address pins UTOPIA receive address pins URADDR[4:0] (I), UTOPIA_EN (BEA11 pin) 5-bit Slave receive address input pins driven Master AController identify select Slave devices possible) ASystem. URADDR1 URADDR0 pins tied when UTOPIA peripheral disabled [UTOPIA_EN (BEA11 pin) 8-bit Transmit Data Using Transmit Data Bus, UTOPIA Slave rising edge UXCLK) transmits 8-bit Acells Master AController. When UTOPIA peripheral disabled (UTOPIA_EN [BEA11 pin] these pins tiedoff. TYPE IPD/ DESCRIPTION
UTOPIA SLAVE (ACONTROLLER) TRANSMIT INTERFACE (CONTINUED)
URCLAVY
AA14
AB16
URSOCY
CLKX1/ CLKS1/ CLKR1/ URADDR1Y URADDR0Y
I/O/Z I/O/Z
McBSP1 functions (UTOPIA_EN (BEA11 pin) [default]), MULTICHANNEL BUFFERED SERIAL PORT (McBSP1) section this table. Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.) These pins multiplexed pins. more details, Device Configurations section this data sheet. External pulldowns required: UTOPIA selected (BEA11 these pins connected other devices, then 10-k resistor must used externally pull down each these pins. these pins connects", then only UXCLK URCLK need pulled down other pulldowns necessary. External pullups required: UTOPIA selected (BEA11 these pins connected other devices, then 10-k resistor must used externally pull each these pins. these pins connects", then pullups necessary. C6414 device does support UTOPIA peripheral; therefore, these standalone UTOPIA pins Reserved (leave unconnected, connect power ground) with exception UXCLK URCLK which should connected 10-k pulldown resistor (see square footnote).
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Terminal Functions (Continued)
SIGNAL NAME URDATA7Y URDATA6Y URDATA5Y URDATA4Y URDATA3Y URDATA2Y URDATA1Y URDATA0Y AA10 AA12 RESERVED TEST Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.) External pulldowns required: UTOPIA selected (BEA11 these pins connected other devices, then 10-k resistor must used externally pull down each these pins. these pins connects", then only UXCLK URCLK need pulled down other pulldowns necessary. C6414 device does support UTOPIA peripheral; therefore, these standalone UTOPIA pins Reserved (leave unconnected, connect power ground) with exception UXCLK URCLK which should connected 10-k pulldown resistor (see square footnote). Reserved (leave unconnected, connect power ground) 8-bit Receive Data Bus. Using Receive Data Bus, UTOPIA Slave rising edge URCLK) receive 8-bit Acell data from Master AController. When UTOPIA peripheral disabled (UTOPIA_EN [BEA11 pin] these pins tiedoff. TYPE IPD/ DESCRIPTION
UTOPIA SLAVE (ACONTROLLER) RECEIVE INTERFACE (CONTINUED)
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Terminal Functions (Continued)
SIGNAL NAME AA23 AB10 AB11 AB14 AB15 AB23 AC10 AC12 AC14 AC16 AC19 AC21 AC22 DVDD Input, Output, High impedance, Supply voltage, Ground 3.3-V supply voltage (see Power-Supply Decoupling section this data sheet) TYPE DESCRIPTION SUPPLY VOLTAGE PINS
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Terminal Functions (Continued)
SIGNAL NAME DVDD CVDD AB12 AB13 AB24 AC18 AC20 AD11 AD13 AD15 AD17 Input, Output, High impedance, Supply voltage, Ground supply voltage (see Power-Supply Decoupling section this data sheet) 3.3-V supply voltage (see Power-Supply Decoupling section this data sheet) TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED)
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Terminal Functions (Continued)
SIGNAL NAME AD19 AD21 AD23 CVDD Input, Output, High impedance, Supply voltage, Ground supply voltage (see Power-Supply Decoupling section this data sheet) TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED)
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Terminal Functions (Continued)
SIGNAL NAME CVDD GROUND PINS AA21 AA24 AB22 AC11 AC13 AC15 Input, Output, High impedance, Supply voltage, Ground Ground pins supply voltage (see Power-Supply Decoupling section this data sheet) TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED
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Terminal Functions (Continued)
SIGNAL NAME AC17 AC23 AC24 AD10 AD12 AD14 AD16 AD18 AD20 AD22 Input, Output, High impedance, Supply voltage, Ground Ground pins TYPE GROUND PINS DESCRIPTION
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Terminal Functions (Continued)
SIGNAL NAME Input, Output, High impedance, Supply voltage, Ground Ground pins TYPE DESCRIPTION GROUND PINS (CONTINUED)
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Terminal Functions (Continued)
SIGNAL NAME Input, Output, High impedance, Supply voltage, Ground Ground pins TYPE DESCRIPTION GROUND PINS (CONTINUED)
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development support
offers extensive line development tools TMS320C6000 platform, including tools evaluate performance processors, generate code, develop algorithm implementations, fully integrate debug software hardware modules. following products support development C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS), which provides basic run-time target software needed support application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000 multiprocessor system debug) (Evaluation Module) complete listing development-support tools TMS320C6000 platform, visit Texas Instruments site Worldwide http://www.ti.com uniform resource locator (URL). information pricing availability, contact nearest field sales office authorized distributor.
Code Composer Studio, DSP/BIOS, trademarks Texas Instruments.
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SMJ320C6414, SMJ320C6415, SMJ320C6416 FIXED POINT DIGITAL SIGNAL PROCESSORS
device development-support tool nomenclature designate stages product development cycle, assigns prefixes part numbers TMS320 devices support tools. Each military TMS320 family member three prefixes: SMX, TMP, SMJ. Texas Instruments recommends three possible prefix designators support tools: TMDX TMDS. These prefixes represent evolutionary stages product development from engineering prototypes (SMX TMDX) through fully qualified production devices/tools (SMJ TMDS). Device development evolutionary flow: Preproduction device that necessarily representative final device's electrical specifications Final silicon that conforms device's electrical specifications completed quality reliability verification Fully qualified production device
Support tool development evolutionary flow: TMDX Development-support product that completed Texas Instruments internal qualification testing. Fully qualified development-support product
TMDS
devices TMDX development-support tools shipped with appropriate disclaimers describing their limitations intended uses. Experimental devices (SMX) representative final product Texas Instruments reserves right change discontinue these products without notice. devices TMDS development-support tools have been characterized fully, quality reliability device have been demonstrated fully. TI's standard warranty applies. Predictions show that preproduction prototype devices (SMX TMP) have greater failure rate than standard production devices. Texas Instruments recommends that these devices used production system because their expected end-use failure rate still undefined. Only qualified production devices used. device nomenclature also includes suffix with device family name. This suffix indicates package type (for example, GAD), temperature range (for example, blank default commercial temperature range), device speed range megahertz (for example, -6E3 600-MHz CPU, 133-MHz EMIFA). Figure provides legend reading complete device name SMJ320C64x generation member.
TMS320 trademark Texas Instruments.
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device development-support tool nomenclature (continued) Table SMJ320C6414/C6415/C6416 Device Part Numbers (P/Ns) Ordering Information
DEVICE ORDERABLE C6414 SMJ320C6414DGADW60 SM320C6414DGADW60 C6415 SMJ320C6415DGADW60 SM320C6415DGADW60 C6416 SMJ320C6416DGADW60 SM320C6416DGADW60 Product Preview MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. -55_C 115_C -55_C 115_C MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. -55_C 115_C -55_C 115_C MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. MHz/4800 MIPS, 133-MHz EMIFA, Silicon Rev. -55_C 115_C -55_C 115_C DEVICE SPEED, EMIF SPEED, SILICON REVISION CVDD (CORE VOLTAGE) DVDD (I/O VOLTAGE) OPERATING CASE TEMPERATURE RANGE
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device development-support tool nomenclature (continued)
PREFIX SMX= Experimental device Prototype device Qualified device Preproduction device, MIL-PRF-38535, Commercial processing
6415C
DEVICE SPEED RANGE (500-MHz CPU, 100-MHz EMIF) (600-MHz CPU, 133-MHz EMIFA) (720-MHz CPU, 133-MHz EMIFA) (600-MHz CPU, 133-MHz EMIFA) military TEMPERATURE RANGE (DEFAULT: 90°C) Blank 90°C, commercial temperature -40°C 105°C, extended temperature -55°C 115°C, temp PACKAGE 532-pin plastic 570-pin ceramic micro C64x DSP: 6411 6414D 6415D 6416D
DEVICE FAMILY TMS320t family
TECHNOLOGY CMOS
6414C 6415C 6416C
Recommended Operating Conditions section this data sheet more details. extended temperature version" devices have different operating conditions than commercial temperature devices. Recommended Operating Conditions section this data sheet more details. Ball Grid Array. Grid Array. actual device part numbers (P/Ns) ordering information, Table this data sheet.
Figure SMJ320C64x Device Nomenclature (Including C6414, C6415, C6416 Devices)
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documentation support
Extensive documentation supports TMS320 family generations devices from product announcement through applications development. types documentation available include: data sheets, such this document, with design specifications; complete user's reference guides devices tools; technical briefs; development-support tools; on-line help; hardware software applications. following brief, descriptive list support documentation specific C6000 devices: TMS320C6000 Instruction Reference Guide (literature number SPRU189) describes C6000 (core) architecture, instruction set, pipeline, associated interrupts. TMS320C6000 Peripherals Overview Reference Guide (literature number SPRU190) provides overview briefly describes functionality peripherals available C6000 platform devices. This document also includes table listing peripherals available C6000 devices along with literature numbers hyperlinks associated peripheral documents. TMS320C64x Technical Overview (literature number SPRU395) gives introduction C64x digital signal processor, discusses application areas that enhanced C64x VelociTI.2 VLIW architecture. TMS320C6414, TMS320C6415, TMS320C6416 Digital Signal Processors Silicon Errata (literature number SPRZ011) describes known exceptions functional specifications SMJ320C6414, SMJ320C6415, SMJ320C6416 devices. TMS320C6414/15/16 Power Consumption Summary application report (literature number SPRA811) discusses power consumption user applications with SMJ320C6414, SMJ320C6415, SMJ320C6416 devices. Using IBIS Models Timing Analysis application report (literature number SPRA839) describes properly IBIS models attain accurate timing analysis given system. tools support documentation electronically available within Code Composer Studio Integrated Development Environment (IDE). complete listing C6000 latest documentation, visit Texas Instruments site Worldwide http://www.ti.com uniform resource locator (URL). Worldwide Begin Development Today With TMS320C6414, TMS320C6415, TMS320
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