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Format: <op1>, <op2> <op1>: <op2>: adr:8, <op1> <op1> <op2> adds values <op1> <op2> carry stores result back into <op1> carry generated. Reset not. result zero. Reset not. overflow generated. Reset not. exclusive result.
Operation: Flags: Example:
DM[0080h] DM[IDH:80h]
last instructions, assuming that register pair R1:R0 R3:R2 16-bit signed unsigned numbers. Even result "ADD zero, flag result "ADC R1,R3" zero. Note that zero flag exactly reflect result 16-bit operation. Therefore when programming 16-bit addition, take care change flag.
Format: <op1>, <op2> <op1>: <op2>: adr:8, #imm:8, GPR, @idm Operation: <op1> <op1> <op2> adds values <op1> <op2> stores result back into <op1>. Flags: Example: carry generated. Reset not. result zero. Reset not. overflow generated. Reset not. exclusive result.
Given: IDH:IDL0 80FFh, #12h @ID0 @[ID0 @[ID0 @[ID0 DM[8080h] DM[80FFh], 81h, IDL0 DM[80FCh], 80h, IDL0 DM[8101h], 80h, IDL0 DM[80FDh], 80h, IDL0
last instructions, value IDH:IDL0 changed. Refer Table more detailed explanation about this addressing mode. IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx ID1)
Format: <op1>, <op2> <op1>: <op2>: adr:8, #imm:8, GPR, @idm Operation: <op1> <op1> <op2> performs bit-wise values <op1> <op2> stores result <op1>. Flags: Example: result zero. Reset not. result Reset not. Given: IDH:IDL0 01FFh, #40h @ID0 @[ID0 @[ID0 @[ID0 DM[017Ah] DM[01FFh], IDH:IDL0 0202h DM[01FAh], IDH:IDL0 01FAh DM[0206h], IDH:IDL0 01FFh DM[01FDh], IDH:IDL0 01FFh
first instruction, zero, register garbage value because data memory DM[0051h-007Fh] mapped S3CB205/FB205. last instructions, value IDH:IDL0 changed. Refer Table more detailed explanation about this addressing mode. IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx ID1)
Format: Operation: SR0, #imm:8 imm:8 performs bit-wise operation value imm:8 stores result SR0. Flags: Example: Given: 11000010b nIE0 nIE1 ~02h ~40h ~80h SR0, #nIE nIE0 nIE1 SR0, #11111101b
first example, statement "AND SR0, #nIE|nIE0|nIE1" clear bits global interrupt, interrupt interrupt contrary, cleared bits instruction SR0, #imm:8". Refer instruction more detailed explanation about enabling bit. second example, statement "AND SR0, #11111101b" equal instruction which disabling interrupt globally.
Format: Operation: Flags:
BANK #imm:2 SR0[4:3] imm:2 explanation CalmRISC banked register file usage, please refer chapter BANK BANK #11h #22h Select register bank Bank1's Select register bank Bank2's
Example:
Format: BITC adr:8.bs 3-digit specifier Operation: Flags:
((adr:8) (2**bs)) (adr:8) ((adr:8) (2**bs))
BITC complements specified value read from memory stores result back into memory, depending value clear BMS/BMC instruction. result zero. Reset not. Since destination register fixed, specified explicitly. Given: DM[0180h] FFh, BITC BITC 80h.0 80h.1 FEh, DM[0180h] DM[0180h]
Example:
Format: BITR adr:8.bs 3-digit specifier Operation: Flags:
((adr:8) ((11111111) (2**bs))) (adr:8) ((adr:8) ((11111111) (2**bs)))
BITR resets specified value read from memory stores result back into memory, depending value clear BMS/BMC instruction. result zero. Reset not. Since destination register fixed, specified explicitly. Given: DM[0180h] FFh, BITR BITR 80h.1 80h.2 FDh, DM[0180h] DM[0180h]
Example:
Format: BITS adr:8.bs 3-digit specifier. Operation: Flags:
((adr:8) (2**bs)) (adr:8) ((adr:8) (2**bs))
BITS sets specified value read from memory stores result back into memory, depending value clear BMS/BMC instruction. result zero. Reset not. Since destination register fixed, specified explicitly. Given: DM[0180h] F0h, BITS BITS 80h.1 80h.2 0F2h, DM[0180h] DM[0180h]
Example:
Format: BITT adr:8.bs 3-digit specifier. Operation: ~((adr:8) (2**bs)) BITT tests specified value read from memory. Flags: Example: result zero. Reset not. Given: DM[0080h] F7h, BITT
80h.3
flag Jump label because condition true.
BITS
80h.3
Format: Operation:
BMS/BMC BMC/BMS clears (sets) bit. single flag which determines destination operations, such BITC, BITR, BITS.
Flags:
BMC/BMS only instructions that modify content bit. BITS BITR 81h.1 81h.2
Example:
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Format: CALL cc:4, imm:20 CALL imm:12
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CALL
Wait
HS[sptr][15:0] current sptr sptr 2-word instruction HS[sptr][15:0] current sptr sptr 1-word instruction Address 0088h
CALL
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Wait:
Format: Operation: CALLS imm:12 HS[sptr][15:0] current sptr sptr program size less than word. HS[sptr][19:0] current sptr sptr program size equal over word. PC[11:0] imm:12 CALLS unconditionally calls subroutine residing address specified imm:12. Flags: Example:
CALLS
Wait
Wait:
Because this 1-word instruction, saved returning address stack
Format: imm:8, <op> <op>: Operation: (imm:8) <op> loads value <op> into (imm:8), where imm:8 used access external coprocessor's address space. Flags: Example:
A[15:8] A[7:0] B[15:8] B[7:0]
registers A[15:0] B[15:0] Arithmetic Unit (AU) registers MAC816. Above instructions generate SYSCP[7:0], nCLDID CLDWR signals access MAC816.
Format: Operation: Flags: Example: <op>, imm:8 <op>: <op> (imm:8) loads value from coprocessor, whose address specified imm:8. loaded value <op1> zero. Reset not. loaded value <op1> Reset not.
A[15:8] A[7:0] B[15:8] B[7:0]
registers A[15:0] B[15:0] Arithmetic Unit (AU) registers MAC816. Above instructions generate SYSCP[7:0], nCLDID CLDWR signals access MAC816.
Format: <op> <op>: Operation: <op> ~<op> takes bit-wise complement operation <op> stores result <op>. Flags: Example:
result zero. Reset not. result Reset not. Given: A5h, flag
Format: COM2 <op> <op>: Operation: <op> ~<op> COM2 computes complement <op> stores result <op>. Flags: carry generated. Reset not. result zero. Reset not. overflow generated. Reset not. result negative.
Example:
Given: 00h, COM2 COM2 00h, flags `1'. A6h, flag `1'.
Format: COMC <op> <op>: Operation: <op> ~<op> COMC takes bit-wise complement <op>, adds carry stores result <op>. Flags: carry generated. Reset not. result zero. Reset not. overflow generated. Reset not. result negative. Reset not.
Example:
register pair R1:R0 16-bit number, then complement R1:R0 obtained COM2 COMC following. COM2 COMC
Note that flag exactly reflect result 16-bit operation. example, 16-bit register pair value FF01h, then complement made 00FFh COM2 COMC. this time, instruction COMC, zero flag result complement 16-bit number zero. Therefore when programming 16-bit comparison, take care change flag.
Format: Operation: Flags: Example: #imm:12 passes imm:12 coprocessor generating SYSCP[11:0] nCOPID signals. #0D01h #0234h generate word instruction code(FD01h) generate word instruction code(F234h)
above instructions equal statement "ELD #1234h" MAC816 operation. microcode instruction "ELD #1234h" "FD01F234", 2-word instruction. this, code indicates `COP' instruction.
Format: <op1>, <op2> <op1>: <op2>: adr:8, #imm:8, GPR, @idm Operation: <op1> ~<op2> compares values <op1> <op2> subtracting <op2> from <op1>. Contents <op1> <op2> changed. Flags: Example: carry generated. Reset not. result zero (i.e., <op1> <op2> same). Reset not. overflow generated. Reset not. result negative. Reset not.
Given: 73h, A5h, IDH:IDL0 0123h, DM[0123h] #73h @ID0 @[ID0 @[ID0 @[ID0 flag flags flag flags
last instructions, value IDH:IDL0 changed. Refer Table more detailed explanation about this addressing mode. IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx ID1)
Format: <op1>, <op2> <op1>: <op2>: adr:8, Operation: Flags: Example: <op1> <op1> ~<op2> compares <op1> <op2> subtracting <op2> from <op1>. Unlike however, adds result. Contents <op1> <op2> changed. carry generated. Reset not. result zero. Reset not. overflow generated. Reset not. result negative. Reset not.
register pair R1:R0 R3:R2 16-bit signed unsigned numbers, then compare 16-bit numbers follows.
Because considers when comparing <op1> <op2>, used pair compare 16-bit operands. note that zero flag exactly reflect result 16-bit operation. Therefore when programming 16-bit comparison, take care change flag.
Format: <op> <op>: Operation: Flags: <op> <op> 0FFh decrease value <op> adding 0FFh <op>. carry generated. Reset not. result zero. Reset not. overflow generated. Reset not. result negative. Reset not.
Example:
Given: 80h, 7Fh, flags FFh, flags
Format: DECC <op> <op>: Operation: Flags: <op> <op> 0FFh DECC decrease value <op> when carry set. When there carry, there change value <op>. carry generated. Reset not. result zero. Reset not. overflow generated. Reset not. result negative. Reset not.
Example:
register pair R1:R0 16-bit signed unsigned number, then DECC decrement 16-bit number follows. DECC
Note that zero flag exactly reflect result 16-bit operation. Therefore when programming 16-bit decrement, take care change flag.
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Format: Operation: Flags: Example: Disables interrupt globally. same "AND SR0, #0FDh" instruction sets bit1 (ie: global interrupt enable) register Given: 11111101b
instruction clears SR0[1] `0', disabling interrupt processing.
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Format: Operation: Flags: Example: Enables interrupt globally. same SR0, #02h" instruction sets bit1 (ie: global interrupt enable) register
00000010b
Given:
statement "EI" sets SR0[1] `1', enabling interrupts.
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Format: Operation: IDLE IDLE instruction stops clock while allowing system clock oscillation continue. Idle mode released interrupt reset operation. IDLE instruction pseudo instruction. assembled "SYS #05H", this generates SYSCP[7-0] signals. Then these signals decoded decoded signals execute idle operation.
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Flags:
Example: IDLE
IDLE instruction stops clock system clock.
Format: <op> <op>: Operation: Flags: <op> <op> increase value <op>. carry generated. Reset not. result zero. Reset not. overflow generated. Reset not. result negative. Reset not.
Example:
Given: 7Fh, 80h, flag 00h, flags
Format: INCC <op> <op>: Operation: <op> <op> INCC increase value <op> only there carry. When there carry, value <op> changed. Flags: Example: carry generated. Reset not. result zero. Reset not. overflow generated. Reset not. exclusive result.
register pair R1:R0 16-bit signed unsigned number, then INCC increment 16-bit number following. INCC
Assume R1:R0 0010h, statement "INC increase without carry statement "INCC zero flag result 16-bit increment zero. Note that zero flag exactly reflect result 16-bit operation. Therefore when programming 16-bit increment, take care change flag.
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Format: Operation: Flags:
IRET HS[sptr sptr sptr IRET pops return address (after interrupt handling) from hardware stack assigns (i.e., SR0[1]) allow further interrupt generation. program size (indicated nP64KW signal) determines which portion updated. When program size less than word, only lower bits updated (i.e., PC[15:0] HS[sptr 2]). When program size word more, action taken PC[19:0] HS[sptr
Example: SF_EXCEP:
Stack full exception service routine
IRET
Format: JNZD <op>, imm:8 <op>: (bank only) imm:8 signed number Operation: PC[delay slot] complement imm:8 <op> <op> JNZD performs backward PC-relative jump <op> evaluates non-zero. Furthermore, JNZD decrease value <op>. instruction immediately following JNZD (i.e., delay slot) always executed, this instruction must cycle instruction. Flags:
Typically, delay slot will filled with instruction from loop body. noted, however, that chosen instruction should "dead" outside loop executes even when loop exited (i.e., JNZD taken). Given: 03h, BANK JNZD
Example:
#0FFh IDL0, @ID0,
used loop counter bank3 zero, jump Clear register pointed
This example used clear routine. last instruction executed even loop exited.
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Format: Operation: cc:4 imm:20 cc:4 imm:9 access target address, command assembled word instruction) linking time, else assembled word instruction) instruction. There different conditions that used, described table 7-6.
Example:
#10h
Assume address label 020Dh
Address 0264h Address 0265h
#20h
Assume address label 089Ch
above example, statement %B1" assembled instruction. Assuming that current 0264h condition true, next made PC[11:0] PC[11:0] offset, offset value "64h A9h" without carry. `A9' means complement offset value jump backward. Therefore next 020Dh. other hand, statement %F2" assembled instruction because offset address exceeds range imm:9.
cc:4 imm:9 cc:4: 4-bit condition code
Format:
Operation:
PC[11:0] PC[11:0] imm:9 condition true. imm:9 signed number, which sign-extended bits when added There different conditions that used, described table 7-6. Unlike LJP, target address PC-relative. case imm:9 added compute actual jump address, while directly jumps imm:20, target.
Flags:
Example:
Assume current 1000h
Address 10A5h
After first instruction executed, next become 10A5h flag `1'. range relative address from +255 -256 because imm:9 signed number.
Format: Operation: LCALL cc:4, imm:20 HS[sptr][15:0] current sptr sptr PC[15:0] imm[15:0] condition holds program size less than word. HS[sptr][19:0] current sptr sptr PC[19:0] imm:20 condition holds program size equal over word. PC[11:0] PC[11:0] otherwise. LCALL instruction used call subroutine whose starting address specified imm:20. Flags: Example: LCALL LCALL
Label allocated same other section. Because this 2-word instruction, saved returning address stack
4Format: adr:8, <op> <op>: Operation: DM[00h:adr:8] <op> DM[IDH:adr:8] <op> adr:8 loads value <op> into memory location. memory location determined adr:8. Flags: Example: Given: 80h,
zero, statement 80h, load value into DM[0080h], else `1', statement 80h, load value into DM[0180h]
Format: @idm, <op> <op>: Operation: (@idm) <op> @idm loads value <op> into memory location determined @idm. Details @idm format actual address calculated found chapter Flags: Example: Given 5Ah, IDH:IDL0 8023h, @ID0, @ID0 @[ID0-5], @[ID0+4]!, @[ID0-2]!, DM[8023h] DM[8023h] 5Ah, IDL0 DM[801Eh] 5Ah, IDL0 DM[8027h] 5Ah, IDL0 DM[8021h] 5Ah, IDL0
last instructions, value IDH:IDL0 changed. Refer Table more detailed explanation about this addressing mode. IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx ID1)
Format: <op1>, <op2> <op1>: <op2>: GPR, SPR, adr:8, @idm, #imm:8 Operation: <op1> <op2> loads value specified <op2> into register designated <op1>. Flags: Example: result zero. Reset not. exclusive result. Given: 5Ah, AAh, IDH:IDL0 8023h, #11h @ID0+1 @[ID0-2] @[ID0+3]! @[ID0-5]! DM[8080h] DM[8023h], IDL0 DM[8021h], IDL0 DM[8026h], IDL0 DM[801Eh], IDL0
last instructions, value IDH:IDL0 changed. Refer Table more detailed explanation about this addressing mode. IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx ID1)
Format: <op1>, <op2> <op1>: GPR: bankd <op2>: GPR: banks Operation: <op1> <op2> loads value register specified bank (banks) into another register specified bank (bankd). Flags: Example: result zero. Reset not. exclusive result.
R2:1, R0:3 R0:0, R0:2
Bank1's bank3's Bank0's bank2's
Format: <op1>, <op2> <op1>: <op2>: TBH/TBL Operation: <op1> <op2> loads value specified <op2> into register designated <op1>. Flags: Example: result zero. Reset not. exclusive result. Given: register pair R1:R0 16-bit unsigned data. TBH:TBL PM[ILX:ILH:ILL]
Format: <op1>, <op2> <op1>: TBH/TBL <op2>: Operation: <op1> <op2> loads value specified <op2> into register designated <op1>. Flags: Example: Given: register pair R1:R0 16-bit unsigned data. TBH, TBL,
Format: <op1>, <op2> <op1>: <op2>: Operation: <op1> <op2> loads value into SPR. Refer Table more detailed explanation about kind SPR. Flags: Example: Given: register pair R1:R0 1020h ILH, ILL,
Format: Operation: SPR0, #imm:8 SPR0 imm:8 SPR0 loads 8-bit immediate value into SPR0. Flags: Example: Given: (index register bank selection) IDH, #80h IDL1, #44h IDL0, #55h SR0, #02h point page
last instruction (global interrupt enable) `1'. Special register group (SPR1) registers supported this addressing mode.
Format: Operation: <op1> <op1>: @IL, @IL+ TBH:TBL PM[ILX:ILH:ILL] (@IL+ only) loads data item from program memory stores TBH:TBL register pair. @IL+ increase value ILL, efficiently implementing table lookup operations. Flags: Example:
ILX, ILH, ILL,
Loads value PM[ILX:ILH:ILL] into TBH:TBL Move data TBH:TBL GPRs further processing
statement "LDC @IL" increase, statement "LDC @IL+", register increased after instruction execution.
Format: cc:4, imm:20 cc:4: 4-bit condition code Operation: PC[15:0] imm[15:0] condition true program size less than word. program equal larger than word, PC[19:0] imm[19:0] long condition true. There different conditions that used, described table 7-6. cc:4 imm:20 2-word instruction whose immediate field directly specifies target address jump.
Flags:
Example:
Assume current 0812h
Address 10A5h
After first instruction executed, directly jumps address 10A5h condition true.
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Format: LLNK cc:4, imm:20 cc:4: 4-bit condition code Operation: condition true, IL[19:0] {PC[19:12], PC[11:0] Further, when program equal larger than word, PC[19:0] imm[19:0] long condition true. program smaller than word, PC[15:0] imm[15:0]. There different conditions that used, described table 7-6. Flags:
LLNK used conditionally call subroutine with return address saved link register (IL) without- This 2-word instruction. LLNK
Example:
Address 005Ch, ILX:ILH:ILL 00:00:5Eh Address 005Eh
LRET
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Format: Operation: cc:4, imm:20 imm:12 LNKS access target address there conditional code (cc:4), command assembled LNKS word instruction) linking time, else assembled LLNK word instruction).
Example:
Link1 Link2
Equal "LLNK Link1" Equal "LNKS Link2"
Link2:
LRET
Subroutines section CODE, 0A00h Subroutines Link1:
LRET
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Format: Operation: Flags:
LNKS imm:12 IL[19:0] {PC[19:12], PC[11:0] PC[11:0] imm:12 LNKS saves current link register jumps address specified imm:12. LNKS used call subroutine with return address saved link register (IL) without-
Example:
LNKS
Link1
Address 005Ch, ILX:ILH:ILL 00:00:5Dh Address 005Dh
Link1:
LRET
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Format: Operation: Flags: LRET IL[19:0] LRET returns from subroutine assigning saved return address
Example: Link1:
Link1
LRET
PC[19:0] ILX:ILH:ILL
Format: Operation: operation. When instruction executed program, operation occurs. Instead, instruction time delayed approximately machine cycle each instruction encountered. Flags: Example:
Format: <op1>, <op2> <op1>: <op2>: adr:8, #imm:8, GPR, @idm Operation: Flags: Example: <op1> <op1> <op2> performs bit-wise operation <op1> <op2> stores result <op1>. result zero. Reset not. exclusive result. Given: IDH:IDL0 031Eh, #40h @ID0 @[ID0-1] @[ID0+1]! @[ID0-1]! DM[0380h] Mask bit6 DM[031Eh], IDL0 DM[031Dh], IDL0 DM[031Fh], IDL0 DM[031Dh], IDL0
last instructions, value IDH:IDL0 changed. Refer Table more detailed explanation about this addressing mode. IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx ID1)
Format: Operation: SR0, #imm:8 imm:8 performs bit-wise operation imm:8 stores result SR0. Flags: Example: Given: 00000000b IDB1 SR0, SR0, #00000010b
first example, statement SR0, #EID|IE|IE0" global interrupt(ie), interrupt 0(ie0) interrupt 1(ie1) SR0. contrary, enabled bits cleared with instruction "AND SR0, #imm:8". Refer instruction more detailed explanation about disabling bit. second example, statement SR0, #00000010b" equal instruction which enabling interrupt globally.
Format: Operation: sptr sptr decrease sptr bytes hardware stack therefore invalidated. Flags: Example: Given: sptr[5:0] 001010b This instruction decrease sptr[5:0] Therefore sptr[5:0] 001000b.
Format: <op> <op>: GPR, Operation: Flags: Example: <op> HS[sptr sptr sptr copies value stack <op> decrease sptr value copied <op> zero. Reset not. value copied <op> negative. Reset not. When <op> SPR, flags affected, including
HS[sptr-1], sptr sptr-1 HS[sptr-1], sptr sptr-1
first instruction, value HS[sptr-1] loaded second instruction "POP IDH" load value HS[sptr-1] register IDH. Refer chapter more detailed explanation about operations hardware stack.
Format: PUSH <op> <op>: GPR, Operation: HS[sptr] <op>, sptr sptr PUSH stores value <op> stack increase sptr Flags: Example: PUSH PUSH HS[sptr] sptr sptr HS[sptr] IDH, sptr sptr
first instruction, value register loaded HS[sptr-1] second instruction "PUSH IDH" load value register HS[sptr-1]. Current pointed stack point sptr[5:0] emptied. Refer chapter more detailed explanation about PUSH operations hardware stack.
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Format: Operation: HS[sptr sptr sptr pops address hardware stack into that control returns subroutine call site. Flags: Example: Given: sptr[5:0] 001010b CALLS
Wait
Address 00120h
Wait:
Address 01000h
After first instruction CALLS execution, "PC+1", 0121h loaded HS[5] hardware stack pointer sptr[5:0] have 001100b next became 01000h. instruction pops value 0121h hardware stack HS[sptr-2] load then stack pointer sptr[[5:0] became 001010b.
Format: <op> <op>: Operation: <op>[7], <op> {<op>[6:0], <op>[7]} rotates value <op> left stores result back into <op>. original <op> copied into carry (C). Flags: Example: <op> (before rotating) Reset not. result zero. Reset not. <op> (after rotating) Reset not. Given: 01001010b, 10100101b flag `1', 10010100b flag `1', 01001011b
Format: <op> <op>: Operation: <op>[7], <op> {<op>[6:0], rotates value <op> left stores result back into <op>. original <op> copied into carry (C), original copied into <op>[0]. Flags: Example: <op> (before rotating) Reset not. result zero. Reset not. <op> (after rotating) Reset not. Given: A5h, 4Ah, flag
second example, assuming that register pair R1:R0 16-bit number, then used 16-bit rotate left operation. note that zero flag exactly reflect result 16-bit operation. Therefore when programming 16-bit decrement, take care change flag.
Format: <op> <op>: Operation: <op>[0], <op> {<op>[0], <op>[7:1]} rotates value <op> right stores result back into <op>. original <op> copied into carry (C). Flags: Example: <op> (before rotating) Reset not. result zero. Reset not. <op> (after rotating) Reset not. Given: 01011010b, 10100101b change flag, 00101101b flags `1', 11010010b
Format: <op> <op>: Operation: <op>[0], <op> <op>[7:1]} rotates value <op> right stores result back into <op>. original <op> copied into carry (C), copied MSB. Flags: Example: <op> (before rotating) Reset not. result zero. Reset not. <op> (after rotating) Reset not. Given: A5h, 52h, flag
second example, assuming that register pair R1:R0 16-bit number, then used 16-bit rotate right operation. note that zero flag exactly reflect result 16-bit operation. Therefore when programming 16-bit decrement, take care change flag.
Format: <op1>, <op2> <op1>: <op2>: adr:8, Operation: Flags: <op1> <op1> ~<op2> computes (<op1> <op2>) when there carry (<op1> <op2> when there carry. carry generated. Reset not. result zero. Reset not. overflow generated. result negative. Reset not.
Example:
~DM[0080h] ~DM[IDH:80h]
last instructions, assuming that register pair R1:R0 R3:R2 16-bit signed unsigned numbers. Even result "ADD zero, zero flag result "SBC R1,R3" zero. Note that zero flag exactly reflect result 16-bit operation. Therefore when programming 16-bit addition, take care change flag.
Format: <op> <op>: Operation: Flags: Example: <op>[7], <op> {<op>[6:0], shifts <op> left bit. original <op> copied into carry (C). <op> (before shifting) Reset not. result zero. Reset not. <op> (after shifting) Reset not. Given: 01001010b, 10100101b flag `1', 10010100b flag `1', 01001010b
Format: Operation: Flags: <op> <op>: <op>[7], <op> {<op>[6:0], shifts <op> left bit. original <op> copied into carry (C). <op> (before shifting) Reset not. result zero. Reset not. result different from Reset not. <op> (after shifting) Reset not.
Example:
Given: flags `1',
Format: Operation: <op> <op>: <op>[0], <op> <op>[7:1]} shifts <op> right bit. original <op> (i.e., <op>[0]) copied into carry (C). Flags: <op> (before shifting) Reset not. result zero. Reset not. <op> (after shifting) Reset not. Given: 01011010b, 10100101b change flags, 00101101b flag `1', 01010010b
Example:
Format: Operation: <op> <op>: <op>[0], <op> {<op>[7], <op>[7:1]} shifts <op> right while keeping sign <op>. original <op> (i.e., <op>[0]) copied into carry (C). Flags: <op> (before shifting) Reset not. result zero. Reset not. <op> (after shifting) Reset not.
@&G-/ @,#HI6 /2(@&GJ*.* /(A(A
Example:
Given: 10100101b flags `1', 11010010b flag `1', 11101001b flags `1', 11110100b flags `1', 11111010b
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Format: Operation: STOP STOP instruction stops both clock system clock causes microcontroller enter STOP mode. STOP mode, contents on-chip registers, peripheral registers, port control data register retained. reset operation external internal interrupts release stop mode. STOP instruction pseudo instruction. assembled "SYS #0Ah", which generates SYSCP[7-0] signals. These signals decoded stop operation. next instruction STOP instruction executed, please instruction after STOP instruction. STOP
Example:
this example, instructions provide necessary timing delay oscillation stabilization before next instruction program sequence executed. Refer timing diagrams oscillation stabilization, described Figure 15-4, 15-5
Format: <op1>, <op2> <op1>: <op2>: adr:8, #imm:8, GPR, @idm Operation: Flags: <op1> <op1> ~<op2> adds value <op1> with complement <op2> perform subtraction <op1> <op2> carry generated. Reset not. result zero. Reset not. overflow generated. Reset not. result negative. Reset not.
Example:
Given: IDH:IDL0 0150h, DM[0143h] 26h, 52h, 14h, #16h @ID0+1 @[ID0-2] @[ID0+3]! @[ID0-2]! ~DM[0143h] FEh, flag ~DM[0150h] IDL0 ~DM[014Eh] IDL0 ~DM[0153h] IDL0 ~DM[014Eh] IDL0
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example description shows used pair subtract 16-bit number from another.
Format: SWAP <op1>, <op2> <op1>: <op2>: Operation: Flags:
<op1> <op2>, <op2> <op1> SWAP swaps values operands. Among SPRs, used <op2>. Given: IDH:IDL0 8023h, 56h, SWAP SWAP IDL0 80h, 23h, IDL0
Example:
After execution instructions, index registers IDH:IDL0 (ID0) have address 0156h.
!Format: Operation: Flags:
#imm:8 generates SYSCP[7:0] nSYSID signals. Mainly used system peripheral interfacing. #0Ah #05h
Example:
first example, statement "SYS #0Ah" equal STOP instruction second example "SYS #05h" equal IDLE instruction. This instruction does nothing increase generates SYSCP[7:0] nSYSID signals.
Format: <op>, #imm:8 <op>: Operation: Flags: Example: performs bit-wise operation <op> imm:8 sets flags. content <op> changed. result zero. Reset not. result negative. Reset not. Given: 01001101b #00100010b flag
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Format: <op1>, <op2> <op1>: <op2>: adr:8, #imm:8, GPR, @idm Operation: Flags: Example: <op1> <op1> <op2> performs bit-wise exclusive-OR operation <op1> <op2> stores result <op1>. result zero. Reset not. result negative. Reset not. Given: IDH:IDL0 8080h, DM[8043h] 26h, 52h, 14h,
#00101100b @ID0 @[ID0-2] @[ID0+3]! @[ID0-5]!
DM[8080h], IDL0 DM[807Eh], IDL0 DM[8083h], IDL0 DM[807Bh], IDL0
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