16-Bit 24-Bit ADCs with Ultra Noise PGIA Chopper General Des

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16-Bit 24-Bit ADCs with Ultra Noise PGIA Chopper General Des

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CS5531/32/33/34
16-Bit 24-Bit ADCs with Ultra Noise PGIA
Chopper
General Description
CS5531/32/33/34 highly integrated Analogto-Digital Converters (ADCs) which charge-balance techniques achieve 16-bit (CS5531/33) 24-bit (CS5532/34) performance. ADCs optimized measuring low-level unipolar bipolar signals weigh scale, process control, scientific, medical applications. accommodate these applications, ADCs come either two-channel (CS5531/32) four-channel (CS5533/34) devices include very noise chopper-stabilized instrumentation amplifier nV/Hz with selectable gains These ADCs also include fourth order modulator followed digital filter which provides selectable output word rates 1.92 kHz, 3.84 (MCLK 4.9152 MHz). ease communication between ADCs microcontroller, converters include simple three-wire serial interface which Microwire compatible with Schmitt Trigger input serial clock (SCLK). High dynamic range, programmable output rates, flexible power supply options makes these ADCs ideal solutions weigh scale process control applications. ORDERING INFORMATION page
Stabilized PGIA (Programmable Gain Instrumentation Amplifier, 64x)
nV/Hz noise) Input Current with Gains
Delta-Sigma
Analog-to-Digital Converter
Linearity Error: 0.0007% Noise Free Resolution: bits
Scalable
Four Channel Differential Input Span Calibration
Scalable
VREF Input: Analog Supply On-chip Guard Drive Output Buffer Simple three-wire serial interface
SPI®and MicrowireCompatible Schmitt Trigger Serial Clock (SCLK)
Calibration Registers Channel Selectable Word Rates: 3,840 Power Supply Configurations
+2.5 -2.5
VREF+
VREF-
AIN1+ AIN1AIN2+ AIN2AIN3+ AIN3AIN4+ AIN4MUX
PGIA 1,2,4,8,16 32,64
DIFFERENTIAL ORDER MODULATOR
PROGRAMMABLE SINC FILTER SERIAL INTERFACE SCLK
(CS5533/34 SHOWN)
CLOCK GENERATOR CALIBRATION SRAM/CONTROL LOGIC
LATCH
A0/GUARD
OSC1
OSC2
DGND
Preliminary Product Information
P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.cirrus.com
This document contains information product. Cirrus Logic reserves right modify this product without notice.
Copyright Cirrus Logic, Inc. 1999 (All Rights Reserved)
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CS5531/32/33/34
TABLE CONTENTS
CHARACTERISTICS SPECIFICATIONS ANALOG CHARACTERISTICS.4 TYPICAL NOISE (NV), CS5531/32/33/34-AS TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-AS TYPICAL NOISE (NV), CS5532/34-BS TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-BS DIGITAL CHARACTERISTICS DIGITAL CHARACTERISTICS DYNAMIC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS SWITCHING CHARACTERISTICS GENERAL DESCRIPTION 2.1. Analog Input 2.1.1. Analog Input Span 2.1.2. Multiplexed Settling Limitations 2.1.3. Voltage Noise Density Performance 2.1.4. Offset 2.2. Overview Register Structure Operating Modes 2.2.1. System Initialization 2.2.2. Command Register Quick Reference 2.2.3. Command Register Descriptions 2.2.4. Serial Port Interface 2.2.5. Reading/Writing On-Chip Registers 2.2.6. Setting CSRs Measurement 2.2.7. Channel-Setup Register Descriptions 2.3. Configuration Register 2.3.1. Power Consumption 2.3.2. Reset System 2.3.3. Input Short 2.3.4. Guard Signal 2.3.5. Voltage Reference Select 2.3.6. Output Latch Pins 2.3.7. Configuration Register Descriptions 2.4. Calibration 2.4.1. Calibration Registers 2.4.2. Gain Register 2.4.3. Offset Register 2.4.4. Performing Calibrations
Contacting Cirrus Logic Support
complete listing Direct Sales, Distributor, Sales Representative contacts, visit Cirrus Logic site
registered trademark International Business Machines Corporation. Microwire trademark National Semiconductor Corporation. Preliminary product information describes products which production, which full characterization data available. Advance product information describes products which development subject development changes. Cirrus Logic, Inc. made best efforts ensure that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). responsibility assumed Cirrus Logic, Inc. this information, infringements patents other rights third parties. This document property Cirrus Logic, Inc. implies license under patents, copyrights, trademarks, trade secrets. part this publication copied, reproduced, stored retrieval system, transmitted, form means (electronic, mechanical, photographic, otherwise) without prior written consent Cirrus Logic, Inc. Items from Cirrus Logic website disk printed user. However, part printout electronic files copied, reproduced, stored retrieval system, transmitted, form means (electronic, mechanical, photographic, otherwise) without prior written consent Cirrus Logic, Inc.Furthermore, part this publication used basis manufacture sale items without prior written consent Cirrus Logic, Inc. names products Cirrus Logic, Inc. other vendors suppliers appearing this document trademarks service marks their respective owners which registered some jurisdictions. list Cirrus Logic, Inc. trademarks service marks found http://www.cirrus.com.
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2.4.5. Self Calibration 2.4.6. System Calibration 2.4.7. Calibration Tips 2.4.8. Limitations Calibration Range 2.5. Performing Conversions 2.5.1. Single Conversion Mode 2.5.2. Multiple Conversions Mode 2.5.3. Examples Using CSRs Perform Conversions Calibrations 2.6. Conversion Output Coding 2.6.1. Conversion Data Register Descriptions 2.6.2. Output Coding 2.7. Digital Filter 2.8. Clock Generator 2.9. Power Supply Arrangements 2.10. Getting Started 2.11. Layout DESCRIPTIONS Clock Generator Control Pins Serial Data Measurement Reference Inputs Power Supply Connections SPECIFICATION DEFINITIONS ORDERING GUIDE PACKAGE DRAWINGS
LIST FIGURES
Figure Write Timing (Not Scale). Figure Read Timing (Not Scale).11 Figure Multiplexer Configuration. Figure Input models AIN+ AIN- pins. Figure Measured Voltage Noise Density.13 Figure CS5531/32/33/34 Register Diagram. Figure Command Data Word Timing. Figure Guard Signal Shielding Scheme. Figure Input Reference Model when Figure Input Reference Model when Figure Self Calibration Offset. Figure Self Calibration Gain. Figure System Calibration Offset. Figure System Calibration Gain. Figure Digital Filter Response (Word Rate Hz).36 Figure CS5532 Configured with Single Supply. Figure CS5532 Configured with ±2.5 Analog Supplies. Figure CS5532 Configured with Analog Supplies. Figure Bridge with Series Resistors.
LIST TABLES
Table Command Byte Pointer Table. Table Output Coding 16-bit CS5531/33 24-bit CS5532/34. Table Filter Notch Attenuation.
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CHARACTERISTICS SPECIFICATIONS
ANALOG CHARACTERISTICS
VA+, ±5%; VREF+ VA-, VREF-, DGND MCLK 4.9152 MHz; (Output Word Rate) Bipolar Mode; Gain (See Notes CS5531-AS/CS5533-AS Parameter ±0.0015 DRIFT ±0.003 Unit Bits LSB16 LSB16 nV/°C nV/°C ppm/°C
Accuracy Linearity Error Missing Codes Bipolar Offset
Unipolar Offset Gain Gain Offset Drift /1000 Hours. Bipolar Full Scale Error Unipolar Full Scale Error Full Scale Drift Full Scale Drift /1000 Hours. Offset Drift
(Note (Note (Notes
(Note
CS5532-AS/CS5534-AS Parameter ±0.0015 DRIFT ±0.003
CS5532-BS/CS5534-BS Unit Bits LSB24 LSB24 nV/°C nV/°C ppm/°C
Accuracy Linearity Error Missing Codes Bipolar Offset
Unipolar Offset Offset Drift
(Note (Note
±0.0007 ±0.0015 DRIFT
Gain (Notes Gain Offset Drift /1000 Hours. Bipolar Full Scale Error Unipolar Full Scale Error Full Scale Drift (Note Full Scale Drift /1000 Hours.
Notes: Applies after system calibration temperature within Specifications guaranteed design, characterization, and/or test. bits CS5531/33 bits CS5532/34. offset drift dictated gain setting. offset drift, DRIFT, (TBD nV/°C)/G, where gain amplifier. Further note, specification applies device only does include effects external parasitic thermocouples.
Drift over specified temperature range after calibration power-up
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ANALOG CHARACTERISTICS
(Continued) (See Notes Unit
Parameter Analog Input Common Mode Signal AIN+ AIN-Bipolar/Unipolar Mode Gain VAGain Current AIN+ AINGain (Note Gain Input Current Drift Input Leakage when Open Circuit Detect Current Common Mode Rejection Input Capacitance Guard Drive Output Voltage Reference Input Range (VREF+) (VREF-) Current Common Mode Rejection (Note Input Capacitance System Calibration Specifications Full Scale Calibration Range Bipolar/Unipolar Mode Offset Calibration Range Bipolar/Unipolar Mode CS5531/32/33/34-AS Parameter (Note
pA/°C (VA+)(VA-)
CS5532/34-BS Unit
Power Supplies
Power Supply Currents (Normal Mode) Power Consumption Normal Mode Standby Sleep Positive Supplies Negative Supply
Power Supply Rejection
Notes: section data sheet which discusses input models. outputs unloaded. input CMOS levels.
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TYPICAL NOISE (nV), CS5531/32/33/34-AS (See notes
Output Word Filter Rate (Hz) Frequency (Hz) 1.94 3.88 7.75 15.5 1,920 3,840 1390 2710 Instrumentation Amplifier Gain 1040 1480 1060 2090 1840 3650 5390 10800 21500 2070 2950 4170 7290 43000 4150 5890 8340 14600 86100
Notes: Wideband noise aliased into baseband. Referred input. Typical values shown Peak-to-Peak Noise multiply ranges output rates.
TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-AS (See Note
Output Word Filter Rate (Hz) Frequency (Hz) 1.94 3.88 7.75 15.5 1,920 3,840 Instrumentation Amplifier Gain
Noise Free Resolution LOG((2xInput Span)/(6.6xRMS Noise))/LOG(2) rounded nearest bit. input span calculated analog input span section data sheet.
Specifications subject change without notice.
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TYPICAL NOISE (nV), CS5532/34-BS (See notes
Output Word Filter Rate (Hz) Frequency (Hz) 1.94 3.88 7.75 15.5 1,920 3,840 1360 2690 Instrumentation Amplifier Gain 1020 1450 1030 2060 1810 3620 5380 10800 21500 2050 2900 4110 7230 43000 4090 5810 8230 14500 86000
Notes: Wideband noise aliased into baseband. Referred input. Typical values shown Peak-to-Peak Noise multiply ranges output rates.
TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-BS (See Notes
Output Word Filter Rate (Hz) Frequency (Hz) 1.94 3.88 7.75 15.5 1,920 3,840 Instrumentation Amplifier Gain
Noise Free Resolution LOG((2xInput Span)/(6.6xRMS Noise))/LOG(2) rounded nearest bit. input span calculated analog input span section data sheet.
Note that devices provide best noise specifications.
Specifications subject change without notice.
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DIGITAL CHARACTERISTICS VA+, ±5%; VA-, DGND
Notes 14.) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Capacitance Iout -5.0 Iout Symbol Cout (VD+) Unit
DIGITAL CHARACTERISTICS ±5%; 3.0V±10%; VA-, DGND
Notes 14.) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Capacitance measurements performed under static conditions. Iout -5.0 Iout Symbol Cout (VD+) Unit
DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Frequency Filter Settling Time (Full Scale Step Input) Single conversion mode (See notes Multiple conversions mode, 3840 Multiple conversions mode, 3840 Symbol Ratio MCLK/16 1/OWR 3/OWR 5/OWR Unit
ADCs Sinc5 filter 3840 output word rate (OWR) Sinc3 filter other OWRs. This implies that filter's settling time with full scale step input dictated OWR. single conversion mode only outputs fully settled output conversions. This implies that effective throughput single conversion mode reduced times with less than 3840 reduced times with 3840 multiple conversions mode outputs every conversion. This implies that filter's settling time with full scale step input multiple conversions mode dictated OWR.
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ABSOLUTE MAXIMUM RATINGS (DGND Note 18.)
Parameter Power Supplies (Notes Positive Digital Positive Analog Negative Analog (Notes Symbol VAIIN IOUT (Note VREF pins Pins VINR VINA VIND Tstg -0.3 -0.3 +0.3 -0.3 -0.3 -0.3 +6.0 +6.0 -3.75 (VA+) (VA+) (VD+) Unit
Input Current, Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: voltages with respect ground. must satisfy {(VA+) (VA-)} +6.6 must satisfy {(VD+) (VA-)} +7.5 Applies pins including continuous overvoltage conditions analog input (AIN) pins. Transient current will cause latch-up. Maximum input current power supply Total power dissipation, including input currents output currents. WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
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SWITCHING CHARACTERISTICS ±5%; -2.5V±5%
±10% ±5%;DGND Levels: Logic Logic VD+; Figures Parameter Master Clock Frequency Master Clock Duty Cycle Rise Times (Note Digital Input Except SCLK SCLK Digital Output (Note Digital Input Except SCLK SCLK Digital Output XTAL 4.9152MHz (Note trise tfall tost SCLK Pulse Width High Pulse Width (Note External Clock Internal Oscillator Symbol MCLK 4.9152 Unit
Fall Times
Start-up
Oscillator Start-up Time
Serial Port Timing
Serial Clock Frequency Serial Clock
Write Timing
Enable Valid Latch Clock Data Set-up Time prior SCLK rising Data Hold Time After SCLK Rising SCLK Falling Prior Disable
Read Timing
Data Valid SCLK Falling Data Rising Hi-Z
Notes: Device parameters specified with 4.9125 clock. Specified using points waveform interest. Output loaded with Oscillator start-up time varies with crystal parameters. This specification does apply when using external clock source.
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MSB-1
SCLK
Figure Write Timing (Not Scale).
MSB-1
SCLK
Figure Read Timing (Not Scale).
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GENERAL DESCRIPTION
CS5531/32/33/34 highly integrated Analog-to-Digital Converters (ADCs) which charge-balance techniques achieve 16-bit (CS5531/33) 24-bit (CS5532/34) performance. ADCs optimized measuring low-level unipolar bipolar signals weigh scale, process control, scientific, medical applications. accommodate these applications, ADCs come either two-channel (CS5531/32) fourchannel (CS5533/34) devices include very noise chopper-stabilized programmable gain instrumentation amplifier (PGIA, nV/Hz with selectable gains These ADCs also include fourth order modulator followed digital filter which provides selectable output word rates 1.92 kHz, 3.84 (MCLK 4.9152 MHz). ease communication between ADCs micro-controller, converters include simple three-wire serial interface which Microwire compatible with Schmitt Trigger input serial clock (SCLK).
2.1. Analog Input
Figure illustrates block diagram CS5531/32/33/34. front consists multiplexer, unity gain coarse/fine charge input buffer, programmable gain chopper-stabilized instrumentation amplifier. unity gain buffer activated time conversions performed with gain instrumentation amplifier activated time conversions performed with gain settings greater than one. unity gain buffer designed accommodate rail rail input signals. common-mode plus signal range unity gain buffer amplifier VA+. Typical (sampling) current unity gain buffer amplifier about (MCLK 4.9152 MHz, Figure instrumentation amplifier chopper-stabilized operates with chop clock frequency MCLK/128. (sampling) current into instrumentation amplifier less than over
VREF+ VREFAIN2+ AIN2AIN1+ AIN1-
CS5531/32
1000 XGAIN 1000
AIN4+ AIN4* AIN1+ AIN1-
CS5533/34
ININ+
Differential Order Modulator
Sinc Digital Filter
Programmable Sinc3 Digital Filter
Serial Port
GAIN gain setting PGIA (i.e.
Figure Multiplexer Configuration.
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-40°C +85°C (MCLK=4.9152 MHz). common-mode plus signal range instrumentation amplifier (VA-) (VA+) Figure illustrates input models amplifiers. dynamic input current each pins determined from models shown. tation amplifier (i.e. gain setting other than using gain setting full scale input range quickly 2.5/32 about 78mV. Note that these input ranges assume calibration registers their default values (i.e. Gain Offset 0.0).
2.1.2. Multiplexed Settling Limitations
Gain fVos
MCLK Fine Coarse
Gain
settling performance CS5531/32/33/34 multiplexed applications affected single-pole low-pass filter which follows instrumentation amplifier (see Figure achieve data sheet settling linearity specifications, recommended that capacitor used. Capacitors used with some noise degradation.
2.1.3. Voltage Noise Density Performance
Figure illustrates voltage noise density versus frequency from 0.01 CS5532-BS. device powered with ±2.5 supplies, OWR, gain range, bipolar mode, with input short bits enabled.
fVos MCLK
Figure Input models AIN+ AIN- pins.
Gain
Note:
C=2.5pF 16pF capacitors input current modeling only. physical input capacitance `Input Capacitance' specification under Analog Characteristics.
0.01
2.1.1. Analog Input Span
full scale input signal that converter digitize function gain setting reference voltage connected between VREF+ VREF- pins. full scale input span converter ((VREF+) (VREF-))/(GxA), where gain amplifier After reset, unity gain buffer engaged. With 2.5V reference this would make full scale input range default activating instrumenDS289PP3
Frequency (Hz)
Figure Measured Voltage Noise Density.
2.1.4. Offset
offset included CS553x family because high dynamic range converter eliminates need one. offset register manipulated user mimic function desired.
CS5531/32/33/34
2.2. Overview Register Structure Operating Modes
CS5531/32/33/34 ADCs have on-chip controller, which includes number user-accessible registers. registers used hold offset gain calibration results, configure chip's operating modes, hold conversion instructions, store conversion data words. Figure depicts block diagram on-chip controller's internal registers. Each converters 32-bit registers function offset gain calibration registers each channel. converters with channels have offset gain calibration registers, converters with four channels have four offset four gain calibration registers. These register hold calibration results. contents these registers read written user. This allows calibration data off-loaded into external EEPROM. user also manipulate contents these registers modify offset gain slope converter. converters include 32-bit configuration register which bits used setting options such operating power options, resetting converter, shorting analog inputs, enabling diagnostic test bits like guard signal. group registers, called Channel Setup Registers, also included converters. These registers used hold pre-loaded conversion instructions. Each channel setup register bits long holds 16-bit conversion instructions referred Setups. Upon power these registers initialized users' microcontroller with conversion instructions. user then instruct converter perform single multiple conversions calibrations with converter mode defined Setup referenced. Using single conversion mode, 8-bit command word written into serial port.
Offset Registers Offset
Gain Registers Gain
Channel Setup Registers Setup Setup Setup Setup Setup Setup Setup Setup
Conversion Data Register Data
Offset
Gain
CS5533/34 Only
Offset
Gain
Offset
Gain
Read Only
Serial Interface
SCLK
Configuration Register
Power Save Select Reset System Input Short Guard Signal Voltage Reference Select Output Latch Output Latch Select
Channel Select Gain Word Rate Unipolar/Bipolar Output Latch Delay Time Open Circuit Detect
Write Only Command Register
Figure CS5531/32/33/34 Register Diagram.
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command includes pointer bits which `point' 16-bit command Channel Setup Registers which executed. 16-bit Setups programmed perform conversion input channels converter. More than 16-bit Setups used same analog input channel. This allows user convert same signal with either different conversion speed, different gain range, other options, which channel setup registers. Alternatively, user registers perform different conversion conditions each input channels. ADCs also include multiple conversions capability. User bits configuration register ADCs configured continuously convert 16-bit command Setup, performing conversion according content each 16-bit Setup. multiple conversions mode, conversion data words loaded into data conversion register. converter issues flag when conversion cycle completed user read conversion register. More details will follow. following pages document initialize converter, perform offset gain calibrations, configure converter various conversion modes. Each bits configuration register Channel Setup Registers described. list examples follows description section. Also Command Register Quick Reference used decode valid commands (the first 8-bits into serial port).
2.2.1. System Initialization
CS5531/32/33/34 provide power-on-reset function. initialize ADCs, user must perform software reset resetting ADC's serial port with Serial Port Initialization sequence. This sequence resets serial port command mode accomplished transmitting SYNC1 command bytes (0xFF hexadecimal), followed SYNC0 command (0xFE hexadecimal). Note that this sequence initiated anytime reinitialize serial port. complete system initialization sequence, user must also perform system reset setting Reset System (RS) configuration register. system reset also initiated time writing logic configuration register. After system reset cycle complete, automatically returned logic on-chip registers initialized following states:
Configuration Register: Offset Registers: Gain Registers: Channel Setup Registers: 00000000(H) 00000000(H) 01000000(H) 00000000(H)
After system initialization reset, on-chip controller initialized into command mode where waits valid command (the first 8-bits transmitted into serial port transmitted into command register). Once valid command received decoded, byte instructs converter either acquire data from transfer data internal register(s), perform conversion calibration. Command Register Descriptions section used decode valid commands.
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2.2.2. Command Register Quick Reference
D7(MSB) RSB2 RSB1 RSB0
NAME
Command Bit, Access Registers Arrays,
VALUE FUNCTION
Must logic these commands. These commands invalid this logic Ignore this function. Access respective registers, offset, gain, channel-setup, array registers. particular registers accessed determined bits. registers accessed first with physical channel accessed first followed physical channel next forth. CS1-CS0 provide address (four CS5533/34) physical input channels. These bits also used access calibration registers associated with respective physical input channel. Note that these bits ignored when reading data register. Write selected register. Read from selected register. Reserved Offset Register Gain Register Configuration Register Conversion Data Register (Read Only) Channel-Setup Registers Reserved Reserved CSRP1 CSRP0
D5-D4
Channel Select Bits, CS1-CS0
D2-D0
Read/Write, Register Select Bit, RSB3-RSB0
D7(MSB)
CSRP2
D5-D3
NAME
Command Bit, Multiple Conversions, Channel-Setup Register Pointer Bits, CSRP Conversion/Calibration Bits, CC2-CC0
VALUE FUNCTION
These commands invalid this logic Must logic these commands. Perform fully settled single conversions. Perform conversions continuously. These bits used pointers Channel-Setup registers. Either single conversion continuous conversions performed channel setup register pointed these bits. Normal Conversion Self-Offset Calibration Self-Gain Calibration Reserved Reserved System-Offset Calibration System-Gain Calibration Reserved
D2-D0
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2.2.3. Command Register Descriptions
READ/WRITE OFFSET CALIBRATION REGISTERS
D7(MSB)
Function:
These commands used access offset registers arrays.
Write selected register. Read from selected register.
(Read/Write)
READ/WRITE GAIN CALIBRATION REGISTERS
D7(MSB)
Function:
These commands used access gain registers arrays.
Write selected register. Read from selected register.
(Read/Write)
READ/WRITE CHANNEL-SETUP REGISTERS
D7(MSB)
Function:
These commands used access channel-setup registers arrays.
Write selected register. Read from selected register.
(Read/Write)
READ/WRITE INDIVIDUAL OFFSET REGISTER
D7(MSB)
Function:
These commands used access each offset register separately. decode registers accessed.
Write selected register. Read from selected register.
(Read/Write)
CS[1:0] (Channel Select Bits)
Offset Register (All devices) Offset Register (All devices) Offset Register (CS5533/34 only) Offset Register (CS5533/34 only)
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READ/WRITE INDIVIDUAL GAIN REGISTER
D7(MSB)
Function:
These commands used access each gain register separately. decode registers accessed.
Write selected register. Read from selected register.
(Read/Write)
CS[1:0] (Channel Select Bits)
Gain Register (All devices) Gain Register (All devices) Gain Register (CS5533/34 only) Gain Register (CS5533/34 only)
READ/WRITE INDIVIDUAL CHANNEL-SETUP REGISTER
D7(MSB)
Function:
These commands used access each channel-setup register separately. decode registers accessed.
Write selected register. Read from selected register.
(Read/Write)
CS[1:0] (Channel Select Bits)
Channel-Setup Register (All devices) Channel-Setup Register (All devices) Channel-Setup Register (All devices) Channel-Setup Register (All devices)
READ/WRITE CONFIGURATION REGISTER
D7(MSB)
Function:
These commands used read from write configuration register.
Write selected register. Read from selected register.
(Read/Write)
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PERFORM CONVERSION
D7(MSB) CSRP2 CSRP1 CSRP0
Function:
These commands instruct perform either single conversion continuous conversions physical input channel pointed pointer bits (CSRP2 CRSP0) channel-setup register.
Perform fully settled single conversions. Perform conversions continuously.
(Multiple Conversions)
CSRP [2:0] (Channel Setup Register Pointer Bits)
Setup (All devices) Setup (All devices) Setup (All devices) Setup (All devices) Setup (All devices) Setup (All devices) Setup (All devices) Setup (All devices)
READ CONVERSION DATA REGISTER
D7(MSB)
Function:
This command used read from conversion data register.
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PERFORM CALIBRATION
D7(MSB) CSRP2 CSRP1 CSRP0
Function:
These commands instruct perform calibration physical input channel selected setup register which chosen command byte pointer bits (CSRP2 CSRP0).
Setup (All devices) Setup (All devices) Setup (All devices) Setup (All devices) Setup (All devices) Setup (All devices) Setup (All devices) Setup (All devices)
CSRP [2:0] (Channel Setup Register Pointer Bits)
[2:0] (Calibration Control Bits)
Reserved Self-Offset Calibration Self-Gain Calibration Reserved Reserved System-Offset Calibration System-Gain Calibration Reserved
SYNC1
D7(MSB)
Function:
SYNC0
D7(MSB)
Part serial port re-initialization sequence.
Function:
NULL
D7(MSB)
serial port re-initialization sequence.
Function:
This command used clear port flag keep converter continuous conversion mode.
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2.2.4. Serial Port Interface
CS5531/32/33/34's serial interface consists four control lines: SDI, SDO, SCLK. Figure details command data word timing. Chip Select, control line which enables access serial port. tied low, port function three wire interface. SDI, Serial Data data signal used transfer data converters. SDO, Serial Data Out, data signal used transfer output data from converters. output will held high impedance time logic
SCLK, Serial Clock, serial bit-clock which controls shifting data from ADC's serial port. must held (logic before SCLK transitions recognized port logic. accommodate optoisolators SCLK designed with Schmitt-trigger input allow optoisolator with slower rise fall times directly drive pin. Additionally, capable sinking sourcing directly drive optoisolator LED. will have less than loss drive voltage when sinking sourcing
SCLK
Command Time SCLKs
Data Time SCLKs
Write Cycle
SCLK
Command Time SCLKs
Data Time SCLKs
Read Cycle
SCLK
Command Time SCLKs
MCLK /OWR Clock Cycles
SCLKs Clear Flag Data Conversion Cycle
Data Time SCLKs
MCLK/OWR clock cycles each conversion except first conversion which will take MCLK/OWR clock cycles
Figure Command Data Word Timing.
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2.2.5. Reading/Writing On-Chip Registers
CS5531/32/33/34's offset, gain, configuration, channel-setup registers readable writable while conversion data register read only. shown Figure write particular register user must transmit appropriate write command then follow that command bits data. example, write 0x80000000 (hexadecimal) physical channel one's gain register, user would first transmit command byte 0x02 (hexadecimal) followed data 0x80000000 (hexadecimal). Similarly, read particular register user must transmit appropriate read command then acquire bits data. Once register written read from, serial port returns command mode. addition accessing internal registers time, gain offset registers well channel-setup registers, accessed arrays (i.e. entire register accessed with command). example, write 0x80000000 (hexadecimal) four gain registers, user would transmit command 0x42 (hexadecimal) followed four iterations 0x80000000 (hexadecimal), (i.e. 0x42 followed 0x80000000, 0x80000000, 0x80000000, 0x80000000). registers written read from sequential order (i.e, followed then then Once registers written read from, serial port returns command mode.
2.2.6. Setting CSRs Measurement
CS5531/32/33/34 have four Channel-Setup Registers (CSRs). Each contains 16-bit Setups which programmed user contain data conversion information such which physical channel will converted, what gain will channel converted, what word rate will channel converted, will output conversion unipolar bipolar, what will state output latch during conversion, will converter delay start conversion allow time output latch settle before conversion begun, will open circuit detect current source activated that Setup. Note that particular physical input channel represented more than Setup with different output rates, gain ranges, etc. (i.e. each Setup independently defined). Refer Channel-Setup Register Descriptions section more details. Each 32-bit individually accessible contains 16-bit Setups. example, configure Setup CS5531/32/33/34 with write individual channel-setup register command (0x05 hexadecimal), bits contains information Setup bits contain information Setup Note that while reading/writing CSRs, Setups accessed pairs single 32-bit register. Even Setups isn't used, must written read. Examples detailing power CSRs provided Pointers Command Byte section.
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2.2.7. Channel-Setup Register Descriptions
Setup Bits <127:112> Setup Bits <111:96>
Setup Bits <31:16>
Setup Bits <15:0>
D31(MSB)
CS1-CS0 (Channel Select Bits) [31:30] [15:14]
Select physical channel (All devices) Select physical channel (All devices) Select physical channel (CS5533/34 only) Select physical channel (CS5533/34 only)
G2-G0 (Gain Bits) [29:27] [13:11]
Gain (Input Span [(VREF+)-(VREF-)]/1 unipolar). Gain (Input Span [(VREF+)-(VREF-)]/2 unipolar). Gain (Input Span [(VREF+)-(VREF-)]/4 unipolar). Gain (Input Span [(VREF+)-(VREF-)]/8 unipolar). Gain (Input Span [(VREF+)-(VREF-)]/16 unipolar). Gain (Input Span [(VREF+)-(VREF-)]/32 unipolar). Gain (Input Span [(VREF+)-(VREF-)]/64 unipolar).
WR3-WR0 (Word Rate) [26:23] [10:7]
Word Rates apply continuous conversion mode. single conversion mode, output will take three conversions settle. Only third output will provided serial port. 0000 0001 0010 0011 0100 1000 1001 1010 1011 (4.9152 MHz) 3840 1920 (4.096 MHz) 12.5 6.25 3200 1600 Clock Cycles (40960 MCLK cycles) (81920 MCLK cycles) (163840 MCLK cycles) (327680 MCLK cycles) (655360 MCLK cycles) (1280 MCLK cycles) (2560 MCLK cycles) (5120 MCLK cycles) (10240 MCLK cycles) (20480 MCLK cycles)
1100 other combinations used.
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(Unipolar Bipolar) [22]
Select Bipolar mode. Select Unipolar mode.
OL1-OL0 (Output Latch Bits) [21:20] [5:4]
latch bits will logic state these bits upon command word execution when output latch select (OLS) configuration register logic Note that logic outputs chip powered from VA-.
(Delay Time Bit) [19]
When set, converter will wait delay time before starting conversion. This allows settling time A1outputs before conversion begins. delay time will 1280 MCLK cycles. Normal mode. Wait 1280 MCLK cycles before starting conversion.
(Open Circuit Detect Bit) [18]
When set, this activates current source input channel (AIN+) selected channel select bits. Note that 300nA current source rated 25°C. -55°C, current source doubles approximately 600nA. This feature particularly useful thermocouple applications when user wants drive suspected open thermocouple lead supply rail. Normal mode. Activate current source.
(Not Used) [17:16] [1:0]
These bits reserved future upgrade.
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2.3. Configuration Register
ease architectural design, configuration register thirty-two bits long, however, only thirty bits used. following sections detail bits configuration register. Gain mode, PGIA powered down. this mode, power consumed normal power mode reduced sleep standby modes affected.
2.3.2. Reset System
reset system (RS) permits user perform system reset. system reset initiated time writing logic configuration register. After system reset cycle complete, reset valid (RV) indicating that internal logic properly reset. cleared after configuration register read. Note that on-chip registers initialized following states.
Configuration Register: Offset Registers: Gain Registers: Channel Setup Registers: 00000000(H) 00000000(H) 01000000(H) 00000000(H)
2.3.1. Power Consumption
CS5531/32/33/34 accommodate three power consumption modes: normal, standby, sleep. normal mode, default mode, entered after power applied. this mode, CS5531/32/33/34-AS versions typically consume CS5532/34-BS versions typically consume last modes referred power save modes. They power down most analog portion chip stop filter convolutions. power save modes entered whenever power down (PDW) configuration register logic particular power save mode entered depends state (Power Save Select) bit. logic converter enters standby mode reducing power consumption standby mode leaves oscillator on-chip bias generator analog portion chip active. This allows converter quickly return normal mode once back logic both logic sleep mode entered reducing consumed power around Since this sleep mode disables oscillator, approximately oscillator start-up delay period required before returning normal mode. external clock used delay necessary. Further note that when chips used
Further note that after reset automatically returns logic ADCs return command mode where they wait valid command. Also, only configuration register that when initiating reset.
2.3.3. Input Short
input short allows user internally ground inputs multiplexer. This useful function because allows user easily test grounded input performance eliminate noise effects external system.
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2.3.4. Guard Signal
guard signal that modifies function When set, this outputs common mode voltage instrumentation amplifier This feature useful when user wants connect external shield common mode potential instrumentation amplifier protect against leakage. Figure illustrates typical connection diagram guard signal.
2.3.5. Voltage Reference Select
voltage reference select (VRS) selects size sampling capacitor used sample voltage reference. should based upon magnitude reference voltage achieve optimal performance. Figures model effects reference's input impedance input current each setting. models show, reference includes coarse/fine charge buffer which reduces dynamic current demand external reference. reference's input buffer designed accommodate rail-to-rail (common-mode plus signal) input voltages. differential voltage between VREF+ VREF- voltage from analog supply (depending configured), however, VREF+ cannot above VREF- below VA-. single-ended reference voltage, reference voltage input into VREF+ converter VREF- grounded. Note that supplies used, supplies must established before reference voltage.
CS5531/32/33/34
A0/GUARD
typical
AIN+
VIN+ Common Mode AINcenter
Figure Guard Signal Shielding Scheme.
Fine Coarse 22pF
Fine Coarse 11pF
VREF fVos
VREF fVos
MCLK VREF
MCLK VREF
Figure Input Reference Model when
Figure Input Reference Model when
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2.3.6. Output Latch Pins
A1-A0 pins ADCs mimic D21D20/D5-D4 bits channel-setup registers output latch select logic (default). output latch select logic then A1-A0 mimic output latch setting configuration register. These options give user choice allowing latch outputs change anytime different selected conversion; allow latch bits remain latched fixed state (determined configuration register bit) selections. either case, A1-A0 used control external multiplexers other logic functions outside converter. A1-A0 outputs sink source least recommended limit drive currents less than reduce self-heating chip. These outputs powered from VA-. Their output voltage will limited voltage logic logic
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2.3.7. Configuration Register Descriptions
D31(MSB)
(Power Save Select)[31]
Standby Mode (Oscillator active, allows quick power-up). Sleep Mode (Oscillator inactive).
(Power Down Mode)[30]
Normal Mode Activate power save select mode.
(Reset System)[29]
Normal Operation. Activate Reset cycle. automatically returns logic after reset.
(Reset Valid)[28]
Normal Operation System reset. This read only. cleared logic zero after configuration register read.
(Input Short)[27]
Normal Input signal input pairs each channel shorted internally.
(Guard Signal Bit)[26]
Normal Operation output latch. A0's output modified output common mode output voltage instrumentation amplifier (typically output latch select ignored when guard buffer activated. VREF VREF 2.5V
(Voltage Reference Select)[25]
A1-A0 (Output Latch bits)[24:23]
latch bits will logic state these bits upon command word execution output latch select (OLS) set. Note that these logic outputs powered from VA-.
Output Latch Select, OLS[22]
When low, uses Channel-Setup Register source When set, uses Configuration Register source
(Not Used)[21:0]
Must always logic Reserved future upgrades.
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2.4. Calibration
Calibration used zero gain slope ADC's transfer function. CS5531/32/33/34 offer both self calibration system calibration.
Note: After ADCs reset, they functional perform measurements without being calibrated (remember that configuration register must configured). this case, converter will utilize initialized values on-chip registers (Gain 1.0, Offset 0.0) calculate output words. initial offset gain errors internal circuitry chip will remain. Calibrations steps each take conversion cycle complete. calibration step, falls indicate that calibration complete. Offset calibration must performed before gain calibration because gain slope referenced from offset calibrations.
2.4.1. Calibration Registers
CS5531/32/33/34 converters have individual offset gain register each channel input. gain offset registers, which used during both self system calibration, used zero gain slope converter's transfer function. shown Offset Register section, offset register 2-24 proportion input span (bipolar span times unipolar span). offset register determines offset trimmed positive negative positive, negative). Note that magnitude offset that trimmed from input mapped through gain register. converter typically trim ±100 percent input span. shown Gain Register section, gain register spans from 2-22). decimal equivalent meaning gain register
where binary numbers have value either zero (bD28 corresponds D28).
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2.4.2. Gain Register
2-24
gain register span from (32-2-24). After Reset other bits `0'.
2.4.3. Offset Register
Sign 2-17
2-19
2-20
2-21
2-22
2-23
2-24
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-18
represents 2-24 proportion input span (bipolar span times unipolar span). Offset data word bits align MSB. After reset, bits `0'.
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2.4.4. Performing Calibrations
perform calibration user must send command byte with MSB=1, pointer bits (CSRP2-CSRP0) address desired Setup calibrate, appropriate calibration bits (CC2CC0) choose type calibration performed. Note that calibration assumes that CSRs have been previously initialized because information concerning physical channel, filter rate, gain range, polarity, comes from channel-setup register being addressed pointer bits command byte. Once CSRs initialized, calibration performed with command byte. Once calibration cycle complete, falls results stored either gain offset register physical channel being calibrated. Note that additional calibrations performed same physical channel referenced different Setups with different filter rates, gain ranges, conversion modes, last calibration results will replace effects from previous calibration only offset gain register available physical channel. Further note that only calibration performed with each command byte. calibrate channels additional calibration commands necessary.
2.4.5. Self Calibration
CS5531/32/33/34 offer both self offset self gain calibrations. self-calibration offset, converters internally inputs amplifier together routes them AIN- shown Figure proper self-calibration offset occur, pins must proper common-mode-voltage specified Analog Characteristics section. self-calibration gain, differential inputs modulator connected VREF+ VREF- shown Figure Self-calibration gain performed GAIN mode without regard setup register's gain setting. Gain errors PGIA gain steps calibrated this would require accurate voltage source other than reference voltage. system calibration gain should performed accurate gains achieved ranges.
OPEN AIN+ CLOSED AIN+ XGAIN
OPEN AIN+ XGAIN AINVREF+ Reference VREFOPEN
CLOSED
CLOSED
Figure Self Calibration Offset.
Figure Self Calibration Gain.
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2.4.6. System Calibration
system calibration functions, user must supply converters calibration signals which represent ground full scale. When system offset calibration performed, ground reference signal must applied converters. Figure illustrates system offset calibration. shown Figure user must input signal representing positive full scale point perform system gain calibration. either case, calibration signals must within specified calibration limits each specific calibration step (refer System Calibration Specifications). maximum accuracy, calibrations should performed both offset gain (selected changing G2-G0 bits channel-setup registers). Note that only gain range calibrated physical channel. factory calibration user's system performed using system calibration capabilities CS5531/32/33/34, offset gain register contents read system microcontroller recorded EEPROM. These same calibration words then uploaded into offset gain registers converter when power first applied system, when gain range changed. Note that user wants uncalibrated conversions, uncalibrated gain accuracy percent. Further note that gain tracking from range range affected calibration. Gain tracking from range range percent. Note that gain from offset register output approximately decimal, user wants calculate calibration coefficients externally, they will need divide content offset register scale factor 01D5C315 hexadecimal while bipolar mode (for unipolar mode divide two).
2.4.7. Calibration Tips
Calibration steps performed output word rate selected WR2-WR0 bits channel setup registers. Since higher word rates result conversion words with more peak-to-peak noise, calibration should performed lower output word rates. Also, minimize digital noise near device, user should wait each calibration step completed before reading writing serial port.
External Connections AIN+ AINXGAIN
Full Scale
External Connections AIN+ XGAIN AIN+
Figure System Calibration Offset.
Figure System Calibration Gain.
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2.4.8. Limitations Calibration Range
System calibration limited signal headroom analog signal path inside chip discussed under Analog Input section this data sheet. gain calibration, full scale input signal reduced point which gain register reaches upper limit (32-2-64 decimal). Under nominal conditions, this occurs with full scale input signal equal about 1/32 nominal full scale. With converter's intrinsic gain error, this full scale input signal higher lower. defining minimum Full Scale Calibration Range (FSCR) under Analog Characteristics, margin retained accommodate intrinsic gain error. Alternatively input full scale signal increased point which modulator reaches density limit percent, which under nominal condition occurs when full scale input signal times nominal full scale. With chip's intrinsic gain error, this input full scale input signal maybe higher lower. defining maximum FSCR, margin again incorporated accommodate intrinsic gain error. clear flag. During first SCLKs, must logic last SCLKs needed read conversion result. Note that user forced read conversion single conversion mode will remain (i.e. serial port data mode) until SCLK transitions times. After reading data, serial port returns command mode, where waits command issued.
Note: single conversion mode only fully settled data conversions output data conversion register. Since converter uses Sinc5 filter 3840 word rate, effective word rate single conversion mode will normal rate (3840/5 which MCLK 4.9152 MHz). Since converter uses Sinc3 filter other rates, their effective rates will three conversion required fully settle Sinc3 filter.
2.5.2. Multiple Conversions Mode
Based information provided channelsetup registers (CSRs), continuous conversions repeatedly performed using Setup register contents pointed conversion command. command byte includes pointer address Setup register used during conversion. Once transmitted, serial port enters data mode where waits until conversion complete. After conversion done, falls logic Forty SCLKs then needed read conversion. first SCLKs used clear flag. last SCLKs needed read conversion result. `00000000' provided during first SCLKs when flag cleared, converter remains this conversion mode continues convert selected channel using same Setup. While this mode, every conversion word needs read. user needs only read conversion words required application rises falls indicate availability conversion. Note that conversion read will lost replaced conversion. exit this conversion mode
2.5. Performing Conversions
CS5531/32/33/34 offers modes performing conversions. three sections that follow detail differences provide examples illustrating conversion modes with channel-setup registers.
2.5.1. Single Conversion Mode
Based information provided channelsetup registers (CSRs), single conversion performed after user transmits single conversion command. command byte includes pointer address Setup register used during conversion. Once transmitted, serial port enters data mode where waits until conversion complete. After conversion done, falls logic Forty SCLKs then needed read conversion. first SCLKs used
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CS5531/32/33/34
user must provide `11111111' during first SCLKs. user decides exit, SCLKs required clock last conversion before converter will return command mode.
Note: calibration single conversion performed before multiple conversions command given, user must ignore first three (for OWRs less than 3840 MCLK 4.9152 MHz) first five (for equal 3840 conversions multiple conversions mode residual filter coefficients must flushed from filter before accurate conversion performed.
Example single conversion with Setup command issued `10000000'. These settings instruct converter perform single conversion with Setup settings CSRP2 CSRP0 `000' (which happens physical channel this example). After command received decoded performs conversion physical channel then falls indicate that conversion complete. read conversion, SCLKs then required. Once acquired, serial port returns command mode. Example continuous conversion with Setup command issued `11010000'. These settings instruct converter perform continuous conversions with Setup settings CSRP2 CSRP0 `010' (which happens physical channel this example). After command received decoded performs conversion physical channel then falls indicate that conversion complete. user three options. user acquire conversion remain this mode, acquire conversion exit this mode, ignore conversion wait conversion next update interval. Example calibration with Setup command issued `10011001'. These settings instruct converter perform self offset calibration with Setup settings CSRP2 CSRP0 `011' (which happens physical channel this example). After command received decoded performs self offset calibration physical channel then falls indicate that calibration complete. perform additional calibrations, more commands have issued.
Note: CSRs need written. they initialized, Setups point their default settings irrespective single conversion, multiple single conversion, calibration mode (i.e conversion performed, only physical channel will converted). Further note that filter convolutions reset (i.e. flushed) consecutive conversions
2.5.3. Examples Using CSRs Perform Conversions Calibrations
time calibration conversion command issued CC2-CC0 bits must properly set), CSRP2-CSRP0 bits command byte used pointers address Setups channel-setup registers (CSRs). Table details address decoding pointer bits.
(CSRP2-CSRP0) Location Setup
CSR#4
Table Command Byte Pointer Table.
examples that follow detail situations that user might encounter when acquiring conversion calibrating converter. These examples assume that CSRs programmed with following physical channel order: physical channel defined actual input channel (AIN1 AIN4) which external signal connected.
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CS5531/32/33/34
performed different physical channels. consecutive conversions performed same physical channel, filter reset. This allows ADCs more quickly settle full scale step inputs.
2.6. Conversion Output Coding
CS5531/32/33/34 output 16-bit (CS5531/33) 24-bit (CS5532/34) data conversion words. read conversion word user must read conversion data register. conversion data register bits long outputs conversions first. last byte conversion data register 2.6.1. Conversion Data Register Descriptions
CS5531/33 (16-BIT CONVERSIONS)
D31(MSB)
contains data monitoring flags. channel indicator (CI) bits keep track which physical channel converted overrange flag (OF) monitors determine valid conversion performed. Refer Conversion Data Register Descriptions section more details. CS5531/32/33/34 output data conversions binary format when operating unipolar mode two's complement when operating bipolar mode. Refer Output Coding section more details.
CS5532/34 (24-BIT CONVERSIONS)
D31(MSB)
Conversion Data Bits [31:16 CS5531/33; 31:8 CS5532/34]
These bits depict latest output conversion.
(Not Used) [15:3 CS5531/33; CS5532/34]
These bits masked logic zero.
(Over-range Flag Bit)
clear when over-range condition occurred (read only). when input signal more positive than positive full scale, more negative than zero (unipolar mode) when input more negative than negative full scale (bipolar mode).
(Channel Indicator Bits) [1:0]
These bits indicate which physical input channel converted. Physical Channel Physical Channel Physical Channel Physical Channel
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2.6.2. Output Coding
CS5531/33 16-Bit Output Coding Unipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 Offset Binary FFFF FFFF -FFFE 8000 -7FFF 0001 -0000 0000 Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 Two's Complement 7FFF 7FFF -7FFE 0000 -FFFF 8001 -8000 8000 CS5532/34 24-Bit Output Coding Unipolar Input Voltage VFS-1.5 Offset Binary FFFFFF -FFFFFE 800000 -7FFFFF 000001 -000000 Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 Two's Complement 7FFFFF 7FFFFF -7FFFFE 000000 -FFFFFF 800001 -800000 800000
>(VFS-1.5 LSB) FFFFFF
VFS/2-0.5
VFS/2-0.5
-0.5
-0.5
+0.5
+0.5
-VFS+0.5 <(-VFS+0.5 LSB)
-VFS+0.5
<(+0.5 LSB)
<(+0.5 LSB)
000000 <(-VFS+0.5 LSB)
Note: table equals voltage between ground full scale unipolar gain ranges, voltage between full scale bipolar gain ranges. text about error flags under overrange conditions. Table Output Coding 16-bit CS5531/33 24-bit CS5532/34.
2.7. Digital Filter
CS5531/32/33/34 have linear phase digital filters which programmed achieve range output word rates (OWRs) stated ChannelSetup Register Descriptions section. ADCs Sinc5 digital filter output word rates 3840 (MCLK 4.9152 MHz). Other output word rates achieved using Sinc3 filter with programmable decimation (see Figure 15). Sinc3 active output word rates except 3840 (MCLK 4.9152 MHz) rate. converter's digital filters scale with MCLK. example, with output word rate filter's corner frequency typically MCLK increased MHz, increases 1.0175 percent filter's corner frequency moves 31.54 Note that converter isn't specified MCLK clock frequencies greater than MHz.
Gain (dB)
-120
Frequency (Hz)
Figure Digital Filter Response (Word Rate Hz).
Frequency (Hz) (MCLK 4.096MHz) (MCLK 4.9152MHz)
Notch Depth (dB)
Frequency (Hz)
Minimum Attenuation (dB)
Table Filter Notch Attenuation.
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2.8. Clock Generator
CS5531/32/33/34 include on-chip inverting amplifier which connected with external crystal provide master clock chip. chips designed operate using 4.9152 crystal; however, other crystal with frequencies between used. lead crystal should connected OSC1 other OSC2. Lead lengths should minimized reduce stray capacitance. Note that while using chip oscillator, neither OSC1 OSC2 capable directly driving chip logic. When chip oscillator used, voltage OSC2 typically peak-to-peak. This signal compatible with external logic unless additional external circuitry added. OSC2 output should used crystal output used drive other logic. designer external CMOS compatible oscillator drive OSC2 with clock ADC. this scheme, OSC1 left unconnected.
2.9. Power Supply Arrangements
CS5531/32/33/34 designed operate from single dual analog supplies single digital supply. following power supply connections possible: +2.5 -2.5 Figure illustrates CS5532 connected with single +5.0 supply measure differential inputs relative common mode Figure illustrates CS5532 connected with ±2.5 bipolar analog supplies digital supply measure ground referenced bipolar signals. Figure illustrates CS5532 connected with analog supplies digital supply measure ground referenced bipolar signals. Figure illustrates alternate bridge configurations which measured with converter. Voltage measured with PGIA gain input amplifier this gain setting rail-to-rail. Voltage should measured with PGIA gain higher instrumentation amplifier used these gain ranges achieves lower noise.
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Analog Supply
VREF+ VREF3 OSC2
Optional Clock Source 4.9152
OSC1
CS5532 AIN1+ AIN1AIN2+ AIN2A0 SCLK DGND
Serial Data Interface
Figure CS5532 Configured with Single Supply.
+2.5 Analog Supply
VREF+ VREF3 OSC2
Digital Supply Optional Clock Source 4.9152
OSC1
CS5532 AIN1+ AIN1AIN2+ AIN2A0 SCLK DGND
Serial Data Interface
-2.5 Analog Supply
Figure CS5532 Configured with ±2.5 Analog Supplies.
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Analog Supply
VREF+ VREF3 OSC2
OSC1
Optional Clock Source 4.9152
CS5532 AIN1+ AIN1AIN2+ AIN2A0 SCLK DGND
Serial Data Interface
Analog Supply
Figure CS5532 Configured with Analog Supplies.
Figure Bridge with Series Resistors.
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2.10. Getting Started
This part several features. From software programmer's prospective, what should done first? begin, 4.9152 4.096 crystal takes approximately start. accommodate this, recommended that software delay approximately start processor's initialization code. Next, since CS5531/32/33/34 provide power-on-reset function, user must first initialize known state. This accomplished resetting ADC's serial port with Serial Port Initialization sequence. This sequence resets serial port command mode accomplished transmitting SYNC1 command bytes (0xFF hexadecimal), followed SYNC0 command (0xFE hexadecimal). Once known state this case command mode), user must reset internal logic performing system reset. This accomplished setting Reset System (RS) configuration register. After system reset cycle complete, automatically returned logic on-chip logic initialized proper state, returned command mode where waits next valid command execute. next action initialize voltage reference mode. voltage reference select (VRS) configuration register must based upon magnitude reference voltage between VREF+ VREF- pins. After this, initialize channel-setup registers (CSRs) these registers determine calibrations conversions will performed. Once CSRs initialized, user three options calibrating ADC: don't calibrate default settings; perform self system calibrations; upload previously saved calibration results offset gain registers. Once calibrated, ready perform conversions.
2.11. Layout
CS5531/32/33/34 should placed entirely over analog ground plane. Place analog-digital plane split immediately adjacent digital portion chip.
Note: CDB5531/32/33/34 data sheet suggested layout details Applications Note more detailed layout guidelines. Before layout, please call Free Schematic Review Service.
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DESCRIPTIONS
DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT AMPLIFIER CAPACITOR CONNECT AMPLIFIER CAPACITOR CONNECT POSITIVE ANALOG POWER NEGATIVE ANALOG POWER LOGIC OUTPUT (ANALOG)/GUARD LOGIC OUTPUT (ANALOG) MASTER CLOCK MASTER CLOCK
AIN1+
AIN1C1
AIN2+
AIN2VREF+
DIFFERENTIAL ANALOG INPUT
CS5531/2
DIFFERENTIAL ANALOG INPUT VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT DIGITAL GROUND POSITIVE DIGITAL POWER CHIP SELECT SERIAL DATA INPUT SERIAL DATA SERIAL CLOCK INPUT
VAA0 OSC2 OSC1
VREFDGND SCLK
DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT AMPLIFIER CAPACITOR CONNECT AMPLIFIER CAPACITOR CONNECT POSITIVE ANALOG POWER NEGATIVE ANALOG POWER LOGIC OUTPUT (ANALOG)/GUARD LOGIC OUTPUT (ANALOG) MASTER CLOCK MASTER CLOCK
AIN1+ AIN1-
AIN2+ AIN2AIN3+ AIN3-
DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT
VOLTAGE REFERENCE INPUT
AIN4+
AIN4C1
CS5533/4
VREF+
VREFDGND
VAA0 OSC2 OSC1
VOLTAGE REFERENCE INPUT DIGITAL GROUND POSITIVE DIGITAL POWER CHIP SELECT SERIAL DATA INPUT SERIAL DATA SERIAL CLOCK INPUT
SCLK
Clock Generator OSC1; OSC2 Master Clock. inverting amplifier inside chip connected between these pins used with crystal provide master clock device. Alternatively, external (CMOS compatible) clock (powered relative VD+) supplied into OSC2 provide master clock device. Control Pins Serial Data Chip Select. When active low, port will recognize SCLK. When high will output high impedance state. should changed when SCLK
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Serial Data Input. input serial input port. Data will input rate determined SCLK. Serial Data Output. serial data output. will output high impedance state SCLK Serial Clock Input. clock signal this determines input/output rate data SDI/SDO pins respectively. This input Schmitt trigger allow slow rise time signals. SCLK will recognize clocks only when low. Logic Output (Analog)/Guard, Logic Output (Analog). logic states A0-A1 mimic states D22/D10-D23/D11 bits channel-setup register. Logic Output VA-, Logic Output VA+. used guard drive instrumentation amplifier with proper setting Configuration Register. Measurement Reference Inputs AIN1+, AIN1-, AIN2+, AIN2- AIN3+, AIN3-, AIN4+, AIN4- Differential Analog Input. Differential input pins into CS5531. VREF+, VREF- Voltage Reference Input. Fully differential inputs which establish voltage reference on-chip modulator. Amplifier Capacitor Inputs. Connections instrumentation amplifier's capacitor. Power Supply Connections Positive Analog Power. Positive analog supply voltage. Positive Digital Power. Positive digital supply voltage (nominally +3.0 Negative Analog Power. Negative analog supply voltage. DGND Digital Ground. Digital Ground.
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SPECIFICATION DEFINITIONS
Linearity Error deviation code from straight line which connects endpoints transfer function. endpoint located below first code transition other endpoint located beyond code transition ones. Units percent fullscale. Differential Nonlinearity deviation code's width from ideal width. Units LSBs. Full Scale Error deviation last code transition from ideal [{(VREF+) (VREF-)} LSB]. Units LSBs. Unipolar Offset deviation first code transition from ideal (1/2 above voltage AIN- pin.). When unipolar mode (U/B Units LSBs. Bipolar Offset deviation mid-scale transition (111.111 000.000) from ideal (1/2 below voltage AIN- pin). When bipolar mode (U/B Units LSBs.
ORDERING GUIDE
Model Number CS5531-AS CS5533-AS CS5532-AS CS5532-BS CS5534-AS CS5534-BS Bits Channels Linearity Error (Max) Temperature Range ±0.003% ±0.003% ±0.003% ±0.0015% ±0.003% ±0.0015% -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C Package 20-pin 0.2" Plastic SSOP 24-pin 0.2" Plastic SSOP 20-pin 0.2" Plastic SSOP 20-pin 0.2" Plastic SSOP 24-pin 0.2" Plastic SSOP 24-pin 0.2" Plastic SSOP
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PACKAGE DRAWINGS
SSOP PACKAGE DRAWING
SIDE VIEW
VIEW
SEATING PLANE
VIEW
INCHES -0.002 0.064 0.009 0.272 0.291 0.197 0.024 0.025 0.084 0.010 0.074 0.015 0.295 0.323 0.220 0.027 0.040
MILLIMETERS -2.13 0.05 0.25 1.62 1.88 0.22 0.38 6.90 7.50 7.40 8.20 5.00 5.60 0.61 0.69 0.63 1.03
NOTE
Notes: "E1" reference datums included mold flash protrusions, include mold mismatch measured parting line, mold flash protrusions shall exceed 0.20 side. Dimension does include dambar protrusion/intrusion. Allowable dambar protrusion shall 0.13 total excess dimension maximum material condition. Dambar intrusion shall reduce dimension more than 0.07 least material condition. These dimensions apply flat section lead between 0.10 0.25 from lead tips.
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SSOP PACKAGE DRAWING
SIDE VIEW
VIEW
SEATING PLANE
VIEW
INCHES -0.002 0.064 0.009 0.311 0.291 0.197 0.024 0.025 0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.027 0.040
MILLIMETERS -2.13 0.05 0.25 1.62 1.88 0.22 0.38 7.90 8.50 7.40 8.20 5.00 5.60 0.61 0.69 0.63 1.03
NOTE
Notes: "E1" reference datums included mold flash protrusions, include mold mismatch measured parting line, mold flash protrusions shall exceed 0.20 side. Dimension does include dambar protrusion/intrusion. Allowable dambar protrusion shall 0.13 total excess dimension maximum material condition. Dambar intrusion shall reduce dimension more than 0.07 least material condition. These dimensions apply flat section lead between 0.10 0.25 from lead tips.
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16-Bit 24-Bit ADCs with Ultra Noise PGIA Chopper General Des

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