dual UART, Mbit/s (max.), with 64-byte FIFOs Motorola interface R

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dual UART, Mbit/s (max.), with 64-byte FIFOs Motorola interface R

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SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs Motorola interface
Rev. April 2005 Product data sheet
SC68C752B dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, data rates Mbit/s. SC68C752B offers enhanced features. Transmission Control Register (TCR) that stores receiver FIFO threshold levels start/stop transmission during hardware software flow control. With FIFO register, software gets status TXRDY/RXRDY four ports access. On-chip status registers provide user with error indications, operational status, modem interface control. System interrupts tailored meet user requirements. internal loop-back capability allows on-board diagnostics. UART transmits data, sent over peripheral 8-bit bus, signal receives characters signal. Characters programmed bits. UART 64-byte receive FIFO transmit FIFO programmed interrupt different trigger levels. UART generates desired baud rate based upon programmable divisor input clock. transmit even, odd, parity 1.5, stop bits. receiver detect break, idle, framing errors, FIFO overflow, parity errors. transmitter detect FIFO underflow. UART also contains software interface modem control operations, software flow control hardware flow control capabilities. SC68C752B available plastic LQFP48 package.
Features
Dual channel with Motorola interface Mbit/s data rate 64-byte transmit FIFO 64-byte receive FIFO with error flags Programmable selectable transmit receive FIFO trigger levels interrupt generation Software/hardware flow control Programmable Xon/Xoff characters Programmable Auto-RTS Auto-CTS Optional data flow resume character signalling capability both received transmitted data Supports operation tolerant inputs Software selectable baud rate generator
Philips Semiconductors
SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
Prescaler provides additional divide-by-4 function Industrial temperature range (-40 Fast data access time Programmable Sleep mode Programmable serial interface characteristics 8-bit characters Even, odd, parity generation detection 1.5, stop generation False start detection Complete status reporting capabilities both normal Sleep mode Line break generation detection Internal test loop-back capabilities Fully prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR,
Ordering information
Table Ordering information Package Name SC68C752BIB48 LQFP48 Description plastic profile quad flat package; leads; body Version SOT313-2 Type number
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Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
Block diagram
SC68C752B
TRANSMIT FIFO REGISTER RESET DATA CONTROL LOGIC FLOW CONTROL LOGIC TRANSMIT SHIFT REGISTER
TXA,
INTERCONNECT LINES CONTROL SIGNALS
RECEIVE FIFO REGISTER
RECEIVE SHIFT REGISTER
RXA,
REGISTER SELECT LOGIC
FLOW CONTROL LOGIC
DTRS, DTRB RTSA, RTSB OPA, MODEM CONTROL LOGIC
TXRDYA, TXRDYB RXRDYA, RXRDYB
INTERRUPT CONTROL LOGIC
CLOCK BAUD RATE GENERATOR
CTSA, CTSB RIA, CDA, DSRA, DSRB
002aab017
XTAL1
XTAL2
Block diagram SC68C752B
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Product data sheet
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Philips Semiconductors
SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
Pinning information
Pinning
TXRDYA
DSRA
CTSA
TXRDYB
n.c. RESET DTRB DTRA RTSA RXRDYA n.c. n.c.
002aab018
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SC68C752BIB48
n.c. XTAL1 XTAL2 RXRDYB DSRB RTSB CTSB
configuration LQFP48
description
Table Symbol CDA, description Type Description Address select bit. Internal registers address selection. Address select bit. Internal registers address selection. Address select bit. Internal registers address selection. Address used select Channel Channel logic selects Channel logic HIGH selects Channel (See Table Carrier Detect (active LOW). These inputs associated with individual UART Channel Channel logic these pins indicates that carrier been detected modem that channel. state these inputs reflected Modem Status Register (MSR). Chip Select (active LOW). This enables data transfers between user SC68C752B channel(s) addressed. Individual UART sections addressed Table Clear Send (active LOW). These inputs associated with individual UART Channel Channel logic (LOW) pins indicates modem data ready accept transmit data from SC68C752B. Status tested reading MSR[4]. These pins only affect transmit receive operations when Auto-CTS function enabled Enhanced Feature Register EFR[7] hardware flow control operation.
CTSA, CTSB
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Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
Table Symbol
description .continued Type Description Data (bi-directional). These pins 8-bit, 3-state data transferring information from controlling CPU. least significant first data transmit receive serial data stream. Data Ready (active LOW). These inputs associated with individual UART Channel Channel logic (LOW) these pins indicates modem data powered-on ready data exchange with UART. state these inputs reflected Modem Status Register (MSR). Data Terminal Ready (active LOW). These outputs associated with individual UART Channel Channel logic (LOW) these pins indicates that SC68C752B powered-on ready. These pins controlled modem control register. Writing logic MCR[0] will output logic (LOW), enabling modem. output these pins will logic after writing logic MCR[0], after reset. Signal power ground. Interrupt Request. Interrupts from UART Channel Channel wire-ORed internally function single interrupt. This transitions logic enabled interrupt enable register) whenever UART channel(s) requires service. Individual channel interrupt status determined addressing each channel through associated internal register, using external pull-up resistor must connected between this VCC. logic this will transfer contents data (D[0:7]) from external internal register that defined address bits A[0:2]. logic HIGH this will load contents internal register defined address bits A[0:2] SC68C752B data (D[0:7]) access external CPU. connected. User defined outputs. This function associated with individual Channel Channel state these pins defined user through software settings MCR[3]. OPA/OPB logic when MCR[3] logic OPA/OPB logic when MCR[3] logic output these pins HIGH after reset. Reset (active LOW). This will reset internal registers outputs. UART transmitter output receiver input will disabled during reset time. RESET active input. Ring Indicator (active LOW). These inputs associated with individual UART Channel Channel logic these pins indicates modem received ringing signal from telephone line. LOW-to-HIGH transition these input pins generates modem status interrupt, enabled. state these inputs reflected Modem Status Register (MSR). Request Send (active LOW). These outputs associated with individual UART Channel Channel logic indicates transmitter data ready waiting send. Writing logic Modem Control Register MCR[1] will this logic indicating data available. After reset these pins logic These pins only affect transmit receive operations when Auto-RTS function enabled Enhanced Feature Register (EFR[6]) hardware flow control operation. Receive data input. These inputs associated with individual serial channel data SC68C752B. During local loop-back mode, these input pins disabled data connected UART input internally.
DSRA, DSRB
DTRA, DTRB
n.c. OPA,
RESET
RIA,
RTSA, RTSB
RXA,
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Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
Table Symbol RXRDYA, RXRDYB TXA,
description .continued Type Description Receive Ready (active LOW). RXRDYA RXRDYB goes when trigger level been reached FIFO least character. goes HIGH when FIFO empty. Transmit data These outputs associated with individual serial transmit channel data from SC68C752B. During local loop-back mode, output disabled data internally connected UART input. Transmit Ready (active LOW). TXRDYA TXRDYB when there least trigger level number spaces available when FIFO empty. goes HIGH when FIFO full empty. Power supply input. Crystal external clock input. Functions crystal input external clock input. crystal connected between XTAL1 XTAL2 form internal oscillator circuit (see Figure 12). Alternatively, external clock connected this provide custom data rates. Output crystal oscillator buffered clock. (See also XTAL1.) XTAL2 used crystal oscillator output buffered clock output. Channel selection using UART channel none Channel Channel
TXRDYA, TXRDYB XTAL1
XTAL2
Table
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Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
Functional description
UART will perform serial-to-parallel conversion data characters received from peripheral devices modems, parallel-to-parallel conversion data characters transmitted processor. complete status each channel SC68C752B UART read time during functional operation processor. SC68C752B placed alternate mode (FIFO mode) relieving processor excessive software overhead buffering received/transmitted characters. Both receiver transmitter FIFOs store bytes (including three additional bits error status byte receiver FIFO) have selectable programmable trigger levels. Primary outputs RXRDY TXRDY allow signalling transfers. SC68C752B selectable hardware flow control software flow control. Hardware flow control significantly reduces software overhead increases system efficiency automatically controlling serial data flow using output input signals. Software flow control automatically controls data flow using programmable Xon/Xoff characters. UART includes programmable baud rate generator that divide timing reference clock input divisor between (216
Trigger levels
SC68C752B provides independent selectable programmable trigger levels both receiver transmitter interrupt generation. After reset, both transmitter receiver FIFOs disabled effect, trigger level default value byte. selectable trigger levels available FCR. programmable trigger levels available Trigger Level Register (TLR).
Hardware flow control
Hardware flow control comprised Auto-CTS Auto-RTS. Auto-CTS Auto-RTS enabled/disabled independently programming EFR[7:6]. With Auto-CTS, must active before UART transmit data. Auto-RTS only activates output when there enough room FIFO receive data de-activates output when FIFO sufficiently full. halt resume trigger levels determine levels which activated/deactivated. both Auto-CTS Auto-RTS enabled, when connected CTS, data transmission does occur unless receiver FIFO empty space. Thus, overrun errors eliminated during hardware flow control. enabled, overrun errors occur transmit data rate exceeds receive FIFO servicing latency.
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Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
UART SERIAL PARALLEL FIFO FLOW CONTROL PARALLEL SERIAL FIFO FLOW CONTROL
UART PARALLEL SERIAL FIFO FLOW CONTROL SERIAL PARALLEL FIFO FLOW CONTROL
002aaa228
Auto flow control (Auto-RTS Auto-CTS) example
6.2.1 Auto-RTS
Auto-RTS data flow control originates receiver block (see Figure "Block diagram SC68C752B" page Figure shows functional timing. receiver FIFO trigger levels used Auto-RTS stored TCR. active FIFO level below halt trigger level TCR[3:0]. When receiver FIFO halt trigger level reached, de-asserted. sending device (for example, another UART) send additional byte after trigger level reached (assuming sending UART another byte send) because recognize de-assertion until begun sending additional byte. automatically reasserted once receiver FIFO reaches resume trigger level programmed TCR[7:4]. This re-assertion allows sending device resume transmission.
Start
byte
Stop
Start
byte
Stop
Start
002aab086
receiver FIFO trigger level. blocks dashed lines cover case where additional byte sent, described Section 6.2.1.
functional timing
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Product data sheet
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Philips Semiconductors
SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
6.2.2 Auto-CTS
transmitter circuitry checks before sending next data byte. When active, transmitter sends next byte. stop transmitter from sending following byte, must de-asserted before middle last stop that currently being sent. Auto-CTS function reduces interrupts host system. When flow control enabled, level changes trigger host interrupts because device automatically controls transmitter. Without Auto-CTS, transmitter sends data present transmit FIFO receiver overrun error result.
Start
byte
Stop
Start
byte
Stop
002aaa227
When LOW, transmitter keeps sending serial data out. When goes HIGH before middle last stop current byte, transmitter finishes sending current byte, does send next byte. When goes from HIGH LOW, transmitter begins sending data again.
functional timing
Software flow control
Software flow control enabled through enhanced feature register modem control register. Different combinations software flow control enabled setting different combinations EFR[3:0]. Table shows software flow control options.
Table EFR[3] Software flow control options (EFR[0:3]) EFR[2] EFR[1] EFR[0] software flow controls transmit flow control transmit Xon1, Xoff1 transmit Xon2, Xoff2 transmit Xon1, Xon2, Xoff1, Xoff2 receive flow control receiver compared Xon1, Xoff1 receiver compares Xon2, Xoff2 transmit Xon1, Xoff1 receiver compares Xon1 Xon2, Xoff1 Xoff2 transmit Xon2, Xoff2 receiver compares Xon1 Xon2, Xoff1 Xoff2 transmit Xon1, Xon2, Xoff1, Xoff2 receiver compares Xon1 Xon2, Xoff1 Xoff2
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Product data sheet
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Philips Semiconductors
SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
There other enhanced features relating software flow control:
function (MCR[5]): Operation will resume after receiving character
after recognizing Xoff character. possible that Xon1 character recognized character, which could cause Xon2 character written FIFO.
Special character (EFR[5]): Incoming data compared Xoff2. Detection
special character sets Xoff interrupt (IIR[4]) does halt transmission. Xoff interrupt cleared read IIR. special character transferred FIFO.
6.3.1
When software flow control operation enabled, SC68C752B will compare incoming data with Xoff1,2 programmed characters certain cases, Xoff1 Xoff2 must received sequentially). When correct Xoff character received, transmission halted after completing transmission current character. Xoff detection also sets IIR[4] enabled IER[5]) causes HIGH. resume transmission, Xon1,2 character must received certain cases Xon1 Xon2 must received sequentially). When correct characters received, IIR[4] cleared, Xoff interrupt disappears.
6.3.2
Xoff1/2 character transmitted when FIFO passed HALT trigger level programmed TCR[3:0]. Xon1/2 character transmitted when FIFO reaches RESUME trigger level programmed TCR[7:4]. transmission Xoff/Xon(s) follows exact same protocol transmission ordinary byte from FIFO. This means that even word length characters, then least significant bits Xoff1,2/Xon1,2 will transmitted. (Note that transmission bits character seldom done, this functionality included maintain compatibility with earlier designs.) assumed that software flow control hardware flow control will never enabled simultaneously. Figure shows example software flow control.
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Product data sheet
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Philips Semiconductors
SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
6.3.3 Software flow control example
UART1 UART2
TRANSMIT FIFO
RECEIVE FIFO
PARALLEL-TO-SERIAL
data
SERIAL-TO-PARALLEL
Xoff-Xon-Xoff SERIAL-TO-PARALLEL PARALLEL-TO-SERIAL
Xon-1 WORD
Xon-1 WORD
Xon-2 WORD
Xon-2 WORD
Xoff-1 WORD
Xoff-1 WORD
Xoff-2 WORD
compare programmed Xon-Xoff characters
Xoff-2 WORD
002aaa229
Software flow control example
6.3.3.1
Assumptions UART1 transmitting large text file UART2. Both UARTs using software flow control with single character Xoff (0F) (0D) tokens. Both have Xoff threshold (TCR[3:0] threshold (TCR[7:4] Both have interrupt receive threshold (TLR[7:4] UART1 begins transmission sends characters, which point UART2 will generate interrupt processor service FIFO, assume interrupt latency fairly long. UART1 will continue sending characters until total characters have been sent. this time, UART2 will transmit UART1, informing UART1 halt transmission. UART1 will likely send 61st character while UART2 sending Xoff character. UART2 serviced processor reads enough data FIFO that level drops UART2 will send UART1, informing UART1 resume transmission.
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Product data sheet
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Philips Semiconductors
SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
Reset
Table summarizes state register after reset.
Table Register Interrupt Enable Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Modem Status Register Enhanced Feature Register Receiver Holding Register Transmitter Holding Register Transmission Control Register Trigger Level Register Register reset functions Reset control RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET Reset state bits cleared set; other bits cleared bits cleared reset 00011101 (1Dh) bits cleared bits set; other bits cleared bits cleared; bits input signals bits cleared pointer logic cleared pointer logic cleared bits cleared bits cleared
Interrupt Identification Register RESET
Remark: Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, Xoff2 reset top-level reset signal RESET, that they hold their initialization values during reset. Table summarizes state registers after reset.
Table Signal RXRDY TXRDY Signal RESET functions Reset control RESET RESET RESET RESET RESET Reset state HIGH HIGH HIGH HIGH
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Product data sheet
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Philips Semiconductors
SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
Interrupts
SC68C752B interrupt generation prioritization (six prioritized levels interrupts) capability. Interrupt Enable Register (IER) enables each types interrupts signal response interrupt generation. also disable interrupt system clearing bits 0:3, 5:7. When interrupt generated, indicates that interrupt pending provides type interrupt through IIR[5:0]. Table summarizes interrupt control functions.
Table IIR[5:0] 000001 000110 Interrupt control functions Priority level None Interrupt type none receiver line status Interrupt source none errors occur characters FIFO Interrupt reset method none erroneous characters read from FIFO. read 001100 000100 time-out interrupt stale data FIFO DRDY (data ready) (FIFO disable) FIFO above trigger level (FIFO enable) 000010 interrupt (THR empty) (FIFO disable) FIFO passes above trigger level (FIFO enable) 000000 010000 100000 modem status Xoff interrupt CTS, MSR[3:0] receive Xoff character(s)/special character read receive character(s)/Read read write read read
change state from read active (LOW) inactive (HIGH)
important note that framing error, parity error, break conditions, LSR[7] generates interrupt. LSR[7] when there error anywhere FIFO, cleared only when there more errors remaining FIFO. LSR[4:2] always represent error status received character FIFO. Reading FIFO updates LSR[4:2] appropriate status character FIFO. FIFO empty, then LSR[4:2] zeros. Xoff interrupt, Xoff flow character detection caused interrupt, interrupt cleared flow character detection. special character detection caused interrupt, interrupt cleared read IIR.
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Product data sheet
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Philips Semiconductors
SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
6.5.1 Interrupt mode operation
interrupt mode IER[3:0] processor informed status receiver transmitter interrupt signal, IRQ. Therefore, necessary continuously poll Line Status Register (LSR) interrupt needs serviced. Figure shows interrupt mode operation.
PROCESSOR
002aab096
Interrupt mode operation
6.5.2 Polled mode operation
polled mode (IER[3:0] 0000) status receiver transmitter checked polling Line Status Register (LSR). This mode alternative FIFO interrupt mode operation where status receiver transmitter automatically known means interrupts sent CPU. Figure shows FIFO polled mode operation.
PROCESSOR
002aab097
FIFO polled mode operation
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Product data sheet
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Philips Semiconductors
SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
operation
There modes operation, mode mode selected FCR[3]. mode FIFO disable (FCR[0] occurs single character transfers. mode multi-character block) transfers managed relieve processor longer periods time.
6.6.1 Single transfers (DMA mode 0/FIFO disable)
Figure shows TXRDY RXRDY mode 0/FIFO disable.
TXRDY
RXRDY
wrptr
least location filled
rdptr
least location filled
TXRDY
RXRDY
wrptr
FIFO EMPTY
rdptr
FIFO EMPTY
002aaa232
TXRDY RXRDY mode 0/FIFO disable
6.6.1.1
Transmitter When empty, TXRDY signal becomes active. TXRDY will inactive after character been loaded into
6.6.1.2
Receiver RXRDY active when there least character FIFO. becomes inactive when receiver empty.
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Product data sheet
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SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
6.6.2 Block transfers (DMA mode
Figure shows TXRDY RXRDY mode
wrptr
trigger level TXRDY rdptr
RXRDY least location filled
FIFO full trigger level wrptr TXRDY
RXRDY
rdptr
FIFO EMPTY
002aaa234
TXRDY RXRDY mode
6.6.2.1
Transmitter TXRDY active when there trigger level number spaces available. becomes inactive when FIFO full.
6.6.2.2
Receiver RXRDY becomes active when trigger level been reached, when time-out interrupt occurs. will inactive when FIFO empty error FIFO flagged LSR[7].
Sleep mode
Sleep mode enhanced feature SC68C752B UART. enabled when EFR[4], enhanced functions bit, when IER[4] set. Sleep mode entered when:
serial data input line, idle (see Section "Break time-out
conditions").
FIFO shift register empty. There interrupts pending except time-out interrupts.
Remark: Sleep mode will entered there data FIFO. Sleep mode, UART clock baud rate clock stopped. Since most registers clocked using these clocks, power consumption greatly reduced. UART will wake when change detected line, when there change state modem input pins, data written FIFO. Remark: Writing divisor latches, DLH, baud clock, must done during Sleep mode. Therefore, advisable disable Sleep mode using IER[4] before writing DLH.
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Product data sheet
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SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
Break time-out conditions
idle condition detected when receiver line, been HIGH character time. receiver line sampled midway through each bit. When break condition occurs, line pulled LOW. break condition activated setting LCR[6].
Programmable baud rate generator
SC68C752B UART contains programmable baud generator that takes clock input divides divisor range between (216 additional divide-by-4 prescaler also available selected MCR[7], shown Figure output frequency baud rate generator baud rate. formula divisor XTAL1 crystal input frequency prescaler divisor desired baud rate Where: prescaler when MCR[7] after reset (divide-by-1 clock selected) prescaler when MCR[7] after reset (divide-by-4 clock selected). Remark: default value prescaler after reset divide-by-1. Figure shows internal prescaler baud rate generator circuitry.
PRESCALER LOGIC (DIVIDE-BY-1) XTAL1 XTAL2 INTERNAL OSCILLATOR LOGIC
MCR[7] internal baud rate clock transmitter receiver
input clock reference clock MCR[7]
BAUD RATE GENERATOR LOGIC
PRESCALER LOGIC (DIVIDE-BY-4)
002aaa233
Prescaler baud rate generator block diagram
must written order program baud rate. least significant most significant byte baud rate divisor. both zero, UART effectively disabled, baud clock will generated. Remark: programmable baud rate generator provided select both transmit receive clock rates. Table Table show baud rate divisor correlation crystal with frequency 1.8432 3.072 MHz, respectively. Figure shows crystal clock circuit reference.
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Product data sheet
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Philips Semiconductors
SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
Baud rates using 1.8432 crystal Divisor used generate clock 2304 1536 1047 Baud rates using 3.072 crystal Divisor used generate clock 2304 2560 1745 1428 1280 1.23 0.628 0.312 0.026 0.034 Percent error difference between desired actual 2.86 0.69 0.026 0.058 Percent error difference between desired actual
Table
Desired baud rate 134.5 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 Table
Desired baud rate 134.5 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400
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Product data sheet
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Philips Semiconductors
SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
XTAL1
XTAL2
XTAL1
XTAL2
1.8432
1.8432
002aaa870
Crystal oscillator connections
Register descriptions
Each register selected using address lines some cases, bits from other registers. programming combinations register selection shown Table
Table
Register read/write properties Read mode Receive Holding Register (RHR) Interrupt Enable Register (IER) Interrupt Identification Register (IIR) Line Control Register (LCR) Modem Control Register (MCR) Line Status Register (LSR) Modem Status Register (MSR) ScratchPad Register (SPR) Divisor Latch (DLL) Divisor Latch Xon1 word Xon2 word Xoff1 word Xoff2 word Trigger Level Register (TLR) FIFO ready register (DLH) Enhanced Feature Register (EFR) scratchpad register divisor latch divisor latch enhanced feature register Xon1 word Xon2 word Xoff1 word Xoff2 word trigger level register Write mode Transmit Holding Register (THR) interrupt enable register FIFO Control Register (FCR) line control register modem control register
Transmission Control Register (TCR) transmission control register
MCR[7] only modified when EFR[4] set. Accessed combination address pins register bits. Accessible only when LCR[7] logic Accessible only when 10111111 (xBF). Accessible only when EFR[4] MCR[6] that EFR[4] MCR[6] read/write enables. Accessible only when MCR[2] loop-back disabled (MCR[4]
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Product data sheet
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SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
Table lists describes SC68C752B internal registers.
Table SC68C752B internal registers Read/ Write
Register General register
0/Xoff
0/RTS 0/CTS interrupt interrupt enable enable trigger level (MSB) FCR[0] trigger level (LSB) FCR[0]
Sleep modem mode status interrupt 0/TX trigger level (LSB) 0/Xoff mode select interrupt priority parity enable
receive line status empty interrupt interrupt FIFO reset
data available interrupt
0/TX trigger level (MSB) 0/CTS,
FIFO FIFO reset enable
interrupt priority
interrupt priority
interrupt status word length
DLAB
break control
parity parity type select
number word stop bits length FIFO ready enable parity error
clock
0/Xon enable
0/enable OPA/ loop-back control break interrupt FIFO status framing error
0/error FIFO empty empty FIFO status
overrun error
data receiver
FIFO
FIFO FIFO status status software flow control software flow control
Special register Auto Auto software Special Enable character enhanced flow detect functions control software flow control
Enhanced register
Xon1 Xon2 Xoff1 Xoff2
These registers accessible only when LCR[7] This only modified register EFR[4] enabled, that enhanced functions enabled. Special Register accessible only when LCR[7] logic
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Product data sheet
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Philips Semiconductors
SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
Enhanced Feature Register; Xon1/Xon2 Xoff1/Xoff2 accessible only when `BFh'.
Remark: Refer notes under Table more register access information.
Receiver Holding Register (RHR)
receiver section consists Receiver Holding Register (RHR) Receiver Shift Register (RSR). actually 64-byte FIFO. receives serial data from terminal. data converted parallel data moved RHR. receiver section controlled line control register. FIFO disabled, location zero FIFO used store characters. Remark: this case, characters overwritten overflow occurs. overflow occurs, characters lost. also stores error status bits associated with each character.
Transmit Holding Register (THR)
transmitter section consists Transmit Holding Register (THR) Transmit Shift Register (TSR). actually 64-byte FIFO. receives data shifts into TSR, where converted serial data moved terminal. FIFO disabled, FIFO still used store byte. Characters lost overflow occurs.
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Product data sheet
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SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
FIFO Control Register (FCR)
This write-only register that used enabling FIFOs, clearing FIFOs, setting transmitter receiver trigger levels, selecting type signalling. Table shows FIFO Control Register settings.
Table FIFO Control Register bits description Description
Symbol
FCR[7] (MSB), RCVR trigger. Sets trigger level FIFO. FCR[6] (LSB) characters characters characters characters
FCR[5] (MSB), trigger. Sets trigger level FIFO. FCR[4] (LSB) spaces spaces spaces spaces FCR[5:4] only modified enabled when EFR[4] set. This because transmit trigger level regarded enhanced function.
FCR[3]
mode select. logic mode logic mode
FCR[2]
Reset FIFO. logic FIFO transmit reset (normal default condition) logic Clears contents transmit FIFO resets FIFO counter logic (the transmit shift register cleared altered). This will return logic after clearing FIFO.
FCR[1]
Reset FIFO. logic FIFO receive reset (normal default condition) logic Clears contents receive FIFO resets FIFO counter logic (the receive shift register cleared altered). This will return logic after clearing FIFO.
FCR[0]
FIFO enable. logic disable transmit receive FIFO (normal default condition) logic enable transmit receive FIFO
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Line Control Register (LCR)
This register controls data communication format. word length, number stop bits, parity type selected writing appropriate bits LCR. Table shows line control register settings.
Table Line Control Register bits description Description Divisor latch enable. logic divisor latch disabled (normal default condition) logic divisor latch enabled LCR[6] Break control bit. When enabled, Break control causes break condition transmitted (the output forced logic state). This condition exists until disabled setting LCR[6] logic logic break condition (normal default condition) logic forces transmitter output (TX) logic alert communication terminal line break condition LCR[5] parity. LCR[5] selects forced parity format LCR[3] logic parity forced (normal default condition) LCR[5] logic LCR[4] logic parity forced logical transmit receive data. LCR[5] logic LCR[4] logic parity forced logical transmit receive data. LCR[4] Parity type select. logic parity generated LCR[3] logic even parity generated LCR[3] LCR[3] Parity enable. logic parity (normal default condition). logic parity generated during transmission receiver checks received parity. LCR[2] Number stop bits. Specifies number stop bits. stop (word length stop bits (word length stop bits (word length LCR[1:0] Word length bits These bits specify word length transmitted received. bits bits bits bits
Symbol LCR[7]
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Line Status Register (LSR)
Table shows Line Status Register settings.
Table Line Status Register bits description Description FIFO data error. logic error (normal default condition) logic least parity error, framing error, break indication receiver FIFO. This cleared when more errors present FIFO. LSR[6] empty. This Transmit Empty indicator. logic transmitter hold shift registers empty logic transmitter hold shift registers empty LSR[5] empty. This Transmit Holding Register Empty indicator. logic Transmit Hold Register empty logic Transmit Hold Register empty. processor load bytes data into FIFO enabled. LSR[4] Break interrupt. logic break condition (normal default condition) logic break condition occurred associated byte that character time frame. LSR[3] Framing error. logic framing error data being read from FIFO (normal default condition) logic Framing error occurred data being read from FIFO, that received data have valid stop bit. LSR[2] Parity error. logic parity error (normal default condition) logic parity error data being read from FIFO LSR[1] Overrun error. logic overrun error (normal default condition) logic overrun error occurred LSR[0] Data receiver. logic data receive FIFO (normal default condition) logic least character FIFO
Symbol LSR[7]
When read, LSR[4:2] reflect error bits (BI, character FIFO (next character read). LSR[4:2] registers physically exist, data read from FIFO output directly onto output data bus, D[4:2], when read. Therefore, errors character identified reading then reading RHR. LSR[7] when there error anywhere FIFO, cleared only when there more errors remaining FIFO. Reading does cause increment FIFO read pointer. FIFO read pointer incremented reading RHR.
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Remark: three error bits (parity, framing, break) updated correctly first read when input clock (XTAL1) running faster than MHz. However, second read always correct. strongly recommended that when using this device with clock faster than MHz, that read twice only second read used decision making. other bits correct reads.
Modem Control Register (MCR)
controls interface with mode, data set, peripheral device that emulating modem. Table shows modem control register settings.
Table Modem Control Register bits description Symbol MCR[7]
Description Clock select. logic divide-by-1 clock input logic divide-by-4 clock input
MCR[6]
enable. logic action. logic enable access registers
MCR[5]
Any. logic disable function logic enable function
MCR[4]
Enable loop-back. logic normal operating mode logic Enable local loop-back mode (internal). this mode MCR[3:0] signals looped back into MSR[7:4] output looped back input internally.
MCR[3]
OPA/OPB control. logic forces OPA/OPB output HIGH state logic forces OPA/OPB output state. loop-back mode, controls MSR[7].
MCR[2]
FIFO Ready enable. logic Disable FIFO register logic Enable FIFO register. loop-back mode, controls MSR[6].
MCR[1]
logic force output inactive (HIGH) logic force output active (LOW). loop-back mode, controls MSR[4]. Auto-RTS enabled, output controlled hardware flow control.
MCR[0]
logic force output inactive (HIGH) logic force output active (LOW). loop-back mode, controls MSR[5].
MCR[7:5] only modified when EFR[4] set, that EFR[4] write enable.
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Modem Status Register (MSR)
This 8-bit register provides information about current state control lines from mode, data set, peripheral device processor. also indicates when control input from modem changes state. Table shows modem status register settings channel.
Table Modem Status Register bits description Description (active HIGH, logical This complement input during normal mode. During internal loop-back mode, equivalent MCR[3]. (active HIGH, logical This complement input during normal mode. During internal loop-back mode, equivalent MCR[2]. (active HIGH, logical This complement input during normal mode. During internal loop-back mode, equivalent MCR[0]. (active HIGH, logical This complement input during normal mode. During internal loop-back mode, equivalent MCR[1]. Indicates that input MCR[3] loop-back mode) changed state. Cleared read. Indicates that input MCR[2] loop-back mode) changed state from HIGH. Cleared read. DSR. Indicates that input MCR[0] loop-back mode) changed state. Cleared read. CTS. Indicates that input MCR[1] loop-back mode) changed state. Cleared read.
Symbol MSR[7] MSR[6] MSR[5] MSR[4]
MSR[3] MSR[2] MSR[1] MSR[0]
primary inputs CTS, active LOW, their registered equivalents loop-back) registers active HIGH.
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Interrupt Enable Register (IER)
Interrupt Enable Register (IER) enables each types interrupt, receiver error, interrupt, interrupt, Xoff received, CTS/RTS change state from HIGH. output signal activated response interrupt generation. Table shows interrupt enable register settings.
Table Interrupt Enable Register bits description Description interrupt enable. logic disable interrupt (normal default condition) logic enable interrupt IER[6] interrupt enable. logic disable interrupt (normal default condition) logic enable interrupt IER[5] Xoff interrupt. logic disable Xoff interrupt (normal default condition) logic enable Xoff interrupt IER[4] Sleep mode. logic disable Sleep mode (normal default condition) logic enable Sleep mode. Section "Sleep mode" details. IER[3] Modem Status Interrupt. logic disable modem status register interrupt (normal default condition) logic enable modem status register interrupt IER[2] Receive Line Status interrupt. logic disable receiver line status interrupt (normal default condition) logic enable receiver line status interrupt IER[1] Transmit Holding Register interrupt. logic disable interrupt (normal default condition) logic enable interrupt IER[0] Receive Holding Register interrupt. logic disable interrupt (normal default condition) logic enable interrupt
IER[7:4] only modified EFR[4] set, that EFR[4] write enable. Re-enabling IER[1] will cause interrupt below threshold.
Symbol IER[7]
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Interrupt Identification Register (IIR)
read-only 8-bit register which provides source interrupt prioritized manner. Table shows interrupt identification register settings.
Table Interrupt Identification Register bits description Description Mirror contents FCR[0]. RTS/CTS LOW-to-HIGH change state Xoff/Special character been detected 3-bit encoded interrupt. Table Interrupt status. logic interrupt pending logic interrupt pending
Symbol IIR[7:6] IIR[5] IIR[4] IIR[3:1] IIR[0]
interrupt priority list shown Table
Table Priority level Interrupt priority list IIR[5] IIR[4] IIR[3] IIR[2] IIR[1] IIR[0] Source interrupt receiver line status error receiver time-out interrupt interrupt interrupt modem interrupt received Xoff signal/ special character CTS, change state from active (LOW) inactive (HIGH)
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7.10 Enhanced Feature Register (EFR)
This 8-bit register enables disables enhanced features UART. Table shows enhanced feature register settings.
Table Enhanced Feature Register bits description Description flow control enable. logic flow control disabled (normal default condition) logic flow control enabled. Transmission will stop when HIGH signal detected pin. EFR[6] flow control enable. logic flow control disabled (normal default condition) logic flow control enabled. goes HIGH when receiver FIFO HALT trigger level TCR[3:0] reached, goes when receiver FIFO RESUME transmission trigger level TCR[7:4] reached. EFR[5] Special character detect. logic special character detect disabled (normal default condition) logic special character detect enabled. Received data compared with Xoff-2 data. match occurs, received data transferred FIFO IIR[4] logical indicate special character been detected. EFR[4] Enhanced functions enable bit. logic disables enhanced functions writing IER[7:4], FCR[5:4], MCR[7:5] logic enables enhanced function IER[7:4], FCR[5:4], MCR[7:5] modified, that this therefore write enable EFR[3:0] Combinations software flow control selected programming these bits. Table "Software flow control options (EFR[0:3])" page
Symbol EFR[7]
7.11 Divisor latches (DLL, DLH)
These 8-bit registers which store 16-bit divisor generation baud clock baud rate generator. stores most significant part divisor. stores least significant part divisor. Note that only written before Sleep mode enabled, that before IER[4] set.
7.12 Transmission Control Register (TCR)
This 8-bit register used store FIFO threshold levels stop/start transmission during hardware/software flow control. Table shows transmission control register settings.
Table Transmission Control Register bits description Description FIFO trigger level resume transmission bytes bytes). FIFO trigger level halt transmission bytes bytes).
Symbol TCR[7:4] TCR[3:0]
trigger levels available from bytes bytes with granularity four.
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Remark: only written when EFR[4] MCR[6] programmer must program such that TCR[3:0] TCR[7:4]. There built-in hardware check make sure this condition met. Also, must programmed with this condition before Auto-RTS software flow control enabled avoid spurious operation device.
7.13 Trigger Level Register (TLR)
This 8-bit register pulsed store transmit received FIFO trigger levels used interrupt generation. Trigger levels from programmed with granularity Table shows trigger level register settings.
Table Trigger Level Register bits description Description FIFO trigger levels 60), number characters available. FIFO trigger levels 60), number spaces available.
Symbol TLR[7:4] TLR[3:0]
Remark: only written when EFR[4] MCR[6] TLR[3:0] TLR[7:4] logical selectable trigger levels FIFO control register (FCR) used transmit receive FIFO trigger levels. Trigger levels from bytes bytes available with granularity four. should programmed N/4, where desired trigger level. When trigger level setting zero, SC68C752B uses trigger level setting defined FCR. non-zero trigger level value, trigger level defined discarded. This applies both transmit FIFO receive FIFO trigger level setting. When used trigger level control, FCR[7:6] should left default state, that `00'.
7.14 FIFO ready register
FIFO ready register provides real-time status transmit receive FIFOs both channels.
Table FIFO ready register bits description Description unused; always FIFO status; related FIFO status; related unused; always FIFO status; related FIFO status; related
Symbol FIFO Rdy[7:6] FIFO Rdy[5] FIFO Rdy[4] FIFO Rdy[3:2] FIFO Rdy[1] FIFO Rdy[0]
FIFO register read-only register that accessed when UARTs selected MCR[2] (FIFO Enable) logic loop-back disabled. address 111.
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Programmer's guide
base registers that used during high-speed data transfer have straightforward access method. extended function registers require special access bits decoded along with address lines. following guide will help with programming these registers. Note that descriptions below individual register access. Some streamlining through interleaving obtained when programming registers.
Table Command baud rate VALUE1, VALUE2 Register programming guide Actions read (03), save temp (03) (00) VALUE1 (01) VALUE2 (03) temp Xoff-1, Xon-1 VALUE1, VALUE2 read (03), save temp (03) Xoff-1 (06) VALUE1 Xon-1 (04) VALUE2 (03) temp Xoff-2, Xon-2 VALUE1, VALUE2 read (03), save temp (03) Xoff-2 (07) VALUE1 Xon-2 (05) VALUE2 (03) temp software flow control mode VALUE read (03), save temp (03) (02) VALUE (03) temp flow control threshold VALUE read (03), save temp1 (03) read (02), save temp2 (02) temp2 (03) read (04), save temp3 (04) temp3 (06) VALUE (04) temp3 (03) (02) temp2 (03) temp1
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Register programming guide .continued Actions read (03), save temp1 (03) read (02), save temp2 (02) temp2 (03) read (04), save temp3 (04) temp3 (07) VALUE (04) temp3 (03) (02) temp2 (03) temp1
Table Command
FIFO FIFO thresholds VALUE
Read FIFO register
read (04), save temp1 temp2 temp1
(04) temp2 read (07), save temp2 pass temp2 back host (04) temp1 prescaler value divide-by-1 read (03), save temp1 (03) read (02), save temp2 (02) temp2 (03) read (04), save temp3 (04) temp3 (03) (02) temp2 (03) temp1 prescaler value divide-by-4 read (03), save temp1 (03) read (02), save temp2 (02) temp2 (03) read (04), save temp3 (04) temp3 (03) (02) temp2 (03) temp1
sign here means bit-AND.
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Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134). Symbol Tamb Tstg
Parameter supply voltage input voltage output voltage operating ambient temperature storage temperature
Conditions
-0.3 -0.3
+150
Unit
free-air
Stresses beyond those listed under Table "Limiting values" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under recommended operating conditions implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability.
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Static characteristics
Table Static characteristics Tolerance Symbol Parameter supply voltage input voltage HIGH-level input voltage LOW-level input voltage output voltage HIGH-level output voltage -800 -400 LOW-level output voltage Tamb input capacitance operating ambient temperature junction temperature input clock frequency clock duty cycle supply current
Conditions 1.85 1.85
0.65
Unit
f(i)XTAL1
+125
+125
ICC(sleep) sleep current
Meets levels, VIL(min) VIH(max) non-hysteresis inputs. Applies external output buffers. These parameters apply D[7:0]. These parameters apply DTRA, DTRB, RTSA, RTSB, RXRDYA, RXRDYB, TXRDYA, TXRDYB, TXA, TXB. Except XTAL2, typical. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature customer responsible verifying junction temperature. Applies external clock; crystal oscillator max. MHz. Measurement condition, normal operation other than Sleep mode: Tamb Full duplex serial activity serial (UART) channels clock frequency specified recommended operating conditions with divisor
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Dynamic characteristics
Table Dynamic characteristics Tamb tolerance unless specified otherwise. Symbol td10 td11 td12 td13 td14 td15 td16 td17 td18 t1w, fXTAL t(RESET) tsu1 tsu2
Parameter chip select read cycle delay delay from data data disable time write cycle delay delay from WRITE output delay interrupt from modem input delay reset interrupt from READ delay from stop interrupt delay from READ reset interrupt delay from start interrupt delay from WRITE transmit start delay from WRITE reset interrupt delay from stop RXRDY delay from READ reset RXRDY delay from WRITE TXRDY delay from start reset TXRDY hold time from data hold time address hold time clock cycle period clock speed RESET pulse width address setup time data setup time strobe width
Conditions
1TRCLK
Unit
1TRCLK
load load load load load load load
8TRCLK
24TRCLK 1TRCLK
8TRCLK
24TRCLK 1TRCLK
16TRCLK
16TRCLK
RCLK internal signal derived from Divisor Latch (DLL) Divisor Latch (DLM) divisor latches. Applies external clock; crystal oscillator MHz. Maximum frequency
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11.1 Timing diagrams
tsu1
valid address
valid address
valid data
valid data
002aab087
General read timing
tsu1
valid address
valid address
tsu2
valid data
valid data
002aab088
General write timing
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(write)(1)
active
RTSA, RTSB DTRA, DTRB
change state
change state
CDA, CTSA, CTSB DSRA, DSRB
change state
change state
active
active
active
(read)(2)
active
active
active
RIA,
change state
002aab089
timing during write cycle. Figure timing during read cycle. Figure
Modem input/output timing
EXTERNAL CLOCK
002aaa112
XTAL External clock timing
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Start
data bits data bits data bits data bits
parity
Stop
next data Start
RXA,
td10 active td11
(read)
active
baud rate clock
002aab090
Receive timing
Start
data bits
parity
Stop
next data Start
RXA,
td15 RXRDYA, RXRDYB active data ready td16 (read)
active
002aab091
Receive ready timing non-FIFO mode
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Start
data bits
parity
Stop
RXA,
first byte that reaches trigger level
td15 RXRDYA, RXRDYB active data ready td16 (read)
active
002aab092
Receive ready timing FIFO mode
Start
data bits data bits data bits data bits active ready
parity
Stop
next data Start
TXA,
td12 td13
td14 active
(write)
active
baud rate clock
002aab093
Transmit timing
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Start TXA,
data bits
parity
Stop
next data Start
(write)
active
byte
td18
td17 TXRDYA, TXRDYB active transmitter ready transmitter ready
002aab094
Transmit ready timing non-FIFO mode
start
data bits
parity
stop
TXA,
data bits data bits data bits (write) active td18 byte
td17 TXRDYA, TXRDYB trigger lead
002aab377
Transmit ready timing FIFO mode
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Package outline
LQFP48: plastic profile quad flat package; leads; body SOT313-2
detail
index
scale
DIMENSIONS original dimensions) UNIT max. 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 9.15 8.85 9.15 8.85 0.75 0.45 0.12 0.95 0.55 0.95 0.55
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT313-2 REFERENCES 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Package outline SOT313-2 (LQFP48)
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Soldering
13.1 Introduction soldering surface mount packages
This text gives very brief insight complex technology. more in-depth account soldering found Data Handbook IC26; Integrated Circuit Packages (document order number 9398 90011). There soldering method that ideal surface mount packages. Wave soldering still used certain surface mount ICs, suitable fine pitch SMDs. these situations reflow soldering recommended.
13.2 Reflow soldering
Reflow soldering requires solder paste suspension fine solder particles, flux binding agent) applied printed-circuit board screen printing, stencilling pressure-syringe dispensing before package placement. Driven legislation environmental forces worldwide lead-free solder pastes increasing. Several methods exist reflowing; example, convection convection/infrared heating conveyor type oven. Throughput times (preheating, soldering cooling) vary between seconds seconds depending heating method. Typical reflow peak temperatures range from depending solder paste material. top-surface temperature packages should preferably kept:
below (SnPb process) below (Pb-free process)
BGA, HTSSON.T SSOP.T packages packages with thickness packages with thickness volume called thick/large packages.
below (SnPb process) below (Pb-free process) packages with
thickness volume called small/thin packages. Moisture sensitivity precautions, indicated packing, must respected times.
13.3 Wave soldering
Conventional single wave soldering recommended surface mount devices (SMDs) printed-circuit boards with high component density, solder bridging non-wetting present major problems. overcome these problems double-wave soldering method specifically developed. wave soldering used following conditions must observed optimal results:
double-wave soldering method comprising turbulent wave with high upward
pressure followed smooth laminar wave.
packages with leads sides pitch (e):
larger than equal 1.27 footprint longitudinal axis preferred parallel transport direction printed-circuit board;
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smaller than 1.27 footprint longitudinal axis must parallel transport direction printed-circuit board. footprint must incorporate solder thieves downstream end.
packages with leads four sides, footprint must placed angle
transport direction printed-circuit board. footprint must incorporate solder thieves downstream side corners. During placement before soldering, package must fixed with droplet adhesive. adhesive applied screen printing, transfer syringe dispensing. package soldered after adhesive cured. Typical dwell time leads wave ranges from seconds seconds depending solder material applied, SnPb Pb-free respectively. mildly-activated flux will eliminate need removal corrosive residues most applications.
13.4 Manual soldering
component first soldering diagonally-opposite leads. voltage less) soldering iron applied flat part lead. Contact time must limited seconds When using dedicated tool, other leads soldered operation within seconds seconds between
13.5 Package related soldering information
Table Package BGA, HTSSON.T [3], LBGA, LFBGA, SQFP, SSOP.T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, PLCC [5], LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN.L [8], PMFP [9], WQCCN.L
Suitability surface mount packages wave reflow soldering methods Soldering method Wave suitable suitable Reflow suitable suitable
suitable recommended recommended
suitable suitable suitable suitable
suitable
more detailed information packages refer (LF)BGA Application Note (AN01026); order copy from your Philips Semiconductors sales office. surface mount (SMD) packages moisture sensitive. Depending upon moisture content, maximum temperature (with respect time) body size package, there risk that internal external package cracks occur vaporization moisture them (the called popcorn effect). details, refer Drypack information Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages extremely sensitive reflow soldering conditions must account processed through more than soldering cycle subjected infrared reflow soldering with peak temperature exceeding measured atmosphere reflow oven. package body peak temperature must kept possible.
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These packages suitable wave soldering. versions with heatsink bottom side, solder cannot penetrate between printed-circuit board heatsink. versions with heatsink side, solder might deposited heatsink surface. wave soldering considered, then package must placed angle solder wave direction. package footprint must incorporate solder thieves downstream side corners. Wave soldering suitable LQFP, TQFP packages with pitch larger than definitely suitable packages with pitch equal smaller than 0.65 Wave soldering suitable SSOP, TSSOP, VSSOP packages with pitch equal larger than 0.65 definitely suitable packages with pitch equal smaller than Image sensor packages principle should soldered. They mounted sockets delivered pre-mounted flex foil. However, image sensor package mounted client flex foil using soldering process. appropriate soldering profile provided request. soldering manual soldering suitable PMFP packages.
Abbreviations
Table Acronym FIFO UART Abbreviations Description Central Processing Unit Direct Memory Access First In/First Least Significant Most Significant Universal Asynchronous Receiver Transmitter
Revision history
Table Revision history Release date 20050428 Data sheet status Product data sheet Change notice Doc. number 9397 14963 Supersedes SC68C752B_1 Document SC68C752B_2 Modifications:
Added `and Motorola interface' descriptive title first page. Section "Features" page first bullet: added `with Motorola interface second bullet re-written
SC68C752B_1
Added Section "Trademarks" page Product data sheet 9397 13857
20050329
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Data sheet status
Level Data sheet status Objective data Preliminary data Product status Development Qualification Definition This data sheet contains data from objective specification product development. Philips Semiconductors reserves right change specification manner without notice. This data sheet contains data from preliminary specification. Supplementary data will published later date. Philips Semiconductors reserves right change specification without notice, order improve design supply best possible product. This data sheet contains data from product specification. Philips Semiconductors reserves right make changes time order improve design, manufacturing supply. Relevant changes will communicated Customer Product/Process Change Notification (CPCN).
Product data
Production
Please consult most recently issued data sheet before initiating completing design. product status device(s) described this data sheet have changed since this data sheet published. latest information available Internet data sheets describing multiple type numbers, highest-level product status determines data sheet status.
Definitions
Short-form specification data short-form specification extracted from full data sheet with same type number title. detailed information relevant data sheet data handbook. Limiting values definition Limiting values given accordance with Absolute Maximum Rating System (IEC 60134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Applications that described herein these products illustrative purposes only. Philips Semiconductors make representation warranty that such applications will suitable specified without further testing modification.
customers using selling these products such applications their risk agree fully indemnify Philips Semiconductors damages resulting from such application. Right make changes Philips Semiconductors reserves right make changes products including circuits, standard cells, and/or software described contained herein order improve design and/or performance. When product full production (status `Production'), relevant changes will communicated Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes responsibility liability these products, conveys license title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified.
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Disclaimers
Life support These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. Philips Semiconductors
Contact information
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9397 14963
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C752B
dual UART, Mbit/s (max.), with 64-byte FIFOs
Contents
6.2.1 6.2.2 6.3.1 6.3.2 6.3.3 6.3.3.1 6.5.1 6.5.2 6.6.1 6.6.1.1 6.6.1.2 6.6.2 6.6.2.1 6.6.2.2 7.10 7.11 7.12 7.13 7.14 General description Features Ordering information Block diagram Pinning information Pinning description Functional description Trigger levels. Hardware flow control Auto-RTS Auto-CTS Software flow control Software flow control example Assumptions Reset Interrupts Interrupt mode operation Polled mode operation operation Single transfers (DMA mode FIFO disable) Transmitter Receiver Block transfers (DMA mode Transmitter Receiver Sleep mode. Break time-out conditions Programmable baud rate generator Register descriptions Receiver Holding Register (RHR). Transmit Holding Register (THR) FIFO Control Register (FCR) Line Control Register (LCR) Line Status Register (LSR) Modem Control Register (MCR) Modem Status Register (MSR). Interrupt Enable Register (IER) Interrupt Identification Register (IIR). Enhanced Feature Register (EFR) Divisor latches (DLL, DLH) Transmission Control Register (TCR) Trigger Level Register (TLR). FIFO ready register. 11.1 13.1 13.2 13.3 13.4 13.5 Programmer's guide Limiting values Static characteristics Dynamic characteristics Timing diagrams. Package outline Soldering Introduction soldering surface mount packages Reflow soldering. Wave soldering. Manual soldering Package related soldering information Abbreviations Revision history Data sheet status. Definitions Disclaimers Trademarks Contact information
Koninklijke Philips Electronics N.V. 2005
rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent- other industrial intellectual property rights. Date release: April 2005 Document number: 9397 14963
Published Netherlands

dual UART, Mbit/s (max.), with 64-byte FIFOs Motorola interface R

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