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SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs Motorola interface
Rev. April 2005 Product data sheet
SC68C2550B channel Universal Asynchronous Receiver Transmitter (UART) used serial data communications. principal function convert parallel data into serial data vice versa. UART handle serial data rates Mbit/s. SC68C2550B provides enhanced UART functions with 16-byte FIFOs, modem control interface, mode data transfer. mode data transfer controlled FIFO trigger levels TXRDY RXRDY signals. On-board status registers provide user with error indications operational status. System interrupts modem control features tailored software meet specific user requirements. internal loop-back capability allows on-board diagnostics. Independent programmable baud rate generators provided select transmit receive baud rates. SC68C2550B operates industrial temperature range, available plastic LQFP48 package.
Features
channel UART with Motorola interface operation Industrial temperature range Mbit/s data rate Mbit/s 16-byte transmit FIFO reduce bandwidth requirement external 16-byte receive FIFO with error flags reduce bandwidth requirement external Independent transmit receive UART control Four selectable Receive FIFO interrupt trigger levels Software selectable baud rate generator Standard asynchronous error framing bits (Start, Stop, Parity Overrun Break) Transmit, Receive, Line Status, Data interrupts independently controlled Fully programmable character formatting: 8-bit characters Even, odd, no-parity formats 11/2, 2-stop Baud generation Mbit/s) False start-bit detection Complete status reporting capabilities 3-state output drive capabilities bi-directional data control
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Line break generation detection Internal diagnostic capabilities: Loop-back controls communications link fault isolation Prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR,
Ordering information
Table Ordering information Package Name SC68C2550BIB48 LQFP48 Description plastic profile quad flat package; leads; body Version SOT313-2 Type number
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Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Block diagram
SC68C2550B
TRANSMIT FIFO REGISTER RESET DATA CONTROL LOGIC TRANSMIT SHIFT REGISTER
TXA,
INTERCONNECT LINES CONTROL SIGNALS
RECEIVE FIFO REGISTER
RECEIVE SHIFT REGISTER
RXA,
REGISTER SELECT LOGIC
DTRA, DTRB RTSA, RTSB OP2A, OP2B MODEM CONTROL LOGIC
TXRDYA, TXRDYB RXRDYA, RXRDYB
INTERRUPT CONTROL LOGIC
CLOCK BAUD RATE GENERATOR
CTSA, CTSB RIA, CDA, DSRA, DSRB
002aab334
XTAL1
XTAL2
Block diagram SC68C2550B
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Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Pinning information
Pinning
TXRDYA
DSRA
CTSA
TXRDYB OP2B
n.c. RESET DTRB DTRA RTSA OP2A RXRDYA n.c. n.c.
002aab335
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SC68C2550BIB48
n.c. XTAL1 XTAL2 RXRDYB DSRB RTSB CTSB
configuration LQFP48
description
Table Symbol description Type Description Address select bit. Internal register address selection. Address select bit. Internal register address selection. Address select bit. Internal register address selection. Address used select Channel Channel logic selects Channel logic HIGH selects Channel (See Table Chip Select (active LOW). This enables data transfers between user SC68C2550B channel(s) addressed. Individual UART sections addressed Table Data (bi-directional). These pins 8-bit, 3-state data transferring information from controlling CPU. least significant first data transmit receive serial data stream. Signal power ground. Interrupt Request. Interrupts from UART channels wire-ORed internally function single interrupt. This transitions logic enabled interrupt enable register) whenever UART channel(s) requires service. Individual channel interrupt status determined addressing each channel through associated internal register, using external pull-up resistor must connected between this VCC.
Rev. April 2005
9397 14941
Product data sheet
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Table Symbol
description .continued Type Description logic this will transfer contents data (D[0:7]) from external internal register that defined address bits A[0:2]. logic HIGH this will load contents internal register defined address bits A[0:2] SC68C2550B data (D[0:7]) access external CPU. Output (user-defined). This function associated with individual channels state these pins defined user through software settings MCR[3]. OP2A/OP2B logic when MCR[3] logic OP2A/OP2B logic when MCR[3] logic output these pins HIGH after reset. Reset (active LOW). logic this will reset internal registers outputs. UART transmitter output receiver input will disabled during reset time. (See Section 7.10 "SC68C2550B external reset condition" initialization details.) Receive Ready (active LOW). This function associated with PLCC44 LQFP48 packages only. This function provides FIFO/RHR status individual receive channels (A-B). RXRDYn primarily intended monitoring mode transfers receive data FIFOs. logic indicates there receive data read/upload, that receive ready status with more characters available FIFO/RHR. This logic when FIFO/RHR empty when programmed trigger level been reached. This signal also used single mode transfers (DMA mode Transmit Ready (active LOW). This function associated with PLCC44 LQFP48 packages only. These outputs provide FIFO/THR status individual transmit channels (A-B). TXRDYn primarily intended monitoring mode transfers transmit data FIFOs. individual channel's TXRDYA, TXRDYB buffer ready status indicated logic that lease location empty available FIFO THR. This goes logic (DMA mode when there more empty locations FIFO THR. This signal also used single mode transfers (DMA mode Power supply input Crystal external clock input. Functions crystal input external clock input. crystal connected between this XTAL2 form internal oscillator circuit. Alternatively, external clock connected this provide custom data rates. (See Section "Programmable baud rate generator".) Figure Output crystal oscillator buffered clock. (See also XTAL1.) Crystal oscillator output buffered clock output. Should left open external clock connected XTAL1. extended frequency operation, this should tied resistor. Carrier Detect (active LOW). These inputs associated with individual UART channels through logic this indicates that carrier been detected modem that channel. Clear Send (active LOW). These inputs associated with individual UART channels, through logic indicates modem data ready accept transmit data from SC68C2550B. Status tested reading MSR[4]. This effect UART's transmit receive operation. Data Ready (active LOW). These inputs associated with individual UART channels, through logic this indicates modem data powered-on ready data exchange with UART. This effect UART's transmit receive operation.
OP2A, OP2B
RESET
RXRDYA, RXRDYB
TXRDYA, TXRDYB
XTAL1
XTAL2
CDA, CTSA, CTSB
DSRA, DSRB
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Product data sheet
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Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Table Symbol DTRA, DTRB
description .continued Type Description Data Terminal REady (active LOW). These outputs associated with individual UART channels, through logic this indicates that SC68C2550B powered-on ready. This controlled modem control register. Writing logic MCR[0] will output logic enabling modem. This will logic after writing logic MCR[0], after reset. This effect UART's transmit receive operation. Ring Indicator (active LOW). These inputs associated with individual UART channels, through logic this indicates modem received ringing signal from telephone line. logic transition this input will generate interrupt. Request Send (active LOW). These outputs associated with individual UART channels, through logic indicates transmitter data ready waiting send. Writing logic modem control register MCR[1] will this logic indicating data available. After reset this will logic This effect UART's transmit receive operation. Receive data These inputs associated with individual serial channel data SC68C2550B receive input circuits, A-B. signal will logic during reset, idle data), when transmitter disabled. During local loop-back mode, input disabled data connected UART input, internally. Transmit data These outputs associated with individual serial transmit channel data from SC68C2550B. signal will logic during reset, idle data), when transmitter disabled. During local loop-back mode, output disabled data internally connected UART input. connected
RIA,
RTSA, RTSB
RXA,
TXA,
n.c.
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Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Functional description
SC68C2550B provides serial asynchronous receive data synchronization, parallel-to-serial serial-to-parallel data conversions both transmitter receiver sections. These functions necessary converting serial data stream into parallel data that required with digital data systems. Synchronization serial data stream accomplished adding start stop bits transmit data form data character (character orientated protocol). Data integrity insured attaching parity data character. parity checked receiver transmission errors. electronic circuitry provide these functions fairly complex, especially when manufactured single integrated silicon chip. SC68C2550B represents such integration with greatly enhanced features. SC68C2550B fabricated with advanced CMOS process. SC68C2550B upward solution that provides dual UART capability with bytes transmit receive FIFO memory. SC68C2550B designed work with high speed modems shared network environments that require fast data processing time. Increased performance realized SC68C2550B transmit receive FIFOs. This allows external processor handle more networking tasks within given time. example, ST16C2450 without receive FIFO, will require unloading microseconds (this example uses character length bits, including start/stop bits 115.2 kbit/s). This means external will have service receive FIFO less than every microseconds. However, with 16-byte FIFO SC68C2550B, data buffer will require unloading/loading 1.53 This increases service interval, giving external additional time other applications reducing overall UART interrupt servicing time. addition, four selectable receive FIFO trigger interrupt levels uniquely provided maximum data throughput performance especially when operating multi-channel environment. FIFO memory greatly reduces bandwidth requirement external controlling CPU, increases performance, reduces power consumption. SC68C2550B capable operation Mbit/s with clock. With crystal external clock input 7.3728 MHz, user select data rates 460.8 kbit/s. rich feature SC68C2550B available through internal registers. Selectable receive FIFO trigger levels, selectable baud rates, modem interface controls standard features.
UART functions
UART provides user with capability bi-directionally transfer information between external CPU, SC68C2550B package, external serial device. logic chip select (LOW HIGH) allows user configure, send data, and/or receive data UART channels Individual channel select functions shown Table
Table
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Channel selection using UART select none channel channel
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Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Internal registers
SC68C2550B provides sets internal registers consisting registers each monitoring controlling functions each channel UART. These registers shown Table UART registers function data holding registers (THR/RHR), interrupt status control registers (IER/ISR), FIFO control register (FCR), line status control registers (LCR/LSR), modem status control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), user accessible scratchpad register (SPR).
Table
Internal registers decoding Read mode Receive Holding Register Interrupt Enable Register Interrupt Status Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratchpad Register (DLL/DLM) Divisor Latch Divisor Latch Divisor Latch Divisor Latch Write mode Transmit Holding Register Interrupt Enable Register FIFO Control Register Line Control Register Modem Control Register Scratchpad Register
General register (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)
Baud rate register
These registers accessible only when LCR[7] logic These registers accessible only when LCR[7] logic
FIFO operation
byte transmit receive data FIFOs enabled FIFO Control Register (FCR) user receive trigger level FCR[7:6], transmit trigger level. receiver FIFO section includes time-out function ensure data delivered external CPU. interrupt generated whenever Receive Holding Register (RHR) been read following loading character receive trigger level been reached.
Table Flow control mechanism activation
Selected trigger level (characters)
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Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Hardware/software time-out interrupts
interrupts enabled IER[0-3]. Care must taken when handling these interrupts. Following reset, Interrupt Enable Register (IER) SC68C2550B will issue Transmit Holding Register interrupt. This interrupt must serviced prior continuing operations. register provides current singular highest priority interrupt only. condition exist where higher priority interrupt mask lower priority interrupt(s). Only after servicing higher pending interrupt will lower priority interrupt(s) reflected status register. Servicing interrupt without investigating further interrupt conditions result data errors. When interrupt conditions have same priority, important service these interrupts correctly. Receive Data Ready Receive Time-Out have same interrupt priority (when enabled IER[0]). receiver issues interrupt after number characters have reached programmed trigger level. this case, SC68C2550B FIFO hold more characters than programmed trigger level. Following removal data byte, user should re-check LSR[0] additional characters. Receive Time-Out will occur receive FIFO empty. time-out counter reset center each stop received each time receive holding register (RHR) read. actual time-out value character time, including data information length, start bit, parity bit, size stop bit, that times.
Programmable baud rate generator
SC68C2550B supports high speed modem technologies that have increased input data rates employing data compression schemes. example, 33.6 kbit/s modem that employs data compression require 115.2 kbit/s input data rate. 128.0 kbit/s ISDN modem that supports data compression need input data rate 460.8 kbit/s. SC68C2550B support standard data rate 921.6 kbit/s. single baud rate generator provided transmitter receiver, allowing independent TX/RX channel control. programmable Baud Rate Generator (BRG) capable operating with frequency MHz. obtain maximum data rate, necessary full rail swing clock input. SC68C2550B configured internal external clock operation. internal clock oscillator operation, industry standard microprocessor crystal connected externally between XTAL1 XTAL2 pins. Alternatively, external clock connected XTAL1 clock internal baud rate generator standard custom rates (see Table generator divides input clock divisor from (216 SC68C2550B divides basic external clock basic clock provides table rates support standard custom applications using same system design. rate table configured internal register functions. Customized baud rates achieved selecting proper divisor values sections baud rate generator. Programming baud rate generator registers (MSB) (LSB) provides user capability selecting desired final baud rate. example Table shows selectable baud rate table available when using 1.8432 external clock input.
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Product data sheet
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Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
XTAL1
XTAL2
1.8432
002aab325
Crystal oscillator connection Table Output baud rate 1200 2400 3600 4800 7200 9600 19.2 38.4 57.6 115.2 Baud rate generator programming table using 1.8432 clock Output clock divisor (decimal) 2304 1536 1047 Output clock divisor (HEX) program value (HEX) program value (HEX)
operation
SC68C2550B FIFO trigger level provides additional flexibility user block mode operation. LSR[6:5] provide indication when transmitter empty empty location(s). user optionally operate transmit receive FIFOs mode (FCR[3]). When transmit receive FIFOs enabled mode de-activated (DMA Mode SC68C2550B activates interrupt output each data transmit receive operation. When mode activated (DMA Mode user takes advantage block mode operation loading unloading FIFO block sequence determined receive trigger level transmit FIFO. this mode, SC68C2550B sets TXRDY RXRDY) output when characters transmit FIFO below characters receive FIFOs above receive trigger level.
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Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Loop-back mode
internal loop-back capability allows on-board diagnostics. Loop-back mode, normal modem interface pins disconnected reconfigured loop-back internally (see Figure MCR[3:0] register bits used controlling loop-back diagnostic testing. Loop-back mode, transmitter output (TX) receiver input (RX) disconnected from their associated interface pins, instead connected together internally. CTS, DSR, disconnected from their normal modem control inputs pins, instead connected internally RTS, DTR, MCR[3] (OP2) MCR[2] (OP1). Loop-back test data entered into transmit holding register user data interface, transmit UART serializes data passes serial data receive UART internal loop-back connection. receive UART converts serial data back into parallel data that then made available user data interface user optionally compares received data initial transmitted data verifying error-free operation UART TX/RX circuits. this mode, receiver transmitter interrupts fully operational. Modem Control Interrupts also operational.
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Product data sheet
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Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
SC68C2550B
TRANSMIT FIFO REGISTERS RESET DATA CONTROL LOGIC MCR[4] TRANSMIT SHIFT REGISTER
TXA,
INTERCONNECT LINES CONTROL SIGNALS
RECEIVE FIFO REGISTERS
RECEIVE SHIFT REGISTER
RXA,
REGISTER SELECT LOGIC
RTSA, RTSB
CTSA, CTSB DTRA, DTRB MODEM CONTROL LOGIC TXRDYA, TXRDYB RXRDYA, RXRDYB INTERRUPT CONTROL LOGIC CLOCK BAUD RATE GENERATOR
DSRA, DSRB (OP1A, OP1B)
RIA, (OP2A, OP2B)
CDA,
002aab336
XTAL1 XTAL2
Internal Loop-back mode diagram
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Product data sheet
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Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Register descriptions
Table details assigned functions SC68C2550B internal registers. assigned functions more fully defined Section through Section 7.10.
Table SC68C2550B internal registers Register Default transmit holding register interrupt RCVR FIFO reset priority receive holding register FIFOs enable status word length receive data ready
General Register
modem receive status line interrupt status interrupt mode select priority parity enable XMIT FIFO reset priority
RCVR trigger (MSB) FIFOs enabled divisor latch enable FIFO data error
RCVR trigger (LSB) FIFOs enabled
reserved
reserved
break parity even parity
stop bits word length (OP1) parity error overrun error
loop back control break interrupt framing error
empty empty
Special Register
value shown represents register's initialized value; n/a. Accessible only when LCR[7] logic Baud rate registers accessible only when LCR[7] logic
Transmit (THR) Receive (RHR) Holding Registers
serial transmitter section consists 8-bit Transmit Hold Register (THR) Transmit Shift Register (TSR). status provided Line Status Register (LSR). Writing transfers contents data UART THR, providing that empty. empty flag register will logic when transmitter empty when data transferred TSR. Note that write operation performed when empty flag (logic least byte FIFO/THR, logic FIFO/THR empty). serial receive section also contains 8-bit Receive Holding Register (RHR) Receive Serial Shift Register (RSR). Receive data removed from SC68C2550B receive FIFO reading register. receive section provides mechanism
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Product data sheet
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Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
prevent false starts. falling edge start false start bit, internal receiver counter starts counting clocks clock rate. After 71/2 clocks, start time should shifted center start bit. this time start sampled, still logic validated. Evaluating start this manner prevents receiver from assembling false character. Receiver status codes will posted LSR.
Interrupt Enable Register (IER)
Interrupt Enable Register (IER) masks interrupts from receiver ready, transmitter empty, line status modem status registers. These interrupts would normally seen output pin.
Table Interrupt Enable Register bits description Symbol IER[7:4] IER[3] Description used Modem Status Interrupt. This interrupt will issued whenever there modem status change reflected MSR[3:0]. logic disable modem status register interrupt (normal default condition) logic enable modem status register interrupt IER[2] Receive Line Status interrupt. This interrupt will issued whenever receive data error condition exists reflected LSR[4:1]. logic disable receiver line status interrupt (normal default condition) logic enable receiver line status interrupt IER[1] Transmit Holding Register interrupt. 16C450 mode, this interrupt will issued whenever empty, associated with LSR[5]. FIFO modes, this interrupt will issued whenever FIFO empty. logic disable Transmit Holding Register Empty (TXRDY) interrupt (normal default condition) logic enable TXRDY (ISR level interrupt IER[0] Receive Holding Register. 68C450 mode, this interrupt will issued when data, cleared when empty. FIFO mode, this interrupt will issued when FIFO reached programmed trigger level cleared when FIFO drops below trigger level. logic disable receiver ready (ISR level RXRDY) interrupt (normal default condition) logic enable RXRDY (ISR level interrupt
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Product data sheet
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SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
7.2.1 versus Transmit/Receive FIFO interrupt mode operation
When receive FIFO (FCR[0] logic receive interrupts (IER[0] logic enabled, receive interrupts register status will reflect following:
receive RXRDY interrupt (Level interrupt) issued external
when receive FIFO reached programmed trigger level. will cleared when receive FIFO drops below programmed trigger level.
Receive FIFO status will also reflected user accessible register when
receive FIFO trigger level reached. Both register receive status interrupt will cleared when FIFO drops below trigger level.
receive data ready (LSR[0]) soon character transferred from
shift register (RSR) receive FIFO. reset when FIFO empty.
When Transmit FIFO interrupts enabled, interrupt generated when
transmit FIFO empty unloading data UART transmission transmission media. interrupt cleared either reading register, loading with data characters.
7.2.2 versus Receive/Transmit FIFO polled mode operation
When FCR[0] logic resetting IER[3:0] enables SC68C2550B FIFO polled mode operation. this mode, interrupts generated user must poll register and/or data status. Since receiver transmitter have separate bits either both used polled mode selecting respective transmit receive control bit(s).
LSR[0] will logic long there byte receive FIFO. LSR[4:1] will provide type receive errors, receive break, encountered. LSR[5] will indicate when transmit FIFO empty. LSR[6] will indicate when both transmit FIFO transmit shift register empty. LSR[7] will show FIFO data errors occurred.
FIFO Control Register (FCR)
This register used enable FIFOs, clear FIFOs, receive FIFO trigger levels, select mode.
7.3.1 mode
7.3.1.1 Mode (FCR enable interrupt each single transmit receive operation, similar 68C450 mode. Transmit Ready (TXRDY) will logic whenever FIFO (THR, FIFO enabled) empty. Receive Ready (RXRDY) will logic whenever Receive Holding Register (RHR) loaded with character. 7.3.1.2 Mode (FCR enable interrupt block mode operation. transmit interrupt when transmit FIFO empty. TXRDY remains logic long empty FIFO location available. receive interrupt when receive FIFO fills programmed
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Product data sheet
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SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
trigger level. However, FIFO continues fill regardless programmed level until FIFO full. RXRDY packages transitions when FIFO reaches trigger level, transitions HIGH when FIFO empties.
7.3.2 FIFO mode
Table FIFO Control Register bits description Symbol FCR[7:6] Description RCVR trigger. These bits used trigger level receive FIFO interrupt. logic cleared) normal default condition logic trigger level interrupt generated when number characters FIFO equals programmed trigger level. However, FIFO will continue loaded until full. Refer Table FCR[5:4] FCR[3] used; initialized logic mode select logic mode logic mode Transmit operation mode `0': When SC68C2550B 68C450 mode (FIFOs disabled; FCR[0] logic FIFO mode (FIFOs enabled; FCR[0] logic FCR[3] logic when there characters transmit FIFO transmit holding register, TXRDY will logic Once active, TXRDY will logic after first character loaded into transmit holding register. Receive operation mode `0': When SC68C2550B mode (FCR[0] logic FIFO mode (FCR[3] logic there least character receive FIFO, RXRDY will logic Once active, RXRDY will logic when there more characters receiver. Transmit operation mode `1': When SC68C2550B FIFO mode (FCR[0] logic FCR[3] logic TXRDY will logic when transmit FIFO completely full. will logic more FIFO locations empty. Receive operation mode `1': When SC68C2550B FIFO mode (FCR[0] logic FCR[3] logic trigger level been reached, Receive Time-Out occurred, RXRDY will logic Once activated, will logic after there more characters FIFO. FCR[2] XMIT FIFO reset logic transmit FIFO reset (normal default condition) logic clears contents transmit FIFO resets FIFO counter logic (the transmit shift register cleared altered). This will return logic after clearing FIFO. FCR[1] RCVR FIFO reset logic receive FIFO reset (normal default condition) logic clears contents receive FIFO resets FIFO counter logic (the receive shift register cleared altered). This will return logic after clearing FIFO.
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Product data sheet
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SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
FIFO Control Register bits description .continued Symbol FCR[0] Description FIFOs enabled logic disable transmit receive FIFO (normal default condition). logic enable transmit receive FIFO. This must when other bits written they will programmed.
Table
Table FCR[7]
RCVR trigger levels FCR[6] FIFO trigger level
Interrupt Status Register (ISR)
SC68C2550B provides four levels prioritized interrupts minimize external software interaction. Interrupt Status Register (ISR) provides user with four interrupt status bits. Performing read cycle will provide user with highest pending interrupt level serviced. other interrupts acknowledged until pending interrupt serviced. lower level interrupt seen after servicing higher level interrupt re-reading interrupt status bits. Table shows data values (bit four prioritized interrupt levels interrupt sources associated with each these interrupt levels.
Table Priority level Table Interrupt source ISR[3] ISR[2] ISR[1] ISR[0] Source interrupt (Receiver Line Status Register) RXRDY (Received Data Ready) RXRDY (Receive Data Time-out) TXRDY (Transmitter Holding Register Empty) (Modem Status Register)
Interrupt Status Register bits description Symbol ISR[7:6] Description FIFOs enabled. These bits logic when FIFOs being used 68C450 mode. They logic when FIFOs enabled SC68C2550B mode. logic cleared default condition used priority bits These bits indicate source pending interrupt interrupt priority levels (see Table 11). logic cleared default condition status logic interrupt pending contents used pointer appropriate interrupt service routine logic interrupt pending (normal default condition)
ISR[5:4] ISR[3:1]
ISR[0]
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Product data sheet
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Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Line Control Register (LCR)
Line Control Register used specify asynchronous data communication format. word length, number stop bits, parity selected writing appropriate bits this register.
Table Line Control Register bits description Symbol LCR[7] Description Divisor Latch enable. internal baud rate counter latch Enhanced Feature mode enable. logic Divisor Latch disabled (normal default condition). Logic Divisor Latch enabled. LCR[6] break. When enabled, Break control causes break condition transmitted (the output forced logic state). This condition exists until disabled setting LCR[6] logic logic break condition (normal default condition) logic forces transmitter output (TX) logic alerting remote receiver line break condition LCR[5:3] LCR[2] programs parity conditions (see Table Stop bits. length stop specified this conjunction with programmed word length (see Table 15). logic cleared default condition LCR[1:0] Word length bits These bits specify word length transmitted received (see Table 16). logic cleared default condition Table LCR[5] Table LCR[2] Table LCR[1] LCR[5:3] parity selection LCR[4] LCR[3] Parity selection parity parity even parity forced parity forced parity
LCR[2] stop length Word length Stop length (bit times) 11/2
LCR[1:0] word length LCR[0] Word length
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Product data sheet
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SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Modem Control Register (MCR)
This register controls interface with modem peripheral device.
Table Modem Control Register bits description Symbol MCR[7:5] MCR[4] Description reserved; Loop-back. Enable local Loop-back mode (diagnostics). this mode transmitter output (TX) receiver input (RX), CTS, DSR, disconnected from SC68C2550B pins. Internally modem data control pins connected into loop-back data configuration (see Figure this mode, receiver transmitter interrupts remain fully operational. Modem Control Interrupts also operational, interrupts' sources switched lower four bits Modem Control. Interrupts continue controlled register. logic disable Loop-back mode (normal default condition) logic enable local Loop-back mode (diagnostics) MCR[3] control logic forces output HIGH state logic forces output state. Loop-back mode, controls MSR[7]. MCR[2] (OP1). OP1A/OP1B available external signal SC68C2550B. This instead used Loop-back mode only. Loop-back mode, this used write state modem interface signal. logic force output logic (normal default condition) logic force output logic MCR[0] logic force output logic (normal default condition) logic force output logic
MCR[1]
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Product data sheet
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SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Line Status Register (LSR)
This register provides status data transfers between SC68C2550B CPU.
Table Line Status Register bits description Description FIFO data error logic error (normal default condition) logic least parity error, framing error break indication current FIFO data. This cleared when there remaining error flags associated with remaining data FIFO. LSR[6] empty. This Transmit Empty indicator. This logic whenever Transmit Holding Register Transmit Shift Register both empty. reset logic whenever either contains data character. FIFO mode, this whenever transmit FIFO transmit shift register both empty. empty. This Transmit Holding Register Empty indicator. This indicates that UART ready accept character transmission. addition, this causes UART issue interrupt when interrupt enable set. logic when character transferred from Transmit Holding Register into Transmit Shift Register. reset logic concurrently with loading Transmit Holding Register CPU. FIFO mode, this when transmit FIFO empty; cleared when least byte written transmit FIFO. Break interrupt logic break condition (normal default condition) logic receiver received break signal logic character frame time). FIFO mode, only break character loaded into FIFO. LSR[3] Framing error logic framing error (normal default condition) logic framing error. receive character have valid stop bit(s). FIFO mode, this error associated with character FIFO. LSR[2] Parity error logic parity error (normal default condition) logic parity error. receive character does have correct parity information suspect. FIFO mode, this error associated with character FIFO. LSR[1] Overrun error logic overrun error (normal default condition) logic overrun error. data overrun error occurred receive shift register. This happens when additional data arrives while FIFO full. this case, previous data shift register overwritten. Note that under this condition, data byte Receive Shift Register transferred into FIFO, therefore data FIFO corrupted error. LSR[0] Receive data ready logic data Receive Holding Register FIFO (normal default condition) logic data been received saved Receive Holding Register FIFO
9397 14941 Koninklijke Philips Electronics N.V. 2005. rights reserved.
Symbol LSR[7]
LSR[5]
LSR[4]
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Modem Status Register (MSR)
This register provides current state control interface signals from modem, other peripheral device which SC68C2550B connected. Four bits this register used indicate changed information. These bits logic whenever control input from modem changes state. These bits logic whenever reads this register.
Table Modem Status Register bits description Symbol MSR[7] MSR[6] MSR[5] MSR[4] MSR[3] Description During normal operation, this complement input. Reading this Loop-back mode produces state MCR[3] (OP2). During normal operation, this complement input. Reading this Loop-back mode produces state MCR[2] (OP1). DSR. During normal operation, this complement input. During Loop-back mode, this equivalent MCR[0] (DTR). CTS. During normal operation, this complement input. During Loop-back mode, this equivalent MCR[1] (RTS).
logic change (normal default condition) logic input SC68C2550B changed state since last time read. Modem Status Interrupt will generated. MSR[2]
logic change (normal default condition) logic input SC68C2550B changed from logic logic Modem Status Interrupt will generated. MSR[1]
logic change (normal default condition) logic input SC68C2550B changed state since last time read. Modem Status Interrupt will generated. MSR[0]
logic change (normal default condition) logic input SC68C2550B changed state since last time read. Modem Status Interrupt will generated.
Whenever logic Modem Status Interrupt will generated.
9397 14941
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Scratchpad Register (SPR)
SC68C2550B provides temporary data register store bits user information.
7.10 SC68C2550B external reset condition
Table Register Table Output TXA, OP2A, OP2B RTSA, RTSB DTRA, DTRB Reset state registers Reset state IER[7:0] FCR[7:0] ISR[7:1] ISR[0] LCR[7:0] MCR[7:0] LSR[7] LSR[6:5] LSR[4:0] MSR[7:4] input signals; MSR[3:0] SFR[7:0] DLL[7:0] DLM[7:0] Reset state outputs Reset state logic logic logic logic 3-state condition
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134). Symbol Tamb Tstg Ptot(pack) Parameter supply voltage voltage operating temperature storage temperature total power dissipation package Conditions +150 Unit
9397 14941
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Static characteristics
Table Static characteristics Tamb unless otherwise specified. Symbol VIL(CK) VIH(CK) Parameter LOW-level clock input voltage HIGH-level clock input voltage LOW-level input voltage (except clock) HIGH-level input voltage (except clock) LOW-level output voltage outputs (data bus) (other outputs) (data bus) (other outputs) HIGH-level output voltage (data bus) (other outputs) -800 (data bus) -400 (other outputs) ILIL
Conditions
-0.3 -0.3 1.85 1.85 0.45 0.65
-0.3 -0.3
-0.5 -0.5
Unit
LOW-level input leakage current clock leakage supply current input capacitance
Except XTAL2, typical.
9397 14941
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Dynamic characteristics
Table Dynamic characteristics Tamb unless specified otherwise. Symbol td10 td11 td12 td13 td14 td15 td16 td17 td18 t1w, fXTAL t(RESET) tsu1 tsu2
Parameter chip select read cycle delay delay from data data disable time write cycle delay delay from write output delay interrupt from modem input delay reset interrupt from read delay from stop interrupt delay from read reset interrupt delay from start interrupt delay from write transmit start delay from write reset interrupt delay from stop RXRDY delay from read reset RXRDY delay from write TXRDY delay from start reset TXRDY hold time from data hold time address hold time clock cycle period clock speed RESET pulse width address setup time data setup time strobe width
Conditions
1TRCLK
Unit 8TRCLK
1TRCLK
load load load load load load
load
8TRCLK
24TRCLK
24TRCLK 1TRCLK
1TRCLK
16TRCLK
16TRCLK
RCLK internal signal derived from Divisor Latch (DLL) Divisor Latch (DLM) divisor latches. Applies external clock; crystal oscillator MHz.
XTAL
9397 14941
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
10.1 Timing diagrams
tsu1
valid address
valid address
valid data
valid data
002aab087
General read timing
tsu1
valid address
valid address
tsu2
valid data
valid data
002aab088
General write timing
9397 14941
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
(write)(1)
active
RTSA, RTSB DTRA, DTRB
change state
change state
CDA, CTSA, CTSB DSRA, DSRB
change state
change state
active
active
active
(read)(2)
active
active
active
RIA,
change state
002aab089
timing during write cycle. Figure timing during read cycle. Figure
Modem input/output timing
EXTERNAL CLOCK
002aaa112
XTAL External clock timing
9397 14941
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Start
data bits data bits data bits data bits
parity
Stop
next data Start
RXA,
td10 active td11
(read)
active
baud rate clock
002aab090
Receive timing
Start
data bits
parity
Stop
next data Start
RXA,
td15 RXRDYA, RXRDYB active data ready td16 (read)
active
002aab091
Receive ready timing non-FIFO mode
9397 14941
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Start
data bits
parity
Stop
RXA,
first byte that reaches trigger level
td15 RXRDYA, RXRDYB active data ready td16 (read)
active
002aab092
Receive ready timing FIFO mode
Start
data bits data bits data bits data bits active ready
parity
Stop
next data Start
TXA,
td12 td13
td14 active
(write)
active
baud rate clock
002aab093
Transmit timing
9397 14941
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Start TXA,
data bits
parity
Stop
next data Start
(write)
active
byte
td18
td17 TXRDYA, TXRDYB active transmitter ready transmitter ready
002aab094
Transmit ready timing non-FIFO mode
start
data bits
parity
stop
TXA,
data bits data bits data bits (write) active td18 byte
td17 TXRDYA, TXRDYB trigger lead
002aab337
Transmit ready timing FIFO mode
9397 14941
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Package outline
LQFP48: plastic profile quad flat package; leads; body SOT313-2
detail
index
scale
DIMENSIONS original dimensions) UNIT max. 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 9.15 8.85 9.15 8.85 0.75 0.45 0.12 0.95 0.55 0.95 0.55
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT313-2 REFERENCES 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Package outline SOT313-2 (LQFP48)
9397 14941 Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Soldering
12.1 Introduction soldering surface mount packages
This text gives very brief insight complex technology. more in-depth account soldering found Data Handbook IC26; Integrated Circuit Packages (document order number 9398 90011). There soldering method that ideal surface mount packages. Wave soldering still used certain surface mount ICs, suitable fine pitch SMDs. these situations reflow soldering recommended.
12.2 Reflow soldering
Reflow soldering requires solder paste suspension fine solder particles, flux binding agent) applied printed-circuit board screen printing, stencilling pressure-syringe dispensing before package placement. Driven legislation environmental forces worldwide lead-free solder pastes increasing. Several methods exist reflowing; example, convection convection/infrared heating conveyor type oven. Throughput times (preheating, soldering cooling) vary between seconds seconds depending heating method. Typical reflow peak temperatures range from depending solder paste material. top-surface temperature packages should preferably kept:
below (SnPb process) below (Pb-free process)
BGA, HTSSON.T SSOP.T packages packages with thickness packages with thickness volume called thick/large packages.
below (SnPb process) below (Pb-free process) packages with
thickness volume called small/thin packages. Moisture sensitivity precautions, indicated packing, must respected times.
12.3 Wave soldering
Conventional single wave soldering recommended surface mount devices (SMDs) printed-circuit boards with high component density, solder bridging non-wetting present major problems. overcome these problems double-wave soldering method specifically developed. wave soldering used following conditions must observed optimal results:
double-wave soldering method comprising turbulent wave with high upward
pressure followed smooth laminar wave.
packages with leads sides pitch (e):
larger than equal 1.27 footprint longitudinal axis preferred parallel transport direction printed-circuit board;
9397 14941 Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
smaller than 1.27 footprint longitudinal axis must parallel transport direction printed-circuit board. footprint must incorporate solder thieves downstream end.
packages with leads four sides, footprint must placed angle
transport direction printed-circuit board. footprint must incorporate solder thieves downstream side corners. During placement before soldering, package must fixed with droplet adhesive. adhesive applied screen printing, transfer syringe dispensing. package soldered after adhesive cured. Typical dwell time leads wave ranges from seconds seconds depending solder material applied, SnPb Pb-free respectively. mildly-activated flux will eliminate need removal corrosive residues most applications.
12.4 Manual soldering
component first soldering diagonally-opposite leads. voltage less) soldering iron applied flat part lead. Contact time must limited seconds When using dedicated tool, other leads soldered operation within seconds seconds between
12.5 Package related soldering information
Table Package BGA, HTSSON.T [3], LBGA, LFBGA, SQFP, SSOP.T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, PLCC [5], LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN.L [8], PMFP [9], WQCCN.L
Suitability surface mount packages wave reflow soldering methods Soldering method Wave suitable suitable Reflow suitable suitable
suitable recommended recommended
suitable suitable suitable suitable
suitable
more detailed information packages refer (LF)BGA Application Note (AN01026); order copy from your Philips Semiconductors sales office. surface mount (SMD) packages moisture sensitive. Depending upon moisture content, maximum temperature (with respect time) body size package, there risk that internal external package cracks occur vaporization moisture them (the called popcorn effect). details, refer Drypack information Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages extremely sensitive reflow soldering conditions must account processed through more than soldering cycle subjected infrared reflow soldering with peak temperature exceeding measured atmosphere reflow oven. package body peak temperature must kept possible.
9397 14941
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
These packages suitable wave soldering. versions with heatsink bottom side, solder cannot penetrate between printed-circuit board heatsink. versions with heatsink side, solder might deposited heatsink surface. wave soldering considered, then package must placed angle solder wave direction. package footprint must incorporate solder thieves downstream side corners. Wave soldering suitable LQFP, TQFP packages with pitch larger than definitely suitable packages with pitch equal smaller than 0.65 Wave soldering suitable SSOP, TSSOP, VSSOP packages with pitch equal larger than 0.65 definitely suitable packages with pitch equal smaller than Image sensor packages principle should soldered. They mounted sockets delivered pre-mounted flex foil. However, image sensor package mounted client flex foil using soldering process. appropriate soldering profile provided request. soldering manual soldering suitable PMFP packages.
Abbreviations
Table Acronym FIFO ISDN UART Abbreviations Description Central Processing Unit Direct Memory Access First In/First Integrated Service Digital Network Least Significant Most Significant Transistor-Transistor Logic Universal Asynchronous Receiver Transmitter
Revision history
Table Revision history Release date 20050428 Data sheet status Product data sheet Change notice Doc. number 9397 14941 Supersedes SC68C2550B_1 Document SC68C2550B_2 Modifications:
Added `and Motorola interface' descriptive title first page. Section "Features" page first bullet: added `with Motorola interface' Added Section "Trademarks" page Product data sheet 9397 14698
SC68C2550B_1
20050329
9397 14941
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Data sheet status
Level Data sheet status Objective data Preliminary data Product status Development Qualification Definition This data sheet contains data from objective specification product development. Philips Semiconductors reserves right change specification manner without notice. This data sheet contains data from preliminary specification. Supplementary data will published later date. Philips Semiconductors reserves right change specification without notice, order improve design supply best possible product. This data sheet contains data from product specification. Philips Semiconductors reserves right make changes time order improve design, manufacturing supply. Relevant changes will communicated Customer Product/Process Change Notification (CPCN).
Product data
Production
Please consult most recently issued data sheet before initiating completing design. product status device(s) described this data sheet have changed since this data sheet published. latest information available Internet data sheets describing multiple type numbers, highest-level product status determines data sheet status.
Definitions
Short-form specification data short-form specification extracted from full data sheet with same type number title. detailed information relevant data sheet data handbook. Limiting values definition Limiting values given accordance with Absolute Maximum Rating System (IEC 60134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Applications that described herein these products illustrative purposes only. Philips Semiconductors make representation warranty that such applications will suitable specified without further testing modification.
customers using selling these products such applications their risk agree fully indemnify Philips Semiconductors damages resulting from such application. Right make changes Philips Semiconductors reserves right make changes products including circuits, standard cells, and/or software described contained herein order improve design and/or performance. When product full production (status `Production'), relevant changes will communicated Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes responsibility liability these products, conveys license title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified.
Trademarks
Notice referenced brands, product names, service names trademarks property their respective owners.
Disclaimers
Life support These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. Philips Semiconductors
Contact information
additional information, please visit: sales office addresses, send email
9397 14941
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Contents
General description Features Ordering information Block diagram Pinning information Pinning description Functional description UART functions Internal registers. FIFO operation Hardware/software time-out interrupts. Programmable baud rate generator operation Loop-back mode Register descriptions Transmit (THR) Receive (RHR) Holding Registers. Interrupt Enable Register (IER) 7.2.1 versus Transmit/Receive FIFO interrupt mode operation. 7.2.2 versus Receive/Transmit FIFO polled mode operation. FIFO Control Register (FCR) 7.3.1 mode 7.3.1.1 Mode (FCR 7.3.1.2 Mode (FCR 7.3.2 FIFO mode Interrupt Status Register (ISR) Line Control Register (LCR) Modem Control Register (MCR) Line Status Register (LSR) Modem Status Register (MSR). Scratchpad Register (SPR) 7.10 SC68C2550B external reset condition Limiting values. Static characteristics. Dynamic characteristics 10.1 Timing diagrams Package outline Soldering 12.1 Introduction soldering surface mount packages 12.2 Reflow soldering 12.3 Wave soldering 12.4 Manual soldering 12.5 Package related soldering information Abbreviations Revision history Data sheet status. Definitions Disclaimers Trademarks Contact information
Koninklijke Philips Electronics N.V. 2005
rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent- other industrial intellectual property rights. Date release: April 2005 Document number: 9397 14941
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