DP83856 Repeater Information Base General Description DP8385

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

DP83856 Repeater Information Base General Description DP8385

Datasheet Thumbnail

Top Searches for this datasheet

DP83856 Repeater Information Base
DP83856 Repeater Information Base
General Description
DP83856 Repeater Information Base designed specifically meet management demands today's high speed Ethernet networking systems DP83856 simplifies design managed multiport repeaters Used conjunction with DP83850s enables repeater system become single managed entity that fully compatible with IEEE clause management requirements DP83856 device incorporates necessary functions counters collecting network statistics Information gathered per-packet per-port basis port which receiving packet active port statistics collection
Features
Supports DP83850 Repeater Interface Controllers (192 ports segment) Fully IEEE clause compatible Network management statistics processed activity (per packet) basis Programmed interface statistics reporting Uses external SRAM maintain port network management statistics counters Single interrupt acknowledgement provides report port SRAM based DP83856 based statistics Parallel register interface (16-bit) Allows indirect access DP83850 Repeater Interface Controller DP83840 Physical Layer Device serial registers through parallel register interface 132-pin PQFP
System Diagram
12392
TRI-STATE registered trademark National Semiconductor Corporation C1996 National Semiconductor Corporation
12392
RRD-B30M36 Printed
http
national
Block Diagram
12392
http
national
Table Contents
CONNECTION DIAGRAM DESCRIPTION Interface SRAM Interface Transmit Management Interface Test Interface Miscellaneous Pins Type Designation FUNCTIONAL DESCRIPTION Statistics Generation SRAM Interface SRAM Arbiter Interrupt Generation Control Register Interface Register Block Management Data Interface REGISTERS Register Memory Configuration Register Interrupt Register SRAM Interface Register Management Interface Register SRAM Write Data Register Write Data Register Device Register SRAM Read Data Registers Carrier Count Register Count Register Network Counters Read Data Registers DP83956 Initialization SRAM Test Initialization Network Counter Initialization Interrupt Initialization Usage Repeater Support Repeater Support SPECIFICATIONS Specifications Specifications
http
national
Connection Diagram
12392
http
national
Description
INTERFACE interface pins generic interface signals designed accommodate many different types with minimal external logic data interface 16-bits wide does provide steering capabilities Furthermore accesses must aligned 16-bit boundaries indicated Register Section Signal Name CINT Type Active Description INTERRUPT Indicates that DP83856 least interrupt pending CINT signal will remain active until reads Interrupt Register software's responsibility keep track multiple interrupts pending service interrupts READY Indicates that DP83856 ready terminate current cycle DP83856 asserts CRDY writes once strobed data into write data holding register DP83856 asserts CRDY reads once strobed data into read data output register CHIP SELECT Chip select internal DP83856 registers Generated external logic address decode DP83856 register space must remain valid entire cycle READ-WRITE Read Write strobe DP83856 internal registers Read Write ADDRESS Address DP83856 register accesses DP83856 latches address internal within being asserted DATA 16-bit data DP83856 register accesses correspond 16-bits data DP83856 implements Endian convention data storage register accesses should 16-bit accesses aligned 16-bit boundaries
CRDY
SRAM INTERFACE SRAM interface pins used connect DP83856 fast external SRAM DP83856 supports 16-bit SRAM configuration This configuration provides maximum 32-bit statistics values port Signal Name Type Active Description SRAM ADDRESS SRAM address should directly connected fast external SRAM's address inputs SRAM DATA SRAM data should directly connected fast external SRAM's data pins SRAM READ-WRITE Should directly connected fast external SRAM's write enable Read Write SRAM CHIP SELECT Should directly connected fast external SRAM's active chip select SRAM OUTPUT ENABLE Should directly connected fast external SRAM's (active low) output enable
http
national
Description (Continued)
TRANSMIT MANAGEMENT Signal Name Type High Active Description TRANSMIT DATA Transfers data from local DP83850 DP83856 synchronous local clock signal framed transmit ready signal TRANSMIT DATA READY Asserted local DP83850 when non-idle symbols repeated DP83850's output ports DP83856 uses this signal framing signal transmit data transmit error management data management error collision data valid enable carrier network utilization timing TRANSMIT DATA ERROR Asserted local DP83850 when transmit error occurs DP83856 monitors this signal determine current reception Symbol Code violation error synchronous local clock signal INTER REPEATER COLLISION Asserted (all) DP83850s system which currently experiencing collision DP83856 monitors this signal during valid uses information statistics processing collision counting INTER REPEATER DATA VALID Asserted DP83850 system which Inter Repeater arbitration transmitting valid data symbols DP83856 monitors this line beginning frame establish whether frame false carrier event valid invalid when DP83856 samples line then false carrier event counted MANAGEMENT DATA Data which sourced DP83850 system that Inter Repeater arbitration This data synchronous management clock framed transmit ready signal DP83856 uses this data determine source current data stream (DP83850 number Port number) MANAGEMENT DATA VALID Asserted DP83850 system which Inter Repeater arbitration when places valid data DP83856 monitors this line when valid determine when latch DP83850 number port number current reception synchronous MANAGEMENT CLOCK data transfers management synchronized rising edge this clock reference clock used latch active DP83850 port elasticity buffer errors current packet reception sourced DP83850 system which Inter Repeater arbitration MANAGEMENT ERROR Asserted DP83850 system which Inter Repeater arbitration when data rate mismatch error occurs (elasticity buffer over underrun) DP83856 monitors this line during valid determine current frame contains data rate management error synchronous Note that data rate mismatch errors will asserted until after DP83850 number port number have been sent DP83856 from DP83850 will sent prior frame (before de-asserted)
High
INTERFACE Signal Name RDIO Type Active Description REGISTER DATA CLOCK clock which continuously output from DP83856 Used synchronize data transfers serial register REGISTER DATA Serial register data signal Used transfer data from DP83856 register accesses This signal should buffered onto backplane using RRDIR signal direction control buffer buffer does require tri-state enable High REGISTER DIRECTION Serial Register Direction drive external buffer buffer should default READ toggle WRITE only when DP83856 initiating register access Slave (DP83850 PHY) drives RDIO DP83856 drives RDIO SERIAL DATA VALID Indicates that valid access progress asserted half clock prior start cycle remains valid half clock after cycle complete
RRDIR
http
national
Description (Continued)
TEST INTERFACE Signal Name TSTATE Type Active Description TRI-STATE Pulling this puts DP83856 into test mode that tri-states outputs except NAND NAND This allows external tester drive outputs DP83856 TEST MODE ENABLE HIGH OUTPUT TEST Forces DP83856's outputs High state defined TEST This allows automatic test machines check outputs stuck High TEST MODE OUTPUT HIGH When TEST taken DP83856's output pins groups) forced into High state defined below TEST Group Outputs Group Outputs
TEST
TEST
Group output numbers Group output numbers NAND NAND TREE EVEN INPUTS OUTPUT logical NAND even numbered inputs (except test input TEST inputs High output will inputs output will remain High NAND TREE INPUTS OUTPUT logical NAND numbered inputs (except test inputs TSTATE TEST inputs High output will inputs output will remain High
NAND
MISCELLANEOUS PINS Signal Name Type Active Description LOCAL CLOCK Primary clock DP83856 device DP83856 internal state machines This clock must same local clock used drive local DP83850 because signals which DP83856 must sychronized) synchronous local clock Must duty cycle RESET DP83856 reset when this signal asserted Asserting this signal will cause DP83856 state machines registers enter their reset state statistics SRAM cleared must cleared preset software RESERVED OUTPUT Connect RESERVED OUTPUT Connect
RES1 RES2
TYPE DESIGNATION Type Input buffer Input buffer with internal pull-up resistor Output buffer drive Output buffer with high impedance capability drive Bi-directional buffer with high impedance capability drive Bi-directional buffer with high impedance capability medium drive Bi-directional buffer with high impedance capability pull-up resistor drive Description
http
national
Functional Description
following sections describe different functional blocks DP83856 Repeater Information Base Referring block diagram page this datasheet DP83856 used conjuction with number DP83850s management fast SRAM DP83856 collects maintains network management statistics from connected DP83850s makes them available management STATISTICS GENERATION Inputs DP83856 Statistic Generation block include Inter Repeater signals Management signals signals These signals provide data streams necessary create statistics collected DP83856 DP83856 uses fast external SRAM hold statistics current packet reception Statistics current receive packet collected follows Octet Derived majority statistics function octet count Statistics based octet counts imply that valid been detected accurate count number data bytes packet available DP83856 Statistic Generation module detect block which indicates that valid been detected that octet counter enabled Source Address latch used store source address current packet that comparison previous source address made packet reception Octet derived statistics include Frames Octets Errors Alignment Errors Frames Long Source Address Source Address Changes Carrier Derived Other statistics function carrier Carrier derived statistics have high probability occurring activity bursts which include valid ensure accurate statistic gathering carrier based detection scheme implemented nibble counter used calculate length carrier which used create carrier derived statistics DP83856 employs 32-bit counters network utilization false carrier events collisions these counters monitor events ports they aggregate total repeater events Carrier derived statistics gathered DP83856 include Runts Very Long Events (jabber) Network Utilization Repeater False Carrier Events Repeater Collisions (per port collision obtained from DP83850s) DP83850 Notified required statistics DP83856 determining occurrence that event These statistics obtained notification from connected DP83850s DP83850 notified statistics include Data Rate Mismatches Symbol Code Violations
http national
Collision Counter DP83856 32-bit counter which incremented time repeater experiences collision This counter used keep track total number collisions happening repeater Network Utilization Counter Network Utilization counter 32-bit counter that counts nibbles when active network utilization counter will count nibbles relative packet activity This includes short events runts even noise segment network utilization counter used measure packet activity relative overall network bandwidth Since nibbles occurs rate during second update there could maximum million nibbles that could recorded example software second read update 32-bit network utilization counter read million value count network utilization calculated (max total) cent network bandwidth utilized that segment False Carrier Counter DP83856 32-bit counter which incremented time repeater experiences false carrier event This counter used keep track total number false carrier events occurring segment SRAM INTERFACE SRAM interface provides logic required communicate with fast external SRAM interface between DP83856 fast external SRAM very straightforward fast external SRAM dedicated block memory directly accessed only DP83856 DP83856 provides address capability bits SRAM this configuration DP83856 store sixteen 32-bit statistics port
Figure shows memory configuration each port there statistics defined which stored SRAM these statistics 32-bit values 48-bit value (Last Source Address) Last Source Address stored 32-bit values simplicity hardware implementation statistics stored endian mode DP83856 directly connected SRAM there need buffering between DP83856 SRAM DP83856 requires fast SRAM with maximum access time SRAM interface block contains address data multiplexers select between Statistic Update accesses Data multiplexed under control SRAM arbiter
SRAM ARBITER SRAM arbiter controls SRAM data multiplexers depending what type access being performed creates control signals SRAM ensuring timing correct There three events that result SRAM arbitration packet request Runt (Statistic Update State Machine) packet request Legal Length greater (Statistic Update State Machine) request (read write)
Functional Description (Continued)
12392
FIGURE Memory DP83856 Statistics SRAM arbiter assigns highest priority EOP-runts lowest priority requests single statistic reads arbiter produces 16-bit locked read cycles SRAM form 32-bit value block reads SRAM arbiter rearbitrates after each 32-bit SRAM read (two 16-bit locked reads) allow higher priority event access SRAM Writes SRAM must always word (16-bit) accesses byte writes supported INTERRUPT GENERATION CONTROL There four events that generate interrupt SRAM access complete register access complete Invalid register read DP83856 error DP83856 provides interrupt line (CINT) that shared interrupts interrupt active level sensitive signal Interrupts generated based valid event occuring with appropriate mask global interrupt Interrupts cleared reading interrupt register ``SRAM access complete'' interrupt signifies that current SRAM request been serviced data SRAM Read Data Register(s) (10h-40h) ``MII register access complete'' interrupt signifies that current register request been serviced data Read Data Register(s) (A0h-ACh) ``Invalid register read'' interrupt generated based DP83856 detecting error while performing read access register protocol IEEE Clause DP83856 looks leading reads does leading flags read invalid generates interrupt ``DP83856 error'' interrupt signifies that device dropped management data invalid inter-frame (IFG) spacing between packets minimum specified IEEE Clause DP83856 drop management data drops below This event expected happen well formed networks REGISTER INTERFACE register interface block state machine that performs accesses DP83850 Physical Layer Device registers (read write) based requests from This interface uses IEEE clause compliant serial interface protocol Register Interface eliminates need talk directly DP83850 Physical Layer Device registers amount spare management processing bandwidth therefore increased
http
national
Functional Description (Continued)
provides opcode type access (read write) register address device Interface Register then asserts start command writing (MII ACC) Configuration Register protocol performing reads writes follows READ
AAAAA RRRRR line turn-around xxxx xxxx xxxx xxxx
Refer IEEE draft document more details interface function timing REGISTER BLOCK register block provides system management access data DP83856 SRAM connected DP83850s Physical Layer Devices MANAGEMENT DATA INTERFACE every network event DP83850 device with port will send information required DP83856 perform statistics gathering information required DP83856 transferred Management Data Interface which consists nibble wide data with synchronous clock plus framing signal error flag Data transferred nibbles (per network event) first data nibble contains lowest significant bits DP83850 Number second contains most significant DP83850 number third contains number receiving port (port signal indicates elasticity buffer errors (due under-run overrun) DP83850
where k01l start sequence k10l read opcode kAAAAAl device address devices) RRRRR register address registers) line turn-around clock cycle allowed turn-around data leading bits data WRITE
AAAAA RRRRR xxxx xxxx xxxx xxxx
where k01l start sequence k01l write opcode kAAAAAl device address devices) RRRRR register address registers) leading bits data
http
national
Registers
DP83856 registers directly addressable system management Although some bits Configuration Register have been allocated register paging scheme these currently used (available future expansion) should always zero register accesses word (16-bit) wide byte access supported addresses given tables below assume that user connected DP83856 man4 REGISTER MEMORY Address 44h-7Eh Register Configuration Register Interrupt Reserved SRAM Interface Management Interface SRAM Write Data Write Data Device Frame Count High Read Frame Count Read Octet Count High Read Octet Count Read Source Address Change Count High Read Source Address Change Count Read Error Count High Read Error Count Read Alignment Error Count High Read Alignment Error Count Read Frame Long Count High Read Frame Long Count Read Runt Count High Read Runt Count Read Very Long Event Count High Read Very Long Event Count Read Data Rate Mismatch Count High Read Data Rate Mismatch Count Read Invalid Symbol Count High Read Invalid Symbol Count Read Reserved Reserved Source Address High Read Source Address Read Source Address Read Reserved Reserved
http national
agement normal 16-bit manner with address bits from connected bits DP83856 addresses thus offset from base address which DP83856 located system consistent with normal address labeling practice since DP83956 only supports 16-bit accesses supplied
Access
only
Registers (Continued)
REGISTER MEMORY (Continued) Address 1FEh CONFIGURATION REGISTER Address Reset bits cleared zero Name Access Description DP83856 writes after register access completes initiates register access writing This indicates when current DP83850 Physical Layer device register access complete DP83856 writes after SRAM access completes initiates SRAM access writing This indicates when current SRAM access complete TYPE Perform Single Access Perform Block Access (Reads Only) SRAM based statistics will loaded into SRAM (CPU Addr 40h) Statistics gathering disabled Statistics gathering enabled This enables managment statistics gathering Note that subsequent read accesses should read-modify-write instructions that left undisturbed PAGE These bits define which page register pointing Allows pages word registers Always write compatibility with later versions DP83856 Note Page bits implemented current version Reserved Write Read Undefined Carrier Count Register Count Register Register Access
Reserved Repeater Collisions High Read Repeater Collisions Read Network Utilization High Read Network Utilization Read False Carrier High Read False Carrier Read Reserved Read Data Port 0-11 Short Event High Block Read Data DP83850 Port 0-11 Short Event Block Read Data DP83850 Port 0-11 Late Event High Block Read Data DP83850 Port 0-11 Late Event Block Read Data DP83850 Port 0-11 Collision High Block Read Data DP83850 Port 0-11 Collision Block Read Data DP83850 Port 0-11 Auto-Partitions Block Read Data Reserved Reserved only only only only only only only
http
national
Registers (Continued)
INTERRUPT REGISTER Address Reset bits cleared zero Note Mask bits must enable valid status corresponding status bits Name Access Description access complete Interrupt asserted access complete Interrupt asserted Cleared read register Writes ignored SRAM access complete Interrupt asserted SRAM access complete Interrupt asserted Cleared read register Writes ignored DP83856 error Interrupt asserted access complete Interrupt asserted DP83856 error Interrupt asserted Cleared read register Writes ignored register read error Interrupt asserted register read error Interrupt asserted Cleared read register Writes ignored Mask access complete Interrupt Enable access complete Interrupt Mask SRAM access complete Interrupt Enable SRAM access complete Interrupt Mask DP83856 error Interrupt Enable DP83856 error Interrupt Mask Register Error Interrupt Enable Register Error Interrupt Disable CINT signal Enable CINT signal This global enable CINTsignal effect status bits Reserved Write Read Undefined
RIBERR
RIBERR
http
national
Registers (Continued)
SRAM INTERFACE REGISTER Address Reset bits cleared zero Name STAT Access Description These bits which STATISTIC SRAM access destined Values Frame Count Octet Count Change Count Error Count Alignment Error Count Frame Long Count Runt Count Very Long Event Count Data Rate Mismatch Count Invalid Symbol Count Reserved Source Address High Source Address 1Ah-1Eh Reserved Reserved SRAM Always Write SRAM Write SRAM Read This defines whether current SRAM access read write These bits which PORT number access destined Valid values 0h-Bh ports) These bits which DP83850 access destined Valid values 0h-Fh DP83850s)
Note This register should accessed while SRAM access progress Configuration Register then access this register)
D(12
PORT
MANAGEMENT INTERFACE REGISTER Address Reset bits cleared zero D(10 Name ADDR Access Description These bits which register access destined These bits which DEVICE access destined OPCODE VALUE Corresponds opcodes defined specification Extended Addressed Mode Write 16-bit payload Extended Addressed Mode Read 16-bit payload ACCESS TYPE Sets access type single block read Perform Single Access (All Physical Layer device accesses DP83850 accesses except DP83850 counters) Perform Block Read (DP83850 reads only) DP83850 based counters will loaded into registers (Address ACh) OPCODE field block reads ADDR register address corresponding Port ShortEvent Counter desired port D(13 Reserved Write Read Undefined
OPCODE
http
national
Registers (Continued)
SRAM WRITE DATA REGISTER Address Reset bits cleared zero Name DATA Access Description This register contains data written SRAM write access SRAM writes should only performed during DP83856 initialization
WRITE DATA REGISTER Address Reset bits cleared zero Name DATA Access Description This register contains data written register write access
DEVICE REGISTER Address Reset bits cleared zero Name LEVEL Access Description These bits Revision level device embedded into DP83856 silicon Reads initial revision These bits vendor specific code embedded DP83856 Reads initial revision Write Read Undefined
DEVICE Reserved
SRAM READ DATA REGISTERS Addresses 10h-40h Reset bits cleared zero Name SRAM Read Data Access Description Contains data corresponding SRAM location selected
http
national
Registers (Continued)
CARRIER COUNT REGISTER Address Reset D(14 bits cleared zero Name Carrier Count Unused Access Description Contains data which used preset carrier counter TEST PURPOSES ONLY This register only written when CONFIG register Write Read Undefined
COUNT REGISTER Address Reset bits cleared zero D(12 Name Count Unused Access Description Contains data which used preset Octet-Nibble counter TEST PURPOSES ONLY This register only written when CONFIG register Write Read Undefined
NETWORK COUNTERS Addresses Reset bits cleared zero Name Counter Data Access Description Contains data corresponding selected counter Disable Management function writing Config register prior writing these counters
READ DATA REGISTERS Addresses Reset value reset indeterminate Will probably read pull-up D(15 Name Data Access Description Contains read data corresponding register selected
single Physical Layer Management register read accesses single statistic read accesses connected DP83850s read data appears data register address When DP83856 instructed block statistics read from connected DP83850 block read values placed registers register designations given memory Section
http
national
DP83856 Initialization
SRAM TEST INITIALIZATION System vendors will often desire test SRAM part power-up initialization prior enabling management SRAM accesses performed follows SRAM Writes Program SRAM Interface Register (06h) with desired information Program SRAM Write Data Register (0Ah) with desired data Program Configuration Register (00h) disable management perform single SRAM access initiate cycle (Note block access SRAM allowed Writes Poll Configuration Register (00h) SRAM access complete Repeat next write SRAM Reads Program SRAM Interface Register (06h) with desired information Program Configuration Register (00h) enable management perform single SRAM access initiate cycle Poll Configuration Register (00h) SRAM access complete Read appropriate SRAM Read Data Register (10b 40h) obtain data Repeat next read Note that there ``holes'' SRAM space locations which accessible statistic update implementation DP83856 implementation uses SRAM Assuming base address SRAM 0000h then locations (word addresses) which inaccessible given Table below TABLE Unaccessible SRAM Locations word addressing hex) DP83850 Offset Offset Offset Offset 0014 0034 0054 0074 0094 00B4 00D4 00F4 0114 0134 0154 0174 0194 01B4 01D4 01F4 0214 0234 0254 0274 0294 02B4 02D4 02F4 0314 0334 0354 0374 0394 03B4 03D4 03F4 001A 003A 005A 007A 009A 00BA 00DA 00FA 011A 013A 015A 017A 019A 01BA 01DA 01FA 021A 023A 025A 027A 029A 02BA 02DA 02FA 031A 033A 035A 037A 039A 03BA 03DA 03FA 001C 003C 005C 007C 009C 00BC 00DC 00FC 011C 013C 015C 017C 019C 01BC 01DC 01FC 021C 023C 025C 027C 029C 02BC 02DC 02FC 031C 033C 035C 037C 039C 03BC 03DC 03FC 001E 003E 005E 007E 009E 00BE 00DE 00FE 011E 013E 015E 017E 019E 01BE 01DE 01FE 021E 023E 025E 027E 029E 02BE 02DE 02FE 031E 033E 035E 037E 039E 03BE 03DE 03FE
http
national
DP83856 Initialization (Continued)
TABLE Unaccessible SRAM Locations word addressing hex) (Continued) DP83850 Offset Offset Offset Offset 0414 0434 0454 0474 0494 04B4 04D4 04F4 0514 0534 0554 0574 0594 05B4 05D4 05F4 0614 0634 0654 0674 0694 06B4 06D4 06F4 0714 0734 0754 0774 0794 07B4 07D4 07F4 041A 043A 045A 047A 049A 04BA 04DA 04FA 051A 053A 055A 057A 059A 05BA 05DA 05FA 061A 063A 065A 067A 069A 06BA 06DA 06FA 071A 073A 075A 077A 079A 07BA 07DA 07FA 041C 043C 045C 047C 049C 04BC 04DC 04FC 051C 053C 055C 057C 059C 05BC 05DC 05FC 061C 063C 065C 067C 069C 06BC 06DC 06FC 071C 073C 075C 077C 079C 07BC 07DC 07FC 041E 043E 045E 047E 049E 04BE 04DE 04FE 051E 053E 055E 057E 059E 05BE 05DE 05FE 061E 063E 065E 067E 069E 06BE 06DE 06FE 071E 073E 075E 077E 079E 07BE 07DE 07FE DP83850 Offset Offset Offset Offset 0814 0834 0854 0874 0894 08B4 08D4 08F4 0914 0934 0954 0974 0994 09B4 09D4 09F4 0A14 0A34 0A54 0A74 0A94 0AB4 0AD4 0AF4 0B14 0B34 0B54 0B74 0B94 0BB4 0BD4 0BF4 081A 083A 085A 087A 089A 08BA 08DA 08FA 091A 093A 095A 097A 099A 09BA 09DA 09FA 0A1A 0A3A 0A5A 0A7A 0A9A 0ABA 0ADA 0AFA 0B1A 0B3A 0B5A 0B7A 0B9A 0BBA 0BDA 0BFA 081C 083C 085C 087C 089C 08BC 08DC 08FC 091C 093C 095C 097C 099C 09BC 09DC 09FC 0A1C 0A3C 0A5C 0A7C 0A9C 0ABC 0ADC 0AFC 0B1C 0B3C 0B5C 0B7C 0B9C 0BBC 0BDC 0BFC 081E 083E 085E 087E 089E 08BE 08DE 08FE 091E 093E O95E 097E 099E 09BE 09DE 09FE 0A1E 0A3E 0A5E 0A7E 0A9E 0ABE 0ADE 0AFE 0B1E 0B3E 0B5E 0B7E 0B9E 0BBE 0BDE 0BFE
http
national
DP83856 Initialization (Continued)
TABLE Unaccessible SRAM Locations word addressing hex) (Continued) DP83850 Offset Offset Offset Offset 0C14 0C34 0C54 0C74 0C94 0CB4 0CD4 0CF4 0D14 0D34 0D54 0D74 0D94 0DB4 0DD4 0DF4 0E14 0E34 0E54 0E74 0E94 0EB4 0ED4 0EF4 0F14 0F34 0F54 0F74 0F94 0FB4 0FD4 0FF4 0C1A 0C3A 0C5A 0C7A 0C9A 0CBA 0CDA 0CFA 0D1A 0D3A 0D5A 0D7A 0D9A 0DBA 0DDA 0DFA 0E1A 0E3A 0E5A 0E7A 0E9A 0EBA 0EDA 0EFA 0F1A 0F3A 0F5A 0F7A 0F9A 0FBA 0FDA 0FFA 0C1C 0C3C 0C5C 0C7C 0C9C 0CBC 0CDC 0CFC 0D1C 0D3C 0D5C 0D7C 0D9C 0DBC 0DDC 0DFC 0E1C 0E3C 0E5C 0E7C 0E9C 0EBC 0EDC 0EFC 0F1C 0F3C 0F5C 0F7C 0F9C 0FBC 0FDC 0FFC 0C1E 0C3E 0C5E 0C7E 0C9E 0CBE 0CDE 0CFE 0D1E 0D3E 0D5E 0D7E 0D9E 0DBE 0DDE 0DFE 0E1E 0E3E 0E5E 0E7E 0E9E 0EBE 0EDE 0EFE 0F1E 0F3E 0F5E 0F7E 0F9E 0FBE 0FDE 0FFE DP83850 Offset Offset Offset Offset 1014 1034 1054 1074 1094 10B4 10D4 10F4 1114 1134 1154 1174 1194 11B4 11D4 11F4 1214 1234 1254 1274 1294 12B4 12D4 12F4 1314 1334 1354 1374 1394 13B4 13D4 13F4 101A 103A 105A 107A 109A 10BA 10DA 10FA 111A 113A 115A 117A 119A 11BA 11DA 11FA 121A 123A 125A 127A 129A 12BA 12DA 12FA 131A 133A 135A 137A 139A 13BA 13DA 13FA 101C 103C 105C 107C 109C 10BC 10DC 10FC 111C 113C 115C 117C 119C 11BC 11DC 11FC 121C 123C 125C 127C 129C I2BC 12DC 12FC 131C 133C 135C 137C 139C 13BC 13DC 13FC 101E 103E 105E 107E 109E 10BE 10DE 10FE 111E 113E 115E 117E 119E 11BE 11DE 11FE 121E 123E 125E 127E 129E 12BE 12DE 12FE 131E 133E 135E 137E 139E 13BE 13DE 13FE
http
national
DP83856 Initialization (Continued)
TABLE Unaccessible SRAM Locations word addressing hex) (Continued) DP83850 Offset Offset Offset Offset 1414 1434 1454 1474 1494 14B4 14D4 14F4 1514 1534 1554 1574 1594 15B4 15D4 15F4 1614 1634 1654 1674 1694 16B4 16D4 16F4 1714 1734 1754 1774 1794 17B4 17D4 17F4 141A 143A 145A 147A 149A 14BA 14DA 14FA 151A 153A 155A 157A 159A 15BA 15DA 15FA 161A 163A 165A 167A 169A 16BA 16DA 16FA 171A 173A 175A 177A 179A 17BA 17DA 17FA 141C 143C 145C 147C 149C 14BC 14DC 14FC 15IC 153C 155C 157C 159C 15BC 15DC 15FC 161C 163C 165C 167C 169C 16BC 16DC 16FC 171C 173C 175C 177C 179C 17BC 17DC 17FC 141E 143E 145E 147E 149E 14BE 14DE 14FE 151E 153E 155E 157E 159E 15BE 15DE 15FE 161E 163E 165E 167E 169E 16BE 16DE 16FE 171E 173E 175E 177E 179E 17BE 17DE 17FE DP83850 Offset Offset Offset Offset 1814 1834 1854 1874 1894 18B4 18D4 18F4 1914 1934 1954 1974 1994 19B4 19D4 19F4 1A14 1A34 1A54 1A74 1A94 1AB4 1AD4 0AF4 1B14 1B34 1B54 1B74 1B94 1BB4 1BD4 1BF4 181A 183A 185A 187A 189A 18BA 18DA 18FA 191A 193A 195A 197A 199A 19BA 19DA 19FA 1A1A 1A3A 1A5A 1A7A 1A9A 1ABA 1ADA 0AFA 1B1A 1B3A 1B5A 1B7A 1B9A 1BBA 1BDA 1BFA 181C 183C 185C 187C 189C 18BC 18DC 18FC 191C 193C 195C 197C 199C 19BC 19DC 19FC 1A1C 1A3C 1A5C 1A7C 1A9C 1ABC 1ADC 0AFC 1B1C 1B3C 1B5C 1B7C 1B9C 1BBC 1BDC 1BFC 181E 183E 185E 187E 189E 18BE 18DE 18FE 191E 193E 195E 197E 199E 19BE 19DE 19FE 1A1E 1A3E 1A5E 1A7E 1A9E 1ABE 1ADE 0AFE 1B1E 1B3E 1B5E 1B7E 1B9E 1BBE 1BDE 1BFE
http
national
DP83856 Initialization (Continued)
TABLE Unaccessible SRAM Locations word addressing hex) (Continued) DP83850 Offset Offset Offset Offset 1C14 1C34 1C54 1C74 1C94 1CB4 1CD4 1CF4 1D14 1D34 1D54 1D74 1D94 1DB4 1DD4 1DF4 1E14 1E34 1E54 1E74 1E94 1EB4 1ED4 1EF4 1F14 1F34 1F54 1F74 1F94 1FB4 1FD4 1FF4 1C1A 1C3A 1C5A 1C7A 1C9A 1CBA 1CDA 1CFA 1D1A 1D3A 1D5A 1D7A 1D9A 1DBA 1DDA 1DFA 1E1A 1E3A 1E5A 1E7A 1E9A 1EBA 1EDA 1EFA 1F1A 1F3A 1F5A 1F7A 1F9A 1FBA 1FDA 1FFA 1C1C 1C3C 1C5C 1C7C 1C9C 1CBC 1CDC 1CFC 1D1C 1D3C 1D5C 1D7C 1D9C 1DBC 1DDC 1DFC 1E1C 1E3C 1E5C 1E7C 1E9C 1EBC 1EDC 1EFC 1F1C 1F3C 1F5C 1F7C 1F9C 1FBC 1FDC 1FFC 1C1E 1C3E 1C5E 1C7E 1C9E 1CBE 1CDE 1CFE 1D1E 1D3E 1D5E 1D7E 1D9E 1DBE 1DDE 1DFE 1E1E 1E3E 1E5E 1E7E 1E9E 1EBE 1EDE 1EFE 1F1E 1F3E 1F5E 1F7E 1F9E 1FBE 1FDE 1FFE NETWORK COUNTER INITIALIZATION network counters described Sections (Collision Counter) (Network Utilization Counter) (False Carrier Counter) cleared power-up reset require further initialization INTERRUPT INITIALIZATION USAGE DP83856 supports does require external interrupts Interrupts initialized programming Interrupt Register (02h) Interrupt generation control described Section following suggestion interrupts First agent will probably want receive updated statistic information based timer tick once every second Software will want statistics each port needs talk both DP83856 DP83850 Using Block SRAM Read feature DP83856 software will have wait order DP83856 complete SRAM dump port Thus does seem worthwhile interrupts given overhead getting interrupt service routine Using Block Read feature DP83856 software will have walt order DP83856 complete DP83850 register dump accesses access plus overhead) thus this where interrupt usage recommended Allow software something else while DP83850 registers being read next issue read error Software will probably poll stack hubs periodically looking addition removal from stack assumed that this polling routine executed very often perhaps once every interrupts should only generated accessing hubs that there (although damaged units also respond) point that insignificant number interrupts should generated thus very little bandwidth should expended servicing these summary enable interrupts accesses read errors SRAM accesses
http
national
Repeater Support
REPEATER SUPPORT following tables enumerate groups within IEEE Clause Repeater mapping DP83856 DP83850 DP83840 system implementation BASIC GROUP Repeater Managed Object Class aRepeaterID aRepeaterType aRepeaterGroupCapacity aGroupMap aRepeaterHealthState aRepeaterHealthText aRepeaterHealthData aTransmitCollisions acResetRepeater acExecuteNonDisruptiveSelfTest nRepeaterHealth nRepeaterReset nGroupMapChange Group Managed Object Class aGroupID aGroupPortCapacity aPortMap nPortMapChange Implemented DP83856 DP83850 Implemented Repeater Port Managed Object Class Implemented aAIignmentErrors aFramesTooLong aShortEvents aRunts aCollisions aLateEvents aVeryLongEvents aDataRateMismatches aAutoPartitions aIsolates aSymbolErrorDuringPacket aLastSourceAddress aPortAdminControl DP83856 DP83856 DP83850 DP83856 DP83850 DP83850 DP83856 DP83856 DP83850 Plexus DP83856 DP83856 BASIC GROUP (Continued) Repeater Port Managed Object Class Implemented aPortID aPortAdminState aAutoPartitionState aReadableFrames aReadableOctets aFrameCheckSequenceErrors DP83850 DP83856 DP83856 DP83856
http
national
Specifications
SPECIFICATIONS Symbol Parameter Minimum High Level Output Voltage Minimum Level Output Voltage Minimum High Level Input Voltage Maximum Level Input Voltage Input Current Minimum TRI-STATE Output Leakage Current Supply Current (Calculated)
Conditions
Units
SPECIFICATIONS Some timing parameters shown more than once (both same timing diagram different sections) clarity Read Timing Parameter Description Data valid Data valid CRDY Address hold from hold from high Data hold from high Address setup setup high between cycles high CRDY high Data driven (ns) (ns)
12392
http
national
Specifications (Continued)
Write Timing Parameter Description Address hold from hold from high Address setup setup high between cycles high CRDY high CRDY Data valid Data hold from CRDY (ns) (ns)
12392
Slave Timing (DP83856 Receiving Data RDIO) Parameter Description pulse width falling edge RRDIR RDIO setup rising edge RDIO hold from rising edge falling edge high (ns) (ns) (ns)
12392
http
national
Specifications (Continued)
Master Timing (DP83856 Sending Data RDIO) Parameter Description pulse width falling edge falling edge falling edge RDIO valid falling edge RDIO invalid RRDIR rising edge falling edge falling edge rising edge (ns) (ns) (ns)
12392
Timing Parameter Description setup rising edge hold from rising edge setup rising edge hold from rising edge (ns) (ns) (ns)
setup rising edge hold from rising edge
12392
http
national
Specifications (Continued)
Management Timing Parameter Description setup rising edge (ns) (ns) (ns)
setup rising edge hold from rising edge setup rising edge hold from rising edge hold from rising edge
12392
SRAM Read Timing Parameter (Note (Note (Note (Note Description valid valid valid (SRAM tsu) width invalid high high high (ns) (ns) (ns)
Note SRAM read cycles Address controlled Note SRAM must have read access time faster Note DP83856 latches data prior changing value Note DP83856 latches data prior terminating
12392
http
national
Specifications (Continued)
SRAM Write Timing Parameter Description valid valid width valid high high invalid high invalid (ns) (ns) (ns)
12392
http
national
Specifications (Continued)
Test Mode Timing Parameter Description TSTATE Group Outputs Hi-Z TSTATE Group Outputs Hi-Z TSTATE high Group Outputs driven TSTATE high Group Outputs driven TEST TEST TEST TEST TEST TEST TEST TEST TEST setup rising edge setup rising edge Group Outputs high Group Outputs (ns) (ns) (ns)
TEST TEST
high setup rising edge high Group Outputs high Group Outputs high
TEST TEST
high Group Outputs undefined high Group Outputs undefined
12392
Group output numbers Group output numbers
http
national
http
national
DP83856 Repeater Information Base
Physical Dimensions inches
millimeters
132-Lead Molded Plastic Quad Flat Package JEDEC Order Number DP83856 Package Number VF132A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user
National Semiconductor Corporation 1111 West Bardin Road Arlington 76017 1(800) 272-9959 1(800) 737-7018
critical component component life support device system whose failure perform reasonably expected cause failure life support device system affect safety effectiveness
http
national
National Semiconductor Europe 180-530 Email europe support Deutsch 180-530 English 180-532 Fran 180-532 Italiano 180-534
National Semiconductor Hong Kong 13th Floor Straight Block Ocean Centre Canton Tsimshatsui Kowloon Hong Kong (852) 2737-1600 (852) 2736-9960
National Semiconductor Japan 81-043-299-2308 81-043-299-2408
National does assume responsibility circuitry described circuit patent licenses implied National reserves right time without notice change said circuitry specifications

DP83856 Repeater Information Base General Description DP8385

Top Searches for this datasheet

Other recent searches