COP888xG/CS Family 8-Bit CMOS Based Microcontrollers with Memory, Comp
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COP888xG/CS Family, 8-Bit CMOS Based Microcontrollers with Memory, Comparators USART
COP888xG/CS Family 8-Bit CMOS Based Microcontrollers with Memory, Comparators USART
Note: COP8SG devices form-fit-function compatible supersets COP888xG/CL/CS Family devices, replacements these designs, design upgrades with minimum effort. COP888xG based microcontrollers highly integrated COP8Feature core devices with larger memory 24k) advanced features including Analog comparators. These single-chip CMOS devices suited more complex applications requiring full featured controller with range memory sizes, (except EG), comparators, full-duplex USART. software compatible (different range) toor (One Time Device COP684CS COP884CS COP984CS COP688CS COP888CS COP988CS COP884CG COP888CG COP684EG COP884EG COP984EG COP688EG COP888EG COP988EG COP688GG COP888GG COP688HG COP888HG COP688KG COP888KG Memory (bytes) (bytes) Pins 36/40 36/40 36/40 34/38 36/40 36/40 36/40 36/40 36/40 36/40 36/40 36/40 36/40 Programmable) versions available (COP8SGx7 Family). Erasable windowed versions available with range software hardware development tools. Family features include 8-bit memory mapped architecture, with instruction cycle, three multifunction 16-bit timer/counters, full-duplex USART, MICROWIRE/PLUSserial I/O, Analog comparators, power saving HALT/IDLE modes, idle timer, MIWU, high current outputs, software selectable options, WATCHDOGtimer Clock Monitor, 2.5V 5.5V operation, 28/40/44 packages. Devices included this datasheet are:
Packages DIP/SOIC DIP/SOIC DIP/SOIC DIP, PLCC DIP, PLCC DIP, PLCC DIP/SOIC DIP, PLCC DIP, SOIC DIP, SOIC DIP, SOIC DIP, PLCC DIP, PLCC/PQFP DIP, PLCC DIP, PLCC/PQFP DIP, PLCC/PQFP DIP, PLCC DIP, PLCC DIP, PLCC DIP, PLCC
Temperature +125°C +85°C +70°C +125°C +85°C +70°C +85°C +85°C +125°C +85°C +70°C +125°C +85°C +70°C +125°C +85°C +125°C +85°C +125°C +85°C
Comments 4.5V 5.5V 2.5V 4.0V, CSH=4.0V 6.0V 4.5V 5.5V 2.5V 4.0V, CSH=4.0V 6.0V 2.5V 6.0V 2.5V 6.0V 4.5V 5.5V 2.5V 4.0V, EGH=4.0 6.0V 4.5V 5.5V
2.5V 4.0V, EGH=4.0 6.0V 4.5V 5.5V
4.5V 5.5V 4.5V 5.5V
Features
Full duplex USART Three 16-bit timers, each with 16-bit registers supporting: Processor Independent mode
External Event counter mode Input Capture mode Quiet design (low radiated emissions) kbytes on-board bytes on-board
COP8TM, MICROWIRE/PLUSTM, WATCHDOGare trademarks National Semiconductor Corporation. TRI-STATE registered trademark National Semiconductor Corporation. iceMASTER registered trademark MetaLink Corporation.
2000 National Semiconductor Corporation
DS012829
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COP888xG/CS Family
Features
(Continued)
Additional Peripheral Features
Idle Timer Multi-Input Wake-Up (MIWU) with optional interrupts analog comparators (one series) WATCHDOG Clock Monitor logic MICROWIRE/PLUS serial
Features
Memory mapped Software selectable options (TRI-STATE Output, Push-Pull Output, Weak Pull-Up Input, High Impedance Input) high current outputs Schmitt trigger inputs ports Packages: PQFP with pins PLCC with pins with pins DIP/SOIC with pins
fourteen multi-source vectored interrupts servicing External Interrupt with selectable edge Idle Timer Three Timers (one timer series)(each with interrupts) MICROWIRE/PLUS Multi-Input Wake-Up Software Trap USART Default (default interrupt) 8-bit Stack Pointer (stack RAM) 8-bit Register Indirect Data Memory Pointers
Fully Static CMOS
power saving modes: HALT IDLE current drain (typically Single supply operation: 2.5V-5.5V (COP88x) Temperature ranges: +70°C, -40°C +85°C, -55°C +125°C
Development Support
Emulation devices Real time emulation full program debug offered MetaLink's Development System
CPU/Instruction Features
instruction cycle time Versatile easy instruction
Block Diagram
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FIGURE COP888xG Block Diagram
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COP888xG/CS Family
Connection Diagrams
Dual-In-Line Package
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View Order Number COP884CS-XXX/WM, COP984CS-XXX/WM, COP984CSH-XXX/WM, COP684CS-XXX/WM, COP884CG-XXX/WM, COP884EG-XXX/WM COP884CS-XXX/N, COP984CS-XXX/N, COP984CSH-XXX/N, COP884CG-XXX/N, COP884EG-XXX/N Package Number M28B N28A
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View Order Number COP888CS-XXX/N, COP988CS-XXX/N, COP688CS-XXX/N, COP988CSH-XXX/N, COP888CG-XXX/N, COP688EG-XXX/N, COP888GG-XXX/N, COP688GG-XXX/N, COP888GG-XXX/N, COP688HG-XXX/N, COP888HG-XXX/N, COP688KG-XXX/N, COP888KG-XXX/N Package Number N40A
Plastic Chip Carrier
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View Order Number COP688CS-XXX/V, COP888CS-XXX/V, COP988CS/CSH-XXX/V, COP688EG-XXX/V, COP888EG-XXX/V, COP988EG-XXX/V, COP888CG-XXX/V, COP688GG-XXX/V, COP888GG-XXX/V, COP688HG-XXX/V, COP888HG-XXX/V, COP688KG-XXX/V, COP888KG-XXX/V Package Number V44A
DS012829-45
View Order Number COP888EG-XXX/VEJ, COP688GG-XXX/VEJ, COP888GG-XXX/VEJ, Package Number VEJ44A
FIGURE Connection Diagrams
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COP888xG/CS Family
Connection Diagrams
Port RESET
Note available series
(Continued)
Pinouts 28-, 44-Pin Packages Type WDOUT I/CKO COMP1IN- COMP1IN+ COMP1OUT COMP2IN-* COMP2IN+* COMP2OUT* HALT Restart Alt. MIWU MIWU MIWU MIWU MIWU MIWU MIWU MIWU T2A* T2B* T3A* T3B* Alt. 28-Pin DIP/SO 40-Pin 44-Pin PLCC 44-Pin PQFP
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COP888xG/CS Family
Absolute Maximum Ratings (Note
Military/Aerospace specified devices required, please contact National Semiconductor Sales Office/ Distributors availability specifications. Supply Voltage (VCC) Voltage -0.3V 0.3V
Total Current into (Source) Total Current (Sink) Storage Temperature Range
-65°C +140°C
Note Absolute maximum ratings indicate limits beyond which damage device occur. electrical specifications ensured when operating device absolute maximum ratings.
Electrical Characteristics 98xEG 98xCS:
+70°C unless otherwise specified Parameter Operating Voltage COP98xCS, COP98xEG COP98xCSH, COP98xEGH Power Supply Ripple (Note Supply Current (Note HALT Current (Note IDLE Current Input Levels (VIH, VIL) RESET Logic High Logic (External Crystal Osc. Modes) Logic High Logic Other Inputs Logic High Logic Hi-Z Input Leakage Input Pullup Current Port Input Hysteresis Output Current Levels Outputs Source Sink Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) 2.7V 2.5V, 1.8V 3.3V 2.5V, 1.8V 0.4V 2.5V, 0.4V -2.5 -0.4 -0.2 -100 3.3V 2.5V, 1.8V 2.5V, 0.4V -0.4 -0.2 6.0V, 6.0V, (Note -250 0.35 6.0V, 6.0V, 6.0V, 6.0V, 6.0V, 12.5 Peak-to-Peak Conditions Units
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COP888xG/CS Family
Electrical Characteristics 98xEG 98xCS:
+70°C unless otherwise specified Parameter TRI-STATE Leakage Allowable Sink/Source Current Outputs (Sink) others Maximum Input Current without Latchup (Notes Retention Voltage, Input Capacitance Load Capacitance Rise Fall Time (min) 6.0V Conditions
(Continued)
Units
1000
Electrical Characteristics 98xEG 98xCS:
+70°C unless otherwise specified Parameter Instruction Cycle Time (tc) Crystal, Resonator Oscillator Inputs tSETUP tHOLD Output Propagation Delay tPD1, tPD0 Others MICROWIRE Setup Time (tUWS) (Note MICROWIRE Hold Time (tUWH) (Note MICROWIRE Output Propagation Delay (tUPD) Input Pulse Width (Note Interrupt Input High Time Interrupt Input Time Timer Input High Time Timer Input Time Reset Pulse Width 6.0V 2.5V 1.75 6.0V 2.5V 6.0V 2.5V 2.2k, 6.0V 2.5V 6.0V 2.5V Conditions Units
6.0V 2.5V
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COP888xG/CS Family
Absolute Maximum Ratings (Note
Military/Aerospace specified devices required, please contact National Semiconductor Sales Office/ Distributors availability specifications. Supply Voltage (VCC) Voltage -0.3V 0.3V
Total Current into (Source) Total Current (Sink) Storage Temperature Range
-65°C +140°C
Note Absolute maximum ratings indicate limits beyond which damage device occur. electrical specifications ensured when operating device absolute maximum ratings.
Electrical Characteristics 88xCG, 88xCS, 88xEG:
-40°C +85°C unless otherwise specified Parameter Operating Voltage Power Supply Ripple (Note Supply Current (Note (88xCG 88xEG only) (88xCG 88xEG only) HALT Current (Note (88xCG 88xEG only) IDLE Current (88xCG 88xEG only) Input Levels (VIH, VIL) RESET Logic High Logic (External Crystal Osc. Modes) Logic High Logic Other Inputs Logic High Logic Hi-Z Input Leakage Input Pullup Current Port Input Hysteresis Output Current Levels Outputs Source Sink Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) 2.7V 2.5V, 1.8V 3.3V 2.5V, 1.8V 0.4V -2.5 -0.4 -0.2 -100 3.3V 2.5V, 1.8V 2.5V, 0.4V -0.4 -0.2 6.0V 6.0V, (Note -250 0.35 6.0V, 6.0V, 6.0V, 6.0V, 6.0V, 12.5 Peak-to-Peak Conditions Units
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COP888xG/CS Family
Electrical Characteristics 88xCG, 88xCS, 88xEG:
-40°C +85°C unless otherwise specified Parameter TRI-STATE Leakage Allowable Sink/Source Current Outputs (Sink) others Maximum Input Current without Latchup (Notes Retention Voltage, Input Capacitance Load Capacitance Rise Fall Time (min) 6.0V Conditions 2.5V, 0.4V
(Continued)
Units
1000
Electrical Characteristics 888EG, 88xCS, 88xCG:
-40°C +85°C unless otherwise specified Parameter Instruction Cycle Time (tc) Crystal, Resonator Oscillator Inputs tSETUP tHOLD Output Propagation Delay tPD1, tPD0 Others MICROWIRE Setup Time (tUWS) (Note MICROWIRE Hold Time (tUWH) (Note MICROWIRE Output Propagation Delay (tUPD) Input Pulse Width (Note Interrupt Input High Time Interrupt Input Time Timer Input High Time Timer Input Time Reset Pulse Width 6.0V 2.5V 6.0V 2.5V 1.75 6.0V 2.5V 6.0V 2.5V 2.2k, 6.0V 2.5V Conditions Units
6.0V 2.5V
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COP888xG/CS Family
Absolute Maximum Ratings (Note
Military/Aerospace specified devices required, please contact National Semiconductor Sales Office/ Distributors availability specifications. Supply Voltage (VCC) Voltage -0.3V 0.3V
Total Current into (Source) Total Current (Sink) Storage Temperature Range
-65°C +140°C
Note Absolute maximum ratings indicate limits beyond which damage device occur. electrical specifications ensured when operating device absolute maximum ratings.
Electrical Characteristics 888GG, 888HG, 888KG:
-40°C +85°C unless otherwise specified Parameter Operating Voltage Power Supply Ripple (Note Supply Current (Note HALT Current (Note IDLE Current Input Levels (VIH, VIL) RESET Logic High Logic CKI, Other Inputs Logic High Logic Hi-Z Input Leakage Input Pullup Current Port Input Hysteresis Output Current Levels Outputs Source Sink Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage Allowable Sink/Source Current Outputs (Sink) others Maximum Input Current
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Conditions Peak-to-Peak 5.5V, 5.5V, 5.5V, 5.5V, 5.5V,
12.5
Units
5.5V, 5.5V, (Note -250 0.35
3.3V 2.5V, 1.8V 2.5V, 0.4V 2.7V 2.5V, 1.8V 3.3V 2.5V, 1.8V 0.4V 2.5V, 0.4V 5.5V
-0.4 -0.2 -2.5 -0.4 -0.2 -100
COP888xG/CS Family
Electrical Characteristics 888GG, 888HG, 888KG:
-40°C +85°C unless otherwise specified Parameter without Latchup (Notes Retention Voltage, Input Capacitance Load Capacitance (Note Conditions Room Temperature Rise Fall Time (min)
(Continued)
Units
1000
Electrical Characteristics 888GG, 888HG, 888KG:
-40°C +85°C unless otherwise specified Parameter (88xCG 88xEG only) Instruction Cycle Time (tc) Crystal, Resonator Oscillator Inputs tSETUP tHOLD Output Propagation Delay tPD1, tPD0 Others MICROWIRE Setup Time (tUWS) (Note MICROWIRE Hold Time (tUWH) (Note MICROWIRE Output Propagation Delay (tUPD) Input Pulse Width (Note Interrupt Input High Time Interrupt Input Time Timer Input High Time Timer Input Time Reset Pulse Width 5.5V 2.5V 5.5V 2.5V 1.75 5.5V 2.5V 5.5V 2.5V 2.2k, 2.5V 5.5V 2.5V 5.5V Conditions Units
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COP888xG/CS Family
Absolute Maximum Ratings (Note
Military/Aerospace specified devices required, please contact National Semiconductor Sales Office/ Distributors availability specifications. Supply Voltage (VCC) Voltage -0.3V 0.3V
Total Current into (Source) Total Current (Sink) Storage Temperature Range
-65°C +140°C
Note Absolute maximum ratings indicate limits beyond which damage device occur. electrical specifications ensured when operating device absolute maximum ratings.
Electrical Characteristics 68xCS 68xxG:
-55°C +125°C unless otherwise specified Parameter Operating Voltage Power Supply Ripple (Note Supply Current (Note HALT Current (Note IDLE Current Input Levels (VIH, VIL) RESET Logic High Logic (68xCS 68xEG only) Logic High Logic Other Inputs Logic High Logic Hi-Z Input Leakage Input Pullup Current Port Input Hysteresis Output Current Levels Outputs Source Sink Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage Allowable Sink/Source Current Outputs (Sink) others Maximum Input Current without Latchup (Notes Retention Voltage, Input Capacitance Load Capacitance Room Temp Rise Fall Time (min) (Note (Note 1000 4.5V, 2.7V 4.5V, 3.3V 4.5V, 0.4V 5.5V -0.4 -140 4.5V, 3.3V 4.5V, -0.4 5.5V, 5.5V, (Note -400 0.35 5.5V, 5.5V, 5.5V, 5.5V, 5.5V, 12.5 Peak-to-Peak Conditions Units
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COP888xG/CS Family
Electrical Characteristics 68xCS 68xxG:
-55°C +125°C unless otherwise specified Parameter Instruction Cycle Time (tc) Crystal, Resonator Oscillator 68xCS 68xEG only) Inputs tSETUP tHOLD Output Propagation Delay tPD1, tPD0 Others MICROWIRESetup Time (tUWS) (Note MICROWIRE Hold Time (tUWH) (Note MICROWIRE Output Propagation Delay (tUPD) Input Pulse Width (Note Interrupt Input High Time Interrupt Input Time Timer Input High Time Timer Input Time Reset Pulse Width
Note Maximum rate voltage change must less than V/ms. Note Supply current measured after running 2000 cycles with square wave input, open, inputs rails outputs open. Note HALT mode will stop from oscillating Crystal configurations. Measurement HALT done with device neither sourcing sinking current; with G0-G5 programmed outputs driving load; outputs programmed driving load; inputs tied VCC; clock monitor comparators disabled. Parameter refers HALT mode entered setting Port data register. Part will pull during HALT crystal clock mode. Note Pins RESET designed with high voltage input network. These pins allow input voltages greater than pins will have sink current when biased voltages greater than (the pins have source current when biased voltage below VCC). effective resistance (typical). These pins will latch voltage pins must limited less than 14V. WARNING: Voltages excess will cause damage pins. This warning excludes transients. Note Parameter characterized tested. Note Instruction Cycle Time
Conditions 4.5V 4.5V
Units
4.5V 4.5V 2.2k, 4.5V 4.5V
Comparators Characteristics
-40°C +85°C. Parameter Input Offset Voltage Input Common Mode Voltage Range Voltage Gain Level Output Current High Level Output Current Supply Current Comparator (When Enabled) Response Time Overdrive, Load 0.4V 4.6V Conditions 0.4V 1.5V 300k Units
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COP888xG/CS Family
Comparators Characteristics
(Continued)
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FIGURE MICROWIRE/PLUS Timing
Typical Performance Characteristics
(-55°C +125°C)
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COP888xG/CS Family
Typical Performance Characteristics
(-55°C +125°C) (Continued)
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COP888xG/CS Family
Typical Performance Characteristics
(-55°C +125°C) (Continued)
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Descriptions
power supply pins. pins must connected. clock input. This come from generated oscillator, crystal oscillator conjunction with CKO). Oscillator Description section. RESET master reset input. Reset Description section. device contains three bidirectional 8-bit ports where each individual independently configured input (Schmitt Trigger inputs ports output TRI-STATE under program control. Three data memory address locations allocated each these ports. Each port associated 8-bit memory mapped registers, CONFIGURATION register output DATA register. memory mapped address also reserved input pins each port. (See memory various addresses associated with ports.) Figure shows port configurations. DATA CONFIGURATION registers allow each port individually configured under software control shown below:
CONFIGURATION Register DATA Register Hi-Z Input (TRI-STATE Output) Input with Weak Pull-Up Push-Pull Zero Output Push-Pull Output Port Set-Up
MIWU MIWU MIWU Port 8-bit port with pins (G0, G2-G5), input (G6), dedicated output (G1). Pins G2-G6 have Schmitt Triggers their inputs. serves dedicated WDOUT WATCHDOG output, while either input output depending oscillator mask option selected. With crystal oscillator option selected, serves dedicated output clock output. With single-pin oscillator mask option selected, serves general purpose input also used bring device HALT mode with high transition There registers associated with Port, data register configuration register. Therefore, each bits (G0, G2-G5) individually configured under software control. Since input only dedicated clock output (crystal clock option) general purpose input (R/C clock option), associated bits data configuration registers used special purpose functions outlined next page. Reading data bits will return zeros.
PORT 8-bit port. L-pins have Schmitt triggers inputs. Port supports Multi-Input Wake eight pins. used USART external clock. used USART transmit receive. used timer input functions T2B. used timer input functions (execpt series). Port following alternate features: MIWU MIWU MIWU MIWU MIWU
DS012829-5
FIGURE Port Configurations Note that chip will placed HALT mode writing Port Data Register. Similarly chip will placed IDLE mode writing Port Data Register. Writing Port Configuration Register enables MICROWIRE/PLUS operate with alternate
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COP888xG/CS Family
Descriptions
(Continued)
phase clock. configuration bit, high, enables clock start delay after HALT when clock configuration used. Config Reg. CLKDLY Alternate Data Reg. HALT IDLE
8-bit stack pointer, which points subroutine/ interrupt stack RAM). initialized address with reset. 8-bit Data Segment Address Register used extend lower half address range into data segments bytes each. registers memory mapped with exception Accumulator Program Counter (PC). PROGRAM MEMORY program memory consists kbytes ROM. These bytes hold program instructions constant data (data tables LAID instruction, jump vectors instruction, interrupt vectors instruction). program memory addressed 15-bit program counter (PC). interrupts devices vector program memory location Hex. DATA MEMORY data memory address space includes on-chip data registers, registers (Configuration, Data Pin), control registers, MICROWIRE/PLUS shift register, various registers, counters associated with timers (with exception IDLE timer). Data memory addressed directly instruction indirectly pointers register. data memory consists bytes RAM. Sixteen bytes mapped "registers" addresses Hex. These registers loaded immediately, also decremented tested with DRSZ (decrement register skip zero) instruction. memory pointer registers memory mapped into this space address locations respectively, with other registers being available general usage. instruction permits memory set, reset tested. registers (except memory mapped; therefore, bits register bits directly individually set, reset tested. accumulator bits also directly individually tested.
Note: contents undefined upon power-up.
Port following alternate features: (MICROWIRE Serial Data Input) (MICROWIRE Serial Clock) (MICROWIRE Serial Data Output) (Timer I/O) (Timer Capture Input) INTR (External Interrupt Input) Port following dedicated functions: Oscillator dedicated output general purpose input WDOUT WATCHDOG and/or Clock Monitor dedicated output Port 8-bit port. 40-pin device does have full complement Port pins. unavailable pins terminated. read operation these unterminated pins will return unpredicatable values. Port eight-bit Hi-Z input port. Port I1-I3 used Comparator Port I4-I6 used Comparator Port following alternate features: COMP2OUT (Comparator Output) COMP2+IN (Comparator Positive Input) COMP2-IN (Comparator Negative Input) COMP1OUT (Comparator Output) COMP1+IN (Comparator Positive Input) COMP1-IN (Comparator Negative Input) Port 8-bit output port that preset high when RESET goes low. user more port outputs (except together order higher drive.
Functional Description
architecture device modified Harvard architecture. With Harvard architecture, control store program memory (ROM) separated from data store memory (RAM). Both have their separate addressing space with separate address buses. architecture, though based Harvard architecture, permits transfer data from RAM. REGISTERS 8-bit addition, subtraction, logical shift operation instruction (tc) cycle time. There registers: 8-bit Accumulator Register 15-bit Program Counter Register upper bits program counter (PC) lower bits program counter (PC) 8-bit address pointer, which optionally post auto incremented decremented. 8-bit alternate address pointer, which optionally post auto incremented decremented.
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Data Memory Segment Extension
Data memory address used memory mapped location Data Segment Address Register (S). data store memory either addressed directly single byte address within instruction, indirectly relative reference pointers (each contains single-byte address). This single-byte address allows addressing range locations from hex. upper this single-byte address divides data store memory into separate sections outlined previously. With exception register memory from address locations 00F0 00FF, memory memory mapped with upper single-byte address being equal zero. This allows upper single-byte address determine whether base address range (from 0000 00FF) extended. this upper equals (representing address range 0080 00FF), then address extension does take place. Alternatively, this upper equals zero, then data segment extension register used extend base address range (from 0000 007F) from XX00 XX7F, where represents bits from register. Thus 128-byte data segment extensions located from addresses 0100 017F data segment
COP888xG/CS Family
Data Memory Segment Extension (Continued)
0200 027F data segment etc., FF00 FF7F data segment 255. base address range from 0000 007F represents data segment
Figure illustrates register data memory extension used extending lower half base address range hex) into data segments bytes each, with total addressing range kbytes from XX00 XX7F. This organization allows total data segments bytes each with additional upper base segment bytes. Furthermore, addressing modes available data segments. register must changed under program control move from data segment (128 bytes) another. However, upper base segment (containing memory registers, registers, control registers, etc.) always available regardless contents register, since upper base segment (address range 0080 00FF) independent data segment extension. instructions that utilize stack pointer (SP) always reference stack part base segment (Segment regardless contents register. register changed these instructions. Consequently, stack (used with subroutine linkage interrupts) always located base segment. stack pointer will intitialized point data memory location 006F result reset. bytes contained base segment split between lower upper base segments. first bytes resident from address 0000 006F lower base segment, while remaining bytes represent data memory registers located addresses 00F0 00FF upper base segment. located upper sixteen addresses (0070 007F) lower base segment. Additional beyond these initial bytes, however, will always memory mapped groups bytes less) data segment address extensions (XX00 XX7F) lower base segment. additional bytes memory mapped from segment through segment (see Figure
DS012829-6
*Reads ones.
FIGURE Organization
Reset
RESET input when pulled initializes microcontroller. Initialization will occur whenever RESET input pulled low. Upon initialization, data configuration registers ports cleared, resulting these Ports being initialized TRI-STATE mode. Port exception noted below) since dedicated WATCHDOG and/or Clock Monitor error output pin. Port high. PSW, ICNTRL, CNTRL, T2CNTRL T3CNTRL control registers cleared. USART registers PSR, (except that TBMT set), ENUR ENUI cleared. Comparator Select Register cleared. register initialized zero. Multi-Input Wakeup registers WKEN WKEDG cleared. Wakeup register WKPND unknown. stack pointer, initialized hex. device comes reset with both WATCHDOG logic Clock Monitor detector armed, with WATCHDOG service window bits Clock Monitor set. WATCHDOG Clock Monitor circuits inhibited during reset. WATCHDOG service window bits being initialized high default maximum WATCHDOG service window clock cycles. Clock Monitor being initialized high will cause Clock Monitor error following reset clock reached minimum specified frequency termination reset. Clock Monitor error will cause active error output This error output will continue until tC-32 clock cycles following clock frequency reaching minimum specified value, which time output will enter TRI-STATE mode. external network shown Figure should used ensure that RESET held until power supply chip stabilizes.
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COP888xG/CS Family
Reset
(Continued)
(pF)
(pF) 30-36 100-150
Freq (MHz) 0.455
Conditions 2.5V
TABLE Oscillator Configuration, 25°C
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(pF)
Freq (MHz)
Instr. Cycle (µs) 10.8
Conditions
Power Supply Rise Time
FIGURE Recommended Reset Circuit
Oscillator Circuits
chip driven clock input input which between MHz. output clock (crystal configuration). input frequency divided down produce instruction cycle clock (1/tc).
Note: 200k
CONTROL REGISTERS
CNTRL Register (Address X'00EE)
T1C3 T1C2 T1C1 T1C0 MSEL IEDG
Figure shows Crystal oscillator diagrams.
CRYSTAL OSCILLATOR connected make closed loop crystal resonator) controlled oscillator.
Table shows component values required various standard crystal values.
OSCILLATOR selecting single oscillator input, single oscillator circuit connected available general purpose input, and/or HALT restart input.
Table shows variation oscillator frequencies functions component values.
Timer1 (T1) MICROWIRE/PLUS control register contains following bits: T1C3 Timer mode control T1C2 Timer mode control T1C1 Timer mode control T1C0 Timer Start/Stop control timer modes Underflow Interrupt Pending Flag timer mode MSEL Selects MICROWIRE/PLUS signals respectively IEDG External interrupt edge polarity select Rising edge, Falling edge) Select MICROWIRE/PLUS clock divide Register (Address X'00EF)
T1PNDA T1ENA EXPND BUSY EXEN
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FIGURE Crystal Oscillator Diagrams
TABLE Crystal Oscillator Configuration, 25°C (pF) (pF) 30-36 Freq (MHz) Conditions
register contains following select bits: Half Carry Flag Carry Flag T1PNDA Timer Interrupt Pending Flag (Autoreload mode Underflow Mode capture edge mode T1ENA Timer Interrupt Enable Timer Underflow Input capture edge EXPND External interrupt pending BUSY MICROWIRE/PLUS busy shifting flag EXEN Enable external interrupt Global interrupt enable (enables interrupts) Half-Carry flag also affected instructions that affect Carry flag. (Set Carry) (Reset Carry) instructions will respectively clear both carry flags. addition instructions, ADC, SUBC, instructions affect Carry Half Carry flags.
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COP888xG/CS Family
CONTROL REGISTERS
ICNTRL Register (Address X'00E8)
Reserved LPEN T0PND T0EN µWPND
(Continued)
Timers
T1ENB
µWEN
T1PNDB
These devices contain very versatile timers (T0, except series, which only T1). timers associated autoreload/capture registers power containing random data. TIMER (IDLE TIMER) device supports applications that require maintaining real time power with IDLE mode. This IDLE mode support furnished IDLE timer which 16-bit timer. Timer runs continuously fixed rate instruction cycle clock, user cannot read write IDLE Timer which count down timer. Timer supports following functions:
Exit Idle Mode (See Idle Mode description) WATCHDOG logic (See WATCHDOG description) Start delay HALT mode IDLE Timer generate interrupt when thirteenth toggles. This toggle latched into T0PND pending flag, will occur every maximum clock frequency µs). control flag T0EN allows interrupt from thirteenth Timer enabled disabled. Setting T0EN will enable interrupt, while resetting will disable interrupt.
ICNTRL register contains following bits: Reserved This reserved should zero LPEN Port Interrupt Enable (Multi-Input Wakeup/ Interrupt) T0PND Timer Interrupt pending T0EN Timer Interrupt Enable (Bit toggle) µWPND MICROWIRE/PLUS interrupt pending µWEN Enable MICROWIRE/PLUS interrupt T1PNDB Timer Interrupt Pending Flag capture edge T1ENB Timer Interrupt Enable Input capture edge T2CNTRL Register (Address X'00C6)
T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB
T2CNTRL control register contains following bits: T2C3 Timer mode control T2C2 Timer mode control T2C1 Timer mode control T2C0 Timer Start/Stop control timer modes Underflow Interrupt Pending Flag timer mode T2PNDA Timer Interrupt Pending Flag (Autoreload mode Underflow mode capture edge mode T2ENA Timer Interrupt Enable Timer Underflow Input capture edge T2PNDB Timer Interrupt Pending Flag capture edge T2ENB Timer Interrupt Enable Timer Underflow Input capture edge
Note: T2CNTRL register available series.
T3CNTRL Register (Address X'00B6)
T3C3 T3C2 T3C1 T3C0 T3PNDA T3ENA T3PNDB T3ENB
TIMER TIMER TIMER These devices have three powerful timer/ counter blocks, associated features functioning timer block described referring timer block Since three timer blocks, identical, comments equally applicable three timer blocks. Each timer block consists 16-bit timer, supporting 16-bit autoreload/capture registers, RxB. Each timer block pins associated with TxB. supports required timer block, while input timer block. powerful flexible timer block allows device easily perform timer functions with minimal software overhead. timer block three operating modes: Processor Independent mode, External Event Counter mode, Input Capture mode. control bits TxC3, TxC2, TxC1 allow selection different modes operation. Mode Processor Independent Mode name suggests, this mode allows device generate signal with very minimal user intervention. user only define parameters signal time time). Once begun, timer block will continuously generate signal completely independent microcontroller. user software services timer block only when parameters require updating. this mode timer counts down fixed rate Upon every underflow timer alternately reloaded with contents supporting registers, RxB. very first underflow timer causes timer reload from register RxA. Subsequent underflows cause timer reloaded from registers alternately beginning with register RxB. Timer control bits, TxC3, TxC2 TxC1 timer mode operation.
T3CNTRL control register contains following bits: T3C3 Timer mode control T3C2 Timer mode control T3C1 Timer mode control T3C0 Timer Start/Stop control timer modes Underflow Interrupt Pending Flag timer mode T3PNDA Timer Interrupt Pending Flag (Autoreload mode Underflow mode capture edge mode T3ENA Timer Interrupt Enable Timer Underflow Input capture edge T3PNDB Timer Interrupt Pending Flag capture edge T3ENB Timer Interrupt Enable Timer Underflow Input capture edge
Note: T3CNTRL regoster avao;ab;e series.
Figure shows block diagram timer mode.
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COP888xG/CS Family
Timers
(Continued)
underflows programmed toggle output pin. underflows also programmed generate interrupts. Underflows from timer alternately latched into pending flags, TxPNDA TxPNDB. user must reset these pending flags under software control. control enable flags, TxENA TxENB, allow interrupts from timer underflow enabled disabled. Setting timer enable flag TxENA will cause interrupt when timer underflow causes register reloaded into timer. Setting timer enable flag TxENB will cause interrupt when timer underflow causes register reloaded into timer. Resetting timer enable flags will disable associated interrupts. Either both timer underflow interrupts enabled. This gives user flexibility interrupting once period either rising falling edge output. Alternatively, user choose interrupt both edges output.
DS012829-11
FIGURE Timer External Event Counter Mode Mode Input Capture Mode device precisely measure external frequencies time external events placing timer block, input capture mode. this mode, timer constantly running fixed rate. registers, RxB, capture registers. Each register acts conjunction with pin. register acts conjunction with register acts conjunction with pin. timer value gets copied over into register when trigger event occurs corresponding pin. Control bits, TxC3, TxC2 TxC1, allow trigger events specified either positive negative edge. trigger condition each input specified independently. trigger conditions also programmed generate interrupts. occurrence specified trigger condition pins will respectively latched into pending flags, TxPNDA TxPNDB. control flag TxENA allows interrupt either enabled disabled. Setting TxENA flag enables interrupts generated when selected trigger condition occurs pin. Similarly, flag TxENB controls interrupts from pin. Underflows from timer also programmed generate interrupts. Underflows latched into timer TxC0 pending flag (the TxC0 control serves timer underflow interrupt pending flag Input Capture mode). Consequently, TxC0 control should reset when entering Input Capture mode. timer underflow interrupt enabled with TxENA control flag. When interrupt occurs Input Capture mode, user must check both TxPNDA TxC0 pending flags order determine whether input capture timer underflow both) caused interrupt.
DS012829-10
FIGURE Timer Mode Mode External Event Counter Mode This mode quite similar processor independent mode described above. main difference that timer, clocked input signal from pin. timer control bits, TxC3, TxC2 TxC1 allow timer clocked either positive negative edge from pin. Underflows from timer latched into TxPNDA pending flag. Setting TxENA control flag will cause interrupt when timer underflows. this mode input used independent positive edge sensitive interrupt input TxENB control flag set. occurrence positive edge input latched into TxPNDB flag.
Figure shows block diagram timer External Event Counter mode.
Note: output available this mode since being used counter input clock.
Figure shows block diagram timer Input Capture mode.
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COP888xG/CS Family
Timers
(Continued)
DS012829-12
FIGURE Timer Input Capture Mode TIMER CONTROL FLAGS control bits their functions summarized below. TxC3 Timer mode control TxC2 Timer mode control TxC1 Timer mode control TxC0 Timer Start/Stop control Modes (Processor Independent External Event Counter), where Start, Stop Timer Underflow Interrupt Pending Flag Mode (Input Capture) TxPNDA Timer Interrupt Pending Flag TxENA Timer Interrupt Enable Flag Timer Interrupt Enabled Timer Interrupt Disabled TxPNDB Timer Interrupt Pending Flag TxENB Timer Interrupt Enable Flag Timer Interrupt Enabled Timer Interrupt Disabled
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COP888xG/CS Family
Timers
(Continued)
timer mode control bits (TxC3, TxC2 TxC1) detailed below: Mode TxC3 TxC2 TxC1 Description PWM: Toggle PWM: Toggle External Event Counter External Event Counter Captures: Pos. Edge Pos. Edge Captures: Pos. Edge Neg. Edge Captures: Neg. Edge Neg. Edge Captures: Neg. Edge Neg. Edge Interrupt Source Autoreload Autoreload Timer Underflow Timer Underflow Pos. Edge Timer Underflow Pos. Edge Timer Underflow Neg. Edge Timer Underflow Neg. Edge Timer Underflow running immediately since crystal oscillators ceramic resonators have delayed start time reach full amplitude frequency stability. IDLE timer used generate fixed delay ensure that oscillator indeed stabilized before allowing instruction execution. this case, upon detecting valid Wakeup signal, only oscillator circuitry enabled. IDLE timer loaded with value clocked with instruction cycle clock. clock derived dividing oscillator clock down factor Schmitt trigger following inverter chip ensures that IDLE timer clocked only when oscillator sufficiently large amplitude meet Schmitt trigger specifications. This Schmitt trigger part oscillator closed loop. startup timeout from IDLE timer enables clock signals routed rest chip. clock option being used, fixed delay introduced optionally. control bit, CLKDLY, mapped configuration controls whether delay introduced not. delay included CLKDLY set, excluded CLKDLY reset. CLKDLY cleared reset. device mask options associated with HALT mode. first mask option enables HALT mode feature, while second mask option disables HALT mode. With HALT mode enable mask option, device will enter exit HALT mode described above. With HALT disable mask option, device cannot placed HALT mode (writing HALT flag will have effect, HALT flag will remain "0"). IDLE MODE device placed IDLE mode writing IDLE flag data bit). this mode, activities, except associated on-board oscillator circuitry IDLE Timer stopped. power supply requirements
Interrupt Source Autoreload Autoreload Pos. Edge Pos. Edge Pos. Edge
Timer Counts Pos. Edge Pos. Edge
Neg. Edge Neg. Edge Neg. Edge
Power Save Modes
device offers user power save modes operation: HALT IDLE. HALT mode, microcontroller activities stopped. IDLE mode, on-board oscillator circuitry timer active other microcontroller activities stopped. either mode, on-board RAM, registers, states, timers (with exception unaltered. HALT MODE device placed HALT mode writing HALT flag data bit). microcontroller activities, including clock timers, stopped. WATCHDOG logic device disabled during HALT mode. However, clock monitor circuitry enabled remains active will cause WATCHDOG output (WDOUT) low. HALT mode used user does want activate WDOUT pin, Clock Monitor should disabled after device comes reset (resetting Clock Monitor control with first write WDSVR register). HALT mode, power requirements device minimal applied voltage (VCC) decreased 2.0V) without altering state machine. device supports three different ways exiting HALT mode. first method exiting HALT mode with Multi-Input Wakeup feature port. second method with high transition (G7) pin. This method precludes crystal clock configuration (since becomes dedicated output), only used with clock configuration. third method exiting HALT mode pulling RESET low. Since crystal ceramic resonator selected oscillator, Wakeup signal allowed start chip
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COP888xG/CS Family
Power Save Modes
(Continued)
micro-controller this mode operation typically around normal power requirement microcontroller. with HALT mode, device returned normal operation with reset, with Multi-Input Wakeup from Port. Alternately, microcontroller resumes normal operation from IDLE mode when thirteenth (representing 4.096 internal clock frequency MHz, IDLE Timer toggles. This toggle condition thirteenth IDLE Timer latched into T0PND pending flag. user option being interrupted with transition thirteenth IDLE Timer interrupt enabled disabled T0EN control bit. Setting T0EN flag enables interrupt vice versa. user enter IDLE mode with Timer interrupt enabled. this case, when T0PND gets set,
device will first execute Timer interrupt service routine then return instruction following "Enter Idle Mode" instruction. Alternatively, user enter IDLE mode with IDLE Timer interrupt disabled. this case, device will resume normal operation with instruction immediately following "Enter IDLE Mode" instruction.
Note: necessary program instructions following both HALT mode IDLE mode instructions. These instructions necessary allow clock resynchronization following HALT IDLE modes.
Multi-Input Wakeup
Multi-Input Wakeup feature return (wakeup) device from either HALT IDLE modes. Alternately Multi-Input Wakeup/Interrupt feature also used generate edge selectable external interrupts.
Figure shows Multi-Input Wakeup logic.
DS012829-13
FIGURE Multi-Input Wake Logic Multi-Input Wakeup feature utilizes Port. user selects which particular port combination Port bits) will cause device exit HALT IDLE modes. selection done through Register WKEN. Register WKEN 8-bit read/write register, which contains control every port bit. Setting particular WKEN enables Wakeup from associated port pin. user select whether trigger condition selected Port going either positive edge (low high transition) negative edge (high transition). This selection made Register WKEDG, which 8-bit control register with assigned each Port pin. Setting control will select trigger condition negative edge that particular Port pin. Resetting selects trigger condition positive edge. Changing
edge select entails several steps order avoid Wakeup condition result edge change. First, associated WKEN should reset, followed edge select change WKEDG. Next, associated WKPND should cleared, followed associated WKEN being re-enabled. example serve clarify this procedure. Suppose wish change edge select from positive (low going high) negative (high going low) Port where previously been enabled input interrupt. program would follows: RBIT WKEN Disable MIWU SBIT WKEDG Change edge polarity RBIT WKPND Reset pending flag SBIT WKEN Enable MIWU
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COP888xG/CS Family
Multi-Input Wakeup
(Continued)
port bits have been used outputs then changed inputs with Multi-Input Wakeup/Interrupt, safety procedure should also followed avoid wakeup conditions. After selected port bits have been changed from output input before associated WKEN bits enabled, associated edge select bits WKEDG should reset desired edge selects, followed associated WKPND bits being cleared. This same procedure should used following reset, since port inputs left floating result reset. occurrence selected trigger condition Multi-Input Wakeup latched into pending register called WKPND. respective bits WKPND register will occurrence selected trigger edge corresponding Port pin. user responsibility clearing these pending flags. Since WKPND pending register occurrence selected wakeup conditions, device will enter HALT mode Wakeup both enabled pending. Consequently, user must clear pending flags before attempting enter HALT mode. WKEN, WKPND WKEDG read/write registers, cleared reset. PORT INTERRUPTS Port provides user with additional eight fully selectable, edge sensitive interrupts which vectored into same service subroutine. interrupt from Port shares logic with wake circuitry. register WKEN allows interrupts from Port individually enabled disabled. register WKEDG specifies trigger condition either positive negative edge. Finally, register WKPND latches pending trigger conditions. (Global Interrupt Enable) enables interrupt function. control flag, LPEN, functions global interrupt enable Port interrupts. Setting LPEN flag will enable interrupts vice versa. separate global pending flag needed since register WKPND adequate. Since Port also used waking device HALT IDLE modes, user elect exit HALT IDLE modes either with without interrupt enabled. elects disable interrupt, then device will restart execution from instruction immediately following instruction that placed microcontroller HALT IDLE modes. other case, device will first execute interrupt service routine then revert normal operation. (See HALT MODE clock option wakeup information.)
Wakeup signal will start chip running immediately since crystal oscillators ceramic resonators have finite start time. IDLE Timer (T0) generates fixed delay ensure that oscillator indeed stabilized before allowing device execute instructions. this case, upon detecting valid Wakeup signal, only oscillator circuitry IDLE Timer enabled. IDLE Timer loaded with value clocked from instruction cycle clock. clock derived dividing down oscillator clock factor Schmitt trigger following on-inverter ensures that IDLE timer clocked only when oscillator sufficiently large amplitude meet Schmitt trigger specifications. This Schmitt trigger part oscillator closed loop. start-up time-out from IDLE timer enables clock signals routed rest chip. clock option used, fixed delay under software control. control flag, CLKDLY, configuration allows clock start delay optionally inserted. Setting CLKDLY flag high will cause clock start delay inserted resetting will exclude clock start delay. CLKDLY flag high will cause clock start delay. CLKDLY flag cleared during reset, clock start delay present following reset with clock options.
USART
device contains full-duplex software programmable USART. USART (Figure consists transmit shift register, receive shift register seven addressable registers, follows: transmit buffer register (TBUF), receiver buffer register (RBUF), USART control status register (ENU), USART receive control status register (ENUR), USART interrupt clock source register (ENUI), prescaler select register (PSR) baud (BAUD) register. register contains flags transmit receive functions; this register also determines length data frame bits), value ninth transmission, parity selection bits. ENUR register flags framing, data overrun parity errors while USART receiving. Other functions ENUR register include saving ninth received data frame, enabling disabling USART's attention mode operation providing additional receiver/transmitter status information RCVG XMTG bits. determination internal external clock source done ENUI register, well selecting number stop bits enabling disabling transmit receive interrupts. control flag this register also select USART mode operation: asynchronous synchronous.
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COP888xG/CS Family
USART
(Continued)
DS012829-14
FIGURE USART Block Diagram USART CONTROL STATUS REGISTERS operation USART programmed through three registers: ENU, ENUR ENUI. DESCRIPTION USART REGISTER BITS ENU-USART Control Status Register (Address 0BA)
PSEL1 XBIT9/ PSEL0 CHL1 CHL0 RBFL TBMT
PEN: This enables/disables Parity 8-bit modes only). Read/Write, cleared reset. Parity disabled.
Parity enabled. PSEL1, PSEL0: Parity select bits. Read/Write, cleared reset. PSEL1 PSEL0 Parity Parity enabled) PSEL1 PSEL0 Even Parity Parity enabled) PSEL1 PSEL0 Mark(1) Parity enabled) PSEL1 PSEL0 Space(0) Parity enabled) XBIT9/PSEL0: Programs ninth transmission when USART operating with nine data bits frame. seven eight data bits frame, this conjunction with PSEL1 selects parity. Read/Write, cleared reset.
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COP888xG/CS Family
USART
(Continued)
CHL1, CHL0: These bits select character frame format. Parity included generated/verified hardware. Read/Write, cleared reset. CHL1 CHL0 CHL1 CHL0 frame contains eight data bits. frame contains seven data bits. CHL1 CHL0 frame contains nine data bits. CHL1 CHL0 Loopback Mode selected. Transmitter output internally looped back receiver input. Nine framing format used. ERR: This global USART error flag which gets combination errors (DOE, occur. Read only; cannot written software, cleared reset. RBFL: This when USART received complete character copied into RBUF register. automatically reset when software reads character from RBUF. Read only; cannot written software, cleared reset. TBMT: This when USART transfers byte data from TBUF register into TSFT register transmission. automatically reset when software writes into TBUF register. Read only, "one" reset; cannot written software. ENUR-USART Receive Control Status Register (Address 0BB)
Note reserved future use. User must zero.
RCVG: This high whenever framing error occurs goes when goes high. Read only, cleared reset. ENUI-USART Interrupt Clock Source Register (Address 0BC)
STP2 STP78 ETDX SSEL XRCLK XTCLK
Reserved (Note
RBIT9
ATTN
XMTG
RCVG
DOE: Flags Data Overrun Error. Read only, cleared read, cleared reset. Indicates Data Overrun Error been detected since last time ENUR register read. Indicates occurrence Data Overrun Error. Flags Framing Error. Read only, cleared read, cleared reset. Indicates Framing Error been detected since last time ENUR register read. Indicates occurrence Framing Error. Flags Parity Error. Read only, cleared read, cleared reset. Indicates Parity Error been detected since last time ENUR register read. Indicates occurrence Parity Error. SPARE: Reserved future use. Read/Write, cleared reset. RBIT9: Contains ninth data received when USART operating with nine data bits frame. Read only, cleared reset. ATTN: ATTENTION Mode enabled while this set. This cleared automatically receiving character with data nine set. Read/Write, cleared reset. XMTG: This indicate that USART transmitting. gets reset last frame (end last Stop bit). Read only, cleared reset.
STP2: This programs number Stop bits transmitted. Read/Write, cleared reset. STP2 Stop transmitted. STP2 Stop bits transmitted. STP78: This program last Stop 7/8th length. Read/Write, cleared reset. ETDX: (USART Transmit Pin) alternate function assigned Port selected setting ETDX bit. simulate line break generation, software should reset ETDX output logic zero through Port data configuration registers. Read/Write, cleared reset. SSEL: USART mode select. Read/Write, cleared reset. SSEL Asynchronous Mode. SSEL Synchronous Mode. XRCLK: This selects clock source receiver section. Read/Write, cleared reset. XRCLK clock source selected through BAUD registers. XRCLK Signal (L1) used clock. XTCLK: This selects clock source transmitter section. Read/Write, cleared reset. XTCLK clock source selected through BAUD registers. XTCLK Signal (L1) used clock. ERI: This enables/disables interrupt from receiver section. Read/Write, cleared reset. Interrupt from receiver disabled. Interrupt from receiver enabled. ETI: This enables/disables interrupt from transmitter section. Read/Write, cleared reset. Interrupt from transmitter disabled. Interrupt from transmitter enabled.
Associated Pins
Data transmitted received pin. alternate function assigned Port selected setting ETDX ENUI register) one. inherent function Port requiring setup. baud rate clock USART generated on-chip, taken from external source. Port (CKX) external clock pin. either input output, determined Port Configuration Data registers (Bit input, accepts clock signal which selected drive transmitter and/or receiver. output, presents internal Baud Rate Generator output.
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COP888xG/CS Family
USART Operation
USART modes operation: asynchronous mode synchronous mode. ASYNCHRONOUS MODE This mode selected resetting SSEL ENUI register) zero. input frequency USART times baud rate. TSFT TBUF registers double-buffer data transmission. While TSFT shifting current character pin, TBUF register loaded software with next byte transmitted. When TSFT finishes transmitting current character contents TBUF transferred TSFT register Transmit Buffer Empty Flag (TBMT register) set. TBMT flag automatically reset USART when software loads character into TBUF register. There also XMTG which indicate that USART transmitting. This gets reset last frame (end last Stop bit). TBUF read/write register. RSFT RBUF registers double-buffer data being received. USART receiver continually monitors signal level detect beginning Start bit. Upon sensing this level, waits half time samples again. still low, receiver considers this valid Start bit, remaining bits character frame each sampled single time, mid-bit position. Serial data input shifted into RSFT register. Upon receiving complete character, contents RSFT register copied into RBUF register Received Buffer Full Flag (RBFL) set. RBFL automatically reset when software reads character from RBUF register. RBUF read only register. There also RCVG which high when framing error occurs goes once goes high. TBMT, XMTG, RBFL RCVG read only bits. SYNCHRONOUS MODE this mode data transferred synchronously with clock. Data transmitted rising edge received falling edge synchronous clock. This mode selected setting SSEL ENUI register. input frequency USART same baud rate. When external clock input selected pin, data transmit receive performed synchronously with this clock through TDX/RDX pins. data transmit receive selected with clock output, device generates synchronous clock
output pin. internal baud rate generator used produce synchronous clock. Data transmit receive performed synchronously with this clock. FRAMING FORMATS USART supports several serial framing formats (Figure 13). format selected using control bits ENU, ENUR ENUI registers. first format data transmission (CHL0 CHL1 consists Start bit, seven Data bits (excluding parity) 7/8, Stop bits. applications using parity, parity generated verified hardware. second format (CHL0 CHL1 consists Start bit, eight Data bits (excluding parity) 7/8, Stop bits. Parity generated verified hardware. third format transmission (CHL0 CHL1 consists Start bit, nine Data bits 7/8, Stop bits. This format also supports USART "ATTENTION" feature. When operating this format, eight bits TBUF RBUF used data. ninth data transmitted received using bits ENUR registers, called XBIT9 RBIT9. RBIT9 read only bit. Parity generated verified this mode. above framing formats, last Stop programmed 7/8th length. Stop bits selected 7/8th (selected), second Stop will 7/8th length. parity enabled/disabled located register. Parity selected 8-bit modes only. parity enabled (PEN parity selection then performed PSEL0 PSEL1 bits located register. Note that XBIT9/PSEL0 located register serves mutually exclusive functions. This programs ninth transmission when USART operating with nine data bits frame. There parity selection this framing format. other framing formats XBIT9 needed PSEL0 used conjunction with PSEL1 select parity. frame formats receiver differ from transmitter number Stop bits required. receiver only requires Stop frame, regardless setting Stop selection bits control register. Note that implicit assumption made full duplex USART operation that framing formats same transmitter receiver.
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COP888xG/CS Family
USART Operation
(Continued)
DS012829-15
FIGURE Framing Formats USART INTERRUPTS USART capable generating interrupts. Interrupts generated Receive Buffer Full Transmit Buffer Empty. Both interrupts have individual interrupt vectors. bytes program memory space reserved each interrupt vector. vectors located addresses 0xEC 0xEF program memory space. interrupts individually enabled disabled using Enable Transmit Interrupt (ETI) Enable Receive Interrupt (ERI) bits ENUI register. interrupt from Transmitter pending, remains pending, long both TBMT bits set. remove this interrupt, software must either clear write TBUF register (thus clearing TBMT bit). interrupt from receiver pending, remains pending, long both RBFL bits set. remove this interrupt, software must either clear read from RBUF register (thus clearing RBFL bit). basic baud clock created from oscillator frequency through two-stage divider chain consisting 1-16 (increments 0.5) prescaler 11-bit binary counter. (Figure 14). divide factors specified through read/ write registers shown Figure Note that 11-bit Baud Rate Divisor spills over into Prescaler Select Register (PSR). cleared upon reset. shown Table Prescaler Factor corresponds CLOCK. This condition USART power down mode where USART clock turned power saving purpose. user must also turn USART clock when different baud rate chosen. correspondences between 5-bit Prescaler Select Prescaler factors shown Table There many ways calculate divisor factors, particularly effective method would achieve 1.8432 frequency coming first stage. 1.8432 prescaler output then used drive software programmable baud rate counter create clock following baud rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400, 3600, 4800, 7200, 9600, 19200 38400 (Table Other baud rates created using appropriate divisors. clock then divided provide rate serial shift registers transmitter receiver.
Baud Clock Generation
clock inputs transmitter receiver sections USART individually selected come either from external source (port from source selected BAUD registers. Internally,
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COP888xG/CS Family
Baud Clock Generation
(Continued)
DS012829-16
FIGURE USART BAUD Clock Generation
DS012829-17
FIGURE USART BAUD Clock Divisor Registers TABLE Baud Rate Divisors (1.8432 Prescaler Output) Baud Rate (110.03) 134.5 (134.58) 1200 1800 2400 3600 4800 7200 9600 19200 38400 Baud Rate Divisor (N-1) 1046
Prescaler Select 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
Prescaler Factor 10.5 11.5 12.5 13.5 14.5 15.5
Note: entries Table assume prescaler output 1.8432 MHz. asynchronous mode baud rate could high 625k.
TABLE Prescaler Factors Prescaler Select 00000 00001 00010 00011 00100 00101 00110 00111 Prescaler Factor CLOCK
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COP888xG/CS Family
Baud Clock Generation
4.608/1.8432
(Continued)
example, considering Asynchronous Mode clock 4.608 MHz, prescaler factor selected entry available Table 1.8432 prescaler output then used with proper Baud Rate Divisor (Table obtain different baud rates. baud rate 19200 e.g., entry Table value from Table Baud Rate Divisor) Baud Rate 1.8432 MHz/(16 19200 divide performed because asynchronous mode, input frequency USART times baud rate. equation calculate baud rates given below. actual Baud Rate found from: Fc/(16 Where: Baud Rate frequency Baud Rate Divisor (Table Prescaler Divide Factor selected value Prescaler Select Register (Table
Note: Synchronous Mode, divisor replaced two.
cause finite start time requirement crystal oscillator. idle timer (T0) generates fixed (256 delay ensure that oscillator indeed stabilized before allowing device execute code. user consider this delay when data transfer expected immediately after exiting HALT mode.
Diagnostic
Bits CHARL0 CHARL1 register provide loopback feature diagnostic testing USART. When these bits one, following occur: receiver input (RDX) internally connected transmitter output (TDX); output Transmitter Shift Register "looped back" into Receive Shift Register input. this mode, data that transmitted immediately received. This feature allows processor verify transmit receive data paths USART. Note that framing format this mode nine format; Start bit, nine data bits, 7/8, Stop bits. Parity generated verified this mode.
Attention Mode
USART Receiver section supports alternate mode operation, referred ATTENTION Mode. This mode operation selected ATTN ENUR register. data format transmission must also selected having nine Data bits either 7/8, Stop bits. ATTENTION mode operation intended networking device with other processors. Typically such environments messages consists device addresses, indicating which several destinations should receive them, actual data. This Mode supports scheme which addresses flagged having ninth data field ninth reset zero byte Data byte. While ATTENTION mode, USART monitors communication flow, ignores characters until address character received. Upon receiving address character, USART signals that character ready setting RBFL flag, which turn interrupts processor USART Receiver interrupts enabled. ATTN also cleared automatically this point, that data characters well address characters recognized. Software examines contents RBUF responds deciding either accept subsequent data stream leaving ATTN reset) wait until next address character seen setting ATTN again). Operation USART Transmitter affected selection this Mode. value ninth transmitted programmed setting XBIT9 appropriately. value ninth received obtained reading RBIT9. Since this located ENUR register where error flags reside, operation will reset error flags.
Example: Asynchronous Mode: Crystal Frequency Desired baud rate 9600 Using above equation calculated first. 106)/(16 9600) 32.552 32.552 divided each Prescaler Factor (Table obtain value closest integer. This factor happens 6.5). 32.552/6.5 5.008 programmed value (from Table should Using above values calculated 106)/(16 6.5) 9615.384 error (9615.385 9600)/9600 0.16%
Effect HALT/IDLE
USART logic reinitialized when either HALT IDLE modes entered. This reinitialization sets TBMT flag resets read only bits USART control status registers. Read/Write bits remain unchanged. Transmit Buffer (TBUF) affected, Transmit Shift register (TSFT) bits one. receiver registers RBUF RSFT affected. device will exit from HALT/IDLE modes when Start character detected (L3) pin. This feature obtained using Multi-Input Wakeup scheme provided device. Before entering HALT IDLE modes user program must select Wakeup source pin. This selection done setting WKEN (Wakeup Enable) register. Wakeup trigger condition then selected high transition. This done WKEDG register (Bit one.) device halted crystal oscillator used, Wakeup signal will start chip running immediately bewww.national.com
Comparators
device contains differential comparators, each with pair inputs (positive negative) output. Ports I1-I3 I4-I6 used comparators. following Port assignment: Comparator2 output Comparator2 positive input Comparator2 negative input Comparator1 output
COP888xG/CS Family
Comparators
(Continued)
Comparator1 positive input Comparator1 negative input
Only Comparator available series. Comparator Select Register (CMPSL) used enable comparators, read outputs comparators internally, enable outputs comparators pins. control bits (enable output enable) result CMPSL REGISTER (ADDRESS X'00B7) Reserved CMPSL register contains following bits: Reserved These bits reserved must zero CMP20E Selects comparator output provided that CMP2EN enable comparator CMP2RD Comparator result (this read only bit, which will read comparator enabled) CMP2EN Enable comparator CMP10E Selects comparator output provided that CMPIEN enable comparator CMP1RD Comparator result (this read only bit, which will read comparator enabled) CMP1EN Enable comparator
Note: compatibility with existing code with existing Mask ROMMed devices bits CMPSL register will take precedence over associated Port configuration data output bits.
associated with each comparator. comparator result bits (CMP1RD CMP2RD) read only bits which will read zero associated comparator enabled. Comparator Select Register cleared with reset, resulting comparators being disabled. comparators should also disabled before entering either HALT IDLE modes order save power. configuration CMPSL register follows:
CMP20E
CMP2RD
CMP2EN
CMP10E
CMP1RD
CMP1EN
Reserved
Interrupts
INTRODUCTION Each device supports thirteen vectored interrupts. Interrupt sources include Timer Timer Timer Timer Port Wakeup, Software Trap, MICROWIRE/PLUS, External Input. interrupts force branch location 00FF program memory. instruction used vector appropriate service routine from location 00FF Hex. Software trap highest priority while default lowest priority. Each maskable inputs fixed arbitration ranking vector.
Figure shows Interrupt Block Diagram.
DS012829-42
FIGURE Interrupt Block Diagram
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COP888xG/CS Family
Interrupts
(Continued)
MASKABLE INTERRUPTS interrupts other than Software Trap maskable. Each maskable interrupt associated enable pending flag bit. pending when interrupt condition occurs. state interrupt enable bit, combined with determines whether active pending flag actually triggers interrupt. maskable interrupt pending enable bits contained mapped control registers, thus controlled software. maskable interrupt condition triggers interrupt under following conditions: enable associated with that interrupt set. set. device processing non-maskable interrupt. non-maskable interrupt being serviced, maskable interrupt must wait until that service routine completed.) interrupt triggered only when these conditions beginning instruction. different maskable interrupts meet these conditions simultaneously, highest priority interrupt will serviced first, other pending interrupts must wait. Upon Reset, pending bits, individual enable bits, reset zero. Thus, maskable interrupt condition cannot trigger interrupt until program enables setting both individual enable bit. When enabling interrupt, user should consider whether previously activated (set) pending should acknowledged. time interrupt enabled, previous occurrences interrupt should ignored, associated pending must reset zero prior enabling interrupt. Otherwise, interrupt simply enabled; pending already set, will immediately trigger interrupt. maskable interrupt active associated enable pending bits set. interrupt asychronous event which occur before, during, after instruction cycle. interrupt which occurs during execution instruction acknowledged until start next normally executed instruction skipped, skip performed before pending interrupt acknowledged. start interrupt acknowledgment, following actions occur: automatically reset zero, preventing subsequent maskable interrupt from interrupting current service routine. This feature prevents maskable interrupt from interrupting another being serviced. address instruction about executed pushed onto stack. program counter (PC) loaded with 00FF Hex, causing jump that program memory location. device requires seven instruction cycles perform actions listed above. user wishes allow nested interrupts, interrupts service routine writing register, thus allow other maskable interrupts interrupt current service routine. nested interrupts allowed, caution must exercised. user must write program such prevent stack overflow, loss saved context information, other unwanted conditions. interrupt service routine stored location 00FF should instruction determine cause
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interrupt, jump interrupt handling routine corresponding highest priority enabled active interrupt. Alternately, user choose poll interrupt pending enable bits determine source(s) interrupt. more than interrupt active, user's program must decide which interrupt service. Within specific interrupt service routine, associated pending should cleared. This typically done early possible service routine order avoid missing next occurrence same type interrupt event. Thus, same event occurs second time, even while first occurrence still being serviced, second occurrence will serviced immediately upon return from current interrupt routine. interrupt service routine typically ends with RETI instruction. This instruction sets back pops address stored stack, restores that address program counter. Program execution then proceeds with next instruction that would have been executed there been interrupt. there valid interrupts pending, highest-priority interrupt serviced immediately upon return from previous interrupt. INSTRUCTION general interrupt service routine, which starts address 00FF Hex, must capable handling types interrupts. instruction, together with interrupt vector table, directs device specific interrupt handling routine based cause interrupt. single-byte instruction, typically used very beginning general interrupt service routine address 00FF Hex, shortly after that point, just after code used context switching. instruction determines which enabled pending interrupt highest priority, causes indirect jump address corresponding that interrupt source. jump addresses (vectors) possible interrupts sources stored vector table. vector table long bytes (maximum vectors) resides 256-byte block containing instruction. However, instruction very 256-byte block (such 00FF Hex), vector table resides next 256-byte block. Thus, instruction located somewhere between 00FF 01DF (the usual case), vector table located between addresses 01E0 01FF Hex. instruction located between 01FF 02DF Hex, then vector table located between addresses 02E0 02FF Hex, Each vector bits long points beginning specific interrupt service routine somewhere kbyte memory space. Each vector occupies bytes vector table, with higher-order byte lower address. vectors arranged order interrupt priority. vector maskable interrupt with lowest rank located 0yE0 (higher-order byte) 0yE1 (lower-order byte). next priority interrupt located 0yE2 0yE3, forth increasing rank. Software Trap highest rank vector always located 0yFE 0yFF. number interrupts which become active defines size table.
Table shows types interrupts, interrupt arbitration ranking, locations corresponding vectors vector table. vector table should filled user with memory locations specific interrupt service routines.
COP888xG/CS Family
Interrupts
(Continued)
ample, Software Trap routine located 0310 Hex, then vector location 0yFE -0yFF should contain data Hex, respectively. When Software Trap interrupt occurs instruction executed, program jumps address specified vector table. interrupt sources vector table listed order rank, from highest lowest priority. more enabled pending interrupts detected same time, with highest priority serviced first. Upon return from interrupt service routine, next highest-level pending interrupt serviced. instruction executed, interrupts enabled pending, lowest-priority interrupt vector used, jump made corresponding address vector table. This unusual occurrence, result error. legitimately result from change enable bits pending flags prior execution instruction, such executing single cycle instruction which clears enable flag same time that pending flag set. also result, however, from inadvertent execution command outside context interrupt. default interrupt vector useful applications which time critical interrupts occur during servicing another interrupt. Rather than restoring pro-
gram context etc.) executing RETI instruction, interrupt service routine terminated returning instruction. this case, interrupts will serviced turn until further interrupts pending default routine started. After testing ensure that execution erroneous, routine should restore program context execute RETI return interrupted program. This technique save fifty instruction cycles (tc), more, (50µs oscillator) latency pending interrupts with penalty fewer than instruction cycles further interrupts pending. ensure reliable operation, user should always instruction determine source interrupt. Although possible poll pending bits detect source interrupt, this practice recommended. polling allows standard arbitration ranking altered, reliability interrupt system compromised. polling routine must individually test enable pending bits each maskable interrupt. Software Trap interrupt should occur, will serviced last, even though should have highest priority. Under certain conditions, Software Trap could triggered serviced, resulting inadvertent "locking out" maskable interrupts Software Trap pending flag. Problems such this avoided using instruction.
TABLE Interrupt Vector Table Arbitration Ranking Highest (10) (11) (12) (13) (14) (15) (16) Lowest Software Reserved External Timer Timer Timer MICROWIRE/PLUS Reserved UART UART Timer Timer Timer Timer Port L/Wakeup Default Receive Transmit T2A/Underflow T2A/Underflow Port Edge Reserved Underflow T1A/Underflow BUSY Source Description INTR Instruction Vector Address (Note TARGET FNXref NS7955*) (Hi-Low Byte) 0yFE-0yFF 0yFC-0yFD 0yFA-0yFB 0yF8-0yF9 0yF6-0yF7 0yF4-0yF5 0yF2-0yF3 0yF0-0yF1 0yEE-0yEF 0yEC-0yED 0yEA-0yEB 0yE8-0yE9 0yE6-0yE7 0yE4-0yE5 0yE2-0yE3 0yE0-0yE1
Note variable which represents block. vector table must located same 256-byte block except located last address block. this case, table must next block.
Reserved series.
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COP888xG/CS Family
Interrupts
Execution
(Continued)
When instruction executed activates arbitration logic. arbitration logic generates even number between (E0, etc.) depending which active interrupt highest arbitration ranking time cycle executed. example, software trap interrupt active, generated. external interrupt active software trap interrupt not, then generated forth. only active interrupt software trap, than generated. This number replaces lower byte upper byte remains unchanged. therefore pointing vector active interrupt with highest arbitration rank-
ing. This vector read from program memory placed into which pointed instruction service routine active interrupt with highest arbitration ranking.
Figure illustrates different steps performed instruction. Figure shows flowchart instruction. non-maskable interrupt pending flag cleared RPND (Reset Non-Maskable Pending Bit) instruction (under certain conditions) upon RESET.
DS012829-43
FIGURE Operation
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COP888xG/CS Family
Interrupts
(Continued)
DS012829-44
FIGURE Flowchart
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COP888xG/CS Family
Interrupts
(Continued)
Programming Example: External Interrupt CNTRL RBIT RBIT SBIT SBIT SBIT .=0FF =00EF =00EE 0,PORTGC 0,PORTGD IEDG, CNTRL EXEN, GIE, WAIT
WAIT:
configured Hi-Z interrupt polarity; falling edge Enable external interrupt Wait external interrupt
interrupt causes branch address causes branch ;interrupt vector table
.=01FA .ADDRW SERVICE INT_EXIT: RETI RBIT
Vector table (within byte inst.) containing interrupt service routine
SERVICE:
EXPND,
Interrupt Service Routine Reset interrupt pend.
INT_EXIT
Return,
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COP888xG/CS Family
Interrupts
(Continued)
NON-MASKABLE INTERRUPT Pending Flag There pending flag associated with non-maskable interrupt, called STPND. This pending flag memorymapped cannot accessed directly software. pending flag reset zero when device Reset occurs. When non-maskable interrupt occurs, associated pending interrupt service routine should contain RPND instruction reset pending flag zero. RPND instruction always resets STPND flag. Software Trap Software Trap special kind non-maskable interrupt which occurs when INTR instruction (used acknowledge interrupts) fetched from program memory placed instruction register. This happen variety ways, usually because error condition. Some examples causes listed below. program counter incorrectly points memory location beyond available program memory space, nonexistent unused memory location returns zeroes which interpreted INTR instruction. stack popped beyond allowed limit (address Hex), 7FFF will loaded into this last location program memory unprogrammed unavailable, Software Trap will triggered. Software Trap triggered temporary hardware condition such brownout power supply glitch. Software Trap highest priority interrupts. When Software Trap occurs, STPND set. affected pending (not accessible user) used inhibit other interrupts direct program service routine with instruction. Nothing interrupt Software Trap service routine except another Software Trap. STPND reset only RPND instruction chip Reset. Software Trap indicates unusual unknown error condition. Generally, returning normal execution point where Software Trap occurred cannot done reliably. Therefore, Software Trap service routine should reinitialize stack pointer perform recovery procedure that restarts software some known point, similar device Reset, necessarily performing same functions device Reset. routine must also execute RPND instruction reset STPND flag. Otherwise, other interrupts will locked out. extent possible, interrupt routine should record indicate context device that cause Software Trap determined. user wishes return normal execution from point which Software Trap triggered, user must first execute RPND, followed RETSK rather than RETI RET. This because return address stored stack address INTR instruction that triggered interrupt. program must skip that instruction order proceed with next one. Otherwise, infinite loop Software Traps returns will occur. Programming return normal execution requires careful consideration. Software Trap routine interrupted another Software Trap, RPND instruction service routine second Software Trap will reset STPND
flag; upon return first Software Trap routine, STPND flag will have wrong state. This will allow maskable interrupts acknowledged during servicing first Software Trap. avoid problems such this, user program should contain Software Trap routine perform recovery procedure rather than return normal execution. Under normal conditions, STPND flag reset RPND instruction Software Trap service routine. programming error hardware condition (brownout, power supply glitch, etc.) sets STPND flag without providing cleared, other interrupts will locked out. alleviate this condition, user extra RPND instructions main program WATCHDOG service routine present). There harm executing extra RPND instructions these parts program. PORT INTERRUPTS Port provides user with additional eight fully selectable, edge sensitive interrupts which vectored into same service subroutine. interrupt from Port shares logic with wake circuitry. register WKEN allows interrupts from Port individually enabled disabled. register WKEDG specifies trigger condition either positive negative edge. Finally, register WKPND latches pending trigger conditions. (Global Interrupt Enable) enables interrupt function. control flag, LPEN, functions global interrupt enable Port interrupts. Setting LPEN flag will enable interrupts vice versa. separate global pending flag needed since register WKPND adequate. Since Port also used waking device HALT IDLE modes, user elect exit HALT IDLE modes either with without interrupt enabled. elects disable interrupt, then device will restart execution from instruction immediately following instruction that placed microcontroller HALT IDLE modes. other case, device will first execute interrupt service routine then revert normal operation. (See HALT MODE clock option wakeup information.) INTERRUPT SUMMARY device uses following types interrupts, listed below order priority: Software Trap non-maskable interrupt, triggered INTR opcode) instruction. Software Trap acknowledged immediately. This interrupt service routine interrupted only another Software Trap. Software Trap should with RPND instructions followed restart procedure. Maskable interrupts, triggered on-chip peripheral block external device connected device. Under ordinary conditions, maskable interrupt will interrupt other interrupt routine progress. maskable interrupt routine progress interrupted non-maskable interrupt request. maskable interrupt routine should with RETI instruction prior restoring context, should return execute instruction. This particularly useful when exiting long interrupt service routiness time between interrupts short. this case RETI instruction would only executed when default routine reached.
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COP888xG/CS Family
WATCHDOG
device contains WATCHDOG clock monitor. WATCHDOG designed detect user program getting stuck infinite loops resulting loss program control "runaway" programs. Clock Monitor used detect absence clock very slow clock below specified rate pin. WATCHDOG consists independent logic blocks: UPPER LOWER. UPPER establishes upper limit service window LOWER defines lower limit service window. Servicing WATCHDOG consists writing specific value WATCHDOG Service Register named WDSVR which memory mapped RAM. This value composed three fields, consisting 2-bit Window Select, 5-bit Data field, 1-bit Clock Monitor Select field. Table shows WDSVR register. TABLE WATCHDOG Service Register (WDSVR) Window Select Data Clock Monitor
occur after coming reset, instruction cycle clock frequency reached minimum specified value, including case where oscillator fails start. WDSVR register written only once after reset data (bits through WDSVR Register) must match valid write. This write WDSVR register involves irrevocable choices: selection WATCHDOG service window (ii) enabling disabling Clock Monitor. Hence, first write WDSVR Register involves selecting deselecting Clock Monitor, select WATCHDOG service window match WATCHDOG data. Subsequent writes WDSVR register will compare value being written user WATCHDOG service window value data (bits through WDSVR Register. Table shows sequence events that occur. user must service WATCHDOG least once before upper limit service window expires. WATCHDOG serviced more than once every lower limit service window. user service WATCHDOG many times wished time period between lower upper limits service window. first write WDSVR Register also counted WATCHDOG service. WATCHDOG output associated with This WDOUT pin, port WDOUT active low. WDOUT high impedance state inactive state. Upon triggering WATCHDOG, logic will pull WDOUT (G1) additional tc-32 cycles after signal level WDOUT goes below lower Schmitt trigger threshold. After this delay, device will stop forcing WDOUT output low. WATCHDOG service window will restart when WDOUT goes high. recommended that user WDOUT back through resistor order pull WDOUT high. WATCHDOG service while WDOUT signal active will ignored. state WDOUT guaranteed reset, powers then WATCHDOG will time WDOUT will enter high impedance state. Clock Monitor forces upon detecting clock frequency error. Clock Monitor error will continue until clock frequency reached minimum specified value, after which output will enter high impedance TRI-STATE mode following tc-32 clock cycles. Clock Monitor generates continual Clock Monitor error oscillator fails start, fails reach minimum specified frequency. specification Clock Monitor follows: 1/tc clock rejection. 1/tc Guaranteed clock rejection. WATCHDOG CLOCK MONITOR SUMMARY following salient points regarding WATCHDOG CLOCK MONITOR should noted:
lower limit service window fixed 2048 instruction cycles. Bits WDSVR register allow user pick upper limit service window.
Table shows four possible combinations lower upper limits WATCHDOG service window. This flexibility choosing WATCHDOG service window prevents undue burden user software. Bits WDSVR register represent 5-bit Data field. data fixed 01100. WDSVR Register Clock Monitor Select bit.
TABLE WATCHDOG Service Window Select WDSVR WDSVR Clock Monitor Service Window (Lower-Upper Limits) 2048-8k Cycles 2048-16k Cycles 2048-32k Cycles 2048-64k Cycles Clock Monitor Disabled Clock Monitor Enabled
Clock Monitor
Clock Monitor aboard device selected deselected under program control. Clock Monitor guaranteed reject clock instruction cycle clock greater equal kHz. This equates clock input rate greater equal kHz.
WATCHDOG Operation
WATCHDOG Clock Monitor disabled during reset. device comes reset with WATCHDOG armed, WATCHDOG Window Select bits (bits WDSVR Register) set, Clock Monitor (bit WDSVR Register) enabled. Thus, Clock Monitor error will
Both WATCHDOG CLOCK MONITOR detector circuits inhibited during RESET. Following RESET, WATCHDOG CLOCK MONITOR both enabled, with WATCHDOG having maximum service window selected. WATCHDOG service window CLOCK MONITOR enable/disable option only changed once, during initial WATCHDOG service following RESET.
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COP888xG/CS Family
WATCHDOG Operation
(Continued)
initial WATCHDOG service must match data value WATCHDOG Service register WDSVR order avoid WATCHDOG error. Subsequent WATCHDOG services must match three data fields WDSVR order avoid WATCHDOG errors. correct data value cannot read from WATCHDOG Service register WDSVR. attempt read this data value 01100 from WDSVR will read data value 0's. WATCHDOG detector circuit inhibited during both HALT IDLE modes. CLOCK MONITOR detector circuit active during both HALT IDLE modes. Consequently, device inadvertently entering HALT mode will detected CLOCK MONITOR error (provided that CLOCK MONITOR enable option been selected program). With single-pin oscillator mask option selected CLKDLY reset, WATCHDOG service window will resume following HALT mode from where left before entering HALT mode. With crystal oscillator mask option selected, with single-pin oscillator mask option selected CLKDLY set, WATCHDOG service window will selected value from WDSVR following HALT. Consequently, WATCHDOG should serviced least 2048 instruction cycles following HALT, must serviced within selected window avoid WATCHDOG error. IDLE timer initialized with RESET. user sync IDLE counter cycle with IDLE counter (T0) interrupt monitoring T0PND flag. T0PND flag whenever thirteenth IDLE counter toggles (every 4096 instruction cycles). user responsible resetting T0PND flag. hardware WATCHDOG service occurs just device exits IDLE mode. Consequently, WATCHDOG should serviced least 2048 instruction cycles following IDLE, must serviced within selected window avoid WATCHDOG error. Following RESET, initial WATCHDOG service (where service window CLOCK MONITOR enable/ disable must selected) programmed anywhere within maximum service window (65,536 instruction cycles) initialized RESET. Note that this initial WATCHDOG service programmed within initial 2048 instruction cycles without causing WATCHDOG error.
subroutine stack grows down each call (jump subroutine), interrupt, PUSH, grows each return POP. stack pointer initialized location during reset. Consequently, there more returns than calls, stack pointer will point addresses (which undefined RAM). Undefined from addresses (Segment other segments (i.e., Segments etc.) read 1's, which turn will cause program return address 7FFF Hex. This undefined location instruction fetched (all 0's) from this location will generate software interrupt signaling illegal condition. Thus, chip detect following illegal conditions: Executing from undefined Over "POP"ing stack having more returns than calls. When software interrupt occurs, user re-initialize stack pointer recovery procedure before restarting (this recovery program probably similar that following reset, might contain same program initialization procedures). recovery program should reset software interrupt pending using RPND instruction.
MICROWIRE/PLUS
MICROWIRE/PLUS serial synchronous communications interface. MICROWIRE/PLUS capability enables device interface with National Semiconductor's MICROWIRE peripherals (i.e. converters, display drivers, E2PROMs etc.) with other microcontrollers which support MICROWIRE interface. consists 8-bit serial shift register (SIO) with serial data input (SI), serial data output (SO) serial shift clock (SK). Figure shows block diagram MICROWIRE/PLUS logic.
DS012829-19
FIGURE MICROWIRE/PLUS Block Diagram shift clock selected from either internal source external source. Operating MICROWIRE/PLUS arrangement with internal clock source called Master mode operation. Similarly, operating MICROWIRE/ PLUS arrangement with external shift clock called Slave mode operation. CNTRL register used configure control MICROWIRE/PLUS mode. MICROWIRE/PLUS, MSEL CNTRL register one. master mode, clock rate selected bits, SL1, CNTRL register. Table details different clock rates that selected.
Detection Illegal Conditions
device detect various illegal conditions resulting from coding errors, transient noise, power supply voltage drops, runaway programs, etc. Reading undefined gets zeros. opcode software interrupt zero. program fetches instructions from undefined ROM, this will force software interrupt, thus signaling that illegal condition occurred.
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COP888xG/CS Family
MICROWIRE/PLUS
Data Match Don't Care Mismatch Don't Care
(Continued) TABLE WATCHDOG Service Actions Window Data Match Mismatch Don't Care Don't Care Clock Monitor Match Don't Care Don't Care Mismatch Valid Service: Restart Service Window Error: Generate WATCHDOG Output Error: Generate WATCHDOG Output Error: Generate WATCHDOG Output onto Port. must selected input selected output setting resetting appropriate bits Port configuration register. Table summarizes settings required enter Slave mode operation. user must BUSY flag immediately upon entering Slave mode. This will ensure that data bits sent Master will shifted properly. After eight clock pulses BUSY flag will cleared sequence repeated. Alternate Phase Operation device allows either normal clock alternate phase clock shift data register. both modes normally low. normal mode data shifted rising edge clock data shifted falling edge clock. register shifted each falling edge clock. alternate phase operation, data shifted falling edge clock shifted rising edge clock. control flag, SKSEL, allows either normal clock alternate clock selected. Resetting SKSEL causes MICROWIRE/PLUS logic clocked from normal signal. Setting SKSEL flag selects alternate clock. SKSEL mapped into configuration bit. SKSEL flag will power reset condition, selecting normal signal. TABLE MICROWIRE/PLUS Mode Settings This table assumes that control flag MSEL set.
(SO) Config. (SK) Config. Fun. TRISTATE TRISTATE Fun. Int. Int. Ext. Ext. MICROWIRE/PLUS Master MICROWIRE/PLUS Master MICROWIRE/PLUS Slave MICROWIRE/PLUS Slave Operation
Action
TABLE MICROWIRE/PLUS Master Mode Clock Select
Where instruction cycle clock MICROWIRE/PLUS OPERATION Setting BUSY register causes MICROWIRE/PLUS start shifting data. gets reset when eight data bits have been shifted. user reset BUSY software allow less than bits shift. enabled, interrupt generated when eight data bits have been shifted. device enter MICROWIRE/PLUS mode either Master Slave. Figure shows microcontroller devices several peripherals interconnected using MICROWIRE/PLUS arrangements. Warning: register should only loaded when clock low. Loading register while clock high will result undefined data register. clock normally when shifting. Setting BUSY flag when input clock high MICROWIRE/PLUS slave mode cause current clock shift register narrow. safety, BUSY flag should only when input clock low. MICROWIRE/PLUS Master Mode Operation MICROWIRE/PLUS Master mode operation shift clock (SK) generated internally device. MICROWIRE Master always initiates data exchanges. MSEL CNTRL register must enable functions onto Port. pins must also selected outputs setting appropriate bits Port configuration register. Table summarizes settings required Master mode operation. MICROWIRE/PLUS Slave Mode Operation MICROWIRE/PLUS Slave mode operation clock generated external source. Setting MSEL CNTRL register enables functions
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COP888xG/CS Family
MICROWIRE/PLUS
(Continued)
DS012829-20
FIGURE MICROWIRE/PLUS Application
Memory
RAM, ports registers (except mapped into data memory address space. Address S/ADD 0000 006F 0070 007F xx80 xx93 xx94 xx95 xx96 xx97 xxAF xxB0 xxB1 xxB2 xxB3 xxB4 xxB5 xxB6 xxB7 xxB8 xxB9 xxBA xxBB On-Chip bytes (112 bytes) Unused Address Space (Reads Ones) Unused Address Space (Reads Undefined Data) Port data register, PORTFD Port configuration register, PORTFC Port input pins (read only), PORTFP Unused address space (Reads Undefined Data) Timer Lower Byte Timer Upper Byte Timer Autoload Register T3RA Lower Byte Timer Autoload Register T3RA Upper Byte Timer Autoload Register T3RB Lower Byte Timer Autoload Register T3RB Upper Byte Timer Control Register Comparator Select Register (Reg:CMPSL) UART Transmit Buffer (Reg:TBUF) UART Receive Buffer (Reg:RBUF) UART Control Status Register (Reg:ENU) UART Receive Control Status Register (Reg:ENUR) xxC9 xxCA xxCB xxCF xxD0 xxD1 xxD2 xxD3 xxD4 xxD5
Contents
Address S/ADD xxBC xxBD xxBE xxBF xxC0 xxC1 xxC2 xxC3 xxC4 xxC5 xxC6 xxC7 xxC8
Contents UART Interrupt Clock Source Register (Reg:ENUI) UART Baud Register (Reg:BAUD) UART Prescale Select Register (Reg:PSR) Reserved UART Timer Lower Byte Timer Upper Byte Timer Autoload Register T2RA Lower Byte Timer Autoload Register T2RA Upper Byte Timer Autoload Register T2RB Lower Byte Timer Autoload Register T2RB Upper Byte Timer Control Register WATCHDOG Service Register (Reg:WDSVR) MIWU Edge Select Register (Reg:WKEDG) MIWU Enable Register (Reg:WKEN) MIWU Pending Register (Reg:WKPND) Reserved Port Data Register Port Configuration Register Port Input Pins (Read Only) Reserved Port Port Data Register Port Configuration Register
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COP888xG/CS Family
Memory
Address S/ADD xxD6 xxD7 xxD8 xxD9 xxDA xxDB xxDC xxDD xxDF xxE0 xxE5 xxE6 xxE7 xxE8 xxE9 xxEA xxEB
(Continued) Contents
Address S/ADD xxEC xxED xxEE xxEF xxF0 xxFC xxFD xxFE xxFF 0100-017F 0200-027F 0300-037F
Contents Timer Autoload Register T1RA Lower Byte Timer Autoload Register T1RA Upper Byte CNTRL Control Register Register On-Chip Mapped Registers Register Register Register Register On-Chip Bytes On-Chip Bytes (Reads undefined data COP8SGE) On-Chip Bytes (Reads undefined data COP8SGE)
Port Input Pins (Read Only) Port Input Pins (Read Only) (Actually reads Port input pins) Port Data Register Port Configuration Register Port Input Pins (Read Only) Reserved Port Port Reserved Port Reserved Control Registers Timer Autoload Register T1RB Lower Byte Timer Autoload Register T1RB Upper Byte ICNTRL Register MICROWIRE/PLUS Shift Register Timer Lower Byte Timer Upper Byte
Note: Reading memory locations 0070H-007FH (Segment will return ones. Reading unused memory locations 0080H-00AFH (Segment will return undefined data. Reading memory locations from other Segments (i.e., Segment Segment etc.) will return undefined data.
Addressing Modes
There addressing modes, operand addressing four transfer control. OPERAND ADDRESSING MODES Register Indirect This "normal" addressing mode. operand data memory addressed pointer pointer. Register Indirect (with auto post increment decrement pointer) This addressing mode used with instructions. operand data memory addressed pointer pointer. This register indirect mode that automatically post increments decrements register after executing instruction. Direct instruction contains 8-bit address field that directly points data memory operand. Immediate instruction contains 8-bit immediate field operand. Short Immediate This addressing mode used with Load Immediate instruction. instruction contains 4-bit immediate field operand. Indirect This addressing mode used with LAID instruction. contents accumulator used partial address (lower bits accessing data operand from program memory. TRANSFER CONTROL ADDRESSING MODES Relative This mode used instruction, with instruction field being added program counter program location. range from allow 1-byte relative jump implemented instruction). There "pages" when using since bits used. Absolute This mode used with instructions, with instruction field bits replacing lower bits program counter (PC). This allows jumping location current program memory segment. Absolute Long This mode used with JMPL JSRL instructions, with instruction field bits replacing entire bits program counter (PC). This allows jumping location program memory space. Indirect This mode used with instruction. contents accumulator used partial address (lower bits accessing location program memory. contents this program memory location serve partial address (lower bits jump next instruction.
Note: special case Indirect Transfer Control addressing mode, where double byte vector associated with interrupt transferred from adjacent addresses program memory into program counter (PC) order jump associated interrupt service routine.
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COP888xG/CS Family
Instruction
Register Symbol Definition Registers 8-Bit Accumulator Register 8-Bit Address Register 8-Bit Address Register 8-Bit Segment Register 8-Bit Stack Pointer Register 15-Bit Program Counter Register Upper Bits Lower Bits Register Carry Register Half Carry Register Global Interrupt Enable Interrupt Vector Upper Byte Interrupt Vector Lower Byte Symbols Meml Memory Indirectly Addressed Register Memory Indirectly Addressed Register Direct Addressed Memory Direct Addressed Memory Direct Addressed Memory Immediate Data 8-Bit Immediate Data Register Memory: Addresses (Includes Number Loaded with Exchanged with
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COP888xG/CS Family
Instruction
INSTRUCTION SUBC ANDSZ IFEQ IFEQ IFNE IFGT IFBNE DRSZ SBIT RBIT IFBIT RPND LAID DCOR SWAP IFNC PUSH JMPL Addr. Addr. Disp. A,Mem A,[X] A,Meml A,[X] B,Imm Mem,Imm Reg,Imm ],Imm A,Meml A,Meml A,Meml A,Meml A,Imm A,Meml A,Meml MD,Imm A,Meml A,Meml A,Meml
(Continued)
with Carry Subtract with Carry Logical Logical Immed., Skip Zero Logical Logical EXclusive EQual EQual Equal Greater Than Equal Decrement Reg., Skip Zero Reset Reset PeNDing Flag EXchange with Memory EXchange with Memory LoaD with Memory LoaD with Memory LoaD with Immed. LoaD Memory Immed LoaD Register Memory Immed. EXchange with Memory EXchange with Memory LoaD with Memory LoaD with Memory LoaD Memory Immed. CLeaR INCrement DECrement Load InDirect from Decimal CORrect Rotate Right thru Rotate Left thru SWAP nibbles Reset stack into PUSH onto stack Vector Interrupt Service Routine Jump absolute Long Jump absolute Jump relative short
Meml Meml Carry Half Carry MemI Carry Half Carry Meml Skip next Imm) Meml Meml Compare Imm, next Compare Meml, next Meml Compare Meml, next Meml Compare Meml, next Meml next lower bits RegReg Skip bit, (bit immediate) bit, true next instruction Reset Software Interrupt Pending Flag AMem A[X] AMeml A[X] A[B], A[X], [B], [X], Imm, (PU,A) correction (follows ADC, SUBC) A7.A4A3.A0 true, next instruction true, next instruction [SP] [SP] [VU], [VL] bits, 32k) PC9.0 bits) +32, except
#,Mem #,Mem #,Mem
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COP888xG/CS Family
Instruction
JSRL RETSK RETI INTR Addr. Addr
(Continued)
INSTRUCTION (Continued) Jump SubRoutine Long Jump SubRoutine Jump InDirect RETurn from subroutine RETurn SKip RETurn from Interrupt Generate Interrupt OPeration [SP] [SP-1] PU,SP-2, [SP] [SP-1] PU,SP-2, PC9.0 (PU,A) [SP], [SP-1] [SP],PU [SP-1], skip next instruction [SP],PU [SP-1],GIE [SP] [SP-1] SP-2,
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COP888xG/CS Family
Instruction Execution Time
Most instructions single byte (with immediate addressing mode instructions taking bytes). Most single byte instructions take cycle time execute. Skipped instructions require number cycles skipped, where equals number bytes skipped instruction opcode. Bytes Cycles Instruction following table shows number bytes cycles each instruction format byte/cycle. Arithmetic Logic Instructions SUBC IFEQ IFNE IFGT IFBNE DRSZ SBIT RBIT IFBIT RPND Direct Immed.
Instructions Using CLRA INCA DECA LAID DCOR RRCA RLCA SWAPA IFNC PUSHA POPA ANDSZ
Transfer Control Instructions JMPL JSRL RETSK RETI INTR
Memory Transfer Instructions Register Indirect (Note (Note Mem, Reg, IFEQ
Note
Direct
Immed.
Register Indirect Auto Incr. Decr. [B+, [X+,
Memory location addressed directly.
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Opcode Table
Upper Nibble DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ B,#i RETI A,[X] A,[B] [B],#i SBIT 6,[B] SBIT 7,[B] JSRL A,Md RETSK SBIT 5,[B] Md,#i JMPL A,Md POPA SBIT 4,[B] RBIT 4,[B] RBIT 5,[B] RBIT 6,[B] RBIT 7,[B] A,[X-] A,[B-] [B-],#i DECA SBIT 3,[B] RBIT 3,[B] B,#04 B,#03 B,#02 B,#01 B,#00 A,[X+] A,[B+] [B+],#i INCA SBIT 2,[B] RBIT 2,[B] B,#05 IFNE A,[B] IFEQ Md,#i IFNE A,#i IFNC SBIT 1,[B] RBIT 1,[B] B,#06 IFBNE IFBNE IFBNE IFBNE IFBNE IFBNE IFBNE RLCA A,#i SBIT 0,[B] RBIT 0,[B] B,#07 IFBNE A,#i A,[B] IFBIT PUSHA 7,[B] B,#08 IFBNE A,[X] A,[B] A,#i A,[B] IFBIT DCORA 6,[B] B,#09 IFBNE RPND A,#i A,[B] IFBIT SWAPA 5,[B] B,#0A IFBNE LAID A,#i A,[B] IFBIT 4,[B] CLRA B,#0B IFBNE JP+21 x400-x4FF x400-x4FF JP+22 x500-x5FF x500-x5FF JP+23 x600-x6FF x600-x6FF JP+24 x700-x7FF x700-x7FF JP+25 x800-x8FF x800-x8FF A,[X-] A,[B-] IFGT A,#i IFGT A,[B] IFBIT 3,[B] B,#0C IFBNE JP+20 x300-x3FF x300-x3FF JP+4 JP+5 JP+6 JP+7 JP+8 JP+9 A,[X+] A,[B+] IFEQ A,#i IFEQ A,[B] IFBIT 2,[B] B,#0D IFBNE JP+19 x200-x2FF x200-x2FF JP+3 JP+26 JP+10 x900-x9FF x900-x9FF JP+27 JP+11 xA00-xAFF xA00-xAFF JP+28 JP+12 xB00-xBFF xB00-xBFF JP+29 JP+13 xC00-xCFF xC00-xCFF JP+30 JP+14 xD00-xDFF xD00-xDFF JP+31 JP+15 xE00-xEFF xE00-xEFF JP+32 JP+16 xF00-xFFF xF00-xFFF SUBC SUBC A,[B] IFBIT 1,[B] B,#0E IFBNE JP+18 x100-x1FF x100-x1FF JP+2 RRCA A,#i A,[B] IFBIT ANDSZ 0,[B] B,#0F IFBNE JP+17 INTR x000-x0FF x000-x0FF
JP-15
JP-31
0F0,
JP-14
JP-30
0F1,
JP-13
JP-29
0F2,
JP-12
JP-28
0F3,
Instruction Execution Time
JP-11
JP-27
0F4,
JP-10
JP-26
0F5,
(Continued)
JP-9
JP-25
0F6,
JP-8
JP-24
0F7,
0F9,
JP-5
JP-21
0FA,
JP-4
JP-20
0FB,
JP-3
JP-19
0FC,
JP-2
JP-18
0FD,
JP-1
JP-17
0FE,
JP-0
JP-16
0FF,
COP888xG/CS Family
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Where, immediate data directly addressed memory location unused opcode opcode also opcode IFBIT #i,A
Lower Nibble
JP-7
JP-23
0F8,
JP-6
JP-22
COP888xG/CS Family
Mask Options
mask programmable options shown below. options programmed same time pattern submission. OPTION CLOCK CONFIGURATION Crystal Oscillator (CKI/10) (CKO) clock generator output crystal/ resonator with being clock input Single-pin controlled oscillator (CKI/10) available HALT restart and/or general purpose input OPTION HALT Enable HALT mode Disable HALT mode OPTION BONDING OPTIONS 44-Pin PLCC 40-Pin 28-DIP 28-Pin Some device driven clock input input which between MHz. output clock clock option=1 been selected). input frequency divided down produce instruction cycle clock (1/tc). packages available devices, please check order information.
COP8-EVAL-ICUxx: Very cost evaluation design test board COP8ACC COP8SGx Families, from ICU. Real-time environment with add-on A/D, D/A, EEPROM. Includes software routines reference designs. Manuals, Applications Notes, Literature: Available free from site www.national.com/cop8.
COP8 Integrated Software/Hardware Design Development Kits
COP8-EPU: Very cost Evaluation Programming Unit. Windows based development hardwaresimulation tool COPSx/xG families, with COP8 device programmer samples. Includes COP8-NSDEV, Driveway COP8 Demo, MetaLink Debugger, cables power supply.
COP8-DM: Moderate cost Debug Module from MetaLink. Windows based, real-time in-circuit emulation tool with COP8 device programmer. Includes COP8-NSDEV, DriveWay COP8 Demo, MetaLink Debugger, power supply, emulation cables adapters. COP8 Development Languages Environments
COP8-NSASM: Free COP8 Assembler Win32. Macro assembler, linker, librarian COP8 software development. Supports COP8 devices. (DOS/Win16 v4.10.2 available with limited support). (Compatible with WCOP8 IDE, COP8C, DriveWay COP8). COP8-NSDEV: Very cost Software Development Package Windows. integrated development environment COP8, including WCOP8 IDE, COP8NSASM, COP8-MLSIM. COP8C: Moderately priced Cross-Compiler Code Development System from Byte Craft code limit). Includes BCLIDE (Byte Craft Limited Integrated Development Environment) Win32, editor, optimizing CrossCompiler, macro cross assembler, BC-Linker, MetaLink tools support. (DOS/SUN versions available; Compiler installable under WCOP8 IDE; Compatible with DriveWay COP8). EWCOP8-KS: Very cost ANSI C-Compiler Embedded Workbench from (Kickstart version: COP8Sx/Fx only with code limit; FP). fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, Liberian, C-Spy simulator/debugger, PLUS MetaLink EPU/DM emulator support. EWCOP8-AS: Moderately priced COP8 Assembler Embedded Workbench from code limit). fully integrated Win32 IDE, macro assembler, editor, linker, librarian, C-Spy high-level simulator/debugger with interrupts support. (Upgradeable with optional C-Compiler and/or MetaLink Debugger/Emulator support). EWCOP8-BL: Moderately priced ANSI C-Compiler Embedded Workbench from (Baseline version: COP8 devices; code limit; FP). fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, librarian, C-Spy high-level simulator/debugger. (Upgradeable; CWCOP8-M MetaLink tools interface support optional). EWCOP8: Full featured ANSI C-Compiler Embedded Workbench Windows from code limit). fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, librarian, C-Spy high-level simulator/debugger. (CWCOP8-M MetaLink tools interface support optional).
Development Support
OVERVIEW National engaged with international community independent party vendors provide hardware software development tool support. Through National's interaction guidance, these tools cooperate form choice tools that fits each developer's needs. This section provides summary tool development kits currently available. Up-to-date information, selection guides, free tools, demos, updates, purchase information obtained site www.national.com/cop8. SUMMARY TOOLS COP8 Evaluation Tools
COP8-NSEVAL: Free Software Evaluation package Windows. fully integrated evaluation environment COP8, including versions WCOP8 (Integrated Development Environment), COP8-NSASM, COP8-MLSIM, COP8C, DriveWayCOP8, Manuals, other COP8 information. COP8-MLSIM: Free Instruction Level Simulator tool Windows. testing debugging software instructions only interrupt support). COP8-EPU: Very cost COP8 Evaluation Programming Unit. Windows based evaluation hardware-simulation tool, with COP8 device programmer erasable samples. Includes COP8-NSDEV, Driveway COP8 Demo, MetaLink Debugger, cables power supply.
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COP888xG/CS Family
Development Support
(Continued)
EWCOP8-M: Full featured ANSI C-Compiler Embedded Workbench Windows from code limit). fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, librarian, C-Spy high-level simulator/debugger, PLUS MetaLink debugger/hardware interface (CWCOP8-M). COP8 Productivity Enhancement Tools
COP8 Real-Time Emulation Tools COP8-DM: MetaLink Debug Module. moderately priced real-time in-circuit emulation tool, with COP8 device programmer. Includes MetaLink Debugger, power supply, emulation cables adapters. IM-COP8: MetaLink iceMASTER full featured, realtime in-circuit emulator COP8 devices. Includes COP8-NSDEV, Driveway COP8 Demo, MetaLink Windows Debugger, power supply. Package-specific probes surface mount adaptors ordered separately. COP8 Device Programmer Support
WCOP8 IDE: Very cost (Integrated Development Environment) from KKD. Supports COP8C, COP8NSASM, COP8-MLSIM, DriveWay COP8, MetaLink debugger under common Windows Project Management environment. Code development, debug, emulation tools launched from project window framework. DriveWay-COP8: cost COP8 Peripherals Code Generation tool from Aisys Corporation. Automatically generates tested documented Assembly source code modules containing drivers interrupt handlers each on-chip peripheral. Application specific code inserted customization using integrated editor. (Compatible with COP8-NSASM, COP8C, WCOP8 IDE.) COP8-UTILS: Free COP8 assembly code examples, device drivers, utilities speed code development. COP8-MLSIM: Free Instruction Level Simulator tool Windows. testing debugging software instructions only interrupt support). Vendor Tools COP8-NSEVAL COP8-NSASM COP8-MLSIM COP8-NSDEV COP8-EPU Order Number COP8-NSEVAL COP8-NSASM COP8-MLSIM COP8-NSDEV COP8SG-EPU Cost Free Free Free
MetaLink's Debug Module include development device programming capability COP8 devices. Third-party programmers automatic handling equipment cover needs from engineering prototype pilot production, full production environments. Factory programming available high-volume requirements.
TOOLS ORDERING NUMBERS COP888xG/CS FAMILY DEVICES COP888xG/CS devices compatible with COP8SGx devices, tools also used development.
Notes site download Included site download Included site download Included Order from website 110V, 220V; Included p/s, target cable, manuals, software, 16/20/28/40 programming socket; target adapter adapter needed) Included p/s, 28/40/44 DIP/SO/PLCC target cables, manuals, software, 16/20/28/40 DIP/SO PLCC programming socket; adapter target adapter needed) converter PLCC converter Eraseable devices programming SOIC PLCC programming programmer programming 16/20/28 SOIC programmer
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COP8-DM
COP8SG-DM MHz)
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