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Extensions 3DNow! Instruction Sets
Manual
2000 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks AMD, logo, Athlon, combinations thereof, 3DNow! trademarks, AMD-K6 registered trademark Advanced Micro Devices, Inc. trademark Intel Corporation. Other product names used this publication identification purposes only trademarks their respective companies.
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Extensions 3DNow!and MMXInstruction Sets
Contents
Revision History
Extensions 3DNow!and MMXInstruction Sets Extensions 3DNow!Instruction
Introduction
PF2IW. PFNACC PFPNACC. PI2FW. PSWAPD
Extensions MMXInstruction
MASKMOVQ MOVNTQ PAVGB PAVGW PEXTRW PINSRW PMAXSW PMAXUB PMINSW. PMINUB PMOVMSKB PMULHUW PREFETCHNTA PREFETCHT0 PREFETCHT1 PREFETCHT2 PSADBW PSHUFW SFENCE
Contents
Extensions 3DNow!and MMXInstruction Sets
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Contents
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List Tables
Table Table Table Table 3DNow!Technology Extensions MMXInstruction Extensions Numerical Range PF2IW Instruction Locality References Prefetch Instructions
List Tables
Extensions 3DNow!and MMXInstruction Sets
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List Tables
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Revision History
Date August 1999 February 2000 Initial public release
Description Clarification PSWAPD operation page Clarification PINSRW description operation page Clarification PSHUFW description operation page Clarification SFENCE encoding page Clarification PFNACC operation page Clarification PFPNACC operation page
March 2000
Revision History
Extensions 3DNow!and MMXInstruction Sets
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Revision History
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Extensions 3DNow!and MMXInstruction Sets
Introduction
With advent Athlonprocessor, taken 3DNow!Technology next level performance functionality. Athlon processor adds instructions existing 3DNow! MMXinstruction sets. Along with instructions, Athlon enhancements that enable more efficient operation these instructions, programming simplified because there fewer coding restrictions. 3DNow! technology enabled fast frame rates high-resolution rendered scenes, amazing physical modeling real-world environments, sharp detailed imaging, smooth video playback, theater-quality audio. enhanced 3DNow! technology implemented Athlon processor technologies, which allow faster, more accurate speech recognition, DVD-quality audio video, streaming audio video rich Internet experience. instructions described this document extensions instruction sets described 3DNow!Technology Manual, order# 21928 Multimedia Technology Manual, order# 20726. five 3DNow! technology extensions Chapter Extensions 3DNow!and MMXInstruction Sets
Extensions 3DNow!and MMXInstruction Sets
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summarized Table fully described Chapter instructions augmenting existing technology summarized Table fully described Chapter Table
PF2IW PFNACC PFPNACC PI2FW PSWAPD
3DNow!Technology Extensions
Function Packed Floating-Point Integer Word Conversion with Sign Extend Packed Floating-Point Negative Accumulate Packed Floating-Point Mixed Positive-Negative Accumulate Packed Integer Word Floating-Point Conversion Packed Swap Doubleword Opcode imm8
Operation
Table
MMXInstruction Extensions
Function Streaming (Cache Bypass) Store Using Byte Mask Streaming (Cache Bypass) Store Packed Average Unsigned Byte Packed Average Unsigned Word Extract Word into Integer Register Insert Word from Integer Register Packed Maximum Signed Word Packed Maximum Unsigned Byte Packed Minimum Signed Word Packed Minimum Unsigned Byte Move Byte Mask Integer Register Packed Multiply High Unsigned Word Move Data Closer Processor Using Reference Move Data Closer Processor Using Reference Move Data Closer Processor Using Reference Move Data Closer Processor Using Reference Packed Absolute Byte Differences Packed Shuffle Word Store Fence Opcode imm8
Operation MASKMOVQ MOVNTQ PAVGB PAVGW PEXTRW PINSRW PMAXSW PMAXUB PMINSW PMINUB PMOVMSKB PMULHUW PREFETCHNTA PREFETCHT0 PREFETCHT1 PREFETCHT2 PSADBW PSHUFW SFENCE
Note:
number after opcode indicates different prefetch modes ModR/M byte.
Extensions 3DNow!and MMXInstruction Sets
Chapter
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Extensions 3DNow!Instruction
This chapter describes five instructions added 3DNow! instruction first defined 3DNow!Technology Manual, order# 21928. five instructions enhance performance communications applications, including soft modems, soft ADSL, MP3, Dolby Digital Surround sound processing. Programmers should check Extended Feature Flags register after executing extended function 8000_0001h CPUID instruction. set, information, refer Processor Recognition Application Note, order# 20734. Instruction definitions alphabetical order according instruction mnemonics.
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PF2IW
mnemonic PF2IW mmreg1, mmreg2 PF2IW mmreg, mem64 Privilege: Registers Affected: Flags Affected: Exceptions Generated:
Exception Invalid opcode Device available Stack exception (12) General protection (13) Segment overrun (13) Page fault (14) Floating-point exception pending (16) Alignment check (17) Real
opcode imm8
description Packed floating-point integer word conversion with sign extend
none none
Virtual 8086 Protected Description emulate instruction (EM) control register (CR0) task switch (TS) control register (CR0) During instruction execution, stack segment limit exceeded. During instruction execution, effective address segment registers used operand points illegal memory location. instruction data operands falls outside address range 00000h 0FFFFh. page fault resulted from execution instruction. exception pending floating-point execution unit. unaligned memory reference resulted from instruction execution, alignment mask (AM) control register (CR0) Protected Mode,
PF2IW converts register containing single-precision floating-point operands 16-bit signed integers using truncation. Arguments outside range representable signed 16-bit integers saturated largest smallest 16-bit integer, depending their sign. results sign-extended 32-bits. Table page shows numerical range PF2IW instruction.
Extensions 3DNow!Instruction
Chapter
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"PF2IW mmreg1, mmreg2" performs following operations:
(mmreg2[31:0] 215) THEN mmreg1[31:0] 0x0000_7FFF ELSE (mmreg2[31:0] -215) THEN mmreg1[31:0] 0xFFFF_8000 ELSE mmreg1[31:0] int(mmreg2[31:0]) (mmreg2[63:32] 215) THEN mmreg1[63:32] 0x0000_7FFF ELSE (mmreg2[63:32] -215) THEN mmreg1[63:32] 0xFFFF_8000 ELSE mmreg1[63:32] int(mmreg2[63:32])
"PF2IW mmreg, mem64" performs following operations:
(mem64[31:0] 215) THEN mmreg[31:0] 0x0000_7FFF ELSE (mem64[31:0] -215) THEN mmreg[31:0] 0xFFFF_8000 ELSE mmreg[31:0] int(mem64[31:0]) (mem64[63:32] 215) THEN mmreg[63:32] 0x0000_7FFF ELSE (mem64[63:32] -215) THEN mmreg[63:32] 0xFFFF_8000 ELSE mmreg[63:32] int(mem64[63:32])
Table
Numerical Range PF2IW Instruction
Source Source Destination round zero (Source round zero (Source 0x0000_7FFF 0xFFFF_8000 Undefined
Normal, abs(Source Normal, -32768 Source Normal, Source 32768 Normal, Source 32768 Normal, Source -32768 Unsupported
Related Instructions
PF2ID, PI2FW, PI2FD instructions.
Chapter
Extensions 3DNow!Instruction
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PFNACC
mnemonic PFNACC mmreg1, mmreg2 PFNACC mmreg, mem64 Privilege: Registers Affected: Flags Affected: Exceptions Generated:
Exception Invalid opcode Device available Stack exception (12) General protection (13) Segment overrun (13) Page fault (14) Floating-point exception pending (16) Alignment check (17) Real
opcode imm8
description Packed floating-point negative accumulate
none none
Virtual 8086 Protected Description emulate instruction (EM) control register (CR0) task switch (TS) control register (CR0) During instruction execution, stack segment limit exceeded. During instruction execution, effective address segment registers used operand points illegal memory location. instruction data operands falls outside address range 00000h 0FFFFh. page fault resulted from execution instruction. exception pending floating-point execution unit. unaligned memory reference resulted from instruction execution, alignment mask (AM) control register (CR0) Protected Mode,
PFNACC performs negative accumulation doublewords destination operand source operand. PFNACC then stores results high words destination operand, respectively. Both operands single-precision, floating-point operands with 24-bit significands. "PFNACC mmreg1, mmreg2" performs following operations:
temp mmreg2 mmreg1[31:0] mmreg1[31:0] mmreg1[63:32] mmreg1[63:32] temp[31:0] temp[63:32]
"PFNACC mmreg, mem64" performs following operations:
mmreg[31:0] mmreg[31:0] mmreg[63:32] mmreg[63:32] mem64[31:0] mem64[63:32]
Related Instructions
PFACC PFPNACC instructions.
Extensions 3DNow!Instruction
Chapter
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PFPNACC
mnemonic PFPNACC mmreg1, mmreg2 PFPNACC mmreg, mem64 Privilege: Registers Affected: Flags Affected: Exceptions Generated:
Exception Invalid opcode Device available Stack exception (12) General protection (13) Segment overrun (13) Page fault (14) Floating-point exception pending (16) Alignment check (17) Real
opcode imm8
description Packed floating-point mixed positive-negative accumulate
none none
Virtual 8086 Protected Description emulate instruction (EM) control register (CR0) task switch (TS) control register (CR0) During instruction execution, stack segment limit exceeded. During instruction execution, effective address segment registers used operand points illegal memory location. instruction data operands falls outside address range 00000h 0FFFFh. page fault resulted from execution instruction. exception pending floating-point execution unit. unaligned memory reference resulted from instruction execution, alignment mask (AM) control register (CR0) Protected Mode,
PFPNACC performs mixed negative positive accumulation doublewords destination operand source operand. PFPNACC then stores results high words destination operand, respectively. Both operands single-precision, floating-point operands with 24-bit significands. "PFPNACC mmreg1, mmreg2" performs following operations:
temp mmreg2 mmreg1[31:0] mmreg1[31:0] mmreg1[63:32] mmreg1[63:32] temp[31:0] temp[63:32]
"PFPNACC mmreg, mem64" performs following operations:
mmreg[31:0] mmreg[31:0] mmreg[63:32] mem64[31:0] mmreg[63:32] mem64[63:32]
Related Instructions
PFACC PFNACC instructions.
Chapter
Extensions 3DNow!Instruction
Extensions 3DNow!and MMXInstruction Sets
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PI2FW
mnemonic PI2FW mmreg1, mmreg2 PI2FW mmreg, mem64 Privilege: Registers Affected: Flags Affected: Exceptions Generated
Exception Invalid opcode Device available Stack exception (12) General protection (13) Segment overrun (13) Page fault (14) Floating-point exception pending (16) Alignment check (17) Real
opcode imm8
description Packed 16-bit integer floating-point conversion
none none
Virtual 8086 Protected Description emulate instruction (EM) control register (CR0) task switch (TS) control register (CR0) During instruction execution, stack segment limit exceeded. During instruction execution, effective address segment registers used operand points illegal memory location. instruction data operands falls outside address range 00000h 0FFFFh. page fault resulted from execution instruction. exception pending floating-point execution unit. unaligned memory reference resulted from instruction execution, alignment mask (AM) control register (CR0) Protected Mode,
PI2FW converts register containing signed, 16-bit integers single-precision, floating-point operands. "PI2FW mmreg1, mmreg2" performs following operations:
mmreg1[31:0] float(mmreg2[15:0]) mmreg1[63:32] float(mmreg2[47:32])
"PI2FW mmreg, mem64" performs following operations:
mmreg[31:0] float(mem64[15:0]) mmreg[63:32] float(mem64[47:32])
Related Instructions
PI2FD, PF2IW, PF2ID instructions.
Extensions 3DNow!Instruction
Chapter
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PSWAPD
mnemonic PSWAPD mmreg1, mmreg2 PSWAPD mmreg, mem64 Privilege: Registers Affected: Flags Affected: Exceptions Generated
Exception Invalid opcode Device available Stack exception (12) General protection (13) Segment overrun (13) Page fault (14) Floating-point exception pending (16) Alignment check (17) Real
opcode imm8
description Packed swap doubleword
none none
Virtual 8086 Protected Description emulate instruction (EM) control register (CR0) task switch (TS) control register (CR0) During instruction execution, stack segment limit exceeded. During instruction execution, effective address segment registers used operand points illegal memory location. instruction data operands falls outside address range 00000h 0FFFFh. page fault resulted from execution instruction. exception pending floating-point execution unit. unaligned memory reference resulted from instruction execution, alignment mask (AM) control register (CR0) Protected Mode,
PSWAPD instruction swaps reverses upper lower doublewords source operand. "PSWAPD mmreg1, mmreg2" performs following operations:
temp mmreg2 mmreg1[63:32] mmreg1[31:0] temp[31:0] temp[63:32]
"PSWAPD mmreg, mem64" performs following operations:
mmreg[63:32] mmreg[31:0] mem64[31:0] mem64[63:32]
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Extensions 3DNow!and MMXInstruction Sets
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Chapter
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Extensions MMXInstruction
This chapter describes instructions added instruction defined AMD-K6 MMXEnhanced Processor Multimedia Technology Manual, order# 20726. Twelve instructions improve multimedia-enhanced integer math calculations used such applications speech recognition high-quality video processing. Seven instructions dedicated efficiently moving multimedia data into processor. Programmers should check Extended Feature Flags register after executing extended function 8000_0001h CPUID instruction. set, processor supports these instructions. Processor information. Instruction definitions alphabetical order according instruction mnemonics.
Chapter
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MASKMOVQ
mnemonic MASKMOVQ mmreg1, mmreg2 (edi) Privilege: Registers Affected: Flags Affected: Exceptions Generated:
Exception Invalid opcode Device available Stack exception (12) General protection (13) Segment overrun (13) Page fault (14) Floating-point exception pending (16) Alignment check (17) Real
opcode
description Streaming (cache bypass) store using byte mask
none none
Virtual 8086 Protected Description emulate instruction (EM) control register (CR0) task switch (TS) control register (CR0) During instruction execution, stack segment limit exceeded. During instruction execution, effective address segment registers used operand points illegal memory location. instruction data operands falls outside address range 00000h 0FFFFh. page fault resulted from execution instruction. exception pending floating-point execution unit. unaligned memory reference resulted from instruction execution, alignment mask (AM) control register (CR0) Protected Mode,
MASKMOVQ instruction conditionally stores individual bytes register memory location specified register, while using byte mask second register. MASKMOVQ instruction acts streaming store minimize cache pollution. used store data without first reading data write allocate). "MASKMOVQ mmreg1, mmreg2 (edi)" performs following operations:
memory[edi][63:56] memory[edi][55:48] memory[edi][47:40] memory[edi][39:32] memory[edi][31:24] memory[edi][23:16] memory[edi][15:8] memory[edi][7:0] mmreg2[63] mmreg2[55] mmreg2[47] mmreg2[39] mmreg2[31] mmreg2[23] mmreg2[15] mmreg2[7] mmreg1[63:56] mmreg1[55:48] mmreg1[47:40] mmreg1[39:32] mmreg1[31:24] mmreg1[23:16] mmreg1[15:8] mmreg1[7:0] memory[edi][63:56] memory[edi][55:48] memory[edi][47:40] memory[edi][39:32] memory[edi][31:24] memory[edi][23:16] memory[edi][15:8] memory[edi][7:0]
Extensions MMXInstruction
Chapter
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MOVNTQ
mnemonic MOVNTQ mem64, mmreg Privilege: Registers Affected: Flags Affected: Exceptions Generated:
Exception Invalid opcode Device available Stack exception (12) General protection (13) Segment overrun (13) Page fault (14) Floating-point exception pending (16) Alignment check (17) Real
opcode none none
Virtual 8086 Protected Description
description Streaming (cache bypass) store
emulate instruction (EM) control register (CR0) task switch (TS) control register (CR0) During instruction execution, stack segment limit exceeded. During instruction execution, effective address segment registers used operand points illegal memory location. instruction data operands falls outside address range 00000h 0FFFFh. page fault resulted from execution instruction. exception pending floating-point execution unit. unaligned memory reference resulted from instruction execution, alignment mask (AM) control register (CR0) Protected Mode,
MOVNTQ instruction stores individual bytes register memory. MOVNTQ instruction acts streaming store minimize cache pollution. used store data without first reading data write allocate). "MOVNTQ mem64, mmreg" performs following operations:
mem64[63:0] mmreg
Chapter
Extensions MMXInstruction
Extensions 3DNow!and MMXInstruction Sets
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PAVGB
mnemonic PAVGB mmreg1, mmreg2 PAVGB mmreg, mem64 Privilege: Registers Affected: Flags Affected: Exceptions Generated:
Exception Invalid opcode Device available Stack exception (12) General protection (13) Segment overrun (13) Page fault (14) Floating-point exception pending (16) Alignment check (17) Real
opcode
description Packed average unsigned byte
none none
Virtual 8086 Protected Description emulate instruction (EM) control register (CR0) task switch (TS) control register (CR0) During instruction execution, stack segment limit exceeded. During instruction execution, effective address segment registers used operand points illegal memory location. instruction data operands falls outside address range 00000h 0FFFFh. page fault resulted from execution instruction. exception pending floating-point execution unit. unaligned memory reference resulted from instruction execution, alignment mask (AM) control register (CR0) Protected Mode,
PAVGB instruction produces rounded averages eight unsigned 8-bit integer values source operand register 64-bit memory location) eight corresponding unsigned 8-bit integer values destination operand register). does adding source destination byte values 9-bit unsigned intermediate value. intermediate value then incremented finally shifted right position. eight unsigned 8-bit results stored register specified destination operand. PAVGB instruction identical 3DNow! PAVGUSB instruction used pixel averaging MPEG-2 motion compensation video scaling operations.
Extensions MMXInstruction
Chapter
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Functional Illustration PAVGB Instruction
mmreg2/mem64
byte averaging
mmreg1
mmreg1
Indicates value that rounded-up
following list explains functional illustration PAVGB instruction:
rounded byte average FFh. rounded byte average 80h. rounded byte average also 80h. rounded byte average 10h. rounded byte average 01h. rounded byte average 5Ah. rounded byte average 7Fh. rounded byte average A1h.
"PAVGB mmreg1, mmreg2" performs following operations:
mmreg1[7:0] mmreg1[15:8] mmreg1[23:16] mmreg1[31:24] mmreg1[39:32] mmreg1[47:40] mmreg1[55:48] mmreg1[63:56] (mmreg1[7:0] (mmreg1[15:8] (mmreg1[23:16] (mmreg1[31:24] (mmreg1[39:32] (mmreg1[47:40] (mmreg1[55:48] (mmreg1[63:56] mmreg2[7:0] mmreg2[15:8] mmreg2[23:16] mmreg2[31:24] mmreg2[39:32] mmreg2[47:40] mmreg2[55:48] mmreg2[63:56]
Chapter
Extensions MMXInstruction
Extensions 3DNow!and MMXInstruction Sets
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"PAVGB mmreg, mem64" performs following operations:
mmreg[7:0] mmreg[15:8] mmreg[23:16] mmreg[31:24] mmreg[39:32] mmreg[47:40] mmreg[55:48] mmreg[63:56] (mmreg[7:0] (mmreg[15:8] (mmreg[23:16] (mmreg[31:24] (mmreg[39:32] (mmreg[47:40] (mmreg[55:48] (mmreg[63:56] mem64[7:0] mem64[15:8] mem64[23:16] mem64[31:24] mem64[39:32] mem64[47:40] mem64[55:48] mem64[63:56]
Related Instructions
PAVGW instruction.
Extensions MMXInstruction
Chapter
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PAVGW
mnemonic PAVGW mmreg1, mmreg2 PAVGW mmreg, mem64 Privilege: Registers Affected: Flags Affected: Exceptions Generated:
Exception Invalid opcode Device available Stack exception (12) General protection (13) Segment overrun (13) Page fault (14) Floating-point exception pending (16) Alignment check (17) Real
opcode
description Packed average unsigned word
none none
Virtual 8086 Protected Description emulate instruction (EM) control register (CR0) task switch (TS) control register (CR0) During instruction execution, stack segment limit exceeded. During instruction execution, effective address segment registers used operand points illegal memory location. instruction data operands falls outside address range 00000h 0FFFFh. page fault resulted from execution instruction. exception pending floating-point execution unit. unaligned memory reference resulted from instruction execution, alignment mask (AM) control register (CR0) Protected Mode,
PAVGW instruction same PAVGB instruction, except operates packed unsigned words instead. PAVGW produces rounded averages four unsigned 16-bit integer values source operand register 64-bit memory location) four corresponding unsigned 16-bit integer values destination operand register). does adding source destination byte values 17-bit unsigned intermediate value. intermediate value then incremented finally shifted right position. four unsigned 16-bit results stored register specified destination operand. "PAVGW mmreg1, mmreg2" performs following operations:
mmreg1[15:0] mmreg1[31:16] mmreg1[47:32] mmreg1[63:48] (mmreg1[15:0] (mmreg1[31:16] (mmreg1[47:32] (mmreg1[63:48] mmreg2[15:0] mmreg2[31:16] mmreg2[47:32] mmreg2[63:48]
Chapter
Extensions MMXInstruction
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"PAVGW mmreg, mem64" performs following operations:
mmreg[15:0] mmreg[31:16] mmreg[47:32] mmreg[63:48] (mmreg[15:0] (mmreg[31:16] (mmreg[47:32] (mmreg[63:48] mem64[15:0] mem64[31:16] mem64[47:32] mem64[63:48]
Related Instructions
PAVGB instruction.
Extensions MMXInstruction
Chapter
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PEXTRW
mnemonic PEXTRW reg32, mmreg, imm8 Privilege: Registers Affected: Flags Affected: Exceptions Generated:
Exception Invalid opcode Device available Stack exception (12) General protection (13) Segment overrun (13) Page fault (14) Floating-point exception pending (16) Alignment check (17) Real
opcode none none
description Extract word into integer register
Virtual 8086 Protected Description emulate instruction (EM) control register (CR0) task switch (TS) control register (CR0) During instruction execution, stack segment limit exceeded. During instruction execution, effective address segment registers used operand points illegal memory location. instruction data operands falls outside address range 00000h 0FFFFh. page fault resulted from execution instruction. exception pending floating-point execution unit. unaligned memory reference resulted from instruction execution, alignment mask (AM) control register (CR0) Protected Mode,
PEXTRW instruction extracts four words pointed imm8 from register stores that into least significant word 32-bit integer register. "PEXTRW reg32, mmreg, imm8" performs following operations:
index imm8[1:0] reg32[31:16] reg32[15:0] mmreg[index+15:index]
Related Instructions
PINSRW instruction.
Chapter
Extensions MMXInstruction
Extensions 3DNow!and MMXInstruction Sets
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PINSRW
mnemonic PINSRW mmreg, reg32, imm8 PINSRW mmreg, mem16, imm8 Privilege: Registers Affected: Flags Affected: Exceptions Generated:
Exception Invalid opcode Device available Stack exception (12) General protection (13) Segment overrun (13) Page fault (14) Floating-point exception pending (16) Alignment check (17) Real
opcode none none
Virtual 8086 Protected Description
description Insert word from integer register
emulate instruction (EM) control register (CR0) task switch (TS) control register (CR0) During instruction execution, stack segment limit exceeded. During instruction execution, effective address segment registers used operand points illegal memory location. instruction data operands falls outside address range 00000h 0FFFFh. page fault resulted from execution instruction. exception pending floating-point execution unit. unaligned memory reference resulted from instruction execution, alignment mask (AM) control register (CR0) Protected Mode,
PINSRW instruction inserts least significant word source operand integer register 16-bit memory location) into four words destination operand register). "PINSRW mmreg, reg32, imm8" performs following operations:
index imm8[1:0] temp1 temp1[index+15:index] reg32[15:0] temp2 mmreg temp2[index+15:index] mmreg temp1 temp2
"PINSRW mmreg, mem16, imm8" performs following operations:
index imm8[1:0] temp1 temp1[index+15:index] mem16[15:0] temp2 mmreg temp2[index+15:index] mmreg temp1 temp2
Related Instructions
PEXTRW instruction. Extensions MMXInstruction Chapter
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Extensions 3DNow!and MMXInstruction Sets
PMAXSW
mnemonic PMAXSW mmreg1, mmreg2 PMAXSW mmreg, mem64 Privilege: Registers Affected: Flags Affected: Exceptions Generated:
Exception Invalid opcode Device available Stack exception (12) General protection (13) Segment overrun (13) Page fault (14) Floating-point exception pending (16) Alignment check (17) Real
opcode
description Packed maximum signed word
none none
Virtual 8086 Protected Description emulate instruction (EM) control register (CR0) task switch (TS) control register (CR0) During instruction execution, stack segment limit exceeded. During instruction execution, effective address segment registers used operand points illegal memory location. instruction data operands falls outside address range 00000h 0FFFFh. page fault resulted from execution instruction. exception pending floating-point execution unit. unaligned memory reference resulted from instruction execution, alignment mask (AM) control register (CR0) Protected Mode,
PMAXSW instruction operates signed 16-bit data selects maximum signed value between source source each four word positions. "PMAXSW mmreg1, mmreg2" performs following signed operations:
mmreg1[15:0] mmreg1[31:16] mmreg1[47:32] mmreg1[63:48] (mmreg1[15:0] (mmreg1[31:16] (mmreg1[47:32] (mmreg1[63:48] mmreg2[15:0]) mmreg2[31:16]) mmreg2[47:32]) mmreg2[63:48]) mmreg1[15:0] mmreg1[31:16] mmreg1[47:32] mmreg1[63:48] mmreg2[15:0] mmreg2[31:16] mmreg2[47:32] mmreg2[63:48]
"PMAXSW mmreg, mem64" performs following signed operations:
mmreg[15:0] mmreg[31:16] mmreg[47:32] mmreg[63:48] (mmreg[15:0] (mmreg[31:16] (mmreg[47:32] (mmreg[63:48] mem64[15:0]) mem64[31:16]) mem64[47:32]) mem64[63:48]) mmreg[15:0] mmreg[31:16] mmreg[47:32] mmreg[63:48] mem64[15:0] mem64[31:16] mem64[47:32] mem64[63:48]
Related Instructions
PMINSW instruction.
Chapter
Extensions MMXInstruction
Extensions 3DNow!and MMXInstruction Sets
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PMAXUB
mnemonic PMAXUB mmreg1, mmreg2 PMAXUB mmreg, mem64 Privilege: Registers Affected: Flags Affected: Exceptions Generated:
Exception Invalid opcode Device available Stack exception (12) General protection (13) Segment overrun (13) Page fault (14) Floating-point exception pending (16) Alignment check (17) Real
opcode
description Packed maximum unsigned byte
none none
Virtual 8086 Protected Description emulate instruction (EM) control register (CR0) task switch (TS) control register (CR0) During instruction execution, stack segment limit exceeded. During instruction execution, effective address segment registers used operand points illegal memory location. instruction data operands falls outside address range 00000h 0FFFFh. page fault resulted from execution instruction. exception pending floating-point execution unit. unaligned memory reference resulted from instruction execution, alignment mask (AM) control register (CR0) Protected Mode,
PMAXUB instruction operates unsigned 8-bit data selects maximum unsigned value between source source each eight byte positions. "PMAXUB mmreg1, mmreg2" performs following unsigned operations:
mmreg1[7:0] mmreg1[15:8] mmreg1[23:16] mmreg1[31:24] mmreg1[39:32] mmreg1[47:40] mmreg1[55:48] mmreg1[63:56] (mmreg1[7:0] (mmreg1[15:8] (mmreg1[23:16] (mmreg1[31:24] (mmreg1[39:32] (mmreg1[47:40] (mmreg1[55:48] (mmreg1[63:56] mmreg2[7:0]) mmreg2[15:8]) mmreg2[23:16]) mmreg2[31:24]) mmreg2[39:32]) mmreg2[47:40]) mmreg2[55:48]) mmreg2[63:56]) mmreg1[7:0] mmreg1[15:8] mmreg1[23:16] mmreg1[31:24] mmreg1[39:32] mmreg1[47:40] mmreg1[55:48] mmreg1[63:56] mmreg2[7:0] mmreg2[15:8] mmreg2[23:16] mmreg2[31:24] mmreg2[39:32] mmreg2[47:40] mmreg2[55:48] mmreg2[63:56]
Extensions MMXInstruction
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"PMAXUB mmreg, mem64" performs following unsigned operations:
mmreg[7:0] mmreg[15:8] mmreg[23:16] mmreg[31:24] mmreg[39:32] mmreg[47:40] mmreg[55:48] mmreg[63:56] (mmreg[7:0] (mmreg[15:8] (mmreg[23:16] (mmreg[31:24] (mmreg[39:32] (mmreg[47:40] (mmreg[55:48] (mmreg[63:56] mem64[7:0]) mem64[15:8]) mem64[23:16]) mem64[31:24]) mem64[39:32]) mem64[47:40]) mem64[55:48]) mem64[63:56]) mmreg[7:0] mmreg[15:8] mmreg[23:16] mmreg[31:24] mmreg[39:32] mmreg[47:40] mmreg[55:48] mmreg[63:56] mem64[7:0] mem64[15:8] mem64[23:16] mem64[31:24] mem64[39:32] mem64[47:40] mem64[55:48] mem64[63:56]
Related Instructions
PMINUB instruction.
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PMINSW
mnemonic PMINSW mmreg1, mmreg2 PMINSW mmreg, mem64 Privilege: Registers Affected: Flags Affected: Exceptions Generated:
Exception Invalid opcode Device available Stack exception (12) General protection (13) Segment overrun (13) Page fault (14) Floating-point exception pending (16) Alignment check (17) Real
opcode
description Packed minimum signed word
none none
Virtual 8086 Protected Description emulate instruction (EM) control register (CR0) task switch (TS) control register (CR0) During instruction execution, stack segment limit exceeded. During instruction execution, effective address segment registers used operand points illegal memory location. instruction data operands falls outside address range 00000h 0FFFFh. page fault resulted from execution instruction. exception pending floating-point execution unit. unaligned memory reference resulted from instruction execution, alignment mask (AM) control register (CR0) Protected Mode,
PMINSW instruction operates signed 16-bit data selects minimum arithmetic value between source source each word. "PMINSW mmreg1, mmreg2" performs following signed operations:
mmreg1[15:0] mmreg1[31:16] mmreg1[47:32] mmreg1[63:48] (mmreg1[15:0] (mmreg1[31:16] (mmreg1[47:32] (mmreg1[63:48] mmreg2[15:0]) mmreg2[31:16]) mmreg2[47:32]) mmreg2[63:48]) mmreg1[15:0] mmreg1[31:16] mmreg1[47:32] mmreg1[63:48] mmreg2[15:0] mmreg2[31:16] mmreg2[47:32] mmreg2[63:48]
"PMINSW mmreg, mem64" performs following signed operations:
mmreg[15:0] mmreg[31:16] mmreg[47:32] mmreg[63:48] (mmreg[15:0] (mmreg[31:16] (mmreg[47:32] (mmreg[63:48] mem64[15:0]) mem64[31:16]) mem64[47:32]) mem64[63:48]) mmreg[15:0] mmreg[31:16] mmreg[47:32] mmreg[63:48] mem64[15:0] mem64[31:16] mem64[47:32] mem64[63:48]
Related Instructions
PMAXSW instruction.
Extensions MMXInstruction
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PMINUB
mnemonic PMINUB mmreg1, mmreg2 PMINUB mmreg, mem64 Privilege: Registers Affected: Flags Affected: Exceptions Generated:
Exception Invalid opcode Device available Stack exception (12) General protection (13) Segment overrun (13) Page fault (14) Floating-point exception pending (16) Alignment check (17) Real
opcode
description Packed minimum unsigned byte
none none
Virtual 8086 Protected Description emulate instruction (EM) control register (CR0) task switch (TS) control register (CR0) During instruction execution, stack segment limit exceeded. During instruction execution, effective address segment registers used operand points illegal memory location. instruction data operands falls outside address range 00000h 0FFFFh. page fault resulted from execution instruction. exception pending floating-point execution unit. unaligned memory reference resulted from instruction execution, alignment mask (AM) control register (CR0) Protected Mode,
PMINUB instruction operates unsigned 8-bit data selects minimum value between source source each byte position. "PMINUB mmreg1, mmreg2" performs following unsigned operations:
mmreg1[7:0] mmreg1[15:8] mmreg1[23:16] mmreg1[31:24] mmreg1[39:32] mmreg1[47:40] mmreg1[55:48] mmreg1[63:56] (mmreg1[7:0] (mmreg1[15:8] (mmreg1[23:16] (mmreg1[31:24] (mmreg1[39:32] (mmreg1[47:40] (mmreg1[55:48] (mmreg1[63:56] mmreg2[7:0]) mmreg2[15:8]) mmreg2[23:16]) mmreg2[31:24]) mmreg2[39:32]) mmreg2[47:40]) mmreg2[55:48]) mmreg2[63:56]) mmreg1[7:0] mmreg1[15:8] mmreg1[23:16] mmreg1[31:24] mmreg1[39:32] mmreg1[47:40] mmreg1[55:48] mmreg1[63:56] mmreg2[7:0] mmreg2[15:8] mmreg2[23:16] mmreg2[31:24] mmreg2[39:32] mmreg2[47:40] mmreg2[55:48] mmreg2[63:56]
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"PMINUB mmreg1, mem64" performs following unsigned operations:
mmreg[7:0] mmreg[15:8] mmreg[23:16] mmreg[31:24] mmreg[39:32] mmreg[47:40] mmreg[55:48] mmreg[63:56] (mmreg[7:0] (mmreg[15:8] (mmreg[23:16] (mmreg[31:24] (mmreg[39:32] (mmreg[47:40] (mmreg[55:48] (mmreg[63:56] mem64[7:0]) mem64[15:8]) mem64[23:16]) mem64[31:24]) mem64[39:32]) mem64[47:40]) mem64[55:48]) mem64[63:56]) mmreg[7:0] mmreg[15:8] mmreg[23:16] mmreg[31:24] mmreg[39:32] mmreg[47:40] mmreg[55:48] mmreg[63:56] mem64[7:0] mem64[15:8] mem64[23:16] mem64[31:24] mem64[39:32] mem64[47:40] mem64[55:48] mem64[63:56]
Related Instructions
PMAXUB instruction.
Extensions MMXInstruction
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PMOVMSKB
mnemonic PMOVMSKB reg32, mmreg Privilege: Registers Affected: Flags Affected: Exceptions Generated:
Exception Invalid opcode Device available Stack exception (12) General protection (13) Segment overrun (13) Page fault (14) Floating-point exception pending (16) Alignment check (17) Real
opcode none none
description Move byte mask integer register
Virtual 8086 Protected Description emulate instruction (EM) control register (CR0) task switch (TS) control register (CR0) During instruction execution, stack segment limit exceeded. During instruction execution, effective address segment registers used operand points illegal memory location. instruction data operands falls outside address range 00000h 0FFFFh. page fault resulted from execution instruction. exception pending floating-point execution unit. unaligned memory reference resulted from instruction execution, alignment mask (AM) control register (CR0) Protected Mode,
PMOVMSKB instruction selects most significant from each byte position register collapses eight bits into least significant byte integer register. "PMOVMSKB reg32, mmreg" performs following operations:
reg32[31:8] reg32[7] mmreg[63] reg32[6] mmreg[55] reg32[5] mmreg[47] reg32[4] mmreg[39] reg32[3] mmreg[31] reg32[2] mmreg[23] reg32[1] mmreg[15] reg32[0] mmreg[7]
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PMULHUW
mnemonic PMULHUW mmreg1, mmreg2 PMULHUW mmreg, mem64 Privilege: Registers Affected: Flags Affected: Exceptions Generated:
Exception Invalid opcode Device available Stack exception (12) General protection (13) Segment overrun (13) Page fault (14) Floating-point exception pending (16) Alignment check (17) Real
opcode
description Packed multiply high unsigned word
none none
Virtual 8086 Protected Description emulate instruction (EM) control register (CR0) task switch (TS) control register (CR0) During instruction execution, stack segment limit exceeded. During instruction execution, effective address segment registers used operand points illegal memory location. instruction data operands falls outside address range 00000h 0FFFFh. page fault resulted from execution instruction. exception pending floating-point execution unit. unaligned memory reference resulted from instruction execution, alignment mask (AM) control register (CR0) Protected Mode,
PMULHUW instruction multiplies four unsigned words source operand with four unsigned words destination operand. upper bits 32-bit intermediate result placed into destination operand. "PMULHUW mmreg1, mmreg2" performs following operations:
temp1 temp2 temp3 temp4 (mmreg1[15:0] (mmreg1[31:16] (mmreg1[47:32] (mmreg1[63:48] mmreg2[15:0]) mmreg2[31:16]) mmreg2[47:32]) mmreg2[63:48])
mmreg1[15:0] mmreg1[31:16] mmreg1[47:32] mmreg1[63:48]
temp1[31:16] temp2[31:16] temp3[31:16] temp4[31:16]
Extensions MMXInstruction
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"PMULHUW mmreg, mem64" performs following operations:
temp1 temp2 temp3 temp4 (mmreg1[15:0] (mmreg1[31:16] (mmreg1[47:32] (mmreg1[63:48] mem642[15:0]) mem64[31:16]) mem64[47:32]) mem64[63:48])
mmreg1[15:0] mmreg1[31:16] mmreg1[47:32] mmreg1[63:48]
temp1[31:16] temp2[31:16] temp3[31:16] temp4[31:16]
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PREFETCHNTA PREFETCHT0 PREFETCHT1 PREFETCHT2
mnemonic PREFETCHNTA mem8 PREFETCHT0 mem8 PREFETCHT1 mem8 PREFETCHT2 mem8 Privilege: Registers Affected: Flags Affected: Exceptions Generated: opcode ModR/M none none none none description Move data closer processor using reference. Move data closer processor using reference. Move data closer processor using reference. Move data closer processor using reference.
prefetch instruction brings cache line into processor cache level(s) specified locality reference. address prefetched cache line specified mem8 value. prefetch instruction loads cache line even mem8 address aligned with start line. cache line already contained cache level that lower than locality reference memory fault detected, then cycle initiated instruction treated NOP. operation prefetch instructions processor implementation dependent. instructions ignored changed processor implementation, though they will change program behavior. cache line size also implementation dependent having minimum size bytes. Bits ModR/M byte indicate cache locality references. Table Locality References Prefetch Instructions
Description Move specified data into processor with minimal L1/L2 cache pollution. Move specified data into cache levels. Move specified data into cache levels except level cache. Move specified data into cache levels except level caches.
Locality Reference
Note:
level cache implementation dependent.
Extensions MMXInstruction
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PSADBW
mnemonic PSADBW mmreg1, mmreg2 PSADBW mmreg, mem64 Privilege: Registers Affected: Flags Affected: Exceptions Generated:
Exception Invalid opcode Device available Stack exception (12) General protection (13) Segment overrun (13) Page fault (14) Floating-point exception pending (16) Alignment check (17) Real
opcode
description Packed absolute byte differences
none none
Virtual 8086 Protected Description emulate instruction (EM) control register (CR0) task switch (TS) control register (CR0) During instruction execution, stack segment limit exceeded. During instruction execution, effective address segment registers used operand points illegal memory location. instruction data operands falls outside address range 00000h 0FFFFh. page fault resulted from execution instruction. exception pending floating-point execution unit. unaligned memory reference resulted from instruction execution, alignment mask (AM) control register (CR0) Protected Mode,
PSADBW instruction absolute value differences between each byte position source source "PSADBW mmreg1, mmreg2" performs following operations:
mmreg1[63:16] mmreg1[15:0] abs(mmreg1[7:0] abs(mmreg1[15:8] abs(mmreg1[23:16] abs(mmreg1[31:24] abs(mmreg1[39:32] abs(mmreg1[47:40] abs(mmreg1[55:48] abs(mmreg1[63:56] mmreg2[7:0]) mmreg2[15:8]) mmreg2[23:16]) mmreg2[31:24]) mmreg2[39:32]) mmreg2[47:40]) mmreg2[55:48]) mmreg2[63:56])
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"PSADBW mmreg, mem64" performs following operations:
mmreg[63:16] mmreg[15:0] abs(mmreg[7:0] abs(mmreg[15:8] abs(mmreg[23:16] abs(mmreg[31:24] abs(mmreg[39:32] abs(mmreg[47:40] abs(mmreg[55:48] abs(mmreg[63:56] mem64[7:0]) mem64[15:8]) mem64[23:16]) mem64[31:24]) mem64[39:32]) mem64[47:40]) mem64[55:48]) mem64[63:56])
Related Instructions
PAVGUSB instruction.
Extensions MMXInstruction
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PSHUFW
mnemonic PSHUFW mmreg1, mmreg2, imm8 PSHUFW mmreg, mem64, imm8 Privilege: Registers Affected: Flags Affected: Exceptions Generated:
Exception Invalid opcode Device available Stack exception (12) General protection (13) Segment overrun (13) Page fault (14) Floating-point exception pending (16) Alignment check (17) Real
opcode
description Packed shuffle word
none none
Virtual 8086 Protected Description emulate instruction (EM) control register (CR0) task switch (TS) control register (CR0) During instruction execution, stack segment limit exceeded. During instruction execution, effective address segment registers used operand points illegal memory location. instruction data operands falls outside address range 00000h 0FFFFh. page fault resulted from execution instruction. exception pending floating-point execution unit. unaligned memory reference resulted from instruction execution, alignment mask (AM) control register (CR0) Protected Mode,
PSHUFW instruction selects from four words source operand register 64-bit memory location) possible ways defined immediate byte. "PSHUFW mmreg1, mmreg2, imm8" performs following operations:
index3 imm8[7:6] index2 imm8[5:4] index1 imm8[3:2] index0 imm8[1:0] temp mmreg2 mmreg1[63:48] temp[index3+15:index3] mmreg1[47:32] temp[index2+15:index2] mmreg1[31:16] temp[index1+15:index1] mmreg1[15:0] temp[index0+15:index0]
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"PSHUFW mmreg, mem64, imm8" performs following operations:
index3 imm8[7:6] index2 imm8[5:4] index1 imm8[3:2] index0 imm8[1:0] mmreg[63:48] mem64[index3+15:index3] mmreg[47:32] mem64[index2+15:index2] mmreg[31:16] mem64[index1+15:index1] mmreg[15:0] mem64[index0+15:index0]
Extensions MMXInstruction
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SFENCE
mnemonic SFENCE Privilege: Registers Affected: Flags Affected: Exceptions Generated: opcode imm8 none none none none description Store fence
weakly ordered system, hardware allowed reorder reads writes between processor memory. example, writeback stores complete ahead write-combining stores. SFENCE provides mechanism force strong ordering between routines that produce weakly ordered results (such memory types). SFENCE instruction makes previous writes globally visible preceding store. example, SFENCE instruction will force newer write-back store wait until older streaming stores write-combining stores completed. Note: Software should encode SFENCE instruction with ModR/M byte 0xF8. other possible ModR/M encodings reserved future use.
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Extensions MMXInstruction
Chapter

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