Product Overview 10.97 4360 Revision History: Previous Version: P

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Content Addressable Memory Element CAME 4360 Version
Product Overview 10.97
4360 Revision History: Previous Version: Page previous Version) Page current Version) Current Version: 10.97 Subjects (major changes since last revision) Editorial Update
Edition 10.97 This edition realized using software system FrameMaker,. Published Siemens 81541 Siemens 1997. Rights Reserved. Attention please! patents other rights third parties concerned, liability only assumed components, applications, processes circuits implemented within components assemblies. information describes type component shall considered assured characteristics. Terms delivery rights change design reserved. questions technology, delivery prices please contact Semiconductor Group Offices Germany Siemens Companies Representatives worldwide (see address list). technical requirements components contain dangerous substances. information types question please contact your nearest Siemens Office, Semiconductor Group. Siemens approved CECC manufacturer. Packing Please recycling operators known you. also help touch with your nearest sales office. agreement will take packing material back, sorted. must bear costs transport. packing material that returned unsorted which obliged accept, shall have invoice costs incurred. Components used life-support devices systems must expressly authorized such purpose! Critical components1 Semiconductor Group Siemens only used life-support devices systems2 with express written approval Semiconductor Group Siemens critical component component used life-support device system whose failure reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain human life. they fail, reasonable assume that health user endangered.
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Table Contents 4.4.1 4.4.2
Page
Overview Logic Symbol Configuration Definitions Functions System Integration Functional Overview Data Flow Functional Description CAME Programming Search Search Result Pattern Reading Search Pattern Predefined Value Configuration Testing CAME Search Operation Cell Processing Data Structure Request Commands Mode Data Structure Request Commands Mode References Acronyms
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Overview Overview 4310 ASwitching Matrix 4325 ASwitching Preprocessor 4330 ABuffer Manager 4340 AOAM Processor 4350 ALayer Processor ALP. 4360 Content Addressable Memory Element CAME
second generation Siemens Alayer chip consists chips
These chips form complete chip build Aswitch. generic Aswitch consists switching fabric switch ports shown figure
Conn. UTOPI Pol.
Conn.
CAME
Pointer UTOP
Cell
Conn.
UTOPIA
UTOPIA
SLIF
Aswitching fabric
PHYs
4350
4340
4330
4325
consisting 4310
chips
Conn. Conn. connection data Pol. policing data address reduction circuit Cell Acell storage
Conn.
Cell
Conn.
switch port
Figure
ASwitch Basic Configuration
Siemens Alayer chip switching fabric only does cell routing using 4310 ASM, which used stand alone arrays scale switching network throughput from Gbit/s more than Gbit/s. other Alayer functions performed switch ports: policing, header translation cell counting 4350 CAME 4360, functions 4340 traffic management 4330 ABM. 4325 access device switching fabric adds/removes routing header. also supports redundant switching fabrics does multicast. Only interfaces used data transfer: industry standard UTOPIA Level multi-PHY interfaces proprietary Switch Link InterFace SLIF. This serial, differential high speed link using LVDS levels.
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Overview applications single board switch with Mbit/s throughput built with only 4350 4330 ABM. Such mini-switch basically switch port stand alone, without switching network access 4325 ASP. full functionality needed 4340 chip omitted shown figure Minimum multicast functionality also built into 4350 ALP. external Address Reduction Circuit (CAME) required built-in address reduction used.
Conn.
UTOPIA
Pol.
CAME
UTOPIA
Point
Cell
PHYs
4350
4330
connection data policing data address reduction circuit Acell rage
Conn.
Cell
Figure
Mini Switch with Mbit/s Throughput
Apart from applications figure many other combinations chip possible designing Aswitches. Functionality selectable many combinations modular function split chip set. Address reduction, multicast, policing, redundant switching network other functions implemented appropriate chip combinations. number supported connections scales with size external connection RAMs. policing data omitted this function required.Thus functionality size Aswitch tailored exactly what respective application requires, without carrying overhead unnecessary functions.
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Content Addressable Memory Element CAME
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Version Features Co-processor Address Reduction search Port Number corresponding Local Connection Identifier Delivers search result during cell cycle rate MBit/s CAME supports 8192 search entries Master Slave mode selectable cascade CAME supporting 16384 search entries
CMOS
TQFP-144
Data Interface selectable, uses Overwrite Protection valid connections Microprocessor Interface necessary CAME configurated Address Data search modes supported search corresponding search corresponding search corresponding first valid cells Status Report -information search result: single match, mismatch multimatch -information whether connection valid invalid given LCI, -information whether terminated terminated given LCI, Parity error indication Data CAME cascade error indication Boundary Scan support according JTAG Technology TQFP-144 package 3.3V Power Supply Power dissipation Temperature range from +70°C
Type 4360
Semiconductor Group
Ordering Code Q67003-H9328
Package TQFP-144
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Logic Symbol
Test/JTAG Interface
4360 CAME
CAME Cascade Interface
Data Interface
Figure CAME Logic Symbol
Address Interface
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(Top view)
Configuration
TMD0 TMD1 TMD2 TMD3 TMD4 TMD5 TMD6 TMD7 VBIAS RBIAS
EN16 DAT32 DAT31 DAT30 DAT29 DAT28 DAT27 DAT26 DAT25 DAT24 DAT23 DAT22 DAT21 DAT20
CAME 4360
DAT19 DAT18 DAT17 DAT16 DAT15 DAT14 DAT13 DAT12 DAT11 DAT10 DAT9 DAT8 DAT7 DAT6 DAT5 DAT4 DAT3
TRST ADR0 ADR1 ADR2 ADR3 DAT0 DAT1 DAT2
ITP09962
Figure
CAME Configuration
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Definitions Functions
following explanations applies pins field table respectively: Pins with attached connected with internal pull resistor. Definitions Functions Symbol Input Function Output
General pins) Hardware reset signal Active Clock input interface
Data Address Interface between CAME DAT(32:0) Data interface incl. parity (DAT(0)).
ADR(3:0) EN16
Address interface Chip enable signal interface. Active Output enable signal interface. Active Write enable signal interface. Active mode enable signal interface. then DAT(16:0) used. then DAT(32:0) used.
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Definitions Functions (cont'd) Symbol Input Function Output
CAME Cascade Interface 137, 135, 131, 129, CI(2:0) CO(2:0) Cascade interface address input Cascade interface communication channel Cascade interface communication channel
JTAG Interface
TRST
Boundary scan test reset Active Boundary scan test data input Boundary scan test clock input Boundary scan test mode select Boundary scan test data output
Additional Testpins 125, 123, 121, 119, 117, 115, 113, Miscellaneous VBIAS Analog reference voltage input, used precise adjustment internal current sources. VBIAS value: 1.235V ±1%. Calibration output, used define bias current internal current sources. resistor (12.1 ±1%) must connected between RBIAS ground. TMD(7:0) Test Interface. Only test purpose.
RBIAS
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Definitions Functions (cont'd) Supply (P3V3) 100, 102, 105, 108, 111, 114, 118, Supply Voltage (nom. 3.3V) 122, 126, 130, 134, 138, Digital ground (0V) 101, 103, 107, 110, 112, 116, 120, 124, 128, 132, 136, 141, Function
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System Integration System Integration
CAME connected only connections supported. connections second CAME cascaded first CAME. master which controls first CAME. CAME cascaded second CAME configurated slave device which controlled first CAME which operated master mode.
ARCCLK ARCCS ARCWE ARCOE ARCRES ARCADR(3:0)
ADR(3:0) EN16 DAT(16:0)
CAME
(Master)
ARCDAT(16:0)
DAT(32:17) CI(2:0) CO(2:0)
CO(2:0) CI(2:0) ADR(3:0)
CAME
(Slave)
EN16 DAT(16:0)
DAT(32:17)
Figure
CAME Application Connections
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Functional Overview Functional Overview
CAME Content Addressable Memory Element which search programmable pattern corresponding programmable pattern vice versa. Additionally search bits provided support search unused entries support search F4-OAM connections used ATM. CAME supports 8192 entries which extended 16384 entries with second cascadeable CAME without additional glue logic. target application CAME Header Translation mechanism Acells which performed Siemens Alayer chip 4350. extracts from ACell Header sends together with Port Number pattern CAME. After search procedure CAME corresponding pattern send back ALP. pattern used Local Connection Identifier being inserted into Acell header. Herewith CAME translates arbitrary address, inside address range 232, into another arbitrary address inside address range CAME cascaded. complete search process completed during Acell cycle bitrate MBit/s.
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Data Flow Functional Description CAME Data Flow Functional Description CAME
CAME configurated, operated tested request commands. Each request command combination different write read commands which transmitted Data CAME. Address selects request commands. data flow writing search pattern into CAME such that defines address memory where VPI, VCI, auxiliary bits P_IP VCON stored. CAME operated inverse cell processing. this case address memory where stored. Additionally also search report transmitted ALP. request commands activated during cell processing request commands activated microprocessor CAME microprocessor interface. Each request commands described following sections.
Data
Address
CAME
Write Data Register (0:33)
Read Data Register (0:33)
Address Register (0:13)
Conf. Register (13:0)
Configuration control logic PN(3:0), VPI(11:0), VCI(15:0), VCON, P_IP
Memory
LCI(13:0) Search Control logic
Search Address Register (0:31)
Search Data Register (0:13)
Status Register (3:0)
Figure
Block Diagram CAME Programming Search Search Result Pattern
Request Command number should used setup release connection. first bits) auxiliary bits VCON P_IP written data into Write Data Register Address Register. Subsequently written into Write Data Register. subdivision within word allowed. Address Register defines address memory where contents Write Data Register written into memory. After writing entry into memory status information current request stored Status Register which read each request.
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Data Flow Functional Description CAME auxiliary VCON defines whether entry valid invalid. This mechanism used prevent overwriting valid connection corresponding configuration TESTMODE register set. second configuration TESTMODE register foreseen prevent multimatch entry. CAME checks whether already exists. case that entry exists (single multimatch) CAME prevents writing outputs failure report status register. case that entry exists (mismatch) CAME writes entry memory entry invalid otherwise writing also prevented. there checking whether both valid connection changed multimatch condition generated. influence execution time Request Command number auxiliary P_IP defines whether connection point Path Intermediate Point. P_IP values ignored during search process. TESTMODE register foreseen testing memory. write request converted into test write request memory banks written simultaneously. Reading Search Pattern Predefined Value
Request Command number should used user wants check Search Pattern Search result pattern VCON P_IP given LCI. first bits) written data into Address Register. Then VPI, VCI, VCON P_IP written from memory Read Data Register. Read Data Register Status Register read data CAME. TESTMODE register foreseen testing memory. read request converted into test read request memory banks read simultaneously. Configuration Testing CAME
Request Command number should used user wants search Search Pattern with deactivated search fields defined TESTMODE register. This request command should activated microprocessor CAME Interface. used during normal cell processing. first written data into Search Address Register. After predefined search period search result (LCI auxiliary bits VCON P_IP) written into Search Data Register. status information Status Register contents Search Data Register read data CAME. TESTMODE register bits VCEN, VPEN VSET foreseen define whether ignored. Furthermore possible search invalid free entries identified VCON equal zero. Additionally implemented convert search request into test search request which compares memory banks parallel.
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Data Flow Functional Description CAME Request Command number implemented configure CAME operation test. This request substitute microprocessor interface. configuration test mode commands written into TESTMODE register data CAME. Herewith possible check cascade interface between Master Slave CAME check parity data address CAME read version number CAME configure response write request command number configure response search request command number configure test functions CAME. Search Operation Cell Processing
search request commands supported CAME. first search request command number used search processing F4-OAM cells termination point. Normally F4-OAM cell identified value segment end-to-end flow. identifies F4-OAM cells search request command number Herewith written into Search Address Register data CAME. After predefined search period search result (LCI auxiliary bits VCON P_IP) written into Search Data Register. Subsequently search data status information read from ALP. case valid search result value written into GFC, UDF1 field Acell. Herewith CAME borrows from user cell transmit F4-OAM cell which identifies F4-OAM cells value This mechanism saves number needed transport F4OAM cells between AOP. ignores F4-OAM cells mulimatch alarm from CAME obvious that terminated delivers VCIs match only value used search pattern. used value lowest LCI. search request number used search processing cells belonging connection. search request identical search request command except that value also written into Search Address Register. connections auxiliary P_IP must which suppresses search pattern. Herewith only values considered. data structure request commands corresponding write read commands 16bit mode described following sections.
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Data Flow Functional Description CAME 4.4.1 Data Structure Request Commands Mode
CAME Data bit(16) used parity line completes ARCDAT(1:15) ACRADR(0:3) parity.
Note: Shadowed fields represent unused bits.
Request Number Search Processing Flow bit: Write address PN(3:0) Wait command execution Read from address Read from address VPI(11:0)
LCI(13:0)
Request Number Search processing ACells belonging bit: PN(3:0) VPI(11:0) Write address VCI(15:0) Write address Wait command execution Read from address LCI(13:0) Read from address
Request Number Search Processing activated Microprocessor bit: Write address PN(3:0) VPI(11:0) VCI(15:0) Write address Wait command execution LCI(13:0) Read from address Read from address
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Data Flow Functional Description CAME Request Number Write Command Setup Release Connections Microprocessor bit: LCI(13:0) Write address Write address PN(3:0) VPI(11:0) Write address VCI(15:0) Wait command execution Read from address Read from address
Request Number Read Command Verification Connection Entry Microprocessor bit: LCI(13:0) Write address Wait command execution Read from address PN(3:0) VPI(11:0) Read from address VCI(15:0) Read from address Read from address
Request Number CAME Test Configuration Command Microprocessor bit: Testmode(13:0) Write address Wait command execution Read from address Testmode(13:0) Read from address
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Data Flow Functional Description CAME 4.4.2 Data Structure Request Commands Mode
Request Number Search Processing Flow bit:
Write address CAME PN(3:0) VPI(11:0) Wait command execution Read from address CAME LCI(13:0)
Request Number Search processing ACells belonging bit: VCI(15:0)
Write address CAME PN(3:0) VPI(11:0) Wait command execution Read from address CAME Request Number Search Processing activated Microprocessor bit: PN(3:0) VPI(11:0)
LCI(13:0)
VCI(15:0)
Write address CAME Wait command execution Read from address CAME LCI(13:0)
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Data Flow Functional Description CAME Request Number Write Command Setup Release Connections Microprocessor bit: Write address CAME PN(3:0) VPI(11:0) Wait command execution Read from address CAME Request Number Read Command Verification Connection Entry Microprocessor bit: LCI(13:0) Wait command execution Read from address CAME PN(3:0) VPI(11:0) Request Number CAME Test Configuration Command Microprocessor bit: TESTMODE(13:0) Wait command execution Read from address CAME TESTMODE(13:0) VCI(15:0) Read from address CAME LCI(13:0) VCI(15:0)
Write address CAME
Write address CAME
Write address CAME
Note: represents P_IP flag, represents VCON flag.
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References References
UTOPIA Level Specification Version 2.01, March 1994, AForum UTOPIA Level Specification Version 1.0, June 1995, AForum IEEE 1596.3 Standard Low-Voltage Differential Signals SCI, Draft 1.3, Nov. JTAG Acronyms 4330 ABuffer Manager 4350 ALayer Processor 4340 AOAM Processor Address Reduction Circuit ASwitching Fabric 4310 ASwitching Matrix byte octet CAME Content Addressable Memory Element double word Virtual Path Layer Virtual Channel Layer Header Translation Input Output Intermediate Point Local Connection Identifier Least Significant octet byte Operation Maintenance SSRAM Synchronous Static defined Terminating Point Virtual Channel Connection Virtual Channel Identifier standardized Acell Virtual Path specific Virtual Path Connection Virtual Path Identifier standardized Acell word
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Product Overview 10.97 4360 Revision History: Previous Version: P

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