Programmable Bandwidth Mbps Gbps, Gbps serial signaling rate Flex

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Programmable Bandwidth Mbps Gbps, Gbps serial signaling rate Flex

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Programmable Serial Interface PRELIMINARY (High Speed Devices)
Programmable Bandwidth
Mbps Gbps, Gbps serial signaling rate Flexible parallel-to-serial conversion transmit path Flexible serial-to-parallel conversion receive path Multiple selectable loopback/loop-through modes 100K 200K usable gates CPLD logic 240K integrated memory 192K 384Kb synchronous asynchronous SRAM 96Kb true Dual-Port FIFO Internal transmit receive PLLs Logic dedicated Spread Aware Transmit FIFO flexible variable phase clocking Differential serial input with internal termination DC-restoration Differential serial output with source matched impedance 160-240 user programmable I/Os VoltI/O interface Programmable 1.8V, 2.5V, 3.3V Multiple standards LVCMOS, LVTTL, 3.3V PCI, SSTL2(I-II), SSTL3(I-II), HSTL(I-IV), GTL+ Direct interface standard fiber-optic modules Designed drive: Fiberoptic Modules Copper Cables Circuit Board Traces Backplane Links Box-to-Box Links Chip-to-Chip Communication Extremely flexible clocking options Four global clocks additional product term clocks Clock polarity every register Carry chain logic fast efficient arithmetic operations Fully compliant (Rev. 2.2) JTAG programming interface with boundary scan support High-Speed (HS) Frequency Agile (FA) Programmable Serial Interface(PSITM) versions available Power-saving mode serial channels available allow: High-Bandwidth Redundancy Supported standards: InfiniBand- SONET OC-48
Frequency Agile Features[1]
Mbps-1.5 Gbps serial signaling rate channel eight serial channels available allow: Frequency Agile Redundancy Selectable input output clocking options MultiFramereceive framer provides alignment Bit, byte, half-word, word, multi-word COMMA Full K28.5 detect Single Multi-byte framer byte alignment Low-latency option Skew alignment support multiple bytes offset Selectable parity check/generate Serial Built-In-Self-Test (BIST) at-speed link testing Per-channel Link Quality Indicator Analog signal detect Digital signal detect Frequency range detect Supported standards: Fibre Channel Gigabit Ethernet ESCON SMPTE
Development Software
Warp® IEEE 1076/1164 VHDL IEEE 1364 Verilog context sensitive editing Active-HDL graphical finite state machine editor Active-HDL post-synthesis timing simulator Architecture Explorer detailed design analysis Static Timing Analyzer critical path analysis Available Windows® Supports Cypress programmable logic products
High-Speed Gbps/channel serial signaling rate Full Bellcore jitter compliance
Note: more detail, refer "Frequency Agile PSI" data sheet.
Cypress Semiconductor Corporation Document 38-02021 Rev.
3901 North First Street
Jose
95134 408-943-2600 Revised August 2001
Programmable Serial Interface (High Speed Devices) PRELIMINARY
Quick Reference Selection Guide
High-Speed/SONET/SDH Serial Bandwidth Logic Gate Density 100K 200K Gbps 25G01K100 Gbps 25G02K100 25G02K200 Frequency-Agile Serial Bandwidth Gbps 15G04K100 15G04K200 15G08K200 Gbps
Family Standards Supported
Device SONET/SDH CYS25G01K100 CYS25G02K100 CYS25G02K200 High Speed CYP25G01K100 CYP25G02K100 CYP25G02K200 Frequency Agile CYP15G04K100 CYP15G04K200 CYP15G08K200 SONET/SDH (OC48/STM16) InfiniBand Fibre Channel Gigabit Ethernet ESCON SMPTE 259/292 Custom
Family General Selection Guide
Device 25G01K100 25G02K100 25G02K200 15G04K100 15G04K200 15G08K200 Typical Gates 46K-144K 46K-144K 92K-288K 46K-144K 92K-288K 92K-288K Macrocells 1536 1536 3072 1536 3072 3072 Cluster memory (Kbits) Channel memory (Kbits) Maximum User Programmable Package Offering 456-BGA (35x35 1.27 pitch) 456-BGA (35x35 1.27 pitch) 700-BGA (45x45 1.27 pitch) 456-BGA (35x35mm, 1.27 pitch) 700-BGA (45x45 1.27 pitch) (45x45 1.27 pitch)
Shaded areas contain advance information.
Family Performance Selection Guide
Device 25G01K100 25G02K100 25G02K200 15G04K100 15G04K200 15G08K200 Channels Link Speed Gbps Gbps Gbps Gbps Gbps Gbps Total Bandwidth Gbps Gbps Gbps Gbps Gbps 12.0 Gbps fMAX2 (MHz) Logic Speed- Pin-to-Pin (ns) Standby ICC[2]
Note: Standby values with logic utilized, output load, stable inputs. Shaded area preliminary
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
GCLK[1:0] GCTL[3:0]
GCLK[1:0]
Clock
Bank
Bank
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
GCLK[1:0]
Bank
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
GCLK[1:0]
Bank
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Phase Align Buffer
Deserializer
Phase Align Buffer
Deserializer
Serializer
Serializer
Serial Signal Bank
Figure High-Speed PSIBlock Diagram (25G02K100) with Bank Structure.
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XCVR CNTRL
Bank
Bank
Programmable Serial Interface (High Speed Devices) PRELIMINARY
GCLK[1:0]
Clock
GCTL[3:0]
GCLK[1:0]
Bank
Bank
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
GCLK[1:0]
Bank
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
GCLK[1:0]
Bank
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Phase Align Buffer
Deserializer
Serializer
Serial Signal Bank
Figure High-Speed PSIBlock Diagram (25G01K100) with Bank Structure.
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XCVR CNTRL
Bank
Bank
Programmable Serial Interface (High Speed Devices) PRELIMINARY
Functional Description
Programmable Serial Interface (PSI) family point-topoint point-to-multipoint programmable communications building block allowing manipulation transfer data over high-speed serial links signaling speeds ranging from Mbps 1.5Gbps Gbps serial link. family designed combine high speed, predictable timing, high density, power, ease complex programmable logic devices (CPLD) with serializing/deserializing (SERDES) capability high-speed serial transceivers. family divided into groups: High-Speed Frequency-Agile PSI. Both groups have unique transceiver characteristics that define specific transceiver block operation given device. architecture device based logic block clusters (LBC) serial transceiver blocks that connected horizontal vertical routing channels. Each features eight individual logic blocks (LB) marcrocells cluster memory blocks. Adjacent each channel memory block which externally accessible through interface. Each transmit channel transceiver accepts parallel characters, encodes each character transport converts serial data. Each receive channel accepts serial data converts parallel data, decoding data into characters presents these characters routing channels unit. High-Speed transceiver operation high-speed programmable serial interface devices self-contained single block. separate transmit receive PLLs Clock Data Recovery (CDR) unit flexible clocking. transmit channel accepts 16-bit input character from routing channels passes character elasticity buffer. This character then serialized output dual differential transmissionline drivers required bit-rate. receive channel accepts serial bit-stream from differential line receivers. This bit-stream deserialized 16-bit character presented routing channels device. block also features loop-back loop-through modes simplified design debugging. Global Routing Description routing architecture block device made horizontal vertical (H&V) routing channels. These routing channels allow signals move among I/Os, logic blocks memories. addition horizontal vertical routing channels that interconnect banks, channel memory blocks, transceiver blocks logic block clusters, each contains Programmable Interconnect Matrix(PIMTM), which used route signals among logic blocks cluster memory blocks LBC. Figure block diagram routing channels that interface within architecture. exactly same every member family. Transceiver Block Each transceiver block given device will have serializer transmit path deserializer receive path operating speed from Mbps 1.5Gbps Gbps. transceiver block interfaces routing channels device through highly configurable datapath cells. specific architecture operation transceiver blocks please refer Serial Transceiver Operation section (page 17). High-Speed Transceiver Blocks High-Speed devices include transceiver blocks operating Gbps channel. Both channels operate independently each other. They same reference clock. internal interfacing transceiver blocks highspeed device occur through port definition highspeed transceiver block. internal signals their definition described "Pin Signal Description" section (page 46). Standard Datapath Cell Figure block diagram datapath cell. datapath cell contains three-state transmit buffer, receive buffer, register that configured transmit receive register. Transceiver Enable (TE) selected from four global control signals from Output Control Channel (OCC) signals. transmit enable configured always enabled always disabled controlled remaining inputs mux. selection done that includes inputs. global clocks selected clock datapath cell register. clock output input clock polarity that allows transmit/receive register clocked either edge clock.
REFCLK±
System
Programmable Host Interface
Optical Transceiver
Optical Fiber Links
OUT- OUT+
Serial Data
Serial Data
Figure High-Speed System Connections with Optical Interface.
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Registered
From Output
Receive
Routing Channel
Output Control Channel
Global Control Signals
Global Clock Signals
Register Receive
Transmit
Register Enable Clock Polarity
Signal
Clock
Register Reset
Figure Block Diagram Standard Datapath Cell. Logic Block Cluster (LBC) architecture consists several logic block clusters, each which have Logic Blocks (LB) cluster memory blocks connected Programmable Interconnect Matrix (PIM) shown Figure Each cluster memory block consists 8-Kbit single-port RAM, which configurable synchronous asynchronous. cluster memory blocks cascaded with other cluster memory blocks within same well other LBCs implement larger memory functions. cluster memory block specifically utilized designer, Cypress's Warp software automatically implement large blocks logic. LBCs interface with each other horizontal vertical routing channels.
Block
Cluster Memory Block
Cluster
Cluster Memory Block
Channel Memory Block
Channel memory outputs drive dedicated tracks horizontal vertical routing channels
Block
H-to-V V-to-H
inputs from cells drive dedicated tracks horizontal vertical routing channels
Figure Routing Interface.
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Clock Inputs GCLK[3:0]
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Cluster Memory
Cluster Memory
Carry Chain
Inputs From Horizontal Routing Channel
Inputs From Vertical Routing Channel
Outputs Horizontal Vertical cluster-to-channel PIMs
Figure Logic Block Cluster Diagram. Logic Block (LB) logic block basic building block architecture. consists product term array, intelligent productterm allocator, macrocells. Product Term Array Each logic block features programmable product term array. This array accepts inputs from PIM. These inputs originate from device pins macrocell feedbacks well cluster memory channel memory feedbacks. Active active HIGH versions each these inputs generated create full 72-input field. product terms array created from inputs. product terms, general-purpose macrocells logic block. remaining three product terms logic block used asynchronous asynchronous reset product terms. final product term Product Term clock (PTCLK) shared macrocells within logic block. Product Term Allocator Through product term allocator, Warp software automatically distributes product terms needed among macrocells logic block. product term allocator provides important capabilities without affecting performance: product term steering product term sharing. Product Term Steering Product term steering process assigning product terms macrocells needed. example, macrocell requires product terms while another needs just three, product term allocator will "steer" product terms macrocell three other. devices, product terms steered individual basis. number between 1and product terms steered macrocell. Product Term Sharing Product term sharing process using same product term among multiple macrocells. example, more than function more product terms equation that common other functions, those product terms only created once. product term allocator allows sharing across groups four macrocells variable fashion. software automatically takes advantage this capability that user does have intervene. Note that neither product term sharing product term steering have effect speed product. steering sharing configurations have been incorporated timing specifications devices.
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Macrocell Within each logic block there macrocells. Each macrocell accepts product terms from product term array. these product terms output either registered combinatorial mode. Figure displays block diagram macrocell. register asynchronously preset asynchronously reset macrocell level with separate preset reset product terms. Each these product terms features programmable polarity. This allows registers preset reset based expression expression. gate macrocell allows many different types equations realized. used polarity implement true complement form equation product term array toggle turn flip-flop into flip-flop. carry-chain input allows additional flexibility implementation different types logic. macrocell utilize carry chain logic implement adders, subtractors, magnitude comparators, parity tree, even generic logic. output macrocell either registered combinatorial. Carry Chain Logic macrocell features carry chain logic which used fast efficient implementation arithmetic operations. carry logic connects macrocells logic blocks total macrocells. Effective data path operations imCarry (from macrocell n-1)
plemented through carry-in arithmetic, which drives through circuit quickly. Figure shows that carry chain logic within macrocell consists product terms (CPT0 CPT1) from input carry-in carry logic. inputs carry chain connected directly product terms PTA. output carry chain generates carry-out next macrocell logic block well local carry input that connected input input mux. Carry-in configuration inputs gate. This gate provides method segmenting carry chain macrocell logic block. Macrocell Clocks Clocking register highly flexible. Four global synchronous clocks (GCLK[3:0]) Product Term clock (PTCLK) available each macrocell register. Furthermore, clock polarity within each macrocell allows register clocked rising falling edge (see macrocell diagram Figure PRESET/RESET Configurations macrocell register asynchronously preset reset using PRESET RESET mux. Both signals active high controlled either Preset/Reset product terms (PRC[1:0] Figure GND. situations where PRESET RESET active same time, RESET takes priority over PRESET.
PRESET
Carry Chain CPT0 CPT1
Input
Output
PSET
FROM Clock GCLK[3:0] PTCLK Clock Polarity
PRC[1:0]
Carry macrocell n+1)
RESET
Figure Macrocell.
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Embedded Memory Each member family contains types embedded memory blocks. channel memory block placed intersection horizontal vertical routing channels. Each channel memory block 4096 bits size configured asynchronous synchronous Dual-Port RAM, Single-Port RAM, Read-Only memory (ROM), synchronous FIFO memory. memory organization configurable 4Kx1, 2Kx2, 1Kx4 512x8. second type memory block located within each referred cluster memory block. Each contains cluster memory blocks that 8192 bits size. Similar channel memory blocks, cluster memory blocks configured 8Kx1, 4Kx2, 2Kx4 1Kx8 configured either asynchronous synchronous Single-Port ROM. Cluster Memory Each logic block cluster device contains 8192bit cluster memory blocks. Figure block diagram cluster memory block interface cluster memory block cluster PIM. output cluster memory block optionally registered perform synchronous pipelining register asynchronous read write operations. output registers contain asynchronous RESET which used type sequential logic circuits (e.g., state machines). There four global clocks (GCLK[3:0]) local clock available input output registers. local clock input registers independent used output registers. local clock generated user-design macrocell comes from pin. Cluster Memory Initialization cluster memory powers undefined state, user-defined known state during configuration. facilitate look-up-table (LUT) logic applications, cluster memory blocks initialized with given data when device configured power applications, user cannot write memory blocks. Channel Memory architecture includes embedded memory block each crossing point horizontal vertical routing channels. channel memory 4096-bit embedded memory block that configured asynchronous synchronous Single-Port RAM, Dual-Port RAM, ROM, synchronous FIFO memory. Data, address, control inputs channel memory driven from horizontal vertical routing channels. data FIFO logic outputs drive dedicated tracks horizontal vertical routing channels. clocks channel memory block selected from four global clocks inputs from horizontal vertical channels. clock muxes also include polarity each clock that user choose inverted clock. Dual-Port (Channel Memory) Configuration Each port distinct address inputs, well separate data control inputs that accessed simultaneously. inputs Dual-Port memory driven from horizontal vertical routing channels. data outputs drive dedicated tracks routing channels. interface routing such that Port Dual-Port interfaces primarily with horizontal routing channel Port interfaces primarily with vertical routing channel.
DIN[7:0]
Write Control Logic
ADDR[12:0]
Decode (1024 Rows)
Write Pulse
Cluster
GCLK[3:0] Local
1024x8 Asynchronous SRAM
DOUT[7:0]
Read Control Logic
RESET GCLK[3:0] Local
Figure Block Diagram Cluster Memory Block.
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
clocks each port Dual-Port configuration selected from four global clocks local clocks. local clock sourced from horizontal channel other from vertical channel. data outputs dual-port memory also registered. Clocks output registers also selected from four global clocks local clocks. clock polarity port allows true complement polarity input output clocking purposes. Arbitration Dual-Port configuration Channel Memory Block provides arbitration when both ports access same address same time. Depending memory operation being attempted, port always gets priority. Table details which port gets priority read write operations. active-LOW `Address Match' signal generated when address collision occurs. Table Arbitration Result: Address Match Signal Becomes Active Result Port Port Arbitration Read Write Read Read arbitration required Port gets priority Comment Both ports read same time Port requests first then will read current data. output will then change newly written data Port Port requests first then will read current data. output will then change newly written data Port Port blocked until Port finished writing horizontal vertical routing channels. This allows FIFO blocks expanded using multiple FIFO blocks same horizontal vertical routing channel without speed penalty. FIFO mode, write read ports controlled separate clock enable signals. clocks each port selected from four global clocks local clocks. local clock sourced from horizontal channel other from vertical channel. data outputs from read port FIFO also registered. clock polarity port allows using true complement polarity read write operations. write operation controlled clock write enable pin. read operation controlled clock read enable pin. enable pins sourced from horizontal vertical channels. Channel Memory Initialization channel memory powers undefined state, user-defined known state during configuration. facilitate logic applications, channel memory blocks initialized with given data when device configured power applications, user cannot write memory blocks. Channel Memory Routing Interface Similar outputs, channel memory blocks feature dedicated tracks horizontal vertical routing channels data outputs flag outputs, shown Figure This allows channel memory blocks expanded easily. These dedicated lines routed pins chip outputs other logic block clusters used logic equations.
channel memory inputs driven from routing channels
Read
Write
Port gets priority
Write
Write
Port gets priority
FIFO (Channel Memory) Configuration channel memory blocks also configurable synchronous FIFO RAM. FIFO mode operation, channel memory block supports normal FIFO operations without general-purpose logic resources device. FIFO block contains necessary FIFO flag logic, including read write address pointers. FIFO flags include empty/full flag (EF), half-full flag (HF), programmable almost-empty/full (PAEF) flag output. FIFO configuration ability perform simultaneous read write operations using separate clocks. These clocks tied together single operation independently asynchronous read/write (w.r.t. each other) applications. data control inputs FIFO block driven from horizontal vertical routing channels. data flag outputs driven onto dedicated routing tracks both
4096-bit Dual Port Array
Configurable Async/Sync Dual Port Sync FIFO Configurable 4Kx1, 2Kx2, 1Kx4 512x8 block sizes
Global Clock Signals
GCLK[3:0]
Vertical Channel
channel memory outputs drive dedicated tracks routing channels
Horizontal Channel
Figure Block Diagram Channel Memory Block.
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Banks interfaces horizontal vertical routing channels pins through banks. There several banks device shown Figure I/Os from bank located same section package layout convenience. There exist kinds banks; fixed-signal banks user programmable banks. first fixed signal bank Serial Signal Bank. This bank includes differential serial data transmission receive signals. second bank Transceiver Control Bank. This bank includes static signal pins required configuration operation transceiver blocks each devices. Each device several types user programmable banks. table following page indicates availability each type programmable bank device. Supported standards each bank addressed appropriate VREF VCCIO voltages. VREF VCCIO pins bank must connected same VREF VCCIO voltage respectively. This requirement restricts number standards supported bank given time. also dictates standard used GCTL[3:0] pins. architecture defining each programmable bank consists several cells, where each cell contains input/output register, output enable register, programmable slew rate control programmable hold control logic. Each cell drives output device; cell also supplies input device that connects dedicated track associated routing channel. There four dedicated inputs (GCTL[3:0]) that used Global Control Signals available every cell. These global control signals used output enables, register resets register clock enables shown Figure Programmable Banks Device Flexible SemiFlexible Specific VCCIO VREF
25G01K100 Bank[0:3, 25G02K100 Bank[0:3]
Bank[6:7] Bank[4] VCCIO=3.3V 1.5V 0.68-0.90V Bank[5:7] Bank[4] VCCIO=3.3V 1.5V 0.68-0.90V
Standards Standard LVTTL LVCMOS LVCMOS3 LVCMOS2 LVCMOS18 3.3V GTL+ SSTL3 SSTL3 SSTL2 SSTL2 HSTL HSTL HSTL HSTL 1.15 1.15 0.68 0.68 0.68 0.68 1.35 1.35 VREF 1.25 1.25 0.75 0.75 VCCIO Termination Voltage (VTT)
Bank Bank Bank Bank Bank
Serial Bank
XCVR CNTL
Bank Bank Bank
Figure Bank Block Diagram.
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Registered
From Output
Input
Routing Channel
Output Control Channel
Global Control Signals
Global Clock Signals
Register Input
Output
Register Enable Clock Polarity
Hold
Clock
Slew Rate Control
Register Reset
Figure Block Diagram Cell. Cell Figure block diagram cell. cell contains three-state input buffer, output buffer, register that configured input output register. output buffer slew rate control option that used configure output slower slew rate. input device output each configured registered combinatorial, however only path configured registered given design. output enable selected from four global control signals from Output Control Channel (OCC) signals. output enable configured always enabled always disabled controlled remaining inputs mux. selection done that includes inputs. global clocks selected clock cell register. clock output input clock polarity that allows input/output register clocked either edge clock. Slew Rate Control output buffer slew rate control option. This allows ouput buffer slew fast rate V/ns) slow rate V/ns). I/Os default fast slew rate. designs concerned with meeting emissions standards slow edge provides lower system noise. designs requiring very high performance fast edge rate provides maximum system performance. Programmable Hold each pin, user-programmable bus-hold included. Bus-hold, which improved version popular internal Document 38-02021 Rev. Device 25G01K100 25G02K100 pull-up resistor, weak latch connected that does degrade device's performance. latch, bus-hold maintains last state when placed high-impedance state, thus reducing system noise bus-interface applications. Bus-hold additionally allows unused device pins remain unconnected board, which particularly useful during prototyping designers route signals device without cutting trace connections GND. more information, application note "Understanding Bus-Hold Feature Cypress CPLDs." Clocks four primary global clock trees CPLD portion device (INTCLK[3:0]). Each these clock trees distributes clock signal every cluster, channel memory, cell CPLD. global clock trees designed such that clock skew minimized while maintaining acceptable clock delay. Each INTCLKs choose from input sources clock signal: derived output another shown table below: INININTCLK[0] TCLK[1] TCLK[2] GCLK[0] GCLK[0] GCLK[1] RXCLK TXCLK TXCLK INTCLK[3] RXCLK RXCLK_B
GCLK[0] GCLK[1] accessible through pins device package. TXCLK RXCLK provided internally device. TXCLK (transmit clock) intended data transfer from CPLD block transmit channel transceiver block. RXCLK (receive clock) intended data transfer from receive channel transceiver block CPLD block. TXCLK RXCLK also used Page
Programmable Serial Interface (High Speed Devices) PRELIMINARY
logic inside CPLD block, e.g., data processing. RXCLK_B RXCLK second transceiver block. Clock Tree Distribution global clock tree performs primary functions. First, clock tree generates four internal global clocks multiplexing four reference clocks derived from Transceiver Blocks from package pins four driven clocks. Second, clock tree distributes four global clocks every cluster, channel memory, block, datapath cell die. global clock tree designed such that clock skew minimized while maintaining acceptable clock delay. Spread AwarePLL Each device family features on-chip designed using Spread Awaretechnology applications. general, PLLs used implement time-divisionmultiplex circuits achieve higher performance with fewer device resources. example, system that operates 32-bit data path that runs implemented with 16-bit circuitry that runs internally MHz. PLLs also used take advantage positioning internally generated clock edges shift performance towards improved setup, hold clock-to-out times. There several frequency multiply (X1, divide (/1, /16) options available create wide range clock frequencies from single clock input (GCLK[0]). increased flexibility, there seven phase shifting options which allow clock skew/deskew 45°, 90°, 135°, 180°, 225°, 270° 315°. Spread Aware feature refers ability track spread-spectrum input clock such that spread seen output clock with staying locked. total amount spread input clock should limited 0.6% fundamental frequency. Spread Aware feature supported only with multiply options. Voltage Controlled Oscillator (VCO), core designed operate within frequency range MHz. Hence, multiply option combined with input (GCLK[0]) frequency should selected such that this operating frequency requirement met. This demonstrated Table (columns Another feature this ability drive output clock (INTCLK) chip clock other devices board, shown Figure below. This off-chip clock half frequency output clock through register (I/O register macrocell register). This also used board deskewing purpose driving output clock off-chip, routing other devices board feeding back PLL's external feedback input (GCLK[1]). When this feature used, only limited multiply, divide phase shift options used. Table describes valid multiply divide options that used without external feedback. Table describes valid multiply divide options that used with external feedback.
off-chip signal (external feedback) INTCLK0, INTCLK1, INTCLK2, INTCLK3
Register
Send global clock chip GCLK1
Normal signal path Lock Detect/IO Clock Tree Delay
Phase selection
Divide 1-6,8,16 INTCLK0 GCLK0
Lock
Phase selection
Divide 1-6,8,16 INTCLK1 GCLK1
GCLK0
Source Clock
Phase selection
1350 1800 2250 2700
Divide 1-6,8,16 INTCLK2 TXCLK
3150
Phase selection
Divide 1-6,8,16 INTCLK3 RXCLK
GCLK[1:0]
Figure Block Diagram Spread Aware CYP25G01K100.
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
INTCLK0, INTCLK1, INTCLK2, INTCLK3
Register
Send global clock chip INTCLK1
Normal signal path Lock Detect/IO Clock Tree Delay
Phase selection
Divide 1-6,8,16 INTCLK0 GCLK0
Lock
Phase selection
Divide 1-6,8,16 INTCLK1 RXCLK
Source Clock
Phase selection
1350 1800 2250 2700 3150
Divide 1-6,8,16 INTCLK2 TXCLK
Phase selection
Divide 1-6,8,16 INTCLK3 RXCLK_B
GCLK[0]
Figure Block Diagram Spread Aware CYP25G02K100.
Table Multiply Divide Options-without INTCLK1 Feedback Input Frequency (GCLK[0]) fPLLI (MHz) 12.5-25 25-33 33-50 50-66 66-100 100-133 Valid Multiply Options Value Output Frequency (MHz) 100-200 200-266 100-133 133-200 200-266 100-133 133-200 200-266 100-133 Value 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, Valid Divide Options Output Frequency (INTCLK[3:0]) fPLLO (MHz) 6.25-200 12.5-266 6.25-133 8.33-200 12.5-266 6.25-133 8.3-200 12.5-266 6.25-133 Off-Chip Clock Frequency 3.12-100 6.25-133 3.12-66 4.16-100 6.25-133 3.12-66 4.16-100 6.25-133 3.12-66
Table Multiply Divide Options-with External Feedback Valid Multiply Options Input (GCLK) Frequency fPLLI (MHz) 50-66 66-100 100-133 Value Output Frequency (MHz) 100-133 133-200 200-266 Value Valid Divide Options Output (INTCLK) Frequency fPLLO (MHz) 100-133 133-200 200-266 Off-Chip Clock Frequency 50-66 66-100 100-133
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Table describes valid phase shift options that used with without external feedback. Table Phase Shift Options- with without INTCLK1 Feedback Without External Feedback 0°,45°, 90°, 135°, 180°, 225°, 270°, 315° With External Feedback Table example effect available divide phase shift options output MHz. also shows effect division duty cycle resultant clock. Note that duty cycle 50-50 when output divided even number. Also note that phase shift applies output divided output more details architecture operation this please refer application note entitled "PSI Clock Tree."
Table Timing Clock Phases Divide Options Output Frequency Divide Factor Period (ns) Duty Cycle% 40-60 33-67 40-60 (ns) (ns) (ns) 135° (ns) 180° (ns) 225° (ns) 270° (ns) 315° (ns)
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Timing Model important feature family simplicity timing. combinatorial registered/synchronous delays worst case system performance static shown specs section) long data routed through same horizontal vertical channels. Figure illustrates true timing model 200-MHz devices. synchronous clocking macrocells, delay incurred from macrocell clock macrocell clock separate Logic Blocks within same cluster, well separate Logic Blocks within different clusters. This shown tSCS tSCS2 Figure combinatorial paths, input output (from corner corner device), incurs worst-case delay 100K gate regardless amount logic which horizontal vertical channels used. This shown Figure synchronous systems, input set-up time output macrocell register clock output time shown parameters tMCS tMCCO shown Figure These measurements output synchronous clock, regardless logic placement. features: dedicated delays penalty using 0-16 product terms added delay steering product terms added delay sharing product terms output bypass delays simple timing model family eliminates unexpected performance penalties.
tSCS
GCLK[3:0]
Channel
Channel
Channel
Channel
Cluster
Cluster
SRAM
tMCS
Cluster
Cluster
Cluster
Cluster
SRAM
GCLK[3:0]
tSCS2
Channel
Channel
Channel
Channel
Cluster
Cluster
Cluster
Cluster
Cluster
Cluster
Cluster
Cluster
GCLK[3:0]
Channel
Channel
Channel
Channel
Cluster
Cluster
Cluster
Cluster
Cluster
Cluster
Cluster
Cluster
tMCCO
Figure Timing Model 100K gate Devices.
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Serial Transceiver Operation
transceiver block highly configurable transceiver designed support reliable transfer large quantities data, using high-speed serial links, from multiple sources multiple destinations. This block supports either single 16-bit wide channel case High-Speed devices four single-byte single-character channels, that combined support transfer wider buses, case Frequency Agile devices. standard LVPECL drivers, capable driving ACcoupled optical modules transmission lines. Receive Data Path Serial Line Receivers differential line receiver, IN±, available accepting input serial data stream. serial line receiver inputs accommodate high wire interconnect filtering losses transmission line attenuation (VDIF peakto-peak differential), AC-coupled +3.3V powered fiber-optic interface modules. common-mode tolerance these line receivers accommodates wide range signal termination voltages. Lock Data Control Line Receiver routed clock data recovery monitored signal detect (SD) LOCKREF data stream outside normal frequency range (±200 ppm) This status presented (Line Fault Indicator) output signal, which changes asynchronously cases when LOCKREF goes from HIGH LOW. Otherwise, changes synchronously REFCLK. Clock/Data Recovery extraction bit-rate clock recovery data bits from received serial stream performed Clock/Data Recovery (CDR) block. clock extraction function performed high-performance embedded phase-locked loop (PLL) that tracks frequency incoming stream aligns phase internal bit-rate clock transitions selected serial data stream. accepts character-rate (bit-rate reference clock REFCLK input. This REFCLK input used ensure that (within CDR) operating correct frequency (rather than some harmonic bit-rate), improve acquisition time, limit unlocked frequency excursions when data present serial inputs. Regardless type signal present, will attempt recover data stream from frequency recovered data stream outside limits range controls, will track REFCLK instead data stream. When frequency selected data stream returns valid frequency, allowed track received data stream. frequency REFCLK required within ±200 frequency clock that drives REFCLK signal remote transmitter ensure lock incoming data stream. systems using multiple redundant connections, output used select alternate data stream. When indication detected, logic toggle selection input device. When such port switch takes place, necessary re-acquire lock serial stream. External Filter circuit uses external capacitors filter. 0.1-µF capacitor needs connected between RXCN1 Page
High-Speed Transceiver Operation
Transmit Data Path Operating Modes transmit path High-Speed supports 16-bit-wide data paths. Phase-Align Buffer Data from input register passed phase-align buffer (FIFO). This buffer used absorb clock phase differences between transmit input clock internal character clock. Initialization phase-align buffer takes place when FIFO_RST signal asserted LOW. When FIFO_RST returned HIGH, present input clock phase relative TXCLK set. Once set, input clock allowed skew time half character period either direction relative REFCLK; i.e. ±180. This time shift allows delay path character clock (relative REFCLK) change operating voltage temperature while effecting desired operation. FIFO_RST asynchronous signal. FIFO_ERR transmit FIFO Error indicator. When HIGH, transmit FIFO either under overflowed. FIFO externally reset logically reset logic clear error indication action taken, internal clearing mechanism will clear FIFO clock cycles. When FIFO being reset, output data 1010. Transmit Clock Multiplier Transmit Clock Multiplier accepts 156.25-MHz external clock REFCLK input, multiplies that clock generate bit-rate clock transmit shifter. operating serial signaling rate allowable range REFCLK frequencies listed High-Speed Transceiver Timing Parameter Values table under "REFCLK Timing Parameters" (see page 33). REFCLK± input standard LVPECL input. Serializer parallel data from phase-align buffer passed Serializer which converts parallel data serial data using bit-rate clock generated Transmit clock multiplier. TXD[15] most significant output word, transmitted first serial interface. Serial Output Driver serial interface Output Driver makes high-performance differential (Current Mode Logic) provide source-matched driver transmission lines. This driver receives data from Transmit Shifters receive loopback data. outputs have signal swings equivalent that
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
RXCP1. Similarly 0.1-µF capacitor needs connected between RXCN2 RXCP2. recommended packages dielectric material these capacitors 0805 0603 X7R. Deserializer circuit extracts bits from serial data stream clocks these bits into Deserializer bit-clock rate. Deserializer converts serial data into parallel data. RXD[15] most significant output word received first serial interface. Loopback/Timing Modes High-Speed supports various loopback modes described below. Facility Loopback (Line Loopback With Retiming) When LINELOOP signal HIGH, Facility Loopback mode activated high-speed serial receive data (IN±) presented high-speed transmit output (OUT±) after retiming. Facility Loopback mode, high-speed receive data (IN±) also converted parallel data presented low-speed receive data output pins (RXD[15:0]). receive recovered clock also divided down presented speed clock output (RXCLK). Equipment Loopback (Diagnostic Loopback With Retiming) When DIAGLOOP signal HIGH, transmit data looped back PLL, replacing IN±. Data looped back from parallel inputs parallel outputs. data looped back internal serial interface goes through transmit shifter receive CDR. ignored this mode. Line Loopback Mode (Non-retimed Data) When LOOPA signal HIGH, serial data directly buffered transmit serial data. data serial output retimed. Loop Timing Mode When LOOPTIME signal HIGH, bypassed receive bit-rate clock used transmit side shifter. Reset Modes logic circuits device reset using RESET FIFO_RST signals. When RESET LOW, logic circuits except FIFO internally reset. When FIFO_RST LOW, FIFO logic reset. Power-down Mode High-Speed transceiver blocks provide global powerdown signal PWRDN. When LOW, this signal powers down entire device minimal power dissipation state. RESET FIFO_RST signals should asserted along with PWRDN signal ensure power dissipation.
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
(156.25 MHz) TXCLK TXD[15:0] FIFO_RST
FIFO_ERR
TXCLK
(156.25 MHz) REFCLK±
(156.25 MHz) RXCLK
RXD[15:0]
Output Register Shifter Recovered Bit-Clock Lock-to-Ref Retimed Data
Input Register
FIFO
Bit-Clock
Shifter
LOOPTIME DIAGLOOP
LINELOOP LOOPA
Lock-to-Data/ Clock Control Logic
OUT±
PWRDN LOCKREF
RESET
Figure High Speed-PSI Transceiver Logic Block Diagram.
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
IEEE 1149.1 Compliant JTAG Operation family IEEE 1149.1 JTAG interface both Boundary Scan operations. Four dedicated pins reserved each device Test Access Port (TAP). Boundary Scan family supports Bypass, Sample/Preload, Extest, Intest, Idcode Usercode boundary scan instructions. JTAG interface shown Figure Frequency Agile devices also allow system level diagnosis transceiver interface interconnect. Boundary scan supported LVCMOS signals, inputs outputs. highspeed serial inputs part JTAG test chain.
Instruction Register
There multiple configuration options available issuing IEEE 1149.1 JTAG instructions PSI. first method with programming cable software. With this method, pins devices system routed connector edge printed circuit board. programming cable then connected between this connector. simple configuration file instructs software programming operations performed devices system. software then automatically completes necessary data manipulations required accomplish configuration, reading, verifying, other functions. more information Cypress interface, Programming/ISR application notes systems with embedded controllers/processors, controller/processor used configure PSI. software assists this method converting device file into serial stream that contains instruction information addresses data locations configured. controller/processor then simply directs this stream chain devices complete desired reconfiguration diagnostic operations. Contact your local sales office information availability this option. Programming
TCLK
JTAG CONTROLLER
Bypass Reg. Boundary Scan idcode Usercode Prog.
Data Registers
Figure JTAG Interface. In-System Reprogramming(ISRTM) In-System Reprogramming combination capability program reprogram device on-board, ability support design changes without changing system timing device pinout. This combination means design changes during debug field upgrades cause board respins. family implements providing JTAG compliant interface on-board programming, robust routing resources pinout flexibility, simple timing model consistent system performance. Configuration CPLD block each device family designed with Self-Boot capability. embedded on-chip EEPROM used store configuration data. devices, programming defined loading user's design into internal EEPROM. Configuration, other hand, defined loading user's design into volatile CPLD block. Configuration begin ways. initiated toggling Reconfig from HIGH, issuing appropriate IEEE 1149.1 JTAG instruction device JTAG interface. There IEEE 1149.1 JTAG instructions that initiate configuration PSI. Self Config instruction causes (re)configure with data store internal EEPROM. Load Config instruction causes (re)configure with data provided other sources such Automatic Test Equipment (ATE), embedded micro-controller/processor JTAG port. Document 38-02021 Rev.
on-chip EEPROM device CPLD block programmed issuing appropriate IEEE 1149.1 JTAG instruction. This done automatically using ISR/STAPL software. configuration bits sent from through JTAG port into programming cable. data then passed internal EEPROM through NonVolatile (NV) port CPLD block. more information program through ISR/STAPL, please refer ISR/STAPL User Guide. Third-Party Programmers Cypress support available wide variety third-party programmers. major programmers (including Micro, System General, Hi-Lo) support family.
Development Software Support
Warp® Warp state-of-the-art design environment designing with Cypress programmable logic. Warp utilizes subset IEEE 1076/1164 VHDL IEEE 1364 Hardware Description Language (HDL) design entry. Warp accepts VHDL Verilog input, synthesizes optimizes entered design, outputs configuration bitstream desired Delta39K device. simulation, Warp provides graphical waveform simulator well VHDL Verilog Timing Models. VHDL Verilog open, powerful, non-proprietary Hardware Description Languages (HDLs) that standards behavioral design entry simulation. allows designers learn single language that useful facets design process. Third-Party Software Cypress products supported number third-party design entry simulation tools. Refer third-party software data sheet contact your local sales office list currently supported third party vendors. Page
Programmable Serial Interface (High Speed Devices) PRELIMINARY
Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Storage Temperature .-65°C +150°C Soldering Temperature.220°C Ambient Temperature with Power Applied. -40°C +85°C Junction Temperature.135°C relative Ground Potential. -0.5V 4.2V VCCIO relative Ground Potential. -0.5V 4.6V Voltage Applied Outputs High State -0.5V 4.5V Range Commercial Output Current into LVCMOS Outputs (LOW). Input voltage. .-0.5V 4.5V Current into Outputs. mA[4] Static Discharge Voltage.> 2001V (per MIL-STD-883, Method 3015) Latch-Up Current.>
Operating Range
Ambient Temperature +70°C VDDQ 3.3V 1.4V 1.6V
Operating Range
Range Ambient Temperature +70°C Commercial Junction Temperature +85°C Output Condition 3.3V 2.5V 1.8V 1.5V
Notes: current into outputs with HSTL with HSTL
VCCIO 3.3V 0.3V 2.5V 0.2V 1.8V 0.15V 1.5V 0.1V
3.3V 0.3V
VCCJTAG/ VCCCNFG Same VCCIO
VCCPLL Same
VCEP 3.3V 0.3V
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Test Loads Waveforms High-Speed Transceiver Block
3.0V Vth=1.4V 2.0V 0.8V 3.0V 2.0V 0.8V Vth=1.4V VICLL VICHH
LVTTL Input Test Waveform
Input Test Waveform
VIEHH VIELL
LVPECL Input Test Waveform
3.3V OUTPUT R1=330 R2=510 (Includes fixture probe capacitance) OUT+ OUT- =100
Test Load
Test Load
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Electrical Characteristics Over Operating Range
Characteristics VCCIO 3.3V VCCIO 2.5V Parameter Description VDRINT VDRIO IOS[5] IBHL IBHH IBHLO IBHHO Capacitance Parameter CI/O CPCI CCLK CINPECL CSD1 CINC1 Description Input/Output Capacitance compliant Capacitance Clock Signal Capacitance PECL Input Capacitance Input Capacitance Input Capacitance Test Conditions VCCIO 25°C VCCIO 25°C VCCIO 25°C 3.3V 25°C 3.3V 25°C 3.3V 25°C Min. Max. Unit Data Retention Voltage (config data lost below this) Data Retention VCCIO Voltage (config data lost below this) Input Leakage Current Output Leakage Current Output Short Circuit Current Input Hold Sustaining Current Input Hold HIGH Sustaining Current Input Hold Overdrive Current Input Hold HIGH Overdrive Current 3.6V VCCIO VCCIO Max., VOUT 0.5V Min., VPIN Min., VPIN Max. Max. +250 -250 Test Conditions Min. -160 +200 -200 Max. Min. -160 +150 -150 Max. VCCIO 1.8V Min. -160 Max. Unit
Specifications Power Parameter ICC2[6] Device 25G01K100 25G02K100 Description Active Power Supply Current Active Power Supply Current Test Conditions Frequency Commercial Frequency Commercial Standby Typical 1200 Unit
Notes: more than output should tested time. Duration short circuit should exceed second. VOUT=0.5V been chosen avoid test problems caused tester ground degradation. Tested initially after design process changes that affect these parameters. Typical measured with 3.3V, 25°C, RFEN LOW, outputs unloaded.
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Characteristics (I/O) Max. Input/ Output Standard LVTTL LVCMOS LVCMOS3 LVCMOS2 LVCMOS1 3.3V GTL+ SSTL3 SSTL3 SSTL2 SSTL2 HSTL HSTL HSTL HSTL Note -7.6 -15.2 VCCIO-1.1V VCCIO-0.9V VCCIO- 0.62V VCCIO-0.43V VCCIO-0.4V VCCIO-0.4V VCCIO-0.4V VCCIO-0.4V VREF Min. VCCIO -0.1 -0.1 -0.1 -1.0 -2.0 -0.1 -0.5 (Min.) VCCIO-0.2V VCCIO-0.2V VCCIO-0.2V VCCIO-0.45V 0.9VCCIO Note 15.2 (Max.) 0.45 0.5VCCIO VREF+0.2 VREF+0.2 VCCIO+0.3 -0.3V VREF+0.2 VCCIO+0.3 -0.3V VREF+1.8 VCCIO+0.3 -0.3V VREF+1.8 VCCIO+0.3 -0.3V VREF+1.0 VCCIO+0.3 -0.3V VREF+1.0 VCCIO+0.3 -0.3V VREF+1.0 VCCIO+0.3 -0.3V VREF+1.0 VCCIO+0.3 -0.3V Min. -0.3 VCCIO+0.5 -0.5V 0.3VCCIO VREF-0.2 VREF-0.2 VREF-0.2 VREF-0.1 VREF-0.1 VREF-0.1 VREF-0.1 VREF-0.1 VREF-0.1 Unit 0.54 0.35 0.65VCCIO VCCIO+0.3 -0.3V 0.35VCCIO Min. 2.0V 2.0V 2.0V 1.7V Max. Min. Max. 0.8V 0.8V 0.8V 0.7V
VCCIO+0.3 -0.3V VCCIO+0.3 -0.3V VCCIO+0.3 -0.3V VCCIO+0.3 -0.3V
0.1VCCIO
1.15 1.35 1.15 1.35 0.68 0.68 0.68 0.68
Parameter LVTTL Inputs VIHT VILT IIHT IILT VINSGLE VDIFFE VIEHH VIELL IIEH IIEL VOHC VOLC VSGLCO
Description Input HIGH Voltage Input Voltage Input HIGH Current Input Current Input Single-ended Swing Input Differential Voltage Highest Input HIGH Voltage Lowest Input Voltage Input HIGH Current Input Current Output HIGH Voltage (VCC Referenced) Output Voltage (VCC Referenced) Output Single-ended Voltage
Test Conditions 2.0V, High 0.5V -3.0V, High 0.8V Max., Max.,
Max.
REFCLK LVPECL Compatible Inputs VIEHH Max. VIELL Min. differential load differential load differential load -200 0.15 1200
1.45
General Transmitter Differential Compatible Outputs (All High-Speed PSI)
Notes: "Power-up Sequence Requirements" VCCIO requirement. resistor terminated termination voltage 1.5V.
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Parameter VDIFF IACCM VACCM ZMSE IDSHORT VDIFFOC VINSGLC VICHH VICLL IICH IICL VRSENSE ZVTT LCMR VRSD VRMAX VDIFFC Description Differential Output Common Mode Current Common Mode Voltage Differential Output Impedance Single Ended Output Impedance Single Ended Output Impedance Matching Within Single Lane Short Circuit Current Output Differential Swing Input Single-ended Swing Highest Input HIGH Voltage Lowest Input Voltage Input HIGH Current Input Current Input Sensitivity Impedance Differential Return Loss Common Mode Return Loss Voltage Threshold Maximum Input Voltage (p-p) Input Differential Voltage 1200 VICHH Max. VICLL Min. differential load -100 Test Conditions differential load Min. 1000 Max. 1600 1500 Unit Transmitter Differential Compatible Outputs (P25G01K100, P25G02K100 only)
Transmitter Differential Compatible Outputs (S25G01K100, S25G02K100 only) General Receiver Differential Compatible Inputs (All High-Speed PSI)
Receiver Differential Compatible Inputs (P25G01K100, P25G02K100 only)
Receiver Differential Compatible Inputs (S25G01K100, S25G02K100 only)
Configuration Parameters Parameter tRECONFIG Description Reconfig time before goes HIGH Min. Unit
Power-up Sequence Requirements
Upon power-up, outputs remain three-stated until pins have powered-up nominal voltage part completed configuration. part will start configuration until VCC, VCCIO, VCCJTAG, VCCCNFG, VCCPLL VCEPVCEP have reached nominal voltage. pins powered order. This includes VCC, VCCIO, VCCJTAG, VCCCNFG, VCCPLL VCEP. VCCIOs bank should tied same potential powered together. VCCIOs (even unused banks) need powered least 1.5V before configuration completed. Maximum ramp time VCCs should nominal voltage
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Switching Characteristics
Timing Parameter Values Parameter Combinatorial Mode Parameters tPRR tPRO Delay from input, through cluster channel associated with that input, output horizontal vertical channel associated with that cluster Global control output enable Global control output disable Asynchronous macrocell RESET PRESET recovery time from input horizontal vertical channel associated with cluster macrocell Asynchronous macrocell RESET PRESET from input horizontal vertical channel associated with cluster that macrocell output those same channels Asynchronous macrocell RESET PRESET minimum pulse width, from input macrocell farthest cluster horizontal vertical channel associated with Set-up time input macrocell cluster channel associated with that input pin, relative global clock Hold time input macrocell cluster channel associated with that input pin, relative global clock Global clock output macrocell output horizontal vertical channel associated with cluster that macrocell Set-up time input cell register associated with that pin, relative global clock Hold time input cell register associated with that pin, relative global clock Clock output cell register output associated with that register Macrocell clock macrocell clock through array logic within same cluster Macrocell clock macrocell clock through array logic different clusters same channel register clock macrocell clock cluster channel register associated with Macrocell clock register clock horizontal vertical channel associated with cluster that macrocell Clock output disable (high-impedance) Clock output enable (low-impedance) Maximum frequency with internal feedback-within same cluster Maximum frequency with internal feedback-within different clusters opposite ends horizontal vertical channel Set-up time macrocell used input register, from input product term clock Hold time macrocell used input register Product term clock output delay from input Register register delay through array logic different clusters same channel using product term clock Description Min. Max. Unit
tPRW
Synchronous Clocking Parameters tMCS tMCH tMCCO tIOS tIOH tIOCO tSCS tSCS2 tICS tOCS tCHZ tCLZ fMAX fMAX2
Product Term Clocking Parameters tMCSPT tMCHPT tMCCOPT tSCS2PT
Note: tCHSW signals making horizontal vertical channel switch vice-versa.
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Switching Characteristics
Timing Parameter Values (continued) Parameter Channel Interconnect Parameters tCHSW tCL2CL Adder signal switch from horizontal vertical channel vice-versa Cluster Cluster delay adder (through channels channel PIM) Delay from input cluster PIM, through macrocell cluster, back cluster input. This parameter added tSCS parameters each extra pass through AND/OR array required given signal path Adder carry chain logic macrocell Maximum cycle cycle jitter time delay with skew adjustment delay without skew adjustment Lock time Output frequency Input frequency Description Min. Max. Unit
Miscellaneous Parameters tCPLD tMCCD tMCCJ tDWSA tDWOSA tLOCK fPLLO[10] fPLLI[10]
0.25 0.50 0.35 0.35
Parameters
Cluster Memory Timing Parameter Values Parameter Asynchronous Mode Parameters tCLMAA tCLMPWE tCLMSA tCLMHA tCLMSD tCLMHD Cluster memory access time. Delay from address change read data Write enable pulse width Address set-up beginning write enable Address hold after write enable with both signals from same block Data set-up write enable Data hold after write enable Clock cycle time flow-through read write operations (from macrocell register through cluster memory back macrocell register same cluster) Clock cycle time pipelined read write operations (from cluster memory input register through memory cluster memory output register) Address, data, set-up time inputs, relative global clock Address, data, hold time inputs, relative global clock Global clock data valid output pins flow through data Global clock data valid output pins pipelined data Description Min. Max. Unit
Synchronous Mode Parameters tCLMCYC1 tCLMCYC2 tCLMS tCLMH tCLMDV1 tCLMDV2
Note: Refer page application note titled "PSI Clock Tree" details operation specification.
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Cluster Memory Timing Parameter Values (continued) tCLMMACS1 tCLMMACS2 tMACCLMS1 tMACCLMS2 Cluster memory input clock macrocell clock same cluster Cluster memory output clock macrocell clock same cluster Macrocell clock cluster memory input clock same cluster Macrocell clock cluster memory output clock same cluster Asynchronous cluster memory access time from input cluster output cluster
Internal Parameters tCLMCLAA
Channel Memory Timing Parameter Values Parameter Dual-Port Asynchronous Mode Parameters tCHMAA tCHMPWE tCHMSA tCHMHA tCHMSD tCHMHD tCHMBA Channel memory access time. Delay from address change read data Write enable pulse width Address set-up beginning write enable Address hold after write enable with both signals from same block Data set-up write enable Data hold after write enable Channel memory asynchronous dual port address match (busy access time) Clock cycle time flow through read write operations (from macrocell register through channel memory back macrocell register same cluster) Clock cycle time pipelined read write operations (from channel memory input register through memory channel memory output register) Address, data, set-up time inputs, relative global clock Address, data, hold time inputs, relative global clock Global clock data valid output pins flow through data Global clock data valid output pins pipelined data Channel memory synchronous dual-port address match (busy, clock data valid) Channel memory input clock macrocell clock same cluster Channel memory output clock macrocell clock same cluster Macrocell clock channel memory input clock same cluster Macrocell clock channel memory output clock same cluster Read write minimum clock cycle time Data, read enable, write enable set-up time relative inputs Data, read enable, write enable hold time relative inputs Data access time output pins from rising edge read clock (read clock data valid) Channel memory FIFO read clock macrocell clock read data Macrocell clock channel memory FIFO write clock write data Description Min. Max. Unit
Dual-Port Synchronous Mode Parameters tCHMCYC1 tCHMCYC2 tCHMS tCHMH tCHMDV1 tCHMDV2 tCHMBDV tCHMMACS1 tCHMMACS2 tMACCHMS1 tMACCHMS2 tCHMCLK tCHMFS tCHMFH tCHMFRDV tCHMMACS tMACCHMS
Synchronous FIFO Data Parameters
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Channel Memory Timing Parameter Values (continued) Synchronous FIFO Flag Parameters tCHMFO tCHMMACF tCHMFRS tCHMFRSR tCHMFRSF tCHMSKEW1 tCHMSKEW2 tCHMSKEW3 tCHMCHAA Read write clock respective flag output output pins Read write clock macrocell clock with FIFO flag Master Reset Pulse Width Master Reset Recovery Time Master Reset Flag Data Output Time Read/Write Clock Skew Time Full Flag Read/Write Clock Skew Time Empty Flag Read/Write Clock Skew Time Boundary Flags Asynchronous channel memory access time from input channel memory output channel memory 10.0
Internal Parameters
High-Speed Transceiver Timing Parameter Values Parameter Transceiver Interfacing Timing Parameters tTXCLK tTXCLKD tTXCLKR tTXCLKF tTXDS tTXDH tRXCLK tRXCLKD tRXCLKR tRXCLKF tRXDS tRXDH tRXPD TXCLK Frequency (must frequency coherent REFCLK) TXCLK Period TXCLK Duty Cycle TXCLK Rise Time TXCLK Fall Time Write Data Set-up TXCLK Write Data Hold from RXCLK Frequency RXCLK Period RXCLK Duty Cycle RXCLK Rise Time RXCLK Fall Time
[11] [11]
Description
Min. 154.5 6.38 154.5 6.38 -1.0
Max. 156.5 6.47
Unit
TXCLK
156.5 6.47
Recovered Data Set-up with regard RXCLK Recovered Data Hold with regard RXCLK Valid Propagation delay
Note: "slow slew rate" output delay adjustments, refer Warp software's static timing analyzer results.
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
High-Speed Transceiver Timing Parameter Values Parameter REFCLK Timing Parameters tREF tREFP tREFD tREFT tREFR tREFF tDRF tUID tRISE tFALL REFCLK Input Frequency REFCLK Period REFCLK Duty Cycle REFCLK Frequency Tolerance (relative received serial data) REFCLK Rise Time REFCLK Fall Time Driver Rise/Fall Time (20-80% rise, 80-20% fall, balanced load) Deterministic Jitter Total Jitter Unit Interval Output Rise Time (20-80%, balanced load) Output Fall Time (80-20%, balanced load) Total Output Jitter (p-p) Total Output Jitter (rms) Serial Inputs (P25G01K100, P25G02K100 only) tEYE tJDR tJTR opening Deterministic Jitter Receiver Total Jitter Receiver 0.41 0.65 154.5 6.38 -100 0.17 0.35 0.05 0.007 156.5 6.47 +100 Description Min. Max. Unit
Serial Outputs (P25G01K100,P25G02K100 only)
Serial Outputs (S25G01K100, S25G02K100 only)
Transmit Interface Timing High-Speed tTXCLK
tTXCLKDH tTXCLKDL
TXCLK
TXDS tTXDH
TXD[15:0]
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Receive Interface timing High-Speed
tRXCLK tRXCLKDL tRXCLKDH
RXCLK
RXPD
RXDS
tRXDH
RXD[15:0]
Input Output Standard Timing Delay Adjustments timing specifications this data sheet specified based 3.3V compliant inputs outputs (fast slew rates[12]). Apply following adjustments inputs outputs configured operate other standards. Input/Output Standard LVTTL LVCMOS LVCMOS3 LVCMOS2 LVCMOS18 3.3V GTL+ SSTL3 SSTL3 SSTL2 SSTL2 HSTL HSTL HSTL HSTL Output Delay Adjustments tIOD 0.6[13] -0.3 -0.4 -0.1 -0.2 0.05 0.6[13] 0.9[13] Input Delay Adjustments tIOIN tCKIN tIOREGPIN
Notes: These delays based falling edge output. rising edge delay depends size pull resistor termination voltage. RXCLK rise time fall time measured 20-80 percentile region rising falling edge clock signal
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Switching Waveforms General Switching Waveforms
Combinatorial Output
INPUT COMBINATORIAL OUTPUT
Registered Output with Synchronous Clocking (Macrocell)
INPUT tMCS SYNCHRONOUS CLOCK tMCH
REGISTERED OUTPUT tMCCO
Registered Input Cell
DATA INPUT tIOS tIOH
INPUT REGISTER CLOCK
tIOCO
REGISTERED OUTPUT
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Switching Waveforms (continued)
Clock Clock
INPUT REGISTER CLOCK tICS
tSCS
MACROCELL REGISTER CLOCK
Clock Clock
DATA INPUT tMCSPT CLOCK tSCS2PT
Asynchronous Reset/Preset
RESET/PRESET INPUT tPRO REGISTERED OUTPUT
tPRW
tPRR CLOCK
Output Enable/Disable
GLOBAL CONTROL INPUT OUTPUTS
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Switching Waveforms (continued)
Cluster Memory Asynchronous Timing
READ
WRITE
READ
ADDRESS CLUSTER INPUT)
WRITE ENABLE
tCLMPWE
INPUT
tCLMCLAA
tCLMCLAA
OUTPUT
Cluster Memory Asynchronous Timing
READ ADDRESS PIN)
tCLMSA tCLMHA
WRITE
READ
WRITE ENABLE
tCLMPWE
INPUT
tCLMSD tCLMAA tCLMHD tCLMAA
OUTPUT
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Switching Waveforms (continued)
Cluster Memory Synchronous Timing
READ WRITE READ
GLOBAL CLOCK
tCLMS tCLMH tCLMCYC1
ADDRESS
tCLMS tCLMH tCLMS tCLMH
WRITE ENABLE
REGISTERED INPUT
tCLMDV1 tCLMDV1 tCLMDV1
REGISTERED OUTPUT
Cluster Memory Internal Clocking
MACROCELL INPUT CLOCK
tCLMMACS1 tMACCLMS1
CLUSTER MEMORY INPUT CLOCK
tCLMMACS2 tMACCLMS2
CLUSTER MEMORY OUTPUT CLOCK
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Switching Waveforms (continued)
Cluster Memory Output Register Timing (Asynchronous Inputs)
ADDRESS
WRITE ENABLE
INPUT
tCLMCYC2
GLOBAL CLOCK (OUTPUT REGISTER) tCLMDV2
EGISTERED OUTPUT
Cluster Memory Output Register Timing (Synchronous Inputs)
ADDRESS
WRITE ENABLE
INPUT tCLMCYC2 GLOBAL CLOCK (INPUT REGISTER) tCLMS tCLMH
GLOBAL CLOCK (OUTPUT REGISTER) tCLMDV2
REGISTERED OUTPUT
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Switching Waveforms (continued)
Channel Memory Asynchronous Timing
ADDRESS
An-1
An+1
An+2
tCHMSA
tCHMPWE
tCHMHA
WRITE ENABLE
tCHMSD
tCHMHD
DATA INPUT
tCHMAA
tCHMAA
OUTPUT
Dn-1
Dn+1
Channel Memory Internal Clocking
MACROCELL INPUT CLOCK tMACCHMS1
tCHMMACS1 CHANNEL MEMORY INPUT CLOCK
tCHMMACS2
tMACCHMS2
CHANNEL MEMORY OUTPUT CLOCK
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Switching Waveforms (continued)
Channel Memory Internal Clocking
MACROCELL INPUT CLOCK tCHMMACS FIFO READ CLOCK
tMACCHMS FIFO WRITE CLOCK tCHMMACF FIFO READ WRITE CLOCK
Channel Memory SRAM Flow Through Timing
CLOCK tCHMCYC1 tCHMS tCHMH
ADDRESS
An-1
An+1
An+2
An+3
WRITE ENABLE
tCHMS
tCHMH
DATA INPUT
Dn-1
Dn+1
Dn+3
tCHMDV1
tCHMDV1
tCHMDV1
tCHMDV1
OUTPUT
Dn-1
Dn+1
Dn+2
Dn+3
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Switching Waveforms (continued)
Channel Memory SRAM Pipeline Timing
CLOCK tCHMCYC2 tCHMS
tCHMH
ADDRESS
An-1
tCHMH
An+1
An+2
An+3
tCHMS WRITE ENABLE
tCHMS
tCHMH
DATA INPUT
Dn-1
Dn+1
Dn+3
tCHMDV2
tCHMDV2
tCHMDV2
OUTPUT
Dn-1
Dn+1
Dn+2
Dual-Port Asynchronous Address Match Busy Signal
ADDRESS
ADDRESS
An-1
An+1
tCHMBA tCHMBA ADDRESS MATCH
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Switching Waveforms (continued)
Dual-Port Synchronous Address Match Busy Signal
CLOCK
ADDRESS
An-1
ADDRESS
Bn-1 tCHMS
tCHMS
Bn+1
ADDRESS MATCH
tCHMBDV tCHMBDV
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Switching Waveforms (continued)
Channel Memory Synchronous FIFO Empty/Write Timing
PORT CLOCK tCHMCLK tCHMFS tCHMFH
WRITE ENABLE
REGISTERED INPUT
Dn+1
EMPTY FLAG (active low)
tCHMSKEW2
tCHMFO
tCHMFO
PORT CLOCK
READ ENABLE
tCHMFRDV
REGISTERED OUTPUT
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Switching Waveforms (continued)
Channel Memory Synchronous FIFO Full/Read Timing
PORT CLOCK tCHMCLK tCHMFS tCHMFH
READ ENABLE
tCHMFRDV
REGISTERED OUTPUT
FULL FLAG (active low)
tCHMSKEW1
tCHMFO
tCHMFO
PORT CLOCK
WRITE ENABLE
tCHMS
tCHMH
REGISTERED INPUT
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Switching Waveforms (continued)
Channel Memory Synchronous FIFO Programmable Flag Timing
PORT CLOCK tCHMCLK tCHMFH
tCHMFS
WRITE ENABLE
PROGRAMMABLE ALMOST-EMPTY FLAG (active LOW) tCHMSKEW3 tCHMFO tCHMFO
PORT CLOCK
tCHMFS READ ENABLE
tCHMFH
PORT CLOCK tCHMCLK
WRITE ENABLE tCHMFO PROGRAMMABLE ALMOST-FULL FLAG (active LOW) tCHMSKEW3 tCHMFO
PORT CLOCK
READ ENABLE
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Switching Waveforms (continued)
Channel Memory Synchronous FIFO Master Reset Timing
tCHMFRS MASTER RESET INPUT
tCHMFRSR
READ ENABLE WRITE ENABLE tCHMFRSF EMPTY/FULL PROGRAMMABLE ALMOST EMPTY FLAGS tCHMFRSF
HALF-FULL/ PROGRAMMABLE ALMOST FULL FLAGS tCHMFRSF
REGISTERED OUTPUT
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Limiting
High-Speed
Zo=50
OUT+ OUT-
Zo=50
Figure Serial Input Termination.
High-Speed CY7B9532
Zo=50 Zo=50
OUT+ OUT-
Figure Serial Output Termination.
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Signal Description
Name CCLK Config_Done Data GCLK0-1 GCTL0-3 IO/VREF0 IO/VREF1 IO/VREF2 IO/VREF3 IO/VREF4 IO/VREF5 IO/VREF6 IO/VREF7 IO6/Lock MSEL Reconfig Reset TCLK TXD[15:0] TXCLK RXD[15:0] Function Output Output Input Input Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Output Input Input Output Input Internal Internal Internal Signal Description Configuration Clock serial interface with external boot PROM Flag indicating that configuration complete receive configuration data from external boot PROM Global Input Clock signals through Chip select external boot PROM Global Control signals through Dual function pin: Reference Voltage Bank Dual function pin: Reference Voltage Bank Dual function pin: Reference Voltage Bank Dual function pin: Reference Voltage Bank Dual function pin: Reference Voltage Bank Dual function pin: Reference Voltage Bank Dual function pin: Reference Voltage Bank Dual function pin: Reference Voltage Bank Input Output Dual function pin: Bank lock output signal Mode Select start configuration Reset signal interface with external boot PROM JTAG Test Clock JTAG Test Data JTAG Test Data JTAG Test Mode Select Parallel Transmit Data Inputs. 16-bit word, sampled TXCLK. TXD[15] most significant (the first transmitted) Parallel Transmit Data Input Clock. Divide selected transmit bit-rate clock Parallel Receive Data Output. These outputs change following RXCLK. RXD[15] most significant output word, received first serial interface Receive Clock Output. Divide bit-rate clock extracted from received serial stream Common Mode Termination. Capacitor shunt common mode noise Receive Loop Filter Capacitor (Negative) Receive Loop Filter Capacitor (Negative) Receive Loop Filter Capacitor (Positive) Receive Loop Filter Capacitor (Positive) Standard Device Signals
Transmit Path Signals
Receive Path Signals
RXCLK CM_SER RXCN1 RXCN2 RXCP1 RXCP2 REFCLK±
Internal Analog Analog Analog Analog Analog
Transceiver Control Status Signals Differential LVPECL Reference Clock. This clock input used timing reference transmit input receive PLLs. derivative this input clock also used clock transmit parallel interface Internal Line Fault Indicator Output Signal. When LOW, this signal indicates that selected receive data stream been detected invalid either input receive being operated outside specified limits
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Signal Description (continued)
Name RESET LOCKREF FIFO_ERR FIFO_RST PWRDN Function Internal Internal LVTTL input Internal Internal Internal Signal Description Reset logic functions except transmit FIFO Receive Lock Reference Input Signal. When LOW, receive locks REFCLK instead received serial data stream Signal Detect. When LOW, receive locks REFCLK instead received serial data stream Transmit FIFO Error Output Signal. When HIGH transmit FIFO either under overflowed. FIFO must reset clear error indication Transmit FIFO Reset Input Signal. When LOW, pointers transmit FIFO maximum separation Device Power Down Input Signal. When LOW, logic drivers disabled placed into standby condition where only minimal power dissipated Diagnostic Loopback Control Input Signal. When HIGH, transmit data routed through receive clock data recovery presented RXD[15:0] outputs. When LOW, received serial data routed through receive clock data recovery presented RXD[15:0] outputs Line Loopback Control Input Signal. When HIGH, received serial data looped back from receive transmit after being reclocked recovered clock. When LINELOOP LOW, data passed OUT± line driver controlled LOOPA. When both LINELOOP LOOPA LOW, data passed OUT± line driver generated transmit shifter Analog Line Loopback Input Signal. When LINELOOP LOOPA HIGH, received serial data looped back from receive input buffer transmit output buffer, routed through clock data recovery PLL. When LOOPA LOW, data passed OUT± line driver controlled LINELOOP Loop Time Mode Input Signal. When HIGH, extracted receive bit-clock replaces transmit bit-clock. When LOW, REFCLK input multiplied generate transmit clock Differential Serial Data Output. This differential output (+3.3V referenced) capable driving terminated transmission lines commercial fiberoptic transmitter modules Differential Serial Data Input. This differential input accept serial data stream deserialization clock extraction +3.3V Supply (operating voltage) Signal Power Ground +3.3V Quiet Power Quiet Ground +1.5V Supply HSTL Outputs Power Power Power Power Power Power Power Power Power Power bank bank bank bank bank bank bank bank JTAG pins Configuration port Page
Transceiver Loop Control Signals DIAGLOOP Internal
LINELOOP
Internal
LOOPA
Internal
LOOPTIME
Internal
Serial OUT± (OUTP/OUTN) Power VCCQ VSSQ VDDQ VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCJTAG VCCCNFG Power Ground Differential output Differential input
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Programmable Serial Interface (High Speed Devices) PRELIMINARY
Signal Description (continued)
Name VCCPLL VCEP Function Power Power logic Self-Bootsolution embedded boot PROM Signal Description
Configurations
456-Ball (25G01K100) View
HSTLREF
HSTLREF
HSTLREF
HSTLREF
HSTLREF
IO/VRE
IO/VRE
HSTL- HSTLREF
HSTLREF
VDDQ
HSTLREF
IO/VRE
VDDQ
VCCVC VDDQ
GCTL3
VDDQ
VDDQ VDDQ
HSTLREF
GCTL2 GCTL1
VDDQ VDDQ
HSTLREF
VDDQ
VCPLL VDDQ
VDDQ
VDDQ
GCLK1
GCTL0
HSTLREF
IOP6
IO/VRE
VCCO5 VCCO5 VCCO5 VCJTG
IO/VRE
IO/VRE
VCCO0 GCLK0
VCCO0
VSSQ
VSSQ
VCCO0
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
GNPLL
IO/VRE
RXCN1 RXCP1 RXCN2 RXCP2
IO/VRE
VCCQ VCCQ
VCCQ
VCCQ
VSSQ
VSSQ
VCCO1
VSSQ
VSSQ
VSSQ CMSER
IO/VRE IO/VRE
VSSQ
VSSQ
VSSQ
OUTP
OUTN
VCCQ VCCQ
VCCQ
VCCQ
IO/VRE
REF- VCCO4 CLKP REF- VCCO4 CLKN VCEP
VCCO4
VCEP
IO/VRE
VCCO1 IO/VRE
CDONE VCCO1
IO/VRE
CDATA RECON CRST CCLK
VCCFG VCCO2 VCCO2 VCCO2 VCCO2
VDDQ VCCO3 VCCO3
IO/VRE
VCCO4 IO/VRE IO/VRE
VDDQ
VDDQ
IO/VRE
VCCO3 VCCO3 IO/VRE IO/VRE
MSEL IO/VRE
IO/VRE
IO/VRE
IO/VRE
IO/VRE
IO/VRE
IO/VRE
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456-Ball (25G02K100) View
VREF7
VREF7
VREF6
IO/VRE
IO/VRE
VREF6 VREF6
VREF7 VREF7
VREF7
VDDQ
VREF6
IO/VRE
VDDQ
GCTL3
VDDQ
VDDQ
VDDQ
VREF6
GCTL2 GCTL1
VDDQ
VDDQ
VDDQ
VREF7
VDDQ
VCPLL VDDQ
VDDQ
VDDQ
VDDQ
GCTL0
GNDO
VREF6
IOP6
IO/VRE
VCCO5 VCCO5 VCCO5 VCJTG
IO/VRE
SD_B RXCP2 RXCN2 RXCP1 RXCN1 VDDQ VCCQ VCCQ VCCQ VCCQ
IO/VRE
VCCO0 GCLK0
VCCO0
VSSQ
VSSQ
INP_B INN_B
VCCO0
VSSQ
VSSQ
VSSQ CMSER
VSSQ
VSSQ
VSSQ OUTN_ OUTP_ VCCQ VCCQ VCCQ
GNPLL
VDDQ
VCCQ
IO/VRE
RXCN1 RXCP1 RXCN2 RXCP2
IO/VRE
VDDQ
VCCQ
VCCQ VCCQ VCCQ
VSSQ
VSSQ
VCCO1 GNDO
VSSQ
VSSQ
VSSQ CMSER
IO/VRE IO/VRE
VSSQ
VSSQ
VSSQ
OUTP OUTN
VDDQ
VCCQ
VCCQ VCCQ VCCQ
IO/VRE
REF- VCCO4 CLKP REF- VCCO4 CLKN VCEP
VCCO4
VCEP
VCCO1 IO/VRE GNDO IO/VRE
CDONE VCCO1
CDATA RECON CRST CCLK
VCCFG VCCO2 VCCO2 VCCO2 VCCO2
VDDQ VCCO3 VCCO3
IO/VRE
VDDQ VCCO4 IO/VRE IO/VRE VCCO3 VCCO3 IO/VRE IO/VRE
VDDQ
VDDQ
IO/VRE
MSEL IO/VRE
IO/VRE
IO/VRE
VREF3
IO/VRE
IO/VRE
IO/VRE
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456-Ball Table (continued) 456-Ball Table 25G01K100 HSTLREF HSTLREF HSTLREF HSTLREF HSTLREF IO/VREF5 IO/VREF5 HSTLREF HSTLREF HSTLREF VDDQ HSTLREF 25G02K100 IO/VREF7 IO/VREF7 IO/VREF6 IO/VREF6 IO/VREF6 IO/VREF5 IO/VREF5 IO/VREF7 IO/VREF7 IO/VREF7 VDDQ IO/VREF6 25G01K100 IO/VREF5 VDDQ GCTL3 VDDQ VDDQ VDDQ HSTLREF GCTL2 GCTL1 25G02K100 IO/VREF5 VDDQ GCTL3 VDDQ VDDQ VDDQ IO/VREF6 GCTL2 GCTL1 Page
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456-Ball Table (continued) 25G01K100 VDDQ VDDQ VDDQ HSTLREF VDDQ VCPLL VDDQ VDDQ VDDQ GCLK1 GCTL0 HSTLREF IOP6 IO/VREF5 25G02K100 VDDQ VDDQ VDDQ IO/VREF7 VDDQ VCPLL VDDQ VDDQ VDDQ VDDQ GCTL0 GNDO IO/VREF6 IOP6 IO/VREF5 456-Ball Table (continued) 25G01K100 VCCO5 VCCO5 VCCO5 VCJTG IO/VREF0 IO/VREF0 VCCO0 GCLK0 VCCO0 VSSQ VSSQ 25G02K100 VCCO5 VCCO5 VCCO5 VCJTG IO/VREF0 SD_B RXCP2_B RXCN2_B RXCP1_B RXCN1_B IO/VREF0 VCCO0 GCLK0 VDDQ VCCQ VCCQ VCCQ VCCQ VCCO0 VSSQ VSSQ INP_B INN_B Page
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456-Ball Table (continued) 25G01K100 VCCO0 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ GNPLL IO/VREF0 25G02K100 VCCO0 VSSQ VSSQ VSSQ CMSER_B VSSQ VSSQ VSSQ OUTN_B OUTP_B GNPLL VDDQ VCCQ VCCQ VCCQ VCCQ IO/VREF0 456-Ball Table (continued) 25G01K100 RXCN1 RXCP1 RXCN2 RXCP2 IO/VREF0 VCCQ VCCQ VCCQ VCCQ VSSQ VSSQ 25G02K100 RXCN1 RXCP1 RXCN2 RXCP2 IO/VREF0 VDDQ VCCQ VCCQ VCCQ VCCQ VSSQ VSSQ Page
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456-Ball Table (continued) 25G01K100 VCCO1 VSSQ VSSQ VSSQ CMSER IO/VREF1 IO/VREF1 VSSQ VSSQ VSSQ OUTP OUTN VCCQ VCCQ VCCQ VCCQ 25G02K100 VCCO1 GNDO VSSQ VSSQ VSSQ CMSER IO/VREF1 IO/VREF1 VSSQ VSSQ VSSQ OUTP OUTN VDDQ VCCQ VCCQ VCCQ VCCQ 456-Ball Table (continued) AA22 AA23 AA24 AA25 AA26 25G01K100 IO/VREF1 REFCLKP VCCO4 VCCO4 REFCLKN VCCO4 VCEP VCEP IO/VREF4 VCCO1 IO/VREF1 25G02K100 IO/VREF1 REFCLKP VCCO4 VCCO4 REFCLKN VCCO4 VCEP VCEP VCCO1 IO/VREF1 GNDO Page
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456-Ball Table (continued) AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC10 AC11 AC12 AC13 AC14 AC15 AC16 25G01K100 CDONE VCCO1 IO/VREF2 CDATA RECONFIG VCCFG VCCO2 VCCO2 VCCO2 VCCO2 VDDQ VCCO3 VCCO3 25G02K100 CDONE VCCO1 IO/VREF2 CDATA RECONFIG VCCFG VCCO2 VCCO2 VCCO2 VCCO2 VDDQ VCCO3 VCCO3 456-Ball Table (continued) AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 25G01K100 IO/VREF3 VCCO4 IO/VREF4 IO/VREF4 CRST CCLK VDDQ VDDQ IO/VREF2 VCCO3 VCCO3 IO/VREF3 MSEL IO/VREF2 IO/VREF2 25G02K100 IO/VREF3 VDDQ VCCO4 IO/VREF4 IO/VREF4 CRST CCLK VDDQ VDDQ IO/VREF2 VCCO3 VCCO3 IO/VREF3 MSEL IO/VREF2 IO/VREF2 Page
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456-Ball Table (continued) AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 25G01K100 IO/VREF2 IO/VREF3 IO/VREF3 IO/VREF2 IO/VREF3 IO/VREF3 25G02K100 IO/VREF2 IO/VREF3 IO/VREF3 IO/VREF2 IO/VREF3 IO/VREF3 Page 456-Ball Table (continued) AF21 AF22 AF23 AF24 AF25 AF26 25G01K100 25G02K100
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K200
Standard Cypress Designator SONET 1.5Gbps 2.5Gbps 3.2Gbps 10.0Gbps Commercial Industrial Multichip
ball ball
channel channel channel channel channel
Standard Power 3.3V-Vcc Power Mixed 2.5V 3.3V-Vcc K100 100K gates K200 200K gates
Ordering Information
Device 25G01K100 25G02K100 15G04K100 15G04K200 15G08K200 Channels Link Speed Gbps Gbps Gbps Gbps Ordering Code CYP25G01K100V1-MGC CYS25G01K100V1-MGC CYP25G02K100V1-MGC CYS25G02K100V1-MGC Package Name 456MGC 456MGC 456MGC 456MGC 456MGC 700MGC 700MGC Package Type 456-Ball Ball Grid Array 456-Ball Ball Grid Array 456-Ball Ball Grid Array 456-Ball Ball Grid Array 456-Ball Ball Grid Array 700-Ball Ball Grid Array 700-Ball Ball Grid Array Commercial Industrial Commercial Operating Range Commercial
Gbps CYP15G04K100V1-MGC Gbps CYP15G04K200V2-MGC Gbps CYP15G08K200V2-MGC
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Package Diagrams
456-Lead Ball Grid Array 2.33 BG456
51-85133
NoBL, Programmable Interconnect Matrix, PIM, Spread Aware, Warp, AnyVolt, Self-Boot, In-System Reprogrammable, ISR, Programmable Serial Interface, trademarks Cypress Semiconductor Corporation. trademark IDT. InfiniBand trademark InfiniBand Trade Association. trademark Micron, IDT, Cypress Semiconductor Corporation. Windows registered trademark Microsoft Corporation. SpeedWave, ViewDraw trademarks ViewLogic.
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Document Title: Programmable Serial Interface Device Family (High Speed) Programmable Bandwidth Document Number: 38-02021 REV. 106745 107726 109064 Issue Date 05/25/01 06/04/01 09/07/01 Orig. Change Description Change Change from Spec #38-01093 38-02021 Updated Marketing Part Numbers Added feature CHAR data
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Cypress Semiconductor Corporation, 2001. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.

Programmable Bandwidth Mbps Gbps, Gbps serial signaling rate Flex

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