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PM5351 S/UNI-155-TETRA S/UNI TETRA WITH S/UNI ATLAS REFERENCE DES


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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
PM5351
S/UNI-155 TETRA WITH S/UNI ATLAS
REFERENCE DESIGN
RELEASED ISSUE SEPTEMBER 2001
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
PUBLIC REVISION HISTORY Issue Issue Date September 2001 Details Change Document Created
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
CONTENTS DEFINITIONS FEATURES.2 APPLICATIONS.3 REFERENCES APPLICATION EXAMPLES ASWITCH PORT CARD
BLOCK DIAGRAM.6 FUNCTIONAL DESCRIPTION PM5351 S/UNI-155-TETRA PM7324 S/UNI-ATLAS.7 7.2.1 NOTE S/UNI-ATLAS THROUGHPUT 7.2.2 INGRESS SRAM.8 7.2.3 EGRESS SRAM COMPACT INTERFACE MICROPROCESSOR PORT CPLD.9 7.4.1 OUTPUT SELECT 7.4.2 BOARD RESET.
IMPLEMENTATION DESCRIPTION.12 SHEET ROOT DRAWING SHEET 2-3, SUNI-TETRA BLOCK 8.2.1 SHEET TETRA BLOCK.12 8.2.2 SHEET TETRA SUPPLY FILTERING.12
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
SHEETS SUNI-ATLAS BLOCK.12 8.3.1 SHEET SCI-PHY MASTER INTERFACE 8.3.2 SHEET SCI-PHY SLAVE INTERFACE.12 8.3.3 SHEET INGRESS EGRESS SRAM INTERFACES12 8.3.4 SHEET MICROPROCESSOR INTERFACE.13
INTERFACE BLOCK.13 8.4.1 SHEET PLX9050 INTERFACE.13 8.4.2 SHEET MICROPROCESSOR PORT CPLD
SHEET OPTICS BLOCK.13 SHEET INGRESS_SRAM.13 SHEET EGRESS_SRAM.14
SCHEMATICS LAYOUT.16 BILL MATERIALS VHDL CODE EEPROM CONTENTS
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
LIST FIGURES
FIGURE ASWITCH USING S/UNI-155-TETRA S/UNI-ATLAS FIGURE BLOCK DIAGRAM ATLAS-TETRA REFERENCE DESIGN FIGURE OPERATION REFERENCE DESIGN.7 FIGURE CHANNEL SELECTION
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
LIST TABLES TABLE TABLE CPLD OUTPUT CHANNEL SELECT REGISTER 0X00H CHANNEL SELECT
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
DEFINITIONS CPCI Compact PCI. adapted specification from Peripheral Component Interconnect (PCI) Specification later using mechanical form factor suitable tugged environments. Fault Management. mechanism used network inform management entities other network equipment faults within network. Form factor fibre optic connectors which feature receive transmit interfaces single plug. Operations, Administration, Maintenance. maintenance within network. Peripheral Component Interconnect. specification typically used interconnect chipsets. Performance Management. mechanism used network monitor performance parameters particular Virtual Connection. This refers either Virtual Path Connection (VPC) Virtual Channel Connection (VCC) within physical link. Virtual Channel Connection. virtual connection between network elements. virtual channel connection normally constituent member virtual path connection, where consists more VCCs. This sometimes known connection. Virtual Path Connection. virtual connection between network elements. virtual path connection span more physical links. This sometimes known connection.
MT-RJ
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
FEATURES following features supported this reference design. Note that list features exhaustive, does represent full capabilities TETRA ATLAS. Support (Virtual Connections) Ingress header translation Ingress cell rate policing (per-VC per-PHY) OAM-FM OAM-PM bidirectional Egress header translation Four STS-3c interfaces using MT-RJ fibre optic connectors
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
APPLICATIONS ASwitch Port Card
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
REFERENCES
PMC-1971154, "S/UNI-ATLAS Datasheet", Issue 2000. PMC-1971240, "S/UNI-TETRA Datasheet", Issue 2000. PICMG R2.1, "CompactPCI Specification", September 1997 PMC-1980585, "S/UNI-ATLAS Programmers Guide Example Software", Issue 1999. PMC-1981505, "S/UNI-ATLAS Datasheet Errata", Issue June 2001. PMC-1980583,"Switch Port (SPORT) Card Reference Design", Issue 1999. PMC-1990330, "ASwitch Using S/UNI-ATLAS, QRT, Reference Design", Issue July 1999. AForum, "AForum Traffic Management Specification Version 4.1", 1999.
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
APPLICATION EXAMPLES ASwitch Port Card figure below shows complete Aswitch using S/UNI TETRA S/UNI ATLAS line card. This design explained detail PMC-1980583 "Switch Port (SPORT) Card Reference Design" PMC-1990330 "ASwitch Using S/UNI-ATLAS, QRT, Reference Design" Figure ASwitch Using S/UNI-155-TETRA S/UNI-ATLAS
ATLAS-TETRA Reference Design CARD
Timing Card
Mbps
PM5351 S/UNITETRA
PM7324 S/UNI-ATLAS
CARD
Traffic Manager
Mbps
PM5351 S/UNITETRA
PM7324 S/UNI-ATLAS
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
BLOCK DIAGRAM Figure Block Diagram ATLAS-TETRA Reference Design
OC-3 I/Fs
19.44 Oscillator RFCLK TFCLK
PM5351 S/UNI-TETRA
ISYSCLK ESYSCLK ATLAS_RFCLK ATLAS_TFCLK
PHY_SEL_CLK
ISRAMCLK0
SSRAM 128Kx36
ISRAMCLK0
SSRAM 128Kx36
XC95216
PHY_SEL[1.0]
PM7324 S/UNI-ATLAS
SSRAM 128Kx36
IFCLK OFCLK
UL2/PL2 SLAVE
PLX9054 ACCELERATOR
CONTROL SIGNALS DATA ADDRESS
CPCI Connector
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ESRAMCLK
50MHz Oscillator Driver
UL2/PL2 MASTER
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
FUNCTIONAL DESCRIPTION S/UNI-155-TETRA with S/UNI-ATLAS reference board designed demonstrate features PM5351 S/UNI-155-TETRA PM7324 S/UNI-ATLAS small form factor PCB. result, subset complete Aswitch (see Section 5.1). receive side, S/UNI TETRA takes SONET/SDH traffic from 4xOC3 PHYs extracts Acells from SONET/SDH frame subsequent processing S/UNI-ATLAS device. Once Acells passed ATLAS master interface, they processed according their corresponding table. processed cells then passed slave interface that looped back into egress direction ATLAS device. After egress processing occurs, cells passed back S/UNI-TETRA insertion into SONET/SDH frame subsequent transmission over optical medium. Figure Operation Reference Design
Mbps
PM5351 S/UNITETRA
PM7324 S/UNI-ATLAS
PM5351 S/UNI-155-TETRA TETRA responsible physical layer functions. features internal clock data recovery four Mbps optical interfaces. MT-RJ connectors used interface optical fiber. more information PM5351 S/UNI-TETRA, please refer S/UNI-TETRA Datasheet, PMC-1971240.
PM7324 S/UNI-ATLAS PM7324 S/UNI-ALayer Solution (S/UNI-ATLAS) PMC-Sierra standard product that implements following ALayer functions:
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PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
processing according ITU-T I.610 1998. Header Translation full VPI/VCI address range. Prepend/Postpend tagging. Cell rate policing according ITU-T I.371 using Generic Cell Rate Algorithm. Per-PHY queuing prevent head-of-line blocking.
receive direction, S/UNI ATLAS takes cells from S/UNI-155-TETRA performs lookup based number, VPI, identify associated connection. Once connection identified, cell processed according configuration connection. this application, ATLAS perform header translation, per-PHY per-VC policing, performance monitoring, fault management. transmit direction, direct lookup performed ATLAS identify connection. cell then processed according configuration context table that connection. Header translation processing done egress. more detailed description S/UNI-ATLAS, please refer S/UNIATLAS Datasheet, PMC-1971154. 7.2.1 Note S/UNI-ATLAS Throughput This reference design uses clock bus. However, throughput issue S/UNI-ATLAS, explained PMC-1981505 "S/UNIATLAS Datasheet Errata", there certain configurations that allow maximum throughput through device. workaround clock ISYSCLK 59.5 Mhz. this reference design this possible both ISYSCLK ESYSCLK clocked from same source. ESYSCLK limited maximum clock frequency Mhz. addition, clock frequency ISYSCLK increased beyond 52Mhz, HALFSECCLK longer generated internally will faster than Second) must sourced externally. more detailed description workaround options found PMC-1981505 "S/UNI-ATLAS Datasheet Errata". 7.2.2 Ingress SRAM Ingress Table 15-row data structure which contains context information 65536 connections. Ingress Table used connection identification, connection configuration cell processing functions.
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PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
connection identification fields Table located first rows structure, remaining rows used connection configuration cell processing. Ingress Table stored externally S/UNI-ATLAS SRAM (Static Ram). ingress SRAM data bits wide bytes plus byte parity), with address space bits (1M). This creates enough context address space VCs. entire SRAM space does have populated however. less than required, subset ATLAS features used, then SRAM required reduced. However, additional glue logic required achieve savings SRAM. this reference design, enough SRAM used provision VCs. ATLAS, synchronous flow-through non-pipelined SRAMs must used both Ingress Egress. 7.2.3 Egress SRAM Egress table 16-row 32-bit data structure which contains context information 65536 connections. Egress Table used connection identification, connection configuration cell processing functions. connection identification field Egress Table record located first structure, remaining rows used connection configuration cell processing. Like Ingress Table, Egress Table stored external S/UNIATLAS SRAM. egress SRAM data bits wide bytes plus byte parity), with address space bits (1M). This allows connections, with Ingress Table. this design, enough SRAM provided provision VCs. Compact Interface Microprocessor access devices board provided using 9050 bridge chip between compact local microprocessor bus. connector used accordance with CPCI standard. more information functions refer CompactPCI Specification [10]. Microprocessor Port CPLD Xilinx 95216 CPLD used perform following functions. output select
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
Board reset
7.4.1 Output Select CPLD allows user manually select which looped back data will output Table shows what values write each output channel. Figure Channel Selection
Mbps
PM5351 S/UNITETRA
PM7324 S/UNI-ATLAS
IADDR<1.0>
CPLD
CHAN_SEL<1.0>
Table below describes function bits Output Channel Select Register. Table CPLD Output Channel Select Register 0x00h Type Function USED CHAN_SEL(1) CHAN_SEL(0) Default
CHAN_SEL [1.0] These bits used select output PHY. Table Channel Select
Output Channel
CHAN_SEL[1.0]
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
CHAN_SEL[1.0]
Output Channel
7.4.2 Board Reset CPLD also performs master reset devices (TETRA, ATLAS, BRIDGE) when reset button pressed.
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
IMPLEMENTATION DESCRIPTION This section details hardware S/UN-155-TETRA reference design, with reference schematics Section
Sheet Root Drawing This sheet shows interconnection between functional blocks design.
Sheet 2-3, SUNI-TETRA Block
8.2.1 Sheet TETRA Block Sheet shows S/UNI-TETRA it's surrounding connections. 19.44MHz oscillator provides timing reference S/UNI-TETRA. resistor used prevent latchup when exceeds VBIAS. 8.2.2 Sheet TETRA Supply Filtering Sheet shows power supply filtering S/UNI-TETRA. Sheets SUNI-ATLAS Block
8.3.1 Sheet SCI-PHY Master Interface Sheet shows Ingress Input Egress Output cell interfaces ATLAS. RPOLL TPOLL pins both high enable polling. Source terminations used. 8.3.2 Sheet SCI-PHY Slave Interface Sheet shows Ingress Output Egress Input cell interfaces ATLAS. selects between polling mode direct mode. normal operation, polling mode should used. source 50MHz clocks board. Source terminations used. 8.3.3 Sheet Ingress Egress SRAM Interfaces Sheet shows Ingress Egress SRAM interfaces.
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
8.3.4 Sheet Microprocessor Interface Sheet shows ATLAS microprocessor interface. provided allow BUSYB interrupt microprocessor. This useful SRAM access software routines. HALFSECCLK input tied low, since required when ISYSCLK ESYSCLK MHz. resistor used prevent latchup when exceeds VBIAS. tolerance required, VBIAS tied 3.3V. INTERFACE Block
8.4.1 Sheet PLX9050 Interface Sheet shows PLX9050 bridge chip associated circuitry. serial EEPROM used provide configuration information PLX9050 startup. Address Data pins multiplexed. Separate signals provided clock output PLX9050 buffered drive CPLD microprocessor interface. stub terminations provided required CPCI specification. 8.4.2 Sheet Microprocessor Port CPLD Sheet shows CPLD used perform interrupt identification output select. Headers provided allow system programming CPLD. CPLD generates free running clock JTAG interfaces ATLAS TETRA. free-run clock along with these devices being tied high, continuously resets JTAG circuitry ensuring proper operation. Sheet OPTICS Block Sheet shows four MT-RJ optical transceivers. TXD+/- signal traces terminated near optics using 49.9 resistors biasing network. RXD+/- signal traces terminated with resistor across RXD+/-. differential pairs kept equal length. Sheet INGRESS_SRAM Sheet shows connections ingress SRAM interface. There enough SRAM support connections ingress. more connections required, this configuration would maintained, banks would added using ISA[13:15]. instance, second bank SRAM, ISA[13] would
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RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
used select second bank. Terminations required SRAMs placed close enough ATLAS. Sheet EGRESS_SRAM Sheet shows connections egress SRAM interface. There enough SRAM support connections egress. more connections required, this configuration would maintained, banks would added using ESA[13:15]. Terminations required SRAMs placed close enough ATLAS. Technology SRAMS recommended have been tested with S/UNI-ATLAS.
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PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
SCHEMATICS
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PAGE PCI_INTERFACE
REVISIONS
ZONE DESCRIPTION DATE APPR
ORDENB IWRENB OSOC ISOC PHY_SEL_DAT<1> PHY_SEL_DAT<0> PHY_SEL_CLK IADDR<0> IADDR<1> INGRESS_SRAM CSB_TETRA MD<31.0> MA<11.0> ISADSB ISOEB ISRWB ISA<19.0> ISP<7.0> ISD<63.0> ISRAMCLK0 ISRAMCLK1 PAGE 4,5,6,7 SUNI_ATLAS ATLAS_ALE JTAG_CLK ORDENB IWRENB OSOC ISOC PHY_SEL_DAT<1> PHY_SEL_DAT<0> PHY_SEL_CLK IADDR<0> IADDR<1> PAGE
TETRA_INTB ATLAS_INTB RESETB
CSB_TETRA
MD<31.0> MA<11.0>
CSB_ATLAS
ATLAS_ALE JTAG_CLK
TETRA_INTB ATLAS_INTB RESETB
CSB_ATLAS
ATLAS_ALE CSB_ATLAS
RESETB ATLAS_INTB
ISRAMCLK0 ISRAMCLK1 ISD<63.0> ISD<63.0> ISP<7.0> ISP<7.0> ISA<19.0> ISA<19.0> ISRWB ISRWB ISOEB ISOEB ISADSB ISADSB
MD<31.0>
MA<11.0> IADDR<1> IADDR<0> PHY_SEL_CLK PHY_SEL_DAT<0> PHY_SEL_DAT<1> ISOC OSOC IWRENB ORDENB
PAGE TETRA_BLOCK
MA<9.0> MD<7.0> TETRA_INTB RESETB CSB_TETRA PAGE OPTICS_BLOCK TXD1P TXD1N RXD1P RXD1N TXD2P TXD2N RXD2P RXD2N TXD3P TXD3N RXD3P RXD3N TXD4P TXD4N RXD4P RXD4N TXD1P TXD1N RXD1P RXD1N TXD2P TXD2N RXD2P RXD2N TXD3P TXD3N RXD3P RXD3N TXD4P TXD4N RXD4P RXD4N TXD1P TXD1N RXD1P RXD1N
JTAG_CLK
JTAG_CLK
RFCLK RDAT<15.0> RPRTY RENB RADDR<4.0>
RFCLK RDAT<15.0> RPRTY RENB RADDR<4.0>
RFCLK RDAT<15.0> RPRTY RENB RADDR<4.0>
RSOC TXD2P TXD2N RXD2P RXD2N TXD3P TXD3N RXD3P RXD3N TXD4P TXD4N RXD4P RXD4N
RSOC
RSOC
TFCLK TDAT<15.0> TPRTY TENB TADDR<4.0>
TFCLK TDAT<15.0> TPRTY TENB TADDR<4.0>
TFCLK TDAT<15.0> TPRTY TENB TADDR<4.0>
TSOC
TOSC
TSOC
ESRAMCLK ESD<31.0> ESP<3.0> ESA<19.0> ESRWB ESOEB ESADSB
ESRAMCLK ESD<31.0> ESP<3.0> ESA<19.0> ESRWB ESOEB ESADSB
PAGE EGRESS_SRAM ESADSB ESOEB ESRWB ESA<19.0> ESP<3.0> ESD<31.0> ESRAMCLK
DRAWING: TITLE=ATLAS_ROOT ABBREV=ATLAS_ROOT LAST_MODIFIED=Thu 13:56:11 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: TITLE: ATLAS TETRA PORT CARD ROOT DRAWING ENGINEER: ISSUE DATE: 01/06/26 REVISION NUMBER: PAGE:1
REVISIONS
ZONE DESCRIPTION DATE APPR
HCMOS 19.44MHZ 3.3V 20PPM
C224 0.01UF C223 0.1UF 4.7UF
3D2> 3F2> 3H2> 3D6> 3F6> 3H6>
C225
NC/TS
QAVD<2.1> TAVD1<2.1> RAVD4<3.1> RAVD3<3.1> RAVD2<3.1> RAVD1<3.1>
RESISTOR PREVENTS LATCHUP WHEN VBIAS
1.0K 0.1UF C180
C208 0.22UF 0.22UF 0.22UF C172 0.22UF
SBGA RAVD1<3.1> RAVD2<3.1> RAVD3<3.1> RAVD4<3.1> TAVD1<2.1> QAVD<2.1> VDD<36.1> BIAS1 BIAS2
ATB<4.1>
REFCLK CP<4.1> CN<4.1>
JTAG_CLK\I
9B10>
CP<4.1> CN<4.1>
10F6>
RXD1P\I RXD1N\I SD1\I
RXD1+ RXD1SD1 TXC1+ TXC1TXD1+ TXD1-
TRSTB
10F6> 10F6>
RESETB\I
9B10>
TMOD TERR TEOP STPA DTCA/DTPA<4.1>
10F6< 10C6> 10C6>
TXD1N\I
DTCA_TETRA<4.1> TDAT<15.0>\I
RXD2P\I RXD2N\I SD2\I
RXD2+ RXD2SD2 TXC2+ TXC2TXD2+ TXD2-
TDAT<15.0> TPRTY TSOC/TSOP TCA/PTPA TADR<4.0> TENB TFCLK
4D2> 4E2> 4E2> 4E2< 4E2> 4E2> 4E2<> 4E2> 4E2<> 4E2>
TPRTY\I TSOC\I TCA\I TADDR<4.0>\I TENB\I TFCLK\I
4.7K
10C6>
10D6< 10C6< 10F1> 10F1> 10F1>
TXD2P\I TXD2N\I
0.1UF 0.1UF
5G1>
0.1UF
RN73
10G6<
TXD1P\I
0.1UF
RXD3P\I RXD3N\I SD3\I
RXD3+ RXD3SD3 TXC3+ TXC3TXD3+ TXD3 RXD4+ RXD4SD4 TXC4+ TXC4TXD4+ TXD4-
S/UNI TETRA
PM5351
PHY_OEN
RFCLK RENB RADR<4.0> RCA/PRPA RSOC/RSOP RPRTY RDAT<15.0> DRCA/DRP<4.1> REOP RERR RMOD RVAL
RFCLK\I RENB\I RADDR<4.0>\I
5G1> 4E10> 4E10<> 4E9> 4E10< 4E9< 4E10< 4E9<> 4E9>
10G1< 10F1< 10C1> 10C1> 10C1>
TXD3P\I TXD3N\I RXD4P\I RXD4N\I SD4\I
0.1UF 0.1UF
RCA\I RSOC\I RPRTY\I IRDAT<15.0> DRCA_TETRA<4.1>
RDAT<15.0>\I
RN76 RN75 RN75 RN75 RN76 RN77 RN75 RN76 RN77 RN77 RN77 RN74 RN74 RN76 RN74 RN74
10D1< 10C1<
TXD4P\I TXD4N\I
0.1UF 0.1UF
INTB TLDCLK<4.1> TSDCLK<4.1> TLD<4.1>
4.7K
TETRA_INTB\I RESETB\I RDB\I WRB\I CSB_TETRA\I
9B2< 9B10> 8C3> 8C3> 8C3>
RSTB A<10> A<9> A<8> A<7.0> RAVS1<3.1> RAVS2<3.1> RAVS3<3.1> RAVS4<3.1> TAVS1<2.1> D<7.0> QAVS<2.1> VSS<36.1>
4D9<
TSD<4.1>
AC11
TCLK TFPO TFPI RLDCLK<4.1>
4.7K
AB11 4.7K
NC<11.1>
74LPT541
RCLK<4.1> RFPO<4.1> RALRM<4.1> RALRM<4.1>
0.01UF
4.7K
SOIC
MA<9.0>\I
8E2>
CHIP_RES_NETWORK_8
RSDCLK<4.1> RLD<4.1> RSD<4.1>
MD<7.0>\I
7F6<> 8G1<> 9F10<>
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: DRAWING TITLE=TETRA_BLOCK ABBREV=TETRA_BLOCK LAST_MODIFIED=Thu 13:59:04 2001 TITLE: ATLAS TETRA PORT CARD TETRA BLOCK ENGINEER: ISSUE DATE: 01/06/26 REVISION NUMBER: PAGE:2
REVISIONS
ANALOG RECEIVE 3.3VF
0.1UF C171
ZONE
RAVD1<3.1>
2G7<
DESCRIPTION
DATE
APPR
ANALOG RECEIVE
3.3VF
0.1UF C213
RAVD4<3.1>
2G7<
0.1UF C170
0.1UF C207
0.1UF C174
0.1UF 0.1UF C167 C206
ANALOG RECEIVE 3.3VF
RAVD2<3.1>
2G7<
ANALOG TRANSMIT
0.1UF C176
3.3VF
0.1UF C168
TAVD1<2.1>
2G7<
0.1UF 0.1UF C169 C209
ANALOG RECEIVE 3.3VF
0.1UF C210
RAVD3<3.1>
2G7<
ANALOG QAVD
0.1UF C212
QAVD<2.1>
2G7<
0.1UF C204 0.1UF 0.1UF C205 C214
3.3V
LT1121CST
VOUT
3.3VF
47UF
47UF
10UF
0.01UF
C179 0.01UF
C173 0.01UF
C178 0.01UF
0.01UF
C216 0.01UF
C175 0.01UF
C177 0.01UF
C211 0.01UF
C215
C217
PMC-Sierra, Inc.
PLACE DECOUPLING CAPS NEAR DIGITAL PINS DRAWING TITLE=TETRA_BLOCK ABBREV=TETRA_BLOCK LAST_MODIFIED=Thu 13:59:06 2001 DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: TITLE: ATLAS TETRA PORT CARD TETRA BLOCK ENGINEER: ISSUE DATE: 01/06/26 REVISION NUMBER: PAGE:3
REVISIONS
ZONE DESCRIPTION DATE APPR
5G1>
ATLAS_TFCLK
5G1> 2D3> 2D3< 2D3< 2D3< 2D3< 2D3< 2D3> 2D3< 2D3>
ATLAS_RFCLK RSOC\I RADDR<2>\I RADDR<1>\I RADDR<0>\I RADDR<4>\I RADDR<3>\I RCA\I RENB\I RPRTY\I
RN28 RN61 RN61 RN61
1RN28
RPOLL RFCLK RSOC RADDR<2>/RRDENB<4> RADDR<1>/RRDENB<3> RADDR<0>/RRDENB<2> RAVALID/RCA<4> RADDR<4>/RCA<3> RADDR<3>/RCA<2> RCA<1> RRDENB<1> RPRTY RDAT<15> RDAT<14> RDAT<13> RDAT<12> RDAT<11> RDAT<10> RDAT<9> RDAT<8> RDAT<7> RDAT<6> RDAT<5> RDAT<4> RDAT<3> RDAT<2> RDAT<1> RDAT<0>
TPOLL TFCLK TSOC TADDR<2>/TWRENB<4> TADDR<1>/TWRENB<3> TADDR<0>/TWRENB<2> TAVALID/TCA<4> TADDR<4>/TCA<3> TADDR<3>/TCA<2> TCA<1> TWRENB<1> TPRTY TDAT<15> TDAT<14> TDAT<13> TDAT<12> TDAT<11> TDAT<10> TDAT<9> TDAT<8> TDAT<7> TDAT<6> TDAT<5> TDAT<4> TDAT<3> TDAT<2> TDAT<1> TDAT<0>
RN603 RN27 RN60 RN27
RN28 RN27
TSOC\I TADDR<2>\I TADDR<1>\I TADDR<0>\I TADDR<4>\I TADDR<3>\I TCA\I TENB\I TPRTY\I
2E3< 2E3< 2E3< 2E3< 2E3< 2E3< 2E3> 2E3< 2E3<
RN27 RN60 RN58 RN58 RN254 RN25 RN58 RN592 RN25 RN25 RN59 RN26 RN26 RN59 RN59 RN26 RN26 RN60
2D1>
RDAT<15.0>\I
PM7324 S/UNI-ATLAS MASTER UTOPIA
8RN55 5RN55A 7RN57 SPARE
4.7K
TDAT<15.0>\I
2E3<
DRAWING: TITLE=SUNI_ATLAS ABBREV=SUNI_ATLAS LAST_MODIFIED=Thu 13:59:08 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: TITLE: ATLAS TETRA PORT CARD ATLAS SCI-PHY MASTER INTERFACE ENGINEER: ISSUE DATE: 01/06/26 REVISION NUMBER: PAGE:4
REVISIONS
ZONE
DESCRIPTION
DATE
APPR
0.01UF
0.1UF
DECOUPLING DRIVER
C110
C107
C152
0.01UF
0.1UF
DECOUPLING DRIVER
C154
SOIC20W
C108 0.01UF
PI49FCT3807
0.1UF
C109
NC/TS
MSTR_ATLAS_CLK
RN57 RN57 RN56 RN56 RN56 RN52 RN55 RN55
PI49FCT3807
8PIN_DUAL 50.000MHZ 3.3V 100PPM
SOIC20W
RN62
ESYSCLK ISYSCLK ISRAMCLK1\I ISRAMCLK0\I ESRAMCLK\I PHY_SEL_CLK\I OFCLK
7E5< 7E5< 11D10< 11F10< 12E10< 9C10<
TFCLK\I RFCLK\I ATLAS_TFCLK ATLAS_RFCLK
2E3< 2D3< 4F10< 4E9<
IFCLK
PRTY
NOTE HIGH NORMAL OPERATION
HEADER3
9C2<
OSOC\I OCA\I ORDENB\I IADDR<1>\I IADDR<0>\I IWRENB\I ISOC\I
AA31
9C2< 9D2> 9D2> 9D2>
IPOLL IADDR<2>/IWRENB<4> IADDR<1>/IWRENB<3> IADDR<0>/IWRENB<2> IAVALID/ICA<4> IADDR<4>/ICA<3> IADDR<3>/ICA<2> IWRENB<1> ICA<1> IFCLK ISOC IPRTY IDAT<15> IDAT<14> IDAT<13> IDAT<12> IDAT<11> IDAT<10> IDAT<9> IDAT<8> IDAT<7> IDAT<6> IDAT<5> IDAT<4> IDAT<3> IDAT<2> IDAT<1> IDAT<0>
9D2> 9C2>
OTSEN ORDENB OFCLK OSOC OPRTY ODAT<15> ODAT<14> ODAT<13> ODAT<12> ODAT<11> ODAT<10> ODAT<9> ODAT<8> ODAT<7> ODAT<6> ODAT<5> ODAT<4> ODAT<3> ODAT<2> ODAT<1> ODAT<0>
AA30 AB31 AA29 AB30 AA28 AG31 AF29 AF30 AF31 AE29 AD28 AE30 AE31 AD29 AC28 AD30 AD31 AC29 AC30 AC31 AB29
RN521 RN54 RN54 RN30 RN30 RN54 RN54 RN30 RN30 RN53 RN53 RN29 RN29 RN53 RN29 RN29 RN53
PM7324 S/UNI-ATLAS SLAVE UTOPIA
9C2< 9C2<
PHY_SEL_DAT<0>\I PHY_SEL_DAT<1>\I
DAT<15.0>
DRAWING: TITLE=SUNI_ATLAS ABBREV=SUNI_ATLAS LAST_MODIFIED=Thu 13:59:10 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: TITLE: ATLAS TETRA PORT CARD ATLAS SCI-PHY SLAVE INTERFACE ENGINEER: ISSUE DATE: 01/06/26 REVISION NUMBER: PAGE:5
REVISIONS
ZONE DESCRIPTION DATE APPR
ISD<63> ISD<62> ISD<61> ISD<60> ISD<59> ISD<58> ISD<57> ISD<56> ISD<55> ISD<54> ISD<53> ISD<52> ISD<51> ISD<50> ISD<49> ISD<48> ISD<47> ISD<46> ISD<45> ISD<44> ISD<43> ISD<42> ISD<41> ISD<40> ISD<39> ISD<38> ISD<37> ISD<36> ISD<35> ISD<34> ISD<33> ISD<32> ISD<31> ISD<30> ISD<29> ISD<28> ISD<27> ISD<26> ISD<25> ISD<24> ISD<23> ISD<22> ISD<21> ISD<20> ISD<19> ISD<18> ISD<17> ISD<16> ISD<15> ISD<14> ISD<13> ISD<12> ISD<11> ISD<10> ISD<9> ISD<8> ISD<7> ISD<6> ISD<5> ISD<4> ISD<3> ISD<2> ISD<1> ISD<0> ISP<7> ISP<6> ISP<5> ISP<4> ISP<3> ISP<2> ISP<1> ISP<0> ISA<19> ISA<18> ISA<17> ISA<16> ISA<15> ISA<14> ISA<13> ISA<12> ISA<11> ISA<10> ISA<9> ISA<8> ISA<7> ISA<6> ISA<5> ISA<4> ISA<3> ISA<2> ISA<1> ISA<0> ISRWB ISOEB ISADSB
ISD<63.0>\I
AJ10 AH11 AK10 AL10 AJ11 AH12 AK11 AL11 AJ12 AH13 AK12 AL12 AJ13 AK13 AL13 AJ14 AK14 AH15 AJ15 AL16 AK16 AJ16 AH16 AL17 AK17 AJ17 AK18 AH17 AJ18 AL19 AK19 AJ19 AL20 AK20 AH19 AJ20 AL21 AK21 AH20 AJ21 AL22 AJ23 AL24 AK24 AH23 AJ24 AL25 AK25 AH24 AJ25 AL26 AK26 AJ26 AL27 AK27 AH26 AJ27 AH31 AG29 AF28 AG30 AJ22 AL23 AK23
11D10<>
12F3<>
ESD<31.0>\I
12D3<>
ESP<3.0>\I
12F10<
ESA<19.0>\I0
12E10< 12E10< 12D10<
ESADSB\I ESRWB\I ESOEB\I
ESD<31> ESD<30> ESD<29> ESD<28> ESD<27> ESD<26> ESD<25> ESD<24> ESD<23> ESD<22> ESD<21> ESD<20> ESD<19> ESD<18> ESD<17> ESD<16> ESD<15> ESD<14> ESD<13> ESD<12> ESD<11> ESD<10> ESD<9> ESD<8> ESD<7> ESD<6> ESD<5> ESD<4> ESD<3> ESD<2> ESD<1> ESD<0> ESP<3> ESP<2> ESP<1> ESP<0> ESA<19> ESA<18> ESA<17> ESA<16> ESA<15> ESA<14> ESA<13> ESA<12> ESA<11> ESA<10> ESA<9> ESA<8> ESA<7> ESA<6> ESA<5> ESA<4> ESA<3> ESA<2> ESA<1> ESA<0> ESADSB ESRWB ESOEB
ISP<7.0>\I
11C10<>
ISA<19.0>\I
11H10<
ISRWB\I ISOEB\I ISADSB\I
11D10< 11D10< 11D10<
PM7324 S/UNI-ATLAS SRAM INTERFACE
DRAWING: TITLE=SUNI_ATLAS ABBREV=SUNI_ATLAS LAST_MODIFIED=Thu 13:59:12 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: TITLE: ATLAS TETRA PORT CARD ATLAS SRAM INTERFACES ENGINEER: ISSUE DATE: 01/06/26 REVISION NUMBER: PAGE:6
REVISIONS
ZONE DESCRIPTION DATE APPR
RESISTOR PREVENTS LATCHUP WHEN VBIAS
1.0K 0.1UF
8E2>
MA<11.0>\I
AK22
8D1>
ATLAS_ALE\I
8C3> 8C3> 8C3> 9B10>
CSB_ATLAS\I RDB\I WRB\I RESETB\I
D<15> D<14> A<11> D<13> A<10> D<12> A<9> D<11> A<8> D<10> A<7> A<6> D<9> A<5> D<8> A<4> D<7> A<3> D<6> A<2> D<5> A<1> D<4> A<0> D<3> D<2> D<1> D<0> INTB RSTB IDREQ HALFSECCLK EDREQ BUSYB
MD<31.0>\I
C111
2B3<> 8G1<> 9F10<>
VDD<40-1>
5G4> 5G4>
VBIAS
ESYSCLK ISYSCLK
AH21
PM7324 ESYSCLK ISYSCLK
ATLAS_INTB\I
9B2<
TRSTB POWER BLOCK GND<48-1>
JTAG_CLK\I RESETB\I
9B10> 9B10>
PM7324 S/UNI-ATLAS POWER BLOCK
PM7324 S/UNI-ATLAS MICROPROCESSOR INTERFACE
0.01UF
C122 0.01UF
C115 0.01UF
C112 0.01UF
C143 0.01UF
C120 0.01UF
C121 0.01UF
C142 0.01UF
C118 0.01UF
C119 0.01UF
C123
0.01UF C114 0.01UF C139 0.01UF C138 0.01UF C140 0.01UF C116 0.01UF C141 0.01UF C117 0.01UF C144 0.01UF C145 0.01UF
DECOUPLING ATLAS EVERY OTHER POWER DRAWING: TITLE=SUNI_ATLAS ABBREV=SUNI_ATLAS LAST_MODIFIED=Thu 13:59:14 2001
C113
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: TITLE: ATLAS TETRA PORT CARD ATLAS MICRO INTERFACE POWER ENGINEER: ISSUE DATE: 01/06/26 REVISION NUMBER: PAGE:7
REVISIONS
ZONE DESCRIPTION DATE APPR
CPCI CONNECTOR
SIGNALLING
VDD<1> VDD<2> VDD<3> VDD<4> VDD<5> VDD<6> VDD<7> VDD<8> VDD<9> VDD<10>
RN79
4.7K RN78
4.7K
4.7K RN80
RN84
4.7K
PCI_AD<31.0> PCI_CBE<3.0> RN13 RN13 RN13 RN12 RN12 RN12 RN12 RN11 RN11 RN11 RN10 RN10 RN10 RN10 RN90 RN11 RN90 RN90 RN90 RN13
DATA
MD<31.0>\I
PART#352068-1
RN157
RES_ARRAY_4
AD<0> AD<1> AD<2> AD<3> AD<4> AD<5> AD<6> AD<7> AD<8> AD<9> AD<10> AD<11> AD<12> AD<13> AD<14> AD<15> AD<16> AD<17> AD<18> AD<19> AD<20> AD<21> AD<22> AD<23> AD<24> AD<25> AD<26> AD<27> AD<28> AD<29> AD<30> AD<31> C/BEB<0> C/BEB<1> C/BEB<2> C/BEB<3> FRAMEB IRDYB TRDYB STOPB IDSEL DEVSELB PERRB SERRB RSTB INTAB LOCKB EESK EEDO EEDI EECS TEST VSS<1> VSS<2> VSS<3> VSS<4> VSS<5> VSS<6> VSS<7> VSS<8> VSS<9> VSS<10>
4.7K
ZPACK5X22A CPCI
NM93CS46
4.7K
RN158
4.7K
RES_ARRAY_4
4.7K
0.1UF
LAD<0> LAD<1> LAD<2> LAD<3> LAD<4> LAD<5> LAD<6> LAD<7> LAD<8> LAD<9> LAD<10> LAD<11> LAD<12> LAD<13> LAD<14> LAD<15> LAD<16> LAD<17> LAD<18> LAD<19> LAD<20> LAD<21> LAD<22> LAD<23> LAD<24> LAD<25> LAD<26> LAD<27> LAD<28> LAD<29> LAD<30> LAD<31> LA<2> LA<3> LA<4> LA<5> LA<6> LA<7> LA<8> LA<9> LA<10> LA<11> LA<12> LA<13> LA<14> LA<15> LA<16> LA<17> LA<18> LA<19> LA<20> LA<21> LA<22> LA<23> LA<24> LA<25> LA<26> LA<27> LBEB<0> LBEB<1> LBEB<2> LBEB<3> LINTI1 LINTI2 LCLK LHOLD LHOLDA LRESETB BCLKO CSB<0> CSB<1> USER0/WAITOB USER1/LLOCKOB USER2/CS2B USER3/CS3B ADSB BLASTB LRDYIB BTERMB MODE
2B3<> 7F6<> 9F10<>
RN89
4.7K RN88
4.7K
RN87
4.7K RN85
4.7K
4.7K
RN83
4.7K RN82
4.7K
RN81
4.7K
ADDRESS MA<11.0>\I
2B3< 7F9< 9G10<
RN93
RN94
RN92
4.7K
PCI_INTB
9B2>
PCI_RESETB CSB_ATLAS\I CSB_TETRA\I CSB_CPLD
9B10< 7E9< 2C3< 9B10<
74FCT807
ATLAS_ALE\I
7E10<
RN14
RDB\I WRB\I
2C3<7E9< 9H10< 2C3< 7E9< 9H10<
CPLD_CLK
9D10<
C188
RN86
PCI-9050-1
C190 0.1UF C221
4.7K
RN91
4.7K
0.1UF
0.1UF C192 0.1UF 10UF 10UF C191 C228 C189
0.1UF
C227 0.1UF
C219 0.1UF
C226 0.1UF
C218
0.1UF
C220
PMC-Sierra, Inc.
DRAWING TITLE=PCI_INTERFACE ABBREV=PCI_INTERFACE LAST_MODIFIED=Thu 13:59:20 2001 DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: TITLE: ATLAS TETRA PORT CARD INTERFACE ENGINEER: ISSUE DATE: 01/06/26 REVISION NUMBER: PAGE:8
REVISIONS
ZONE DESCRIPTION DATE APPR
8C3> 8C3> 8E2>
WRB\I RDB\I MA<11.0>\I
4.7K
PBNO
0.1UF
C183 0.1UF
RESET SWITCH
8G1<> 7F6<> 2B3<>
C187
C155 0.1UF
MD<31.0>\I
0.1UF
0.1UF
IO4/GSR VCCINT4 VCCIO6 GND12 GND11 IO10 IO10 IO10 IO10 VCCIO5
C184 0.1UF
0.1UF
C181
C156
8C1> 5F4>
CPLD_CLK PHY_SEL_CLK\I
VCCIO1 IO4/GTS3 IO4/GTS4 IO2/GTS1 IO2/GTS2 VCCINT1 GND1 GND2 IO3/GCK1 IO3/GCK2 GND3
XC95216PQ160 10NS
GND10 IO10 IO10 IO10 IO10 IO10 IO10 IO10 IO12 IO12 GND9 IO12 IO12 IO12 IO12 IO12 IO12 IO12 IO12 IO12 GND8 GND7 IO11 IO11 IO11 IO11 VCCINT3 IO11 IO11 IO11 IO11 IO11 IO11 IO11 VCCIO4
C157
RN16 RN16 RN16 RN16
IADDR<0>\I IADDR<1>\I IWRENB\I ORDENB\I PHY_SEL_DAT<0>\I PHY_SEL_DAT<1>\I OCA\I ISOC\I OSOC\I
5D9< 5D9< 5D9< 5D9< 5B9> 5B9> 5D9> 5C9< 5D9>
VCCIO2 IO3/GCK3 VCCINT2 GND4 VCCIO3 GND5 GND6
0.1UF
0.1UF
C182
C185
0.1UF
8C3> 8C3> 7E2<2F3< 7E9<2C3< 7E2<2F2<
CSB_CPLD PCI_RESETB JTAG_CLK\I RESETB\I
C186
TETRA_INTB\I ATLAS_INTB\I PCI_INTB
2C3> 7E6> 8C3<
HEADER ANALYSIS CPLD
CLK2 CLK1
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: DRAWING: TITLE=PCI_INTERFACE ABBREV=PCI_INTERFACE LAST_MODIFIED=Thu 13:59:24 2001 TITLE: ATLAS TETRA PORT CARD INTERFACE ENGINEER: ISSUE DATE: 01/06/26 REVISION NUMBER: PAGE:9
HP_LOGIC_ADAPTOR
HEADER SYSTEM PROGRAMMING
RN72
4.7K
REVISIONS
ZONE DESCRIPTION DATE APPR
OPTICS
0.1UF 10UF C194 0.1UF C150 0.1UF C164 C193
OPTICS
0.1UF C201
10UF
C158
0.01UF
TXD1P\I
2F9>
0.1UF C197 0.01UF 49.9
TXD3P\I
2D9>
49.9
10UF C162
0.1UF C151
10UF C199
C153
C202
49.9
49.9
HFCT5905 VCCT VCCR HFCT5905
TXDP TXDN RXDP RXDN TDIS
TXD1N\I RXD1P\I RXD1N\I SD1\I
2E9> 2F9< 2F9< 2F9<
HFCT5905 VCCT VCCR HFCT5905
TXDP TXDN RXDP RXDN TDIS
TXD3N\I RXD3P\I RXD3N\I SD3\I
2D9> 2D9< 2D9< 2D9<
CHASS1 CHASS2 VEET
CHASS1 CHASS2 VEET
VEER
VEER
OPTICS
0.1UF 10UF C160 0.1UF
OPTICS
C159
C165
10UF
C195
0.1UF
C196 0.1UF C222
C161 10UF C163 0.01UF 49.9 0.1UF
TXD2P\I
2E9>
0.1UF C198 10UF C200 0.01UF 49.9
TXD4P\I
2C9>
C166
49.9
C203
HFCT5905 VCCT VCCR HFCT5905
49.9
TXDP TXDN RXDP RXDN TDIS
TXD2N\I RXD2P\I RXD2N\I SD2\I
2E9> 2E9< 2E9< 2E9<
CHASS1 CHASS2 VEET
HFCT5905 VCCT VCCR HFCT5905
TXDP TXDN RXDP RXDN TDIS
TXD4N\I RXD4P\I RXD4N\I SD4\I
2C9> 2D9< 2D9< 2C9<
VEER
CHASS1 CHASS2 VEET
VEER
PMC-Sierra, Inc.
DRAWING TITLE=OPTICS_BLOCK ABBREV=OPTICS_BLOCK LAST_MODIFIED=Thu 13:59:01 2001 DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: TITLE: ATLAS TETRA PORT CARD OPTICS_BLOCK ENGINEER: ISSUE DATE: 01/06/26 REVISION NUMBER: PAGE:10
REVISIONS
ZONE DESCRIPTION DATE APPR
6C4>
ISA<19.0>\I
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
ISRAMCLK0\I
A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> A<9> A<10> A<11> A<12> A<13> A<14> A<15> A<16> ADSC ADSP
84036
5F4>
DQ<1> DQ<2> DQ<3> DQ<4> DQ<5> DQ<6> DQ<7> DQ<8> DQ<9> DQ<10> DQ<11> DQ<12> DQ<13> DQ<14> DQ<15> DQ<16> DQ<17> DQ<18> DQ<19> DQ<20> DQ<21> DQ<22> DQ<23> DQ<24> DQ<25> DQ<26> DQ<27> DQ<28> DQ<29> DQ<30> DQ<31> DQ<32> DQP<1> DQP<2> DQP<3> DQP<4>
A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> A<9> A<10> A<11> A<12> A<13> A<14> A<15> A<16> ADSC ADSP
84036
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQ<1> DQ<2> DQ<3> DQ<4> DQ<5> DQ<6> DQ<7> DQ<8> DQ<9> DQ<10> DQ<11> DQ<12> DQ<13> DQ<14> DQ<15> DQ<16> DQ<17> DQ<18> DQ<19> DQ<20> DQ<21> DQ<22> DQ<23> DQ<24> DQ<25> DQ<26> DQ<27> DQ<28> DQ<29> DQ<30> DQ<31> DQ<32> DQP<1> DQP<2> DQP<3> DQP<4>
6B4> 6B4>
ISADSB\I ISRWB\I ISOEB\I ISRAMCLK1\I ISD<63.0>\I ISP<7.0>\I
6B4> 5G4> 6G4<> 6D4<>
0.01UF
C148 0.01UF
C146 0.01UF
C147 0.01UF
C130 0.01UF
0.01UF
C126 0.01UF
C124 0.01UF
C129 0.01UF
C128 0.01UF
C127 0.01UF
C125 0.01UF
DECOUPLING GS84036 POWER PINS
C131
C149
DRAWING: TITLE=INGRESS_SRAM ABBREV=INGRESS_SRAM LAST_MODIFIED=Thu 13:59:26 2001
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: TITLE: ATLAS TETRA PORT CARD INGRESS SRAM ENGINEER: ISSUE DATE: 01/06/26 REVISION NUMBER: PAGE:11
REVISIONS
ZONE DESCRIPTION DATE APPR
ESA<19.0>\I
6D8>
A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> A<9> A<10> A<11> A<12> A<13> A<14> A<15> A<16> ADSC ADSP
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
ESD<31.0>\I
DQ<1> DQ<2> DQ<3> DQ<4> DQ<5> DQ<6> DQ<7> DQ<8> DQ<9> DQ<10> DQ<11> DQ<12> DQ<13> DQ<14> DQ<15> DQ<16> DQ<17> DQ<18> DQ<19> DQ<20> DQ<21> DQ<22> DQ<23> DQ<24> DQ<25> DQ<26> DQ<27> DQ<28> DQ<29> DQ<30> DQ<31> DQ<32> DQP<1> DQP<2> DQP<3> DQP<4>
6F8<>
84036
5F4> 6C8> 6C8>
ESRAMCLK\I ESADSB\I ESRWB\I
ESP<3.0>\I
6E8<>
6C8>
ESOEB\I
DECOUPLING GS84036
0.01UF C134 0.01UF C135 0.01UF C137 0.01UF C132 0.01UF C136 0.01UF
POWER PINS
C133
STRIP3
DRAWING: TITLE=EGRESS_SRAM ABBREV=EGRESS_SRAM LAST_MODIFIED=Thu 13:58:59 2001 HOLE_SIZE= 100MIL
MOUNTING HOLE
STRIP2
STRIP1
CPCI STRIP
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1991709 DOCUMENT ISSUE NUMBER: TITLE: ATLAS TETRA PORT CARD EGRESS SRAM ENGINEER: ISSUE DATE: 01/06/26 REVISION NUMBER: PAGE:12
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
LAYOUT
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
BILL MATERIALS
Table Bill Materials
Part Name
49FCT3807_SOIC-BASE
Part Number
PERICOM PI49FCT807TS
Reference Descriptor
"U10, U14"
74AHC540_SOIC-BASE-V CC=3_3V
SN74AHC540DW
74FCT807_SOIC-BASE 74XXX541_SOIC-VCC=3_ 84036_TQFP-BASE "CAPACITOR-0.01UF, 50V, X7R_805"
IDT74FCT807BTSO PI74LPT541SA GS84036T-166 DIGI-KEY -PCC103BNCT-ND
"U12, U13, U16" "C14, C109, C110, C112-C149, C151, C154, C161, C173, C175, C177-C179, C197, C198, C211, C215-C217, C223"
"CAPACITOR-0.1UF, 50V, X7R_805"
NEWARK 96F8740
"C2-C5, C7-C10, C107, C108, C111, C150, C152, C153, C155-C157, C159, C164-C171, C174, C176, C180-C188, C190, C192, C193, C196, C201-C207, C209, C210, C212-C214, C218-C222, C224, C226-C228"
"CAPACITOR-0.22UF, 50V, X7R_1210"
12105C224KATPS
"C1, C172, C208"
"CAPACITOR-10UF, 16V, TANT TEH"
PCT3106CT-ND
"C11, C158, C160, C162, C163, C189, C191, C194, C195, C199, C200"
"CAPACITOR-4.7UF, 16V, TANT TEH"
DIGI-KEY PCT3475CTND DIGI-KEY PCT1476CTND DIGI-KEY U7472CT-ND
C225
"CAPACITOR-47UF, 6.3V, TANT TEH"
"C12, C13"
CHIP_RES_NETWORK_8_S MD-4.7K
HEADER3_100MIL-BASE HEADER6_100MIL-BASE HFCT5905 HP_LOGIC_ADAPTOR-BASE "INDUCTOR-FB, FAIR RITE" "LED-RED, RIGHT
PZC36SAAN PZC36SAAN HFCT-5905E DIGI-KEY S2012-36-ND FAIR RITE 2743019447 DIGI-KEY L20361-ND
"U2, L2-L9 D1-D4
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
Part Name
ANGLE"
Part Number
Reference Descriptor
LT1121CST_SOT-3.3V NM93CS46_DIP8-BASE "OSC_CMOS_8PIN_DUAL-H CMOS, 19.44A"
LT1121CST-3.3 NM93CS46EN MB3020HH19.440MH MB3100HH50.000MH DIGIKEY CKN4002-ND PCI9050-1
"OSC_CMOS_8PIN_DUAL-H CMOS, 50.00A"
PBNO_RIGHT_ANGLE-BASE PCI9050_PQFP-BASE "RESISTOR-1.0K, 805" "RESISTOR-100, 805" "RESISTOR-10K, 805" "RESISTOR-150, 805" "RESISTOR-158, 805" "RESISTOR-180, 805" "RESISTOR-2.2, 805" "RESISTOR-220, 805" "RESISTOR-330, 805" "RESISTOR-4.7, 805" "RESISTOR-4.7K, 805"
"R39, R64" "R5, R11, R12" "R40, R41, R43-R45" "R56-R61, R74-R77, R81, R82" "R1-R4, R7-R10" R18-R21 "R47, R52, R67, R69" "R46, R51, R53, R68" "R16, R42, R62, R63, R65, R79, R80, R84, R85"
"RESISTOR-47, 805" "RESISTOR-49.9, 805" RES_ARRAY_4_SMD-10 RES_ARRAY_4_SMD-4.7K
"R13, R15, R37, R38, R66, R78" "R48, R49, R54, R55, R70-R73" "RN1-RN5, RN8-RN13, RN73, RN90" "RN15, RN72, RN78-RN89, RN91, RN92"
RES_ARRAY_4_SMD-47
"RN7, RN14, RN16, RN25-RN30, RN52RN62, RN74-RN77, RN93, RN94"
SUNIATLAS_SBGA-BASE SUNITETRA_SBGA-BASE XC95216PQ160-10NS ZPACK5X22FH_ASCPCI_2
PM7324 PM5351 XC95216-10PQ160C 352068-1
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
VHDL CODE
library ieee; ieee.std_logic_1164.all; ieee.std_logic_unsigned.all; work.all;
entity Atlas_Tetra port inout std_logic_vector(11 downto 0);-PCI Address inout std_logic_vector(31 downto 0);-PCI Data wrb: std_logic; -PCI Write Enable rdb: std_logic; -PCI Read Enable reset_switch: std_logic; -Reset Switch Input cpld_clk: std_logic; -33MHz clock phy_sel_clk: std_logic; -50MHz clock csb_cpld: std_logic; -CPLD Chip Select osoc: std_logic; -Ingress Output Start Cell atlas_intb,tetra_intb: std_logic; -PMC device interrupts phy_sel_dat: std_logic_vector downto 0);-PHY select bits oca: std_logic; -Ingress Output Cell Available pci_resetb: std_logic; -PCI Interface Reset jtag_clk: std_logic; -JTAG Clock resetb: std_logic; -Reset output iaddr: std_logic_vector(1 downto 0);-Egress Input address iwrenb: std_logic; -Egress Input Write Enable ordenb: std_logic; -Ingress Output Read Enable isoc: std_logic; -Egress Input Start Cell HP_out: std_logic_vector(9 downto pci_intb: std_logic); -PCI Interface interrupt Atlas_Tetra; architecture vhdl Atlas_Tetra signal pci_data: begin -PROCESS GLOBAL_RESET: -This process will reset ATLAS,TETRA,and Bridge global_reset: begin phy_sel_clk'event phy_sel_clk='1' then reset_switch then resetb<='0'; pci_resetb<='0'; else resetb<='1'; pci_resetb<='1'; std_logic_vector(31 downto
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
process global_reset; -PROCESS RW_DATA: -This process will assign LSB's from data -IADDR(1.0) lines rw_data: process(cpld_clk,pci_data(31 downto 0),wrb,csb_cpld) begin cpld_clk='1' cpld_clk'event then csb_cpld='0' then wrb='0' then pci_data(31 downto 0)<=md(31 downto iaddr(1 downto 0)<=md(1 downto else md(31 downto 0)<=(others=>'Z'); process rw_data; -IWRENB ORDENB switched with pci_intb<='Z'; jtag_clk<=cpld_clk; HP_out(9)<= phy_sel_clk; ordenb<=oca; iwrenb<=oca; HP_out(7)<= oca; -ISOC switched with OSOC isoc<=osoc; HP_out(8)<= osoc; ma<=(others=>'Z');
vhdl;
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
EEPROM CONTENTS following table presents contents EEPROM used device initialization. Values little endian format.
Table EEPROM Contents EEPROM Offset (Hex) Value (Hex) 9050 10B5 0660 0000 7324 11F8 FFFF 00FF 0FFF C000 0FFF F000 0FFF FC00 0000 0000 0FFF 0000 0000 0001 0000 4001 Register Device Vendor Class Code ClassCode Subsystem Subsystem Vendor Latency Grant (not loadable) Interrupt Address Space Range Address Space Range Address Space Range Address Space Range Address Space Range Address Space Range Address Space Range Address Space Range Expansion Range Expansion Range Address Space Remap Address Space Remap Address Space Remap Address Space Remap
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
EEPROM Offset (Hex) Value (Hex) 0001 0001 0000 0000 0000 0000 5481 4100 2081 C0C0 0090 A840 0000 0000 0000 0000 0000 2001 0000 4801 0001 0005 0000 0000 0000 0000 0002 44D2
Register Address Space Remap Address Space Remap Address Space Remap Address Space Remap Expansion Remap Expansion Remap Space Descriptor Space Descriptor Space Descriptor Space Descriptor Space Descriptor Space Descriptor Space Descriptor Space Descriptor Expansion Descriptor Expansion Descriptor Register Register Register Register Register Register Register Register Interrupt Control/Status Interrupt Control/Status EEPROM Misc. Control EEPROM Misc. Control
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
EEPROM Offset (Hex) Value (Hex) FFFF
Register Unused
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
NOTES
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED REFERENCE DESIGN PMC-1991709 ISSUE
PM5351 S/UNI-155-TETRA
S/UNI TETRA WITH S/UNI ATLAS REFERENCE DESIGN
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, Canada Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com Tel: (604) 415-4533 Fax: (604) 415-6206 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Site:
None information contained this document constitutes express implied warranty PMC-Sierra, Inc. sufficiency, fitness suitability particular purpose such information fitness, suitability particular purpose, merchantability, performance, compatibility with other parts systems, products PMC-Sierra, Inc., portion thereof, referred this document. PMC-Sierra, Inc. expressly disclaims representations warranties kind regarding contents information, including, limited express implied warranties accuracy, completeness, merchantability, fitness particular use, non-infringement. event will PMC-Sierra, Inc. liable direct, indirect, special, incidental consequential damages, including, limited lost profits, lost business lost data resulting from reliance upon information, whether PMC-Sierra, Inc. been advised possibility such damage. 2001 PMC-Sierra, Inc. PMC-1991709 (R1) PMC-1971240 (R7) Issue date: September 2001
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