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GS88118/32/36AD
Supplemental Datasheet Information
This supplemental information applies GS88118/36AT datasheet, which will find attached this document. This supplement includes package offering (the 165-bump BGA-Package well additional organization (x32, which only offered this part).
GS88118/32/36AD
Supplemental Datasheet Information
Bump BGA-x18 Commom I/O-Top View (Package
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ ADSC ADSP VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
Bump BGA-13mm Body-1.0 Bump Pitch
GS88118/32/36AD
Supplemental Datasheet Information
Bump BGA-x32 Common I/O-Top View (Package
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ ADSC ADSP VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
Bump BGA-13mm Body-1.0 Bump Pitch
GS88118/32/36AD
Supplemental Datasheet Information
Bump BGA-x36 Common I/O-Top View (Package
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ ADSC ADSP VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
Bump BGA-13mm Body-1.0 Bump Pitch
GS88118/32/36AD
Supplemental Datasheet Information
GS88118/32/36AD 165-Bump Description Symbol
A17, DQA1-DQA9 DQB1-DQB9 DQC1-DQC9 DQD1-DQD9 ADSC, ADSP VDDQ
Type
Description
Address field LSBs Address Counter Preset Inputs Address Inputs Address Input Data Input Output pins Byte Write Enable DQA, DQB, DQC, I/Os; active Connect Clock Input Signal; active high Byte Write-Writes enabled bytes; active Global Write Enable-Writes bytes; active Chip Enable; active Chip Enable; active Chip Enable; active high Output Enable; active Burst address counter advance enable; active Address Strobe (Processor, Cache Controller); active Sleep mode control; active high Flow Through Pipeline mode; active Linear Burst Order mode; active Scan Test Mode Select Scan Test Data Scan Test Data Scan Test Clock Must Connect Core power supply Core Ground Output driver power supply
GS88118/32/36AD
Supplemental Datasheet Information
Package Dimensions-165-Bump FPBGA (Package Variation
BOTTOM
15±0.0
0.45±0.05 0.25
0.15
0.20(4
13±0.0
(0.26
0.25~0.4 1.20
SEATING
GS88118/32/36AD
Supplemental Datasheet Information
Ordering Information
512K 512K 512K 512K 512K 512K 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 512K 512K 512K 512K 512K 512K 256K
Part Number1
GS88118AD-250 GS88118AD-225 GS88118AD-200 GS88118AD-166 GS88118AD-150 GS88118AD-133 GS88132AD-250 GS88132AD-225 GS88132AD-200 GS88132AD-166 GS88132AD-150 GS88132AD-133 GS88136AD-250 GS88136AD-225 GS88136AD-200 GS88136AD-166 GS88136AD-150 GS88136AD-133 GS88118AD-250I GS88118AD-225I GS88118AD-200I GS88118AD-166I GS88118AD-150I GS88118AD-133I GS88132AD-250I
Type
Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through
Package
Speed2 (MHz/ns)
250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5
Status
256K GS88132AD-225I Pipeline/Flow Through 225/6 Notes: Customers requiring delivery Tape Reel should character part number. Example: GS88136AD-100IT. speed column indicates cycle frequency (MHz) device Pipeline mode latency (ns) Flow Through mode. Each device Pipeline/Flow Through mode-selectable user. Commercial Temperature Range. Industrial Temperature Range. offers other versions this type device many different configurations with variety different features, only some which covered this data sheet. Technology site (www.gsitechnology.com) complete listing current offerings
GS88118/32/36AD
Supplemental Datasheet Information
Ordering Information
256K 256K 256K 256K 256K 256K 256K 256K 256K
Part Number1
GS88132AD-200I GS88132AD-166I GS88132AD-150I GS88132AD-133I GS88136AD-250I GS88136AD-225I GS88136AD-200I GS88136AD-166I GS88136AD-150I
Type
Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through
Package
Speed2 (MHz/ns)
200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5
Status
256K GS88136AD-133I Pipeline/Flow Through 133/8.5 Notes: Customers requiring delivery Tape Reel should character part number. Example: GS88136AD-100IT. speed column indicates cycle frequency (MHz) device Pipeline mode latency (ns) Flow Through mode. Each device Pipeline/Flow Through mode-selectable user. Commercial Temperature Range. Industrial Temperature Range. offers other versions this type device many different configurations with variety different features, only some which covered this data sheet. Technology site (www.gsitechnology.com) complete listing current offerings
100-Pin TQFP Commercial Temp Industrial Temp Features
IEEE 1149.1 JTAG-compatible Boundary Scan +10%/-10% core power supply supply Linear Interleaved Burst mode Internal input resistors mode pins allow floating mode pins Byte Write (BW) and/or Global Write (GW) operation Internal self-timed write cycle Automatic power-down portable applications JEDEC-standard package
512K 256K Synchronous Burst SRAMs
MHz-133
Flow Through/Pipeline Reads function Data Output register controlled user mode (Pin 14). Holding mode places Flow Through mode, causing output data bypass Data Output Register. Holding high places Pipeline mode, activating risingedge-triggered Data Output Register. Pipelined Reads GS88118/36AT (Single Cycle Deselect) pipelined synchronous SRAM. (Dual Cycle Deselect) versions also available. SRAMs pipeline deselect commands stage less than read commands. RAMs begin turning their outputs immediately after deselect command been captured input registers. Byte Write Global Write Byte write operation performed using Byte Write enable (BW) input combined with more individual byte write signals (Bx). addition, Global Write (GW) available writing bytes time, regardless Byte Write control inputs. Sleep Mode power (Sleep mode) attained through assertion (High) signal, stopping clock (CK). Memory data retained during Sleep mode. Core Interface Voltages GS88118/36AT operates power supply. input compatible. Separate output power (VDDQ) pins used decouple output noise from internal circuits compatible.
Functional Description
Applications GS88118/36AT 9,437,184-bit high performance synchronous SRAM with 2-bit burst address counter. Although type originally developed Level Cache applications supporting high performance CPUs, device finds application synchronous SRAM applications, ranging from main store networking chip support. Controls Addresses, data I/Os, chip enable (E1, E2), address burst control inputs (ADSP, ADSC, ADV) write control inputs (Bx, synchronous controlled positive-edge-triggered clock input (CK). Output enable power down control (ZZ) asynchronous inputs. Burst cycles initiated with either ADSP ADSC inputs. Burst mode, subsequent burst addresses generated internally controlled ADV. burst address counter configured count either linear interleave order with Linear Burst Order (LBO) input. Burst function need used. addresses loaded every cycle with degradation chip performance.
Parameter Synopsis
Pipeline 3-1-1-1 tCycle Curr (x18) Curr (x36) tCycle -250 -225 -200 -166 -150 -133 Unit
Flow Through 2-1-1-1
Curr (x18) Curr (x36)
Rev: 1.03 11/2004
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2001, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS88118A 100-Pin TQFP Pinout (Package
VDDQ VDDQ DQB6 VDDQ DQPB VDDQ
512K View
ADSC ADSP
VDDQ DQPA VDDQ VDDQ VDDQ
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2001, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS88136A 100-Pin TQFP Pinout (Package
DQPC VDDQ VDDQ VDDQ VDDQ DQPD
256K View
ADSC ADSP
DQPB VDDQ VDDQ VDDQ VDDQ DQPA
Rev: 1.03 11/2004 3/29
2001, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
TQFP Description Symbol
ADSP, ADSC VDDQ
Type
Description
Address field LSBs Address Counter preset Inputs Address Inputs
Data Input Output pins
Connect Byte Write-Writes enabled bytes; active Byte Write Enable DQA, Data I/Os; active Clock Input Signal; active high Global Write Enable-Writes bytes; active Chip Enable; active Chip Enable; active high Output Enable; active Burst address counter advance enable; active Address Strobe (Processor, Cache Controller); active Sleep Mode control; active high Scan Test Mode Select Scan Test Data Scan Test Data Scan Test Clock Flow Through Pipeline mode; active Linear Burst Order mode; active Core power supply Core Ground Output driver power supply
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Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS88118/36A Block Diagram
Register
A0-An
Counter Load
ADSC ADSP
Register
Memory Array
Register
Register
Register
Register
Register
Register
Register
Parity Encode Parity Compare
Register
Power Down Control
DQx1-DQx9
Note: Only version shown simplicity.
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2001, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Register
Mode Functions Mode Name
Burst Order Control Output Register Control Power Down Control
Name
State
Function
Linear Burst Interleaved Burst Flow Through Pipeline Active Standby,
Note: There pull-up devices pins pull-down device pin, those input pins unconnected chip will operate default states specified above tables. Burst Counter Sequences
Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
address address address address
Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
address address address address
Note: burst counter wraps initial state clock.
Note: burst counter wraps initial state clock.
1999.05.18
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Byte Write Truth Table Function
Read Read Write byte Write byte Write byte Write byte Write bytes
Notes
Write bytes Notes: byte outputs active read cycles regardless state Byte Write Enable inputs. Byte Write Enable inputs and/or used combination with write single multiple bytes. byte I/Os remain High-Z during write operations regardless state Byte Write Enable inputs. Bytes only available version.
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Synchronous Truth Table Operation
Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst
Address Used
None External External External Next Next Next Next Current Current Current Current
State Diagram Key5
ADSP
ADSC
High-Z
Notes: Don't Care, High, (True) (False) defined Byte Write Truth Table preceding. asynchronous input. driven high time disable active output drivers. only enable active drivers (shown Truth Table above). input combinations shown above tested supported. Input combinations shown gray boxes need used accomplish basic synchronous synchronous burst operations avoided simplicity. Tying ADSP high ADSC allows simple non-burst synchronous operations. BOLD items above. Tying ADSP high while using ADSC load addresses allows simple burst operations. ITALIC items above.
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Simplified State Diagram
Deselect Simple Synchronous Operation
First Write
First Read
Simple Burst Synchronous Operation
Burst Write
Burst Read
Notes: diagram shows only supported (tested) synchronous state transitions. diagram presumes tied low. upper portion diagram assumes active only Enable (E1) Write (BA, control inputs, that ADSP tied high ADSC tied low. upper lower portions diagram together assume active only Enable, Write, ADSC control inputs, assumes ADSP tied high tied low.
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Simplified State Diagram with
Deselect
First Write
First Read
Burst Write
Burst Read
Notes: diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon "Dummy Reads" (Read Cycles with High) used make transition from read cycles write cycles without passing through deselect cycle. Dummy read cycles increment address counter just like normal read cycles. Transitions shown gray tone assume been pulsed high long enough turn RAM's drivers incoming data meet Data Input Time.
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Absolute Maximum Ratings
(All voltages reference VSS)
Symbol
VDDQ VI/O IOUT TSTG TBIAS
Description
Voltage Pins Voltage VDDQ Pins Voltage Pins Voltage Other Input Pins Input Current Output Current Package Power Dissipation Storage Temperature Temperature Under Bias
Value
-0.5 -0.5 -0.5 VDDQ +0.5 max.) -0.5 +0.5 max.) +/-20 +/-20
Unit
Note: Permanent damage device occur Absolute Maximum Ratings exceeded. Operation should restricted Recommended Operating Conditions. Exposure conditions exceeding Absolute Maximum Ratings, extended period time, affect reliability this component.
Power Supply Voltage Ranges Parameter
Supply Voltage Supply Voltage VDDQ Supply Voltage VDDQ Supply Voltage
Symbol
VDD3 VDD2 VDDQ3 VDDQ2
Min.
Typ.
Max.
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC.
Rev: 1.03 11/2004
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Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
VDDQ3 Range Logic Levels Parameter
Input High Voltage Input Voltage VDDQ Input High Voltage VDDQ Input Voltage
Symbol
VIHQ VILQ
Min.
-0.3 -0.3
Typ.
Max.
VDDQ
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC. VIHQ (max) voltage VDDQ pins plus
VDDQ2 Range Logic Levels Parameter
Input High Voltage Input Voltage VDDQ Input High Voltage VDDQ Input Voltage
Symbol
VIHQ VILQ
Min.
0.6*VDD -0.3 0.6*VDD -0.3
Typ.
Max.
0.3*VDD VDDQ 0.3*VDD
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC. VIHQ (max) voltage VDDQ pins plus
Recommended Operating Temperatures Parameter
Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
Min.
Typ.
Max.
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC.
Rev: 1.03 11/2004
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Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Undershoot Measurement Timing
Overshoot Measurement Timing
Capacitance
25oC, MHZ,
Parameter
Input Capacitance Input/Output Capacitance Note: These parameters sample tested.
Symbol
CI/O
Test conditions
VOUT
Typ.
Max.
Unit
Test Conditions Parameter
Input high level Input level Input slew rate Input reference level Output reference level Output load
Conditions
V/ns VDD/2 VDDQ/2 Fig.
Notes: Include scope capacitance. Test conditions specified with output loading shown Fig. unless otherwise noted. Device deselected defined Truth Table.
Output Load VDDQ/2
Distributed Test Capacitance
30pF*
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Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Electrical Characteristics Parameter
Input Leakage Current (except mode pins) Input Current Input Current Output Leakage Current Output High Voltage Output High Voltage Output Voltage
Symbol
IIN1 IIN2 VOH2 VOH3
Test Conditions
Output Disable, VOUT VDDQ 2.375 VDDQ 3.135
-100
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Operating Currents
-250 Mode Symbol 70°C 85°C Unit
-225 70°C 85°C 85°C 85°C 85°C 85°C 70°C 70°C 70°C 70°C
-200
-166
-150
-133
Rev: 1.03 11/2004 Pipeline (x36) Flow Through Pipeline (x18) Flow Through Pipeline Flow Through Pipeline Flow Through IDDQ IDDQ IDDQ IDDQ
Parameter
Test Conditions
Operating Current
Device Selected; other inputs Output open
15/29
Standby Current
Deselect Current
Device Deselected; other inputs
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Notes: IDDQ apply combination VDD3, VDD2, VDDQ3, VDDQ2 operation. parameters listed worst case scenario.
2001, Technology
Electrical Characteristics
Parameter Clock Cycle Time Clock Output Valid Pipeline Clock Output Invalid Clock Output Low-Z Setup time Hold time Clock Cycle Time Clock Output Valid Flow Through Clock Output Invalid Clock Output Low-Z Setup time Hold time Clock HIGH Time Clock Time Clock Output High-Z Output Valid output Low-Z output High-Z setup time hold time recovery Symbol tKQX tLZ1 tKQX tLZ1 tHZ1 tOLZ1 tOHZ1 tZZS2 tZZH2 tZZR -250 -225 -200 -166 -150 -133 Unit
Notes: These parameters sampled 100% tested asynchronous signal. However, order recognized given clock cycle, must meet specified setup hold times specified above.
Rev: 1.03 11/2004
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2001, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Pipeline Mode Timing
Begin
Read
Cont
Cont
Deselect Write Single Write
Read
Read Read Read Cont Burst Read
Deselect
Single Read
ADSP ADSC A0-An
ADSC initiated read
Ba-Bd DQa-DQd tOHZ
Q(A) D(B) only sampled with ADSP ADSC masks ADSP Deselected with
Q(C) Q(C+1) Q(C+2)
tKQX
Q(C+3)
Rev: 1.03 11/2004
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2001, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Flow Through Mode Timing
Begin
Read
Cont
Cont
Write
Read
Read Read Read Read
Cont
Deselect
ADSP ADSC A0-An
Fixed High
ADSC initiated read
Ba-Bd DQa-DQd
Q(A) Deselected with
only sampled with ADSC
tOHZ
D(B)
Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C)
tKQX
Rev: 1.03 11/2004
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2001, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Sleep Mode During normal operation, must pulled low, either user internal pull down resistor. When pulled high, SRAM will enter Power Sleep mode after cycles. this time, internal state SRAM preserved. When returns low, SRAM operates normally after recovery time. Sleep mode current, power-down mode which device deselected current reduced ISB2. duration Sleep mode dictated length time High state. After entering Sleep mode, inputs except become disabled outputs High-Z asynchronous, active high input that causes device enter Sleep mode. When driven high, ISB2 guaranteed after time tZZI met. Because asynchronous input, pending operations operations progress properly completed asserted. Therefore, Sleep mode must initiated until valid pending operations completed. Similarly, when exiting Sleep mode during tZZR, only Deselect Read commands applied while SRAM recovering from Sleep mode.
Sleep Mode Timing Diagram
Setup Hold ADSP ADSC tZZR tZZS tZZH
Application Tips
Single Dual Cycle Deselect devices (like this one) force "dummy read cycles" (read cycles that launched normally that ended with output drivers inactive) fully synchronous environment. Dummy read cycles waste performance their usually assures there will contention transitions from reads writes between banks RAMs. SRAMs waste bandwidth dummy cycles logically simpler manage multiple bank application (wait states need inserted bank address boundary crossings) greater care must exercised avoid excessive contention.
JTAG Port Operation
Overview JTAG Port this operates manner that compliant with IEEE Standard 1149.1-1990, serial boundary scan interface standard (commonly referred JTAG). JTAG Port input interface levels scale with VDD. JTAG output drivers powered VDDQ. Disabling JTAG Port possible this device without utilizing JTAG port. port reset power-up will remain inactive unless clocked. TCK, TDI, designed with internal pull-up circuits.To assure normal operation with JTAG Port unused, TCK, TDI, left floating tied either VSS. should left unconnected.
Rev: 1.03 11/2004
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2001, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
JTAG Descriptions
Name
Test Clock Test Mode Select
Description
Clocks events. inputs captured rising edge outputs propagate from falling edge TCK. input sampled rising edge TCK. This command input controller state machine. undriven input will produce same result logic input level. input sampled rising edge TCK. This input side serial registers placed between TDO. register placed between determined state Controller state machine instruction that currently loaded Instruction Register (refer Controller State Diagram). undriven will produce same result logic input level.
Test Data
Test Data
Output that active depending state state machine. Output changes response falling edge TCK. This output side serial registers placed between TDO.
Note: This device does have TRST (TAP Reset) pin. TRST optional IEEE 1149.1. Test-Logic-Reset state entered while held high five rising edges TCK. Controller also reset automaticly power-up.
JTAG Port Registers
Overview various JTAG registers, refered Test Access Port orTAP Registers, selected (one time) sequences applied strobed. Each Registers serial shift register that captures serial input data rising edge pushes serial data next falling edge TCK. When register selected, placed between pins. Instruction Register Instruction Register holds instructions that executed controller when moved into Run, Test/Idle, various data register states. Instructions bits long. Instruction Register loaded when placed between pins. Instruction Register automatically preloaded with IDCODE instruction power-up whenever controller placed Test-Logic-Reset state. Bypass Register Bypass Register single register that placed between TDO. allows serial test data passed through RAM's JTAG Port another device scan chain with little delay possible. Boundary Scan Register Boundary Scan Register collection flip flops that preset logic level found RAM's input pins. flip flops then daisy chained together levels found shifted serially JTAG Port's pin. Boundary Scan Register also includes number place holder flip flops (always logic relationship between device pins bits Boundary Scan Register described Scan Order Table following. Boundary Scan Register, under control Controller, loaded with contents RAMs ring when controller Capture-DR state then placed between pins when controller moved Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD EXTEST instructions used activate Boundary Scan Register.
Rev: 1.03 11/2004
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2001, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
JTAG Block Diagram
Boundary Scan Register
Bypass Register
Instruction Register Code Register
Control Signals Test Access Port (TAP) Controller
Identification (ID) Register Register 32-bit register that loaded with device vendor specific 32-bit code when controller Capture-DR state with IDCODE command loaded Instruction Register. code loaded from 32-bit on-chip ROM. describes various attributes indicated below. register then placed between pins when controller moved into Shift-DR state. register first reach when shifting begins.
Register Contents
Revision Code Technology JEDEC Vendor Code Presence Register
Used
Configuration
Rev: 1.03 11/2004
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Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Controller Instruction
Overview There classes instructions defined Standard 1149.1-1990; standard (Public) instructions, device specific (Private) instructions. Some Public instructions mandatory 1149.1 compliance. Optional Public instructions must implemented prescribed ways. this device used monitor input pads, used load address, data control signals into preload buffers. When controller placed Capture-IR state least significant bits instruction register loaded with When controller moved Shift-IR state Instruction Register placed between TDO. this state desired instruction serially loaded through input (while previous contents shifted TDO). instructions, executes newly loaded instructions only when controller moved Update-IR state. instruction this device listed following table.
JTAG Controller State Diagram
Test Logic Reset
Test Idle
Select
Select
Capture
Capture
Shift
Shift
Exit1
Exit1
Pause
Pause
Exit2
Exit2
Update
Update
Instruction Descriptions BYPASS When BYPASS instruction loaded Instruction Register Bypass Register placed between TDO. This occurs when controller moved Shift-DR state. This allows board level scan path shortened facilitate testing other devices scan path.
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SAMPLE/PRELOAD SAMPLE/PRELOAD Standard 1149.1 mandatory public instruction. When SAMPLE PRELOAD instruction loaded Instruction Register, moving controller into Capture-DR state loads data RAMs input buffers into Boundary Scan Register. Boundary Scan Register locations associated with input pin, loaded with default state identified Boundary Scan Chain table this section datasheet. Because clock independent from Clock (TCK) possible attempt capture ring contents while input buffers transition (i.e. metastable state). Although allowing sample metastable inputs will harm device, repeatable results cannot expected. input signals must stabilized long enough meet TAPs input data capture set-up plus hold time (tTS plus tTH). RAMs clock inputs need paused other operation except capturing ring contents into Boundary Scan Register. Moving controller Shift-DR state then places boundary scan register between pins. EXTEST EXTEST IEEE 1149.1 mandatory public instruction. executed whenever instruction register loaded with logic EXTEST command does block override RAM's input pins; therefore, RAM's internal state still determined input pins. Typically, Boundary Scan Register loaded with desired pattern data with SAMPLE/PRELOAD command. Then EXTEST command used output Boundary Scan Register's contents, parallel, RAM's data output drivers falling edge when controller Update-IR state. Alternately, Boundary Scan Register loaded parallel using EXTEST command. When EXTEST instruction selected, sate RAM's input pins, well default values Scan Register locations associated with pin, transferred parallel into Boundary Scan Register rising edge Capture-DR state, RAM's output pins drive value Boundary Scan Register location with which each output associated. IDCODE IDCODE instruction causes loaded into register when controller Capture-DR mode places register between pins Shift-DR mode. IDCODE instruction default instruction loaded power time controller placed Test-Logic-Reset state. SAMPLE-Z SAMPLE-Z instruction loaded instruction register, outputs forced inactive drive state (highZ) Boundary Scan Register connected between when controller moved Shift-DR state. These instructions Reserved Future Use. this device they replicate BYPASS instruction.
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2001, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
JTAG Instruction Summary Instruction
EXTEST IDCODE SAMPLE-Z SAMPLE/ PRELOAD
Code
Description
Places Boundary Scan Register between TDO. Preloads Register places between TDO. Captures ring contents. Places Boundary Scan Register between TDO. Forces output drivers High-Z. this instruction; Reserved Future Use. Replicates BYPASS instruction. Places Bypass Register between TDO. Captures ring contents. Places Boundary Scan Register between TDO. private instruction. this instruction; Reserved Future Use. Replicates BYPASS instruction. Places Bypass Register between TDO.
Notes
BYPASS Places Bypass Register between TDO. Notes: Instruction codes expressed binary, left, right. Default instruction automatically loaded power-up test-logic-reset state.
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JTAG Port Recommended Operating Conditions Characteristics Parameter
Test Port Input High Voltage Test Port Input Voltage Test Port Input High Voltage Test Port Input Voltage TMS, Input Leakage Current TMS, Input Leakage Current Output Leakage Current Test Port Output High Voltage Test Port Output Voltage Test Port Output CMOS High Test Port Output CMOS
Symbol
VIHJ3 VILJ3 VIHJ2 VILJ2 IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC
Min.
-0.3 VDD2 -0.3 -300 VDDQ
Max.
VDD3 +0.3 VDD2 +0.3 VDD2
Unit Notes
Notes: Input Under/overshoot voltage must VDDn exceed maximum, with pulse width exceed tTKC. VILJ VDDn VILJn Output Disable, VOUT VDDn output driver served VDDQ supply. IOHJ IOLJ IOHJC -100 IOHJC +100
JTAG Port Test Conditions Parameter
Input high level Input level Input slew rate Input reference level Output reference level
Conditions
V/ns VDDQ/2 VDDQ/2
JTAG Port Test Load
VDDQ/2
Distributed Test Capacitance
30pF*
Notes: Include scope capacitance. Test conditions shown unless otherwise noted.
Rev: 1.03 11/2004
25/29
2001, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
JTAG Port Timing Diagram
tTKC tTKQ Parallel SRAM input
tTKH
tTKL
JTAG Port Electrical Characteristics
Parameter Cycle Time Valid High Pulse Width Pulse Width Time Hold Time Symbol tTKC tTKQ tTKH tTKL Unit
Boundary Scan (BSDL Files) information regarding Boundary Scan Chain, obtain BSDL files this part, please contact Applications Engineering Department apps@gsitechnology.com.
Rev: 1.03 11/2004
26/29
2001, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
TQFP Package Drawing (Package Symbol
Description
Standoff Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Length Coplanarity Lead Angle
Min. Nom.
0.05 1.35 0.20 0.09 21.9 19.9 15.9 13.9 0.45 0.10 1.40 0.30 22.0 20.0 16.0 14.0 0.65 0.60 1.00 0.15 1.45 0.40 0.20 22.1 20.1 16.1 14.1 0.75 0.10
Notes: dimensions millimeters (mm). Package width length include mold protrusion.
Rev: 1.03 11/2004
27/29
2001, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Ordering Information Synchronous Burst RAMs
512K 512K 512K 512K 512K 512K 256K 256K 256K 256K 256K 256K 512K 512K 512K 512K 512K 512K 256K 256K 256K 256K 256K 256K
Part Number1
GS88118AT-250 GS88118AT-225 GS88118AT-200 GS88118AT-166 GS88118AT-150 GS88118AT-133 GS88136AT-250 GS88136AT-225 GS88136AT-200 GS88136AT-166 GS88136AT-150 GS88136AT-133 GS88118AT-250I GS88118AT-225I GS88118AT-200I GS88118AT-166I GS88118AT-150I GS88118AT-133I GS88136AT-250I GS88136AT-225I GS88136AT-200I GS88136AT-166I GS88136AT-150I GS88136AT-133I
Type
Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through
Package
TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP
Speed2 (MHz/ns)
250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5
Status
Notes: Customers requiring delivery Tape Reel should character part number. Example: GS88118AT-150IT. speed column indicates cycle frequency (MHz) device Pipeline mode latency (ns) Flow Through mode. Each device Pipeline/Flow Through mode-selectable user. Commercial Temperature Range. Industrial Temperature Range. offers other versions this type device many different configurations with variety different features, only some which covered this data sheet. Technology site (www.gsitechnology.com) complete listing current offerings.
Rev: 1.03 11/2004
28/29
2001, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old; 88118A_r1 Types Changes Format Content Page;Revisions;Reason Creation datasheet Updated Characteristics table Updated power numbers Updated references from Removed ByteSafe references Changed Updated recovery time diagram Added pinout (pin description table Updated Test Conditions table removed Output Load diagram Removed Preliminary banner Removed locations from description table Removed table Updated format Updated timing diagrams Updated mechanical drawings
88118A_r1; 88118A_r1_01
Content
88118A_r1_01; 88118A_r1_02 88118A_r1_02; 88118A_r1_03
Content
Format/Content
Rev: 1.03 11/2004
29/29
2001, Technology
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.

Supplemental Datasheet Information This supplemental information

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