AK4589 2/8-Channel Audio CODEC with AK4589 24bit CODEC AK458

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

AK4589 2/8-Channel Audio CODEC with AK4589 24bit CODEC AK458

Datasheet Thumbnail

Top Searches for this datasheet

[AK4589]
AK4589
2/8-Channel Audio CODEC with
AK4589 24bit CODEC AK4589 102dB 114dB (AC-3) AK4589 192kHz (DIR)(DIT) Non-PCM AK4589 AK4588 *(AC-3) Dolby Laboratories ADC, 24bit 96kHz -S/(N+D): 92dB S/N: 102dB -HPF -I/F: I2S, 24bit -128 192kHz -248 -SCF -S/(N+D): 94dB S/N: 114dB -I/F: (20bit, 24bit), I2S, (128, 0.5dB) (32kHz, 44.1kHz, 48kHz) 256fs, 384fs, 512fs (fs=32kHz 48kHz) 128fs, 192fs, 256fs (fs=64kHz 96kHz) 128fs (fs=120kHz~ 192kHz)
MS0339-J-00
2004/09
[AK4589]
DIR,DIT AES3, IEC60958, S/PDIF, EIAJ CP1201 32kHz 192kHz PLL/X'tal (32kHz, 44.1kHz, 48kHz, 96kHz) Non-PCM DTS-CD (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz) Unlock Parity Error Validity I/F: Non-PCMPc, Q-subcode 64fs/128fs/256fs/512fs TTLI/F (I2C, 4.75 5.25V 5.25V 80pin LQFP(0.5mm pitch) AK4588()
MS0339-J-00
2004/09
[AK4589]
PVSS PVDD X'tal Oscillator
Clock Generator
Input Selector
Clock Recovery
MCKO1
MCKO2
DAIF Decoder Audio LRCK2 BICK2 SDTO2 DAUX2
AVDD AVSS DVDD
DVSS TVDD
CCLK CDTO CDTI
INT0 INT1
AC-3/MPEG Detect
Error STATUS Detect
Q-subcode buffer
B,C,U, VOUT
LOUT1+
DATT
Audio
LOUT1ROUT1+
MCLK LRCK BICK
MCLK
LRCK1 BICK1 DAUX1
ROUT1LOUT2+
DATT
LOUT2ROUT2+
DATT
ROUT2LOUT3+
DATT
Format Converter
LOUT3ROUT3+ ROUT3-
DATT
SDOUT
DATT
SDTO1
LOUT4+ LOUT4ROUT4+
DATT
SDIN1 SDIN2 SDIN3 SDIN4
SDTI1 SDTI2 SDTI3 SDTI4
ROUT4-
DATT
MS0339-J-00
2004/09
[AK4589]
AK4589VQ AKD4589 +70°C 80pin LQFP(0.5mm pitch)
INT0 MCLK DAUX2 CAD1 CAD0 TEST2 PVDD PVSS
MS0339-J-00
CCLK/SCL CDTI/SDA DAUX1 SDTI4 SDTI3 SDTI2 SDTI1 XTL1 XTL0 MASTER DZF2 DZF1 LOUT4LOUT4+ ROUT4ROUT4+ LOUT3LOUT3+
INT1 BOUT TVDD DVDD DVSS TEST3 MCKO2 MCKO1 COUT UOUT VOUT SDTO2 BICK2 LRCK2 SDTO1 BICK1 LRCK1 CDTO
(Top View)
TEST1 AVSS AVDD VREFH VCOM ROUT1+ ROUT1LOUT1+ LOUT1ROUT2+ ROUT2LOUT2+ LOUT2ROUT3+ ROUT3-
2004/09
[AK4589]
AK4588
Functions AK4588 AK4589 S/(N+D) 90dB 94dB 106dB 114dB Output voltage 3.0Vpp ±2.7Vpp AOUT AOUT=0.6xVREFH AOUT=0.54xVREFH Load Resistance Frequency Response 80kHz +0/-0.6 ±1.0 #35, #37, #39,#41,#43,#45,#47,#49 Min=4.5V, Max=5.5V Min=4.75V, Max=5.25V ()AK4589 ADC/DAC (AK4588 DIR/DIT (AK4588
MS0339-J-00
2004/09
ASAHI KASEI Name INT1 BOUT TVDD DVDD DVSS TEST3 MCKO2 MCKO1 COUT UOUT VOUT SDTO2 BICK2 LRCK2 SDTO1 BICK1 LRCK1 CDTO CCLK CDTI DAUX1 SDTI4 SDTI3 SDTI2 SDTI1 XTL1 XTL0 Function Interrupt Block-Start Output Receiver Input during first flames. Output Buffer Power Supply Pin, 2.7V5.25V Digital Power Supply Pin, 4.75V5.25V Digital Ground X'tal Output X'tal Input Test This should connected DVSS. Master Clock Output Master Clock Output C-bit Output Receiver Input U-bit Output Receiver Input V-bit Output Receiver Input Audio Serial Data Output (DIR/DIT part) Audio Serial Data Clock (DIR/DIT part) Channel Clock (DIR/DIT part) Audio Serial Data Output (ADC/DAC part) Audio Serial Data Clock (ADC/DAC part) Input Channel Clock Control Data Output Serial Mode, I2C= "L". Control Data Clock Serial Mode, I2C= Control Data Clock Serial Mode, I2C= Control Data Input Serial Mode, I2C= "L". Control Data Serial Mode, I2C= "H". Chip Select Serial Mode, I2C= "L". This should connected DVSS, I2C= "H". Audio Serial Data Input (ADC/DAC part) DAC4 Audio Serial Data Input DAC3 Audio Serial Data Input DAC2 Audio Serial Data Input DAC1 Audio Serial Data Input X'tal Frequency Select X'tal Frequency Select
[AK4589]
MS0339-J-00
2004/09
[AK4589]
Name MASTER
DZF2
DZF1 LOUT4LOUT4+ ROUT4ROUT4+ LOUT3LOUT3+ ROUT3ROUT3+ LOUT2LOUT2+ ROUT2ROUT2+ LOUT1LOUT1+ ROUT1ROUT1+ VCOM VREFH
Function Power-Down Mode When "L", AK4589 powered-down, digital output pins "L", registers reset. When CAD1/0 pins changed, AK4589 should reset pin. Master Mode Select "H": Master mode, "L": Slave mode Zero Input Detect (Table When input data group follow total 8192 LRCK cycles with input data, this goes "H". when RSTN "0", PWDAN "0", this goes "H". always when "H". Analog Input Overflow Detect This goes analog input overflows. Zero Input Detect (Table When input data group follow total 8192 LRCK cycles with input data, this goes "H". when RSTN "0", PWDAN "0", this goes "H". Output selected setting DZFE when "H". 470pF capacitor should connected DAC4 Negative Analog Output between LOUT4- LOUT4+. DAC4 Positive Analog Output 470pF capacitor should connected DAC4 Negative Analog Output between ROUT4- ROUT4+. DAC4 Positive Analog Output 470pF capacitor should connected DAC3 Negative Analog Output between LOUT3- LOUT3+. DAC3 Positive Analog Output 470pF capacitor should connected DAC3 Negative Analog Output between ROUT3- ROUT3+. DAC3 Positive Analog Output 470pF capacitor should connected DAC2 Negative Analog Output between LOUT2- LOUT2+. DAC2 Positive Analog Output 470pF capacitor should connected DAC2 Negative Analog Output between ROUT2- ROUT2+. DAC2 Positive Analog Output 470pF capacitor should connected DAC1 Negative Analog Output between LOUT1- LOUT1+. DAC1 Positive Analog Output 470pF capacitor should connected DAC1 Negative Analog Output between ROUT1- ROUT1+. DAC1 Positive Analog Output Analog Input Analog Input Common Voltage Output 2.2µF capacitor should connected AVSS externally. Positive Voltage Reference Input Pin, AVDD
MS0339-J-00
2004/09
[AK4589]
Function Analog Power Supply Pin, 4.75V5.25V Analog Ground Pin, Receiver Channel (Internal biased pin. Internally biased PVDD/2) Connect internal bonding. This should connected PVSS. Receiver Channel (Internal biased pin. Internally biased PVDD/2) Test TEST1 This should connected PVSS. Receiver Channel (Internal biased pin. Internally biased PVDD/2) Connect internal bonding. This should connected PVSS. Receiver Channel (Internal biased pin. Internally biased PVDD/2) PVSS Ground External Resistor +/-1% resistor should connected PVSS externally. PVDD Power supply Pin, 4.75V5.25V Receiver Channel (Internal biased pin. Internally biased PVDD/2) Test TEST2 This should connected PVSS. Receiver Channel (Internal biased pin. Internally biased PVDD/2) Chip Address (ADC/DAC part) CAD0 Receiver Channel (Internal biased pin. Internally biased PVDD/2) Chip Address (ADC/DAC part) CAD1 Receiver Channel (Internal biased pin. Internally biased PVDD/2) Control Mode Select Pin. "L": 4-wire Serial, "H": DAUX2 Auxiliary Audio Data Input (DIR/DIT part) V-bit Input Transmitter Output Master Clock Input MCLK Transmit Channel (Through Data) Output Transmit Channel Output1 When "0", Through Data. When "1", DAUX2 Data. INT0 Interrupt Notes: (RX0-7, LIN, RIN)
PVDD 20k(typ) 20k(typ) PVSS VCOM
Name AVDD AVSS
Internal biased Circuit
MS0339-J-00
2004/09
[AK4589]
Classification Analog Digital Name RX0-7, LOUT1-4, ROUT1-4, LIN, INT0-1, BOUT, XTO, MCKO1-2, COUT, UOUT, VOUT, SDTO1-2, CDTO, DZF1-2, TX1-0 CSN, DAUX1-2, SDTI1-4, XTL0-1 TEST1-3 Setting These pins should open. These pins should open. These pins should connected DVSS. These pins should connected PVSS.
MS0339-J-00
2004/09
[AK4589]
(AVSS, DVSS, PVSS=0V; Note Parameter Power Supplies Analog Digital Output buffer |AVSS-DVSS| (Note |AVSS-PVSS| (Note Input Current (any pins except supplies) Analog Input Voltage (LIN, pins) Digital Input Voltage Except LRCK1-2, BICK1-2, RX0-7, CAD0-1, TEST1-2 pins LRCK1-2, BICK1-2 pins RX0-7, CAD0-1, TEST1-2 pins Ambient Temperature (power applied) Storage Temperature Symbol AVDD DVDD PVDD TVDD GND1 GND2 VINA VIND1 VIND2 VIND3 Tstg -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 AVDD+0.3 DVDD+0.3 TVDD+0.3 PVDD+0.3 Units
Notes: AVSS, DVSS, PVSS
(AVSS, DVSS, PVSS=0V; Note Parameter Power Supplies Analog (Note Digital Output buffer Symbol AVDD DVDD PVDD TVDD 4.75 4.75 4.75 5.25 AVDD AVDD DVDD Units
Notes: AVDD, DVDD, PVDD, TVDDAVDD, DVDD, PVDD 0.5V
MS0339-J-00
2004/09
[AK4589]
(Ta=25°C; AVDD, DVDD, PVDD, TVDD=5V; AVSS, DVSS=0V; VREFH=AVDD; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz20kHz fs=48kHz, 20Hz~40kHz fs=96kHz; 20Hz~40kHz fs=192kHz, unless otherwise specified) Parameter Units Analog Input Characteristics Resolution Bits S/(N+D) (-0.5dBFS) fs=48kHz fs=96kHz (-60dBFS) fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weighted (Note fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weighted Interchannel Isolation Accuracy Interchannel Gain Mismatch Gain Drift ppm/°C AIN=0.62xVREFH 2.90 3.10 3.30 Input Voltage Input Resistance fs=48kHz fs=96kHz Power Supply Rejection (Note Analog Output Characteristics Resolution Bits S/(N+D) fs=48kHz fs=96kHz fs=192kHz (-60dBFS) fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weighted fs=192kHz fs=192kHz, A-weighted (Note fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weighted fs=192kHz fs=192kHz, A-weighted Interchannel Isolation Accuracy Interchannel Gain Mismatch Gain Drift ppm/°C Output Voltage AOUT=0.54xVREFH ±2.5 ±2.7 ±2.9 Load Resistance Load) (Note Power Supply Rejection (Note Power Supplies Power Supply Current Normal Operation (PDN "H") (Note AVDD fs=48kHz,fs=96kHz fs=192kHz PVDD DVDD+TVDD fs=48kHz (Note fs=96kHz fs=192kHz Power-down mode (PDN "L") (Note
MS0339-J-00
2004/09
[AK4589]
Notes: CCIR-ARM96dB(@fs=48kHz) VREFH+5.0VAVDD, DVDD, PVDD, TVDD1kHz, 50mVpp CCIR-ARM102dB (typ. @fs=48kHz) CL=20pF, X'tal=24.576MHz, CM1-0="10", CM1-0="10", OCKS1-0="10"@48kHz,"00"@96kHz, "11"@192kHz. TVDD=13mA(typ). DVSS TEST3= TEST3=
(Ta=25°C; AVDD, DVDD, PVDD=4.755.25V; TVDD=2.75.25V; fs=48kHz) Parameter Symbol Digital Filter (Decimation LPF): Passband (Note ±0.1dB -0.2dB -3.0dB Stopband 28.0 Passband Ripple Stopband Attenuation Group Delay (Note Group Delay Distortion Digital Filter (HPF): Frequency Response (Note -3dB -0.1dB Digital Filter: Passband (Note -0.1dB -6.0dB Stopband 26.2 Passband Ripple Stopband Attenuation Group Delay (Note Digital Filter Analog Filter: Frequency Response: 20.0kHz 40.0kHz (Note 80.0kHz (Note
18.9 ±0.04
Units 1/fs
20.0 23.0
21.8 ±0.02 19.2 ±0.2 ±0.3 +0/-0.6
24.0
1/fs
Notes: -0.1dB 21.8kHz 0.454 fs(DAC) 20/24 40.0kHz@fs=96kHz 80.0kHz@fs=192kHz.
MS0339-J-00
2004/09
[AK4589]
(Ta=25°C; AVDD, DVDD, PVDD=4.755.25V; TVDD=2.75.25V) Parameter Symbol High-Level Input Voltage (Except pin) 70%DVDD (XTI pin) Low-Level Input Voltage (Except pin) (XTI pin) Input Voltage Coupling (XTI pin) (Note15) 40%DVDD High-Level Output Voltage TVDD-0.4 (Except TX0-1, pins: Iout=-400µA) DVDD-0.4 (TX0-1 pin: Iout=-400µA) AVDD-0.4 (DZF pin: Iout=-400µA) Low-Level Output Voltage (Iout=400µA) Input Leakage Current Note: (0.1µF) S/PDIF (Ta=25°C; AVDD, DVDD, PVDD=4.75~5.25V;TVDD=2.7~5.25V) Parameter Symbol Input Resistance Input Voltage (Internally biased PVDD/2) Input Hysteresis Input Sample Frequency
PVDD 20k(typ) 20k(typ) PVSS VCOM
30%DVDD
Units
Units mVpp
Internal biased Circuit
MS0339-J-00
2004/09
[AK4589]
(ADC/DAC) (Ta=25°C; AVDD, DVDD, PVDD=4.755.25V; TVDD=2.75.25V; CL=20pF) Parameter Symbol Master Clock Timing Master Clock 256fsn, 128fsd: fCLK 8.192 Pulse Width tCLKL Pulse Width High tCLKH 384fsn, 192fsd: fCLK 12.288 Pulse Width tCLKL Pulse Width High tCLKH 512fsn, 256fsd, 128fsq: fCLK 16.384 Pulse Width tCLKL Pulse Width High tCLKH
LRCK1 Timing (Slave Mode) Normal mode Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle mode LRCK1 frequency time time mode LRCK1 frequency time time LRCK1 Timing (Master Mode) Normal mode Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle mode LRCK1 frequency time mode LRCK1 frequency time Power-down Reset Timing Pulse Width SDTO1 valid
Units
12.288
18.432
24.576
Duty tLRH tLRL tLRH tLRL
1/256fs 1/256fs 1/128fs 1/128fs
Duty tLRH tLRH tPDV
1/8fs 1/4fs
1/fs
(Note
(Note (Note (Note
Notes: time pinLRCK1
MS0339-J-00
2004/09
[AK4589]
Parameter Audio Interface Timing (Slave Mode) Normal mode BICK1 Period BICK1 Pulse Width Pulse Width High LRCK1 Edge BICK1 (Note BICK1 LRCK1 Edge (Note LRCK1 SDTO1(MSB) BICK1 SDTO1 SDTI1-4,DAUX1 Hold Time SDTI1-4,DAUX1 Setup Time mode BICK1 Period BICK1 Pulse Width Pulse Width High LRCK1 Edge BICK1 (Note BICK1 LRCK1 Edge (Note BICK1 SDTO1 SDTI1 Hold Time SDTI1 Setup Time mode BICK1 Period BICK1 Pulse Width Pulse Width High LRCK1 Edge BICK1 (Note BICK1 LRCK1 Edge (Note BICK1 SDTO1 SDTI1-2 Hold Time SDTI1-2 Setup Time Audio Interface Timing (Master Mode) Normal mode BICK1 Frequency BICK1 Duty BICK1 LRCK1 Edge BICK1"" SDTO1 SDTI1-4,DAUX1 Hold Time SDTI1-4,DAUX1 Setup Time mode BICK1 Frequency BICK1 Duty (Note BICK1 LRCK1 Edge BICK1 SDTO1 SDTI1 Hold Time SDTI1 Setup Time mode BICK1 Frequency BICK1 Duty (Note BICK1 LRCK1 Edge BICK1 SDTO1 SDTI1-2 Hold Time SDTI1-2 Setup Time
Symbol
Units
tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tSDH tSDS tBCK tBCKL tBCKH tLRB tBLR tBSD tSDH tSDS tBCK tBCKL tBCKH tLRB tBLR tBSD tSDH tSDS
fBCK dBCK tMBLR tBSD tSDH tSDS fBCK dBCK tMBLR tBSD tSDH tSDS fBCK dBCK tMBLR tBSD tSDH tSDS
64fs 256fs 128fs
Notes: LRCK1BICK1 MCLK512fs(384fs,256fsDuty) MCLK256fs(128fsDuty)
MS0339-J-00
2004/09
[AK4589]
1/fCLK tCLKH tCLKL
MCLK
1/fsn, 1/fsd, 1/fsq
LRCK1
tBCK tBCKH tBCKL
BICK1
(Normal mode)
1/fCLK tCLKH tCLKL
MCLK
1/fs LRCK1 tLRH tLRL
tBCK BICK1 tBCKH tBCKL
(TDM mode, mode)
MS0339-J-00
2004/09
[AK4589]
LRCK1 tBLR tLRB
BICK1
tLRS tBSD
SDTO1 tSDS
50%TVDD
tSDH
SDTI
(Normal mode)
tBLR tLRB tBSD
LRCK1
BICK1
SDTO1 tSDS
50%TVDD
tSDH
SDTI
(TDM mode, mode)
MS0339-J-00
2004/09
[AK4589]
LRCK1
50%TVDD
tMBLR BICK1 50%TVDD
tBSD
SDTO1 tDXS tDXH
50%TVDD
DAUX1
(Master Mode)
MS0339-J-00
2004/09
[AK4589]
(DIR/DIT) (Ta=25°C; DVDD, AVDD, PVDD=4.75~5.25V, TVDD=2.7~5.25V; CL=20pF) Parameter Symbol Units Master Clock Timing Crystal Resonator Frequency fXTAL 11.2896 24.576 External Clock Frequency fECLK 11.2896 24.576 Duty dECLK MCKO1 Output Frequency fMCK1 4.096 24.576 Duty dMCK1 MCKO2 Output Frequency fMCK2 2.048 24.576 Duty dMCK2 Clock Recover Frequency (RX0-7) fpll LRCK2 Frequency Duty Cycle dLCK Audio Interface Timing Slave Mode tBCK BICK2 Period tBCKL BICK2 Pulse Width tBCKH Pulse Width High tLRB LRCK2 Edge BICK2 (Note tBLR BICK2 LRCK2 Edge (Note tLRM LRCK2 SDTO2 (MSB) tBSD BICK2 SDTO2 tDXH DAUX2 Hold Time tDXS DAUX2 Setup Time Master Mode BICK2 Frequency fBCK 64fs BICK2 Duty dBCK tMBLR BICK2 LRCK2 tBSD BICK2 SDTO2 tDXH DAUX2 Hold Time tDXS DAUX2 Setup Time Notes: LRCK2BICK2
MS0339-J-00
2004/09
[AK4589]
1/fECLK tECLKH tECLKL dECLK tECLKH fECLK tECLKL fECLK
1/fMCK1
MCKO1 tMCKH1 tMCKL1
50%TVDD dMCK1 tMCKH1 fMCK1 tMCKL1 fMCK1
1/fMCK2
MCKO2 tMCKH2 tMCKL2
50%TVDD dMCK2 tMCKH2 fMCK2 tMCKL2 fMCK2
1/fs LRCK2 tLRH tLRL dLCK tLRH tLRL
tBCK tBLR BICK2 tLRB tBCKL tBCKH tLRM tBSD
LRCK2
SDTO2 tDXS tDXH
50%TVDD
DAUX2
(Slave Mode)
MS0339-J-00
2004/09
[AK4589]
LRCK2
50%TVDD
tMBLR BICK2 50%TVDD
tBSD 50%TVDD
SDTO2 tDXS tDXH
DAUX2
(Master Mode)
MS0339-J-00
2004/09
[AK4589]
(ADC/DAC, DIR/DIT (Ta=25°C; AVDD, DVDD, PVDD=4.755.25V; TVDD=2.75.25V; CL=20pF) Parameter Symbol Control Interface Timing (4-wire serial mode) CCLK Period tCCK CCLK Pulse Width tCCKL Pulse Width High tCCKH CDTI Setup Time tCDS CDTI Hold Time tCDH Time tCSW tCSS CCLK tCSH CCLK tDCD CDTO Delay tCCZ CDTO Hi-Z Control Interface Timing (I2C mode) Clock Frequency fSCL Free Time Between Transmissions tBUF Start Condition Hold Time (prior first clock pulse) tHD:STA Clock Time tLOW Clock High Time tHIGH Setup Time Repeated Start Condition tSU:STA Hold Time from Falling (Note tHD:DAT Setup Time from Rising tSU:DAT Rise Time Both Lines Fall Time Both Lines Setup Time Stop Condition tSU:STO Pulse Width Spike Noise Suppressed Input Filter Capacitive load
0.25 Units
Notes: 300ns (SCL) I2CPhilips Semiconductors
I2CPhilipsI2C PhilipsI2C
MS0339-J-00
2004/09
[AK4589]
(ADC/DACDIR/DIT)
tCSS tCCK tCCKL tCCKH CCLK tCDH tCDS
CDTI
CDTO
Hi-Z
WRITE/READ (4-wire serial mode) ADC/DAC
tCSW tCSH CCLK
CDTI
CDTO
Hi-Z
WRITE (4-wire serial mode)
CCLK
CDTI
tDCD
CDTO
Hi-Z
50%TVDD
READ1 (4-wire serial mode) ADC/DAC MS0339-J-00 2004/09
[AK4589]
tCSW tCSH CCLK
CDTI
tCCZ
CDTO
50%TVDD
READ2 (4-wire serial mode) ADC/DAC
tBUF tLOW tHIGH tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start tSU:STO Stop
ADC/DAC
tPDV
SDTO
50%TVDD
MS0339-J-00
2004/09
[AK4589]
(ADC/DAC)
MCLK, LRCK1, BICK1 MCLKLRCK1 MCLKDFS0, DFS1 (Manual Setting Mode) (Auto Setting Mode) 2Manual Setting Mode (ACKS "0": Default)DFS1-0 bit(Table MCLK(Table 3,4,5)Auto Setting Mode (ACKS "1") MCLK(Table (Table 7)DFS MCLKCKS1-0 bit(Table DFS1-0 bit(Table CKS1-0 DFS1-0 BICK1LRCK1 (PDN "H")(MCLK,BICK1,LRCK1) (PDN "L") (RSTN1 "0")ON(PDN "")MCLK, LRCK1 (MCLK)ON (PDN "")MCLK DFS1 DFS0 Sampling Speed (fs) Normal Speed Mode 32kHz~48kHz Double Speed Mode 64kHz~96kHz Quad Speed Mode 120kHz~192kHz
Default
Table (Manual Setting Mode) CKS1 CKS0 Normal Double 256fs 128fs 384fs 192fs 512fs 256fs 256fs 256fs Table (Master Mode) Quad 128fs 128fs 128fs 128fs
Default
LRCK1 MCLK (MHz) BICK1 (MHz) 256fs 384fs 512fs 64fs 32.0kHz 8.1920 12.2880 16.3840 2.0480 44.1kHz 11.2896 16.9344 22.5792 2.8224 48.0kHz 12.2880 18.4320 24.5760 3.0720 Table (Normal Speed Mode @Manual Setting Mode) LRCK1 MCLK (MHz) BICK1 (MHz) 128fs 192fs 256fs 64fs 88.2kHz 11.2896 16.9344 22.5792 5.6448 96.0kHz 12.2880 18.4320 24.5760 6.1440 Table (Double Speed Mode @Manual Setting Mode) (:Double Speed Mode (DFS1="0", DFS0="1")128fs192fs, ADC)
MS0339-J-00
2004/09
[AK4589]
LRCK1 MCLK (MHz) BICK1 (MHz) 128fs 192fs 256fs 64fs 176.4kHz 22.5792 11.2896 192.0kHz 24.5760 12.2880 Table (Quad Speed Mode @Manual Setting Mode) (:Quad Speed Mode (DFS1="1", DFS1="0")ADC) MCLK Sampling Speed 512fs Normal 256fs Double 128fs Quad Table (Auto Setting Mode) LRCK1 MCLK (MHz) 128fs 256fs 512fs 32.0kHz 16.3840 44.1kHz 22.5792 48.0kHz 24.5760 88.2kHz 22.5792 96.0kHz 24.5760 176.4kHz 22.5792 192.0kHz 24.5760 Table (Auto Setting Mode) Sampling Speed Normal Double Quad
IIR3(32kHz, 44.1kHz, 48kHz)(50/15µs) Double Speed ModeQuad Speed Mode DAC1(SDTI1), DAC2(SDTI2), DAC3(SDTI3), DAC4(SDTI4) Mode Sampling Speed DEM1 DEM0 Normal Speed Normal Speed Normal Speed Normal Speed Table 44.1kHz 48kHz 32kHz
Default
ADCDCHPFHPFfcfs=48kHz1.0Hz
MS0339-J-00
2004/09
[AK4589]
MASTER (MASTER LRCK1 pin, BICK1 (MASTER LRCK1 pin, BICK1 LRCK1 pin, BICK1 Table PWADN bit, PWDAN MASTER LRCK1pin Input Input "00" Input "00" Output Table LRCK1 pin, BICK1 BICK1 Input Input Input Output
TDM1-0 "00"8(Table 10)DIF1-0 MSB2's complimentSDTO1BICK1 SDTI/DAUX1BICK1 Figure 14SDOS "0"SDTO1ADC SDOS "1"DAUX1SDTOSDTI mode2, 7,10,11,14,15,18,19,22,2316 20bitLSB Table 10DefaultMode Mode MASTER TDM1 TDM0 DIF1 LRCK1 BICK1 24bit, 20bit, 48fs 24bit, 24bit, 48fs 24bit, 24bit, 48fs 24bit, 24bit, 48fs 24bit, 20bit, 64fs 24bit, 24bit, 64fs 24bit, 24bit, 64fs 24bit, 24bit, 64fs (Normal mode, shows justified, means justified.) DIF0 SDTO1 SDTI1-4, DAUX1
Table
TDM1-0 "01"TDM modeSDTI1 pinDAC(8ch) SDTI2-4BICK1256fsLRCK1 "L"1/256fs(min)8 (Table 11)DIF1-0 bitMSB2's complimentSDTO1BICK1SDTI1BICK1 TDMSDOS bit, LOOP1-0 "0"TDM mode (96kHz)TDM1-0 "10"SDTI1 pinDAC(4ch; L1,R1,L2,R2)SDTI2 DAC(4ch;L3,R3,L4,R4)
MS0339-J-00
2004/09
[AK4589]
Mode
LRCK1 BICK1 24bit, 20bit, 256fs 24bit, 24bit, 256fs 24bit, 24bit, 256fs 24bit, 24bit, 256fs 24bit, 20bit, 256fs 24bit, 24bit, 256fs 24bit, 24bit, 256fs 24bit, 24bit, 256fs Table (TDM mode, shows justified, means justified.)
MASTER
TDM0
DIF1
DIF0
SDTO1
SDTI1
Mode
SDTI1, LRCK1 BICK1 SDTI2 24bit, 20bit, 128fs 24bit, 24bit, 128fs 24bit, 24bit, 128fs 24bit, 24bit, 128fs 24bit, 20bit, 128fs 24bit, 24bit, 128fs 24bit, 24bit, 128fs 24bit, 24bit, 128fs Table (TDM mode, shows justified, means justified.)
MASTER
TDM0
DIF1
DIF0
SDTO1
MS0339-J-00
2004/09
[AK4589]
LRCK1
BICK1(64fs) SDTO1(o) SDTI(i)
Don't Care
Don't Care
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB Data
Data
Figure Mode
LRCK1
BICK1(64fs) SDTO1(o) SDTI(i)
Don't Care 23:MSB, 0:LSB
Don't Care
Data
Data
Figure Mode
LRCK1
BICK1(64fs) SDTO1(o) SDTI(i)
Don't Care
Don't Care
23:MSB, 0:LSB
Data
Data
Figure 3.Mode
LRCK1
BICK1(64fs) SDTO1(o) SDTI(i)
Don't Care
Don't Care
23:MSB, 0:LSB Data Data
Figure Mode
MS0339-J-00
2004/09
[AK4589]
LRCK1
LRCK1
BICK1(256fs) SDTO 1(o)
SDTI1(i)
Figure Mode
LRCK1
LRCK1
BICK1(256fs) SDTO 1(o)
SDTI1(i)
Figure Mode
LRCK1 LRCK1
BICK1(256fs) SDTO 1(o)
SDTI1(i)
Figure Mode
LRCK1
LRCK1
BICK1(256fs) SDTO 1(o)
SDTI1(i)
Figure Mode
MS0339-J-00
2004/09
[AK4589]
LRCK1 LRCK1
BICK1(128fs) SDTO1(o)
SDTI1(i)
SDTI2(i)
Figure Mode
LRCK1
LRCK1
BICK1(128fs)
SDTI1(i)
SDTI2(i)
Figure Mode
LRCK1
LRCK1
BICK1(128fs) SDTO 1(o)
SDTI1(i)
SDTI2(i)
Figure Mode
MS0339-J-00
2004/09
[AK4589]
LRCK1
LRCK1
BICK1(128fs) SDTO1(o)
SDTI1(i)
SDTI2(i)
Figure Mode
MS0339-J-00
2004/09
[AK4589]
AK4589OVFE LchRch(-0.3dBFS)OVF "H"OVFADC 16/fs 333µs @fs=48kHz) (PDN "H") 522/fs (=11.8ms @fs=48kHz)OVF
AK45892GroupDZFM3-0 bit(Table DZF1 pinGroup1DZF2 pinGroup2OVFE DZF2 pinOVF mode DZF1 pin8chAND DZF2 pin("L") OVFE bitDZFTable Group1(Group2)8192 DZF1(DZF2) Group1(Group2) Mode DZFM AOUT DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF2 DZF1 DZF1 DZF2 DZF2 DZF1 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 Disable (DZF1=DZF2 "L") DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1
DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF2 DZF1 DZF1
DZF1 DZF1 DZF1 DZF1 DZF1 DZF2 DZF2 DZF1 DZF1
DZF1 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF1 DZF2
DZF1 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 Default DZF2 DZF2
Disable (DZF1=DZF2 "L")
Table OVFE DZF1 Selectable (Table Selectable (Table DZF2/OVF Selectable (Table output
Table DZF1-2
MS0339-J-00
2004/09
[AK4589]
AK4589(128, 0.5dB) ATT7-0 bit(Table ATT7-0 Attenuation Level -0.5dB -1.0dB -62.5dB -63dB MUTE MUTE MUTE
Default
Table ATT7-0ATS1-0 bit(Table Mode0Mode1 Mode ATS1 ATS0 speed 1792/fs 896/fs 256/fs 256/fs
Default
Table 16.ATT7-0 Mode0 ATT1792 00H(0dB)7FH(MUTE)1792/fs (37.3ms@fs=48kHz) ATT7-000H ATT7-0RSTN1 00HRSTN1
MS0339-J-00
2004/09
[AK4589]
SMUTE ATTATT (Table 16)- ("0") SMUTE
SMUTE
Level Attenuation
AOUT 8192/fs
DZF1,2
(Table Mode 0ATT "00H"1792/fs ATT00H7FH (2)(GD) (3)- (4)8192 Figure
MCLK LRCK1 LRCK1
MS0339-J-00
2004/09
[AK4589]
AK4589ADCDAC(PDN pin) VCOMSDTO1,DZF1-2 SDTO1522 LRCK1DAC VCOMTable
ADCDACPWADN bitPWDAN bitDAC1-4PD1-4 PWADN SDTO1 PWDAN PD1-4 "0"VCOM DZF1-2
Power
522/fs
Internal State
Internal State
Init Cycle
516/fs
Normal Operation
Power-down
Normal Operation
Init Cycle
Power-down
(Analog)
(Digital)
(Digital)
"0"data
"0"data
"0"data
"0"data
(Analog)
Clock
MCLK,LRCK1, BICK1
Don't care
Don't care
1011/fs (10)
DZF1/DZF2
External Mute
Mute
Mute
(GD) PDNPDN512/fs (PDN "L")(MCLK, BICK1, LRCK1) (PDN "L")DZF1-2 (10) ""1011/fsDZF Figure
MS0339-J-00
2004/09
[AK4589]
RSTN1 "0"ADCDAC VCOMDZF1-2 SDTO1 Table 15RSTN1
RSTN1
4~5/fs
1~2/fs
Internal RSTN1
516/fs
Internal State
Internal State
Normal Operation
Digital Block Power-down
Init Cycle
Normal Operation
Normal Operation
Digital Block Power-down
Normal Operation
(Analog)
(Digital)
(Digital)
"0"data
"0"data
(Analog)
Clock
MCLK,LRCK1, BICK1
Don't care
45/fs
DZF1/DZF2
(GD) RSTN1 "0"VCOM RSTN1 45/fsRSTN1 12/fs (RSTN1 "0")(MCLK, BICK1, LRCK1) (MCLK, BICK1, LRCK1)RSTN1 DZF1-2 RSTN1 RSTN1 6~7/fs RSTN1 RSTN 4~5/fs Figure
MS0339-J-00
2004/09
[AK4589]
AK4589 PD1-4 PD1-4 VCOM DZF1-2 PWDAN RSTN1 PD1-4 Figure PD1-4
PD1-4
Power Down Channel
Digital Internal State
Analog Internal State
Normal Operation
Power-down
Normal Operation
Normal Operation
Power-down
Normal Operation Normal Operation
(Digital)
"0"data
(Analog)
8192/fs
Detect Internal State
Normal Operation Channel
(Digital)
"0"data
(Analog)
8192/fs
Detect Internal State
Clock
MCLK,LRCK1, BICK1
DZF1/DZF2
(GD) PD1-4 VCOM PD1-4 DZF1-2 DZF1-2 DZF1-2 Figure
MS0339-J-00
2004/09
[AK4589]
Addr Register Name Control Control LOUT1 Volume Control ROUT1 Volume Control LOUT2 Volume Control ROUT2 Volume Control LOUT3 Volume Control ROUT3 Volume Control De-emphasis speed Power Down Control Zero detect LOUT4 Volume Control ROUT4 Volume Control CKS1 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 DEMD1 OVFE ATT7 ATT7 DFS1 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 DEMD0 DZFM3 ATT6 ATT6 TDM1 LOOP1 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 DEMA1 ATS1 DZFM2 ATT5 ATT5 TDM0 LOOP0 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 DEMA0 ATS0 DZFM1 ATT4 ATT4 DIF1 SDOS ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 DEMB1 DZFM0 ATT3 ATT3 DIF0 DFS0 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 DEMB0 PWVRN ATT2 ATT2 ACKS ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 DEMC1 PWADN ATT1 ATT1 SMUTE CKS0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 DEMC0 RSTN1 PWDAN ATT0 ATT0
0DH1FH RSTN DZF1-2
Addr Register Name Control Default TDM1 TDM0 DIF1 DIF0 SMUTE
SMUTE: DIF1-0: (Table "10", mode TDM1-0: TDM(Table 11,12) Mode TDM1 TDM0 SDTI Sampling Speed Normal, Double, Quad Times Speed Normal Speed Normal, Double Speed
MS0339-J-00
2004/09
[AK4589]
Addr
Register Name Control Default
CKS1
DFS1
LOOP1
LOOP0
SDOS
DFS0
ACKS
CKS0
ACKS: Manual Setting Mode Auto Setting Mode ACKS "1"MCLK ACKS DFS0,1 MCLK DFS1-0: (Table ACKS "1"DFS CKS0-1: (MASTER Mode, Table SDOS: SDTO1 DAUX1 TDM0 "1"SDOS PWADN ="0"PWDAN ="0"SDOS PWADN ="0"SDTO1 pin"L" LOOP1-0: LOUT1, LOUT2, LOUT3, LOUT4 ROUT1, ROUT2, ROUT3, ROUT4 ADC(SDOS "1"DAUX1)DAC DACSDTI1-4 SDTO1mode0mode2mode1 mode3 SDTI1(L) SDTI2(L), SDTI3(L), SDTI4(L) SDTI1(R) SDTI2(R), SDTI3(R), SDTI4(R) DACSDTI2-4 TDM0 "1"LOOP1-0 "00" PWADN ="0"PWDAN ="0"LOOP1-0
MS0339-J-00
2004/09
[AK4589]
Addr
Register Name LOUT1 Volume Control ROUT1 Volume Control LOUT2 Volume Control ROUT2 Volume Control LOUT3 Volume Control ROUT3 Volume Control LOUT4 Volume Control ROUT4 Volume Control Default
ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7
ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6
ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5
ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4
ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3
ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2
ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1
ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0
ATT7-0: (Table
Addr
Register Name De-emphasis Default
DEMD1
DEMD0
DEMA1
DEMA0
DEMB1
DEMB0
DEMC1
DEMC0
DEMA1-0: DAC1(Table "01", DEMB1-0: DAC2(Table "01", DEMC1-0: DAC3(Table "01", DEMD1-0: DAC4(Table "01",
MS0339-J-00
2004/09
ASAHI KASEI Addr Register Name speed Power Down Control Default ATS1 ATS0
[AK4589] RSTN1
RSTN1: DZF1-2 ATS1-0: (Table "00", mode PD1-0: Power-down control Power-up, Power-down) PD1: Power down control DAC1 PD2: Power down control DAC2 PD3: Power down control DAC3 PD4: Power down control DAC4
Addr
Register Name Zero detect Default
OVFE
DZFM3
DZFM2
DZFM1
DZFM0
PWVRN
PWADN
PWDAN
PWDAN: DAC1-4 PWADN: PWVRN: DZFM3-0: (Table "0111", OVFE: pin#33DZF2 pin#33OVF
MS0339-J-00
2004/09
[AK4589]
(DIR/DIT) Non-PCM/DTS-CD
AK4589Non-PCMDolby "AC-3 Data Stream IEC60958 Interface" ModeNon-PCMAUTO sync code 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 0x4E1F4096 sync codesync codeAUTO sync code2(Pc, Pd)DTS-CD DTSCD "1"4096sync code sync codeDTSCD
192kHz
PLL32kHz192kHz20ms (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz)
AK45892PLL X'tal(Table (MCKO1, MCKO2)X'talfsOCKS1-0 96kHz512fs 192kHz256fs,512fs OCKS1 OCKS0 MCKO1 MCKO2 X'tal (max) 256fs 256fs 256fs 256fs 128fs 256fs 512fs 256fs 512fs 128fs 64fs 128fs Table (Stereo mode)
Default
RXDAUX2CM1-0 Mode 2PLLUnlockX'talMode X'tal Mode 3PLLX'tal Mode UNLOCK X'tal Clock source SDTO Default ON(Note) X'tal DAUX2 X'tal DAUX2 X'tal DAUX2 (Power-up), OFF: (Power-Down) Note: X'tal(XTL1-0 "H,H")OFF Table
MS0339-J-00
2004/09
[AK4589]
AK4589XTI X'tal
25k(typ)
AK4589
Figure X'tal Note: (Typ.10-40pF)
Note: DVDD
External Clock External Clock
25k(typ)
25k(typ)
AK4589
AK4589
Figure (Input :CMOS Level) XTI/XTO
Figure (Input :40%DVDD, C=0.1µF)
25k(typ)
AK4589
Figure
MS0339-J-00
2004/09
[AK4589]
AK45892XTL1-0 pinX'tal FS0, FS1, FS2, bitX'tal XTL1-0 "H,H" FS0, FS1, FS2, FS3, XTL1 XTL0 X'tal Frequency 11.2896MHz 12.288MHz 24.576MHz Table XTL1,0= "1,1" Register output
Default
XTL1,0= "1,1"
Consumer mode Professional mode Clock comparison (Note (Note Byte3 Byte0 Byte4 Bit3,2,1,0 Bit7,6 Bit6,5,4,3 44.1kHz 44.1kHz 0000 0000 Reserved Reserved 0001 (Others) 48kHz 48kHz 0010 0000 32kHz 32kHz 0011 0000 88.2kHz 88.2kHz (1000) 1010 96kHz 96kHz (1010) 0010 176.4kHz 176.4kHz (1100) 1011 192kHz 192kHz (1110) 0011 Note ±3%Table 32kHz192kHzFS3-0 "0001" Note Byte3 Bit3-0FS3-0 Table
(CS12=0)1CS12 Byte Bits 0X100 0X100 Table Pre-emphasis Byte Bits Table Pre-emphasis
MS0339-J-00
2004/09
[AK4589]
IIR4 (32kHz, 44.1kHz, 48kHz, 96kHz) (50/15µs) DEAU "1"FS3-0 DEAU DEM0/1, Mode 44.1kHz 48kHz 32kHz 96kHz (Others) Table (DEAU "1": Default) DEM1 DEM0 Mode 44.1kHz 48kHz 32kHz 96kHz Table (DEAU "0")
Default
AK4589PDN pinPWN bitRSTN pin: pinADC/DAC RSTN (00HD0): "0"PWN bitRSTN "0"SDTO2 "L"PWN bitRSTN (00HD1): "0"PLL X'tal
MS0339-J-00
2004/09
[AK4589]
8(RX0-7)IPS2-0 200mVppBCU "1"Block start, IPS2 IPS1 IPS0 INPUT Data Table
Default
1/4fs COUT U,V)
C(R191)
C(L0)
C(R0)
C(L1)
C(L39)
C(R39) C(L40)
SDTO2
R190
L191
R191
LRCK2 (except LRCK2
Figure
MS0339-J-00
2004/09
[AK4589]
TX0/1 pinRXDAUX2IEC60958 bitTX0OPS00, TX1OPS10, bit8TX0/1 DAUX2 bitVIN pin(Figure bit5Byte bit0= "0"(consumer mode)bit20-23(Audio channel)CT20 "1"Sub frame "1000", frame "0100" CT20 "0000"U bitUDIT 2UDIT bit= "0"UDIT "1"U DITU bitDIR-DIT OPS02 OPS01 OPS00 Output Data Table (TX0) OPS11 OPS10 Output Data DAUX2 Table (TX1)
Default
OPS12
Default
LRCK2 (except LRCK2 DAUX2
R191
Figure DAUX2,
MS0339-J-00
2004/09
[AK4589]
0.1uF Coax
AK4589
Figure (Coaxial) Note: Coaxial 50mV
Optical Receiver Optical Fiber
AK4589
Figure CoaxialRXRX AK4589TX0.5V+/-20%Figure 25T11:1
330±2% 100±2% DVSS cable
Figure
MS0339-J-00
2004/09
[AK4589]
Q-subcode
bitCDQ-subcode Subcode sync word (S0,S1) Start start Start 8-16 Q-subcode QINT QINT
number min=0; max=8.
Figure U-(CD)
CTRL
ADRS
TRACK NUMBER INDEX
MINUTE SECOND FRAME ZERO ABSOLUTE MINUTE ABSOLUTE SECOND ABSOLUTE FRAME G(x)=x16+x12+x5+1
Figure Addr Register Name Q-subcode Address Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode Minute Q-subcode Second Q-subcode Frame Figure Q-subcode register
MS0339-J-00
2004/09
[AK4589]
INT1-0 UNLOCK AUTO Non-Linear 4096 DTSCD DTS-CD DTS-CD sync AUDION AUDIO QINT :Q-subcode Sync Sync CINT Sync (Clock Operation Mode INT0/1 INT0 1024/fs (EFH0/1 "H"INT1 PAR, QINT, CINT 18ORINT pin(06H)INT0 1024/fs (EFH0/1 bit) "H"PAR, QINT, CINT "1"06H INT0UNLOCK, bitINT1AUTO, DTSCD, AUDION Event DTSCD AUDION QINT CINT SDTO Previous Data Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output
UNLOCK
AUTO
Table
MS0339-J-00
2004/09
[AK4589]
Error (UNLOCK, PAR,.) INT0
(Error)
Hold Time (max: 4096/fs)
INT1 Register (PAR,CINT,QINT) Register (others) Command MCKO,BICK2,LRCK2 (UNLOCK) MCKO,BICK2,LRCK2 (except UNLOCK) SDTO2 (UNLOCK)
Hold Time
Hold
Reset
READ
Free (fs: around 20kHz)
SDTO2 (PAR error) SDTO2 (others) Vpin (UNLOCK) Vpin (except UNLOCK)
Previous Data
Normal Operation
Figure INT0-1
MS0339-J-00
2004/09
[AK4589]
="L" Initialize Read
INT0/1 ="H"
Release Muting
Mute output
Read
(Each Error Handling)
Read (Resets registers)
INT0/1 ="H"
Figure
MS0339-J-00
2004/09
[AK4589]
="L" Initialize Read
INT1 ="H"
Read Detect QSUB=
(Read Q-buffer)
QCRC INT1 ="L" data valid
data invalid
Figure (Q/CINT)
MS0339-J-00
2004/09
[AK4589]
8(Table 29)MSB2's complement SDTO2BICK21DAUX2 Mode0-5BICK264fsMode 6-7Mode 4-5BICK2fs=48kHz 128fs20(Mode0-2)LSB Mode 3-74AuxFigure (PDN "L")(PDN "H") BICK2LRCK2Hi-Z Parity ErrorSDTO2 "0"DAUX2 SDTO2 Clock Mode unlockClock Mode 2Clock Mode 3DAUX2 pinDAUX2 Mode 724, Left justifiedSDTO2 Mode 7I2S Mode Mode4-5LRCK2BICK2MCKO1/2
sub-frame IEC60958
preamble
Aux.
AK4589 Audio Data (MSB First)
Figure
Mode
DIF2
DIF1 DIF0
LRCK2 24bit, Left justified 16bit, Right justified 24bit, Left justified 18bit, Right justified 24bit, Left justified 20bit, Right justified 24bit, Left justified 24bit, Right justified 24bit, Left justified 24bit, Left justified 24bit, 24bit, 24bit, Left justified 24bit, Left justified 24bit, 24bit, Table DAUX2 SDTO2
BICK2 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs 64-128fs
Default
MS0339-J-00
2004/09
[AK4589]
LRCK2
BICK2 (0:64fs) SDTO2
15:MSB, 0:LSB Data Data
Figure Mode
LRCK2
BICK2 (0:64fs) SDTO2
23:MSB, 0:LSB
Data Data
Figure Mode
LRCK2
BICK2 (64fs) SDTO2
23:MSB, 0:LSB
Data Data
Figure Mode
Mode4 LRCK2, BICK2 Output Mode6 LRCK2, BICK2 Input
LRCK2
BICK2 (64fs) SDTO2
23:MSB, 0:LSB
Data Data
Figure Mode
Mode5 LRCK2, BICK2 Output Mode7 LRCK2, BICK2 Input
MS0339-J-00
2004/09
[AK4589]
Addr Register Name Power Down Control Format De-em Control Input/ Output Control Input/ Output Control INT0 MASK INT1 MASK Receiver status Receiver status Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Q-subcode Address Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode Minute Q-subcode Second Q-subcode Frame CS12 TX1E EFH1 DIF2 OPS12 EFH0 DIF1 OPS11 UDIT DIF0 OPS10 OCKS1 DEAU TX0E OCKS0 DEM1 OPS02 IPS2 MPE0 MPE1 CR10 CR18 CR26 CR34 CT10 CT18 CT26 CT39 PC10 PD10 DEM0 OPS01 IPS1 MAUD0 MAUD1 AUDION QCRC CR17 CR25 CR33 CT17 CT25 CT39 RSTN2 OPS00 IPS0 MPAR0 MPAR1 CCRC CR16 CR24 CR32 CT16 CT24 CT32
MQIT0 MAUT0 MCIT0 MQIT1 MAUT1 MCIT1 QINT CR15 CR23 CR31 CR39 CT15 CT23 CT31 CT39 PC15 PD15 AUTO CR14 CR22 CR30 CR38 CT14 CT22 CT30 CT39 PC14 PD14 CINT CR13 CR21 CR29 CR37 CT13 CT21 CT29 CT39 PC13 PD13
MULK0 MDTS0 MULK1 MDTS1 UNLCK DTSCD CR12 CR20 CR28 CR36 CT12 CT20 CT28 CT39 PC12 PD12 CR11 CR19 CR27 CR35 CT11 CT19 CT27 CT39 PC11 PD11
RSTN2
MS0339-J-00
2004/09
[AK4589]
Reset Initialize
Addr Register Name Power Down Control Default CS12 OCKS1 OCKS0 RSTN2
RSTN2: PWN: OCKS1-0: CM1-0: BCU: 13(BOUT, COUT, UOUT) frame 0frame CS12: Channel Channel bit, AUDION, PEM, FS3-0,
Format De-emphasis Control
Addr Register Name Format De-em Control Default DIF2 DIF1 DIF0 DEAU DEM1 DEM0
DFS: 96kHz DEM1-0: 44.1, 48kHz (Table DEAU: Disable Enable DIF2-0: (Table
MS0339-J-00
2004/09
[AK4589]
Input/Output Control
Addr Register Name Input/ Output Control Default TX1E OPS12 OPS11 OPS10 TX0E OPS02 OPS01 OPS00
OPS02-00: (TX0 pin) OPS12-10: (TX1 pin) TX0E: TX1E: Addr Register Name Input/ Output Control Default EFH1 EFH0 UDIT IPS2 IPS1 IPS0
IPS2-0: DIT: (RX) (DAUX2) UDIT: DITU bit) EFH1-0: INT0 LRCK2 1024 LRCK2 2048 LRCK2: 4096 LRCK2
MS0339-J-00
2004/09
[AK4589]
Mask Control INT0
Addr Register Name INT0 MASK Default MPR0: MAN0: MPE0: MDTS0: MUL0: MCI0: MAT0: MQI0: MQI0 MAT0 MCI0 MUL0 MDTS0 MPE0 MAN0 MPR0
AUDN DTSCD UNLOCK CINT AUTO QINT
Mask Control INT1
Addr Register Name INT1 MASK Default MPR1: MAN1: MPE1: MDTS1: MUL1: MCI1: MAT1: MQI1: MQI1 MAT1 MCI1 MUL1 MDTS1 MPE1 MAN1 MPR1
AUDN DTSCD UNLOCK CINT AUTO QINT
MS0339-J-00
2004/09
[AK4589]
Receiver Status
Addr Register Name Receiver status Default QINT AUTO CINT UNLCK DTSCD AUDION
PAR: 0:No Error 1:Error AUDION: Audio Audio Audio PEM: DTSCD: DTS-CD UNLCK: CINT: AUTO: Non-PCM QINT: QINT, CINT, bit06HREAD
Receiver Status
Addr Register Name Receiver status Default QCRC CCRC
CCRC: QCRC: QCRC 0:Valid 1:Invalid FS3-0: (Table
MS0339-J-00
2004/09
[AK4589]
Receiver Channel Status
Addr Register Name Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Default CR15 CR23 CR31 CR39 CR14 CR22 CR30 CR38 CR13 CR21 CR29 CR37 CR12 CR20 CR28 CR36 CR11 CR19 CR27 CR35 CR10 CR18 CR26 CR34 CR17 CR25 CR33 CR16 CR24 CR32
initialized
CR39-0: Byte
Transmitter Channel Status
Addr Register Name Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Default CT15 CT23 CT31 CT39 CT14 CT22 CT30 CT38 CT13 CT21 CT29 CT37 CT12 CT11 CT20 CT19 CT28 CT27 CT36 CT35 CT10 CT18 CT26 CT34 CT17 CT25 CT335 CT16 CT24 CT32
CT39-0: Byte
Burst Preamble Pc/Pd non-PCM encoded Audio Bitstreams
Addr Register Name Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Default PC15 PD15 PC14 PD14 PC13 PD13 PC12 PD12 PC11 PD11 PC10 PD10
initialized
PC15-0: Byte PD15-0: Byte
MS0339-J-00
2004/09
[AK4589]
Q-subcode Buffer
Addr Register Name Q-subcode Address Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode Minute Q-subcode Second Q-subcode Frame Default
initialized
MS0339-J-00
2004/09
[AK4589]
Non-PCM
sub-frame IEC60958
preamble
Aux.
bits bitstream
Burst_payload
stuffing
repetition time burst
Figure IEC60958 Preamble word Length field Contents bits sync word bits sync word bits Burst info bits Length code Table Value 0xF872 0x4E1F Table numbers bits
MS0339-J-00
2004/09
[AK4589]
Bits
Value
Contents data type NULL data Dolby AC-3 data reserved PAUSE MPEG-1 Layer1 data MPEG-1 Layer2 data MPEG-2 without extension MPEG-2 data with extension MPEG-2 ADTS MPEG-2, Layer1 sample rate MPEG-2, Layer2 sample rate reserved type type type ATRAC ATRAC2/3 reserved reserved, shall error-flag indicating valid burst_payload error-flag indicating that burst_payload contain errors data type dependent info stream number, shall Table
Repetition time burst IEC60958 frames 4096 1536
16-31
1152 1152 1024 1152 1024 2048 1024
8-12 13-15
MS0339-J-00
2004/09
[AK4589]
Non-PCM
Non-PCM 4096
stream
Repetition time
>4096 frames
AUTO
Register
Register
Figure
Non-PCM (MULK0=0
INT0
<20mS (Lock time)
INT0 hold time
stream
Stop
Syncs (B,M
AUTO
<Repetition time
Register
Register
Figure
MS0339-J-00
2004/09
[AK4589]
(ADC/DAC, DIR/DIT
(I2C "L") 4I/F (CSN, CCLK, CDTI, CDTO)I/FChip address (2bits, AK4589ADC/DAC CAD1-0 pinDIR/DIT"00"), Read/Write (1bit), Register address (MSB first, 5bits) Control Data (MSB first, 8bits) CCLK ""Hi-Z CCLK5MHz (max)PDN pin= ADC/DAC
CCLK
CDTI
WRITE
CDTO
CDTI
READ
Hi-Z
CDTO
Hi-Z
Hi-Z
C1,C0:
R/W: A4-A0: D7-D0:
Chip Address: (ADC/DACCAD1,CAD0 CAD1=CAD0 "L") (DIR/DIT "00") READ/WRITE (0:READ, 1:WRITE) Register Address Control Data
Figure 4I/F
MS0339-J-00
2004/09
[AK4589]
(I2C "H") ADC/DAC (2)-1 READWRITE (2)-1-1. SDASCL "H"SDA "L"SCL "L"SCL
DATA LINE STABLE DATA VALID
CHANGE DATA ALLOWED
Figure (2)-1-2. "H"SDA "H"SDA
START CONDITION
STOP CONDITION
Figure
MS0339-J-00
2004/09
[AK4589]
(2)-1-3. 1SDA(HIGH) ICSDA WRITE READAK4589 AK4589 AK4589 ()ADC,DACREAD
Clock pulse acknowledge
FROM MASTER
DATA OUTPUT TRANSMITTER acknowledge DATA OUTPUT RECEIVER START CONDITION acknowledge
Figure (2)-1-4. "00100" CAD1,CAD0 18()R/W bit= "1"READR/W bit= "0"WRITE
CAD1
CAD0
(ADC,DACCAD1,CAD0 CAD1=CAD0="0") (DIR"00") Figure
MS0339-J-00
2004/09
[AK4589]
(2)-2. WRITE "0"AK4589WRITEWRITE2 2MSB first 3Don't care
Don't care) Figure 38MSB first
Figure
Data(n+x)
Slave Address
Register Address(n)
Data(n)
Data(n+1)
Figure WRITE
MS0339-J-00
2004/09
[AK4589]
(2)-3. READ "1"AK4589READ 1FH00H ADC/DAC (2)-3-1. (READWRITE)n "1") READ
Data(n+x)
Slave Address
Data(n)
Data(n+1)
Data(n+2)
Figure CURRENT ADDRESS READ (2)-3-2. "1")WRITE "0") AK4589 "1")AK4589
Data(n+x)
Slave Address
Word Address(n)
Slave Address
Data(n)
Data(n+1)
Figure RANDOM READ
MS0339-J-00
2004/09
[AK4589]
Figure 50(AKD4589) :I2C
Micro Controller
S/PDIF
S/PDIF sources
(S/PDIF sources)
Audio (MPEG/AC3)
TEST2 DAUX2 PVDD CAD1 CAD0 INT0 MCLK
0.1u
PVSS
(Shield) TEST1 AVSS AVDD VREFH VCOM 0.1u (Shield)
INT1 BOUT TVDD DVDD DVSS TEST3 MCKO2
3.3V Digital Digital
0.1u
X'tal
Analog
0.1u 2.2u
MCKO1
(Micro Controller)
COUT UOUT VOUT SDTO2 BICK2 LRCK2 SDTO1 BICK1 LRCK1
AK4589
ROUT1+ ROUT1- LOUT1+ LOUT1- ROUT2+ ROUT2- LOUT2+ LOUT2- ROUT3+ MUTE MUTE MUTE MUTE MUTE
Audio (MPEG/AC3)
MASTER
LOUT3-
LOUT4-
DAUX1
SDTI4
SDTI3
SDTI2
SDTI1
DZF2
DZF1
XTL1
XTL0
LOUT3+
CDTO
ROUT4+
LOUT4+
ROUT4-
ROUT3-
MUTE
MUTE
Micro Controller Audio (MPEG/AC3) Micro Controller
Digital Ground
Analog Ground
Figure Note 470pF AVSS, DVSS, PVSS AK4589 PVSS MS0339-J-00 2004/09
MUTE
(S/PDIF Source)
[AK4589]
AVDD, DVDD, PVDD AVDD, DVDD, PVDD AVSS, DVSS, PVSS VREFH VREFH AVDD AVSS 0.1µF VCOM AVDD/2 2.2µF 0.1µF AVSS VCOM VREFH pin,VCOM VCOM 0.62 VREFH (typ)@fs=48kHz AK4589 AVSS AVDD complement(2 AK4589 64fs 64fs AK4589 64fs AVDD/2 0.54 VREF (typ)AOUT+ AOUT- VAOUT=(AOUT+)-(AOUT-) 5.4Vpp (typ @VREF=5V) complement7FFFFFH(@24bit) 800000H(@24bit)000000H(@24bit) AOUT AOUT+/AOUT- AVDD/2
MS0339-J-00
2004/09
[AK4589]
AK4589 NJM5534D
3.3n
100u
AOUTL+
3.9n
0.1u
NJM5534D
1.0n
0.1u
1.2k
0.1u
3.3n
100u
AOUTL+
3.9n
0.1u
0.1u
NJM5534D
1.2k
0.1u
Figure External order Circuit Example
MS0339-J-00
1.0n NJM5534D
2004/09
[AK4589]
80-pin LQFP Unit
14.0±0.2
12.0±0.2
14.0±0.2
12.0±0.2
0.20±0.1 0.50 1.25TYP
1.40±0.2
0.08
0.125+0.10 -0.05
0.50±0.1
0.10
MS0339-J-00
+0.15 0.10 -0.10
1.85MAX
2004/09
[AK4589]
AK4589VQ
XXXXXXX
indication Asahi Kasei Logo Marking Code: AK4589VQ Date Code: XXXXXXX(7 digits)
Date (YY/MM/DD) 04/09/06 Revision Reason First Edition Page Contents
MS0339-J-00
2004/09

AK4589 2/8-Channel Audio CODEC with AK4589 24bit CODEC AK458

Top Searches for this datasheet

Other recent searches