64/80-Pin Flash Microcontrollers with nanoWatt Technology 2004 Mi
|
|
|
Top Searches for this datasheet
PIC18F6310/6410/8310/8410 Data Sheet
64/80-Pin Flash Microcontrollers with nanoWatt Technology
2004 Microchip Technology Inc.
DS39635A
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like intended through suggestion only superseded updates. your responsibility ensure that your application meets with your specifications. representation warranty given liability assumed Microchip Technology Incorporated with respect accuracy such information, infringement patents other intellectual property rights arising from such otherwise. Microchip's products critical components life support systems authorized except with express written approval Microchip. licenses conveyed, implicitly otherwise, under intellectual property rights.
Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, MATE, PowerSmart, rfPIC, SmartShunt registered trademarks Microchip Technology Incorporated U.S.A. other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel Total Endurance trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2004, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona Mountain View, California October 2003. Company's quality system processes procedures PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
64/80-Pin Flash Microcontrollers with nanoWatt Technology
Power Managed Modes:
Run: peripherals Idle: off, peripherals Sleep: off, peripherals Idle mode currents down typical Sleep mode currents down typical Timer1 Oscillator: kHz, Watchdog Timer: Two-Speed Oscillator Start-up
Peripheral Highlights:
High current sink/source mA/25 Four external interrupts Four input change interrupts Four 8-bit/16-bit Timer/Counter modules Capture/Compare/PWM (CCP) modules Master Synchronous Serial Port (MSSP) module supporting 3-wire SPI(all modes) I2CMaster Slave modes Addressable USART module: Supports RS-485 RS-232 Enhanced Addressable USART module: Supports RS-485, RS-232 Auto-Wake-up Start Auto-Baud Detect 10-bit, 12-channel Analog-to-Digital Converter module (A/D): Auto-acquisition capability Conversion available during Sleep Dual analog comparators with input multiplexing
Flexible Oscillator Structure:
Four Crystal modes: HSPLL: 4-10 (16-40 internal) Phase Lock Loop (available crystal internal oscillators) External modes, External Clock modes, Internal oscillator block: user selectable frequencies, from Provides complete range clock speeds from when used with User-tunable compensate frequency drift Secondary oscillator using Timer1 Fail-Safe Clock Monitor: Allows safe shut down device primary secondary clock fails
Special Microcontroller Features:
compiler optimized architecture: Optional extended instruction designed optimize re-entrant code 1000 erase/write cycle Flash program memory typical Flash Retention: years typical Priority levels interrupts Single-Cycle Hardware Multiplier Extended Watchdog Timer (WDT): Programmable period from 131s stability over temperature In-Circuit Serial Programming(ICSPTM) pins In-Circuit Debug (ICD) pins Wide operating voltage range: 2.0V 5.5V
External Memory Interface (PIC18F8310/8410 Devices only):
Address capability Mbytes 16-bit/8-bit interface
Program Memory (On-Board/External) Device Flash (bytes) PIC18F6310 PIC18F6410 PIC18F8310 8K/0 16K/0 8K/2M Single-Word Instructions 4096/0 8192/0 4096/1M 8192/1M SRAM (bytes) Data Memory
MSSP 10-bit (ch) (PWM) Master SPII2CY
Comparators
EUSART/ AUSART
Timers 8/16-bit
Ext.
PIC18F8410 16K/2M
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
Diagrams
64-Pin TQFP
RE7/CCP2(1)
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
RE2/CS
RE1/WR RE0/RD RG0/CCP3 RG1/TX2/CK2 RG2/RX2/DT2 RG5/MCLR/VPP RF7/SS RF6/AN11 RF5/AN10/CVREF RF4/AN9 RF3/AN8 RF2/AN7/C1OUT
RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3 RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC OSC2/CLKO/RA6 OSC1/CLKI/RA7 RB7/KBI3/PGD RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1
PIC18F6310 PIC18F6410
RF1/AN6/C2OUT
RF0/AN5
RC0/T1OSO/T13CKI
AVSS RA3/AN3/VREF+
RA5/AN4/HLVDIN
RA2/AN2/VREF-
Note alternate CCP2 multiplexing.
DS39635A-page
RA4/T0CKI RC1/T1OSI/CCP2(1)
RC7/RX1/DT1
RC6/TX1/CK1
RA1/AN1
RA0/AN0
AVDD
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
Diagrams (Continued)
80-Pin TQFP
RE7/CCP2(1)/AD15
RD1/AD1/PSP1
RD2/AD2/PSP2
RD3/AD3/PSP3
RD4/AD4/PSP4
RD5/AD5/PSP5
RD6/AD6/PSP6
RH0/A16 RE2/AD10/CS
RH1/A17
RD0/AD0/PSP0
RD7/AD7/PSP7
RE4/AD12
RE5/AD13
RE6/AD14
RE3/AD11
RJ0/ALE
RH2/A18 RH3/A19 RE1/AD9/WR RE0/AD8/RD RG0/CCP3 RG1/TX2/CK2 RG2/RX2/DT2 RG5/MCLR/VPP RF7/SS RF6/AN11 RF5/AN10/CVREF RF4/AN9 RF3/AN8 RF2/AN7/C1OUT RJ2/WRL RJ3/WRH RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3/CCP2(1) RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC OSC2/CLKO/RA6 OSC1/CLKI/RA7 RB7/KBI3/PGD RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1 RJ7/UB RJ6/LB
PIC18F8310 PIC18F8410
RF1/AN6/C2OUT
RF0/AN5
RJ4/BA0
RA4/T0CKI RC1/T1OSI/CCP2(1)
RA2/AN2/VREF-
Note alternate CCP2 multiplexing.
2004 Microchip Technology Inc.
RC0/T1OSO/T13CKI
AVSS RA3/AN3/VREF+
RA5/AN4/HLVDIN
RC7/RX1/DT1
RC6/TX1/CK1
RA1/AN1
RA0/AN0
RJ5/CE
AVDD
RJ1/OE
DS39635A-page
PIC18F6310/6410/8310/8410
Table Contents
Device Overview Oscillator Configurations Power Managed Modes Reset Memory Organization Program Memory. External Memory Interface Hardware Multiplier. Interrupts 10.0 Ports 11.0 Timer0 Module 12.0 Timer1 Module 13.0 Timer2 Module 14.0 Timer3 Module 15.0 Capture/Compare/PWM (CCP) Modules 16.0 Master Synchronous Serial Port (MSSP) Module 17.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) 18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) 19.0 10-Bit Analog-to-Digital Converter (A/D) Module 20.0 Comparator Module. 21.0 Comparator Voltage Reference Module 22.0 High/Low-Voltage Detect (HLVD). 23.0 Special Features 24.0 Instruction Summary 25.0 Development Support. 26.0 Electrical Characteristics 27.0 Characteristics Graphs Tables 28.0 Packaging Information. Appendix Revision History. Appendix Device Differences. Appendix Conversion Considerations Appendix Migration from Baseline Enhanced Devices. Appendix Migration from Mid-Range Enhanced Devices Appendix Migration from High-End Enhanced Devices Index On-Line Support. Systems Information Upgrade Line Reader Response PIC18F6310/6410/8310/8410 Product Identification System
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
VALUED CUSTOMERS
intention provide valued customers with best documentation possible ensure successful your Microchip products. this end, will continue improve publications better suit your needs. publications will refined enhanced volumes updates introduced. have questions comments regarding this publication, please contact Marketing Communications Department E-mail docerrors@mail.microchip.com Reader Response Form back this data sheet (480) 792-4150. welcome your feedback.
Most Current Data Sheet
obtain most up-to-date version this data sheet, please register Worldwide site http://www.microchip.com determine version data sheet examining literature number found bottom outside corner page. last character literature number version number, (e.g., DS30000A version document DS30000).
Errata
errata sheet, describing minor operational differences from data sheet recommended workarounds, exist current devices. device/documentation issues become known will publish errata sheet. errata will specify revision silicon revision document which applies. determine errata sheet exists particular device, please check with following: Microchip's Worldwide site; http://www.microchip.com Your local Microchip sales office (see last page) Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting sales office literature center, please specify which device, revision silicon data sheet (include literature number) using.
Customer Notification System
Register site www.microchip.com/cn receive most current information products.
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
NOTES:
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
DEVICE OVERVIEW
1.1.2
This document contains device specific information following devices: PIC18F6310 PIC18F6410 PIC18F8310 PIC18F8410 PIC18LF6310 PIC18LF6410 PIC18LF8310 PIC18LF8410
MULTIPLE OSCILLATOR OPTIONS FEATURES
devices PIC18F6310/6410/8310/8410 family offer nine different oscillator options, allowing users wide range choices developing application hardware. These include: Four Crystal modes, using crystals ceramic resonators. External Clock modes, offering option using pins (oscillator input divide-by-4 clock output) (oscillator input, with second reassigned general I/O). External Oscillator modes, with same options External Clock modes. internal oscillator block which provides clock (±2% accuracy) INTRC source (approximately kHz, stable over temperature VDD), well range user selectable clock frequencies between total eight clock frequencies. This option frees oscillator pins additional general purpose I/O. Phase Lock Loop (PLL) frequency multiplier, available both High-Speed Crystal Internal Oscillator modes, which allows clock speeds MHz. Used with internal oscillator, gives users complete selection clock speeds from without using external crystal clock circuit. Besides availability clock source, internal oscillator block provides stable reference source that gives family additional features robust operation: Fail-Safe Clock Monitor: This option constantly monitors main clock source against reference signal provided internal oscillator. clock failure occurs, controller switched internal oscillator block, allowing continued low-speed operation safe application shutdown. Two-Speed Start-up: This option allows internal oscillator serve clock source from Power-on Reset wake-up from Sleep mode until primary clock source available.
This family offers advantages PIC18 microcontrollers namely, high computational performance economical price. addition these features, PIC18F6310/6410/8310/8410 family introduces design enhancements that make these microcontrollers logical choice many high-performance, power sensitive applications.
1.1.1
Core Features
nanoWatt TECHNOLOGY
devices PIC18F6310/6410/8310/8410 family incorporate range features that significantly reduce power consumption during operation. items include: Alternate Modes: clocking controller from Timer1 source internal oscillator block, power consumption during code execution reduced much 90%. Multiple Idle Modes: controller also with core disabled, peripherals still active. these states, power consumption reduced even further little normal operation requirements. On-the-Fly Mode Switching: power managed modes invoked user code during operation, allowing user incorporate power-saving ideas into their application's software design. Lower Consumption Modules: power requirements both Timer1 Watchdog Timer have been reduced 80%, with typical values respectively.
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
Other Special Features
Memory Endurance: Flash cells program memory rated last approximately thousand erase/write cycles. Data retention without refresh conservatively estimated greater than years. External Memory Interface: those applications where more program data storage needed, PIC18F8310/8410 devices provide ability access external memory devices. memory interface configurable both 8-bit 16-bit data widths uses standard range control signals enable communication with wide range memory devices. With their 21-bit program counters, 80-pin devices access linear memory space Mbytes. Extended Instruction Set: PIC18F6310/6410/8310/8410 family introduces optional extension PIC18 instruction set, which adds instructions Indexed Addressing mode. This extension, enabled device configuration option, been specifically designed optimize re-entrant application code originally developed high-level languages such `C'. Enhanced Addressable USART: This serial communication module capable standard RS-232 operation provides support protocol. Other enhancements include Automatic Baud Rate Detection 16-bit Baud Rate Generator improved resolution. When microcontroller using internal oscillator block, EUSART provides stable operation applications that talk outside world, without using external crystal accompanying power requirement). 10-bit Converter: This module incorporates programmable acquisition time, allowing channel selected conversion initiated without waiting sampling period thus, reduces code overhead. Extended Watchdog Timer (WDT): This enhanced version incorporates 16-bit prescaler, allowing time-out range from over minutes that stable across operating voltage temperature.
Details Individual Family Members
Devices PIC18F6310/6410/8310/8410 family available 64-pin (PIC18F6310/8310) 80-pin (PIC18F6410/8410) packages. Block diagrams groups shown Figure Figure 1-2, respectively. devices differentiated from each other three ways: Flash Program Memory: Kbytes PIC18FX310 devices, Kbytes PIC18FX410 devices. Ports: bidirectional ports 64-pin devices, bidirectional ports 80-pin devices. External Memory Interface: present 80-pin devices only.
other features devices this family identical. These summarized Table 1-1. pinouts devices listed Table Table 1-3. Like Microchip PIC18 devices, members PIC18F6310/6410/8310/8410 family available both standard low-voltage devices. Standard devices with Flash memory, designated with part number (such PIC18F6310), accommodate operating range 4.2V 5.5V. Low-voltage parts, designated "LF" (such PIC18LF6410), function over extended range 2.0V 5.5V.
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
TABLE 1-1: DEVICE FEATURES
Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) External Memory Interface Interrupt Sources Ports Timers Capture/Compare/PWM Modules Serial Communications Parallel Communications 10-bit Analog-to-Digital Module Resets (and Delays) PIC18F6310 4096 PIC18F6410 8192 PIC18F8310 4096 PIC18F8410 8192
Ports Ports Ports Ports
MSSP, AUSART MSSP, AUSART MSSP, AUSART MSSP, AUSART Enhanced USART Enhanced USART Enhanced USART Enhanced USART Input Channels Input Channels Input Channels Input Channels POR, BOR, RESET POR, BOR, RESET POR, BOR, RESET POR, BOR, RESET Instruction, Instruction, Instruction, Instruction, Stack Full, Stack Full, Stack Full, Stack Full, Stack Underflow Stack Underflow Stack Underflow Stack Underflow (PWRT, OST), (PWRT, OST), (PWRT, OST), (PWRT, OST), MCLR (optional), MCLR (optional), MCLR (optional), MCLR (optional), Instructions; with Extended Instruction enabled 64-pin TQFP Instructions; with Extended Instruction enabled 64-pin TQFP Instructions; with Extended Instruction enabled 80-pin TQFP Instructions; with Extended Instruction enabled 80-pin TQFP
Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction
Packages
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
FIGURE 1-1:
Table Pointer<21> inc/dec logic Program Counter
PCLATU PCLATH
PIC18F6310/6410 (64-PIN) BLOCK DIAGRAM
Data Bus<8> Data Latch Data Memory (8/16 Kbytes) Address Latch Data Address<12> FSR0 FSR1 FSR2 inc/dec logic Access Bank PORTC RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX1/CK1 RC7/RX1/DT1 Instruction Decode Control State Machine Control Signals PRODH PRODL BITOP Multiply ALU<8> PORTF RF0/AN5 RF1/AN6/C2OUT RF2/AN7/C1OUT RF3/AN8 RF4/AN9 RF5/AN10/CVREF RF6/AN11 RF7/SS PORTE RE0/RD RE1/WR RE2/CS RE7/CCP2(1) PORTD RD7/PSP7:RD0/PSP0 PORTB RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3 RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC RB7/KBI3/PGD PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/HLVDIN OSC2/CLKO(3)/RA6 OSC1/CLKI(3)/RA7
Level Stack Address Latch Program Memory (48/64 Kbytes) Data Latch
Table Latch
STKPTR
Latch
Instruction <16>
Address Decode
OSC1(3) OSC2(3) T1OSI T1OSO MCLR(2) VDD,
Internal Oscillator Block INTRC Oscillator Oscillator Single-Supply Programming In-Circuit Debugger
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Fail-Safe Clock Monitor
Precision Band Reference
HLVD
10-bit
Timer0
Timer1
Timer2
Timer3
PORTG RG0/CCP3 RG1/TX2/CK2 RG2/RX2/DT2 RG5(2)/MCLR/VPP
Comparators
CCP1
CCP2
CCP3
MSSP
EUSART1
AUSART2
Note
CCP2 multiplexed with when configuration CCP2MX set, when CCP2MX set. only available when MCLR functionality disabled. OSC1/CLKI OSC2/CLKO only available select oscillator modes when these pins being used digital I/O. Refer Section "Oscillator Configurations" additional information.
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
FIGURE 1-2: PIC18F8310/8410 (80-PIN) BLOCK DIAGRAM
PORTA Data Bus<8> Data Latch Data Memory (8/16 Kbytes) Address Latch Program Counter Data Address<12> STKPTR
Table Pointer<21> inc/dec logic
PCLATU PCLATH
RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/HLVDIN OSC2/CLKO(3)/RA6 OSC1/CLKI(3)/RA7 PORTB RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3/CCP2(1) RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX1/CK1 RC7/RX1/DT1 PORTD
Level Stack System Interface Address Latch Program Memory (48/64 Kbytes) Data Latch
TABLE LATCH
FSR0 FSR1 FSR2 inc/dec logic
Access Bank
LATCH
Instruction <16>
Address Decode
AD15:AD0, A19:A16 (Multiplexed with PORTD, PORTE PORTH)
PORTE
RD7/AD7/PSP7: RD0/AD0/PSP0
State Machine Control Signals
Instruction Decode Control
PRODH PRODL BITOP Multiply ALU<8> PORTF
RE0/AD8/RD RE1/AD9/WR RE2/AD10/CS RE3/AD11 RE4/AD12 RE5/AD13 RE6/AD14 RE7/CCP2(1)/AD15 RF0/AN5 RF1/AN6/C2OUT RF2/AN7/C1OUT RF3/AN8 RF4/AN9 RF5/AN10/CVREF RF6/AN11 RF7/SS
OSC1(3) OSC2
Internal Oscillator Block INTRC Oscillator Oscillator Single-Supply Programming In-Circuit Debugger
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Fail-Safe Clock Monitor
T1OSI T1OSO MCLR(2) VDD,
Precision Band Reference
PORTG RG0/CCP3 RG1/TX2/CK2 RG2/RX2/DT2 RG5(2)/MCLR/VPP PORTH
HLVD
10-bit
RH3/AD19:RH0/AD16 Timer0 Timer1 Timer2 Timer3 PORTJ RJ0/ALE RJ1/OE RJ2/WRL RJ3/WRH RJ4/BA0 RJ5/CE RJ6/LB RJ7/UB RH7:RH4
Comparators
CCP1
CCP2
CCP3
MSSP
EUSART1
AUSART2
Note
CCP2 multiplexing determined settings CCP2MX PM1:PM0 configuration bits. only available when MCLR functionality disabled. OSC1/CLKI OSC2/CLKO only available select oscillator modes when these pins being used digital I/O. Refer Section "Oscillator Configurations" additional information.
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
TABLE 1-2:
Name TQFP RG5/MCLR/VPP MCLR OSC1/CLKI/RA7 OSC1
PIC18F6310/6410 PINOUT DESCRIPTIONS
Number Type Buffer Type Description Master Clear (input) programming voltage (input). Digital input. Master Clear (Reset) input. This active-low Reset device. Programming voltage input.
CLKI
OSC2/CLKO/RA6 OSC2 CLKO
Oscillator crystal external clock input. Oscillator crystal input external clock source input. buffer when configured mode, CMOS otherwise. CMOS External clock source input. Always associated with function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose pin. Oscillator crystal clock output. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. mode, OSC2 outputs CLKO, which frequency OSC1 denotes instruction cycle rate. General purpose pin.
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when configuration CCP2MX set. Alternate assignment CCP2 when configuration CCP2MX cleared.
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
TABLE 1-2:
Name TQFP
PIC18F6310/6410 PINOUT DESCRIPTIONS (CONTINUED)
Number Type Buffer Type Description PORTA bidirectional port.
RA0/AN0 RA1/AN1 RA2/AN2/VREFRA2 VREFRA3/AN3/VREF+ VREF+ RA4/T0CKI T0CKI RA5/AN4/HLVDIN HLVDIN
Analog Analog Digital I/O. Analog input High/Low-Voltage Detect input. OSC2/CLKO/RA6 pin. OSC1/CLKI/RA7 pin. ST/OD Digital I/O. Open-drain when configured output. Timer0 external clock input. Analog Analog Digital I/O. Analog input reference voltage (high) input. Analog Analog Digital I/O. Analog input reference voltage (low) input. Analog Digital I/O. Analog input Analog Digital I/O. Analog input
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when configuration CCP2MX set. Alternate assignment CCP2 when configuration CCP2MX cleared.
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
TABLE 1-2:
Name TQFP
PIC18F6310/6410 PINOUT DESCRIPTIONS (CONTINUED)
Number Type Buffer Type Description PORTB bidirectional port. PORTB software programmed internal weak pull-ups inputs.
RB0/INT0 INT0 RB1/INT1 INT1 RB2/INT2 INT2 RB3/INT3 INT3 RB4/KBI0 KBI0 RB5/KBI1 KBI1 RB6/KBI2/PGC KBI2 RB7/KBI3/PGD KBI3
Digital I/O. Interrupt-on-change pin. In-Circuit Debugger ICSP programming data pin. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger ICSPprogramming clock pin. Digital I/O. Interrupt-on-change pin. Digital I/O. Interrupt-on-change pin. Digital I/O. External interrupt Digital I/O. External interrupt Digital I/O. External interrupt Digital I/O. External interrupt
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when configuration CCP2MX set. Alternate assignment CCP2 when configuration CCP2MX cleared.
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
TABLE 1-2:
Name TQFP
PIC18F6310/6410 PINOUT DESCRIPTIONS (CONTINUED)
Number Type Buffer Type Description PORTC bidirectional port.
RC0/T1OSO/T13CKI T1OSO T13CKI RC1/T1OSI/CCP2 T1OSI CCP2(1) RC2/CCP1 CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX1/CK1 RC7/RX1/DT1
Digital I/O. EUSART1 asynchronous receive. EUSART1 synchronous data (see related TX1/CK1). Digital I/O. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1). Digital I/O. data out. Digital I/O. data data I/O. Digital I/O. Synchronous serial clock input/output SPImode. Synchronous serial clock input/output I2Cmode. Digital I/O. Capture input/Compare output/PWM output. CMOS Digital I/O. Timer1 oscillator input. Capture input/Compare output/PWM output. Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input.
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when configuration CCP2MX set. Alternate assignment CCP2 when configuration CCP2MX cleared.
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
TABLE 1-2:
Name TQFP
PIC18F6310/6410 PINOUT DESCRIPTIONS (CONTINUED)
Number Type Buffer Type Description PORTD bidirectional port.
RD0/PSP0 PSP0 RD1/PSP1 PSP1 RD2/PSP2 PSP2 RD3/PSP3 PSP3 RD4/PSP4 PSP4 RD5/PSP5 PSP5 RD6/PSP6 PSP6 RD7/PSP7 PSP7
Digital I/O. Parallel Slave Port data. Digital I/O. Parallel Slave Port data. Digital I/O. Parallel Slave Port data. Digital I/O. Parallel Slave Port data. Digital I/O. Parallel Slave Port data. Digital I/O. Parallel Slave Port data. Digital I/O. Parallel Slave Port data. Digital I/O. Parallel Slave Port data.
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when configuration CCP2MX set. Alternate assignment CCP2 when configuration CCP2MX cleared.
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
TABLE 1-2:
Name TQFP
PIC18F6310/6410 PINOUT DESCRIPTIONS (CONTINUED)
Number Type Buffer Type Description PORTE bidirectional port.
RE0/RD RE1/WR RE2/CS RE7/CCP2 CCP2(2)
Digital I/O. Capture input/Compare output/PWM output. Digital I/O. Chip select control Parallel Slave Port. Digital I/O. Digital I/O. Digital I/O. Digital I/O. Digital I/O. Write control Parallel Slave Port. Digital I/O. Read control Parallel Slave Port.
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when configuration CCP2MX set. Alternate assignment CCP2 when configuration CCP2MX cleared.
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
TABLE 1-2:
Name TQFP
PIC18F6310/6410 PINOUT DESCRIPTIONS (CONTINUED)
Number Type Buffer Type Description PORTF bidirectional port.
RF0/AN5 RF1/AN6/C2OUT C2OUT RF2/AN7/C1OUT C1OUT RF3/AN8 RF4/AN9 RF5/AN10/CVREF AN10 CVREF RF6/AN11 AN11 RF7/SS
Digital I/O. slave select input. Analog Digital I/O. Analog input Analog Analog Digital I/O. Analog input Comparator reference voltage output. Analog Digital I/O. Analog input Analog Digital I/O. Analog input Analog Digital I/O. Analog input Comparator output. Analog Digital I/O. Analog input Comparator output. Analog Digital I/O. Analog input
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when configuration CCP2MX set. Alternate assignment CCP2 when configuration CCP2MX cleared.
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
TABLE 1-2:
Name TQFP
PIC18F6310/6410 PINOUT DESCRIPTIONS (CONTINUED)
Number Type Buffer Type Description PORTG bidirectional port.
RG0/CCP3 CCP3 RG1/TX2/CK2 RG2/RX2/DT2 AVSS AVDD
Digital I/O. AUSART2 asynchronous receive. AUSART2 synchronous data (see related TX2/CK2). Digital I/O. Digital I/O. RG5/MCLR/VPP pin. Ground reference logic pins. Positive supply logic pins. Ground reference analog modules. Positive supply analog modules. Digital I/O. AUSART2 asynchronous transmit. AUSART2 synchronous clock (see related RX2/DT2). Digital I/O. Capture input/Compare output/PWM output.
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when configuration CCP2MX set. Alternate assignment CCP2 when configuration CCP2MX cleared.
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
TABLE 1-3:
Name TQFP RG5/MCLR/VPP MCLR OSC1/CLKI/RA7 OSC1
PIC18F8310/8410 PINOUT DESCRIPTIONS
Number Type Buffer Type Description Master Clear (input) programming voltage (input). Digital input. Master Clear (Reset) input. This active-low Reset device. Programming voltage input.
CLKI
OSC2/CLKO/RA6 OSC2 CLKO
Oscillator crystal external clock input. Oscillator crystal input external clock source input. buffer when configured mode, CMOS otherwise. CMOS External clock source input. Always associated with function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose pin. Oscillator crystal clock output. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. mode, OSC2 outputs CLKO, which frequency OSC1 denotes instruction cycle rate. General purpose pin.
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Alternate assignment CCP2 when configuration CCP2MX cleared (all operating modes except Microcontroller mode). Default assignment CCP2 operating modes (CCP2MX set). Alternate assignment CCP2 when CCP2MX cleared (Microcontroller mode only).
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
TABLE 1-3:
Name TQFP
PIC18F8310/8410 PINOUT DESCRIPTIONS (CONTINUED)
Number Type Buffer Type Description PORTA bidirectional port.
RA0/AN0 RA1/AN1 RA2/AN2/VREFRA2 VREFRA3/AN3/VREF+ VREF+ RA4/T0CKI T0CKI RA5/AN4/HLVDIN HLVDIN
Analog Analog Digital I/O. Analog input High/Low-Voltage Detect input. OSC2/CLKO/RA6 pin. OSC1/CLKI/RA7 pin. ST/OD Digital I/O. Open-drain when configured output. Timer0 external clock input. Analog Analog Digital I/O. Analog input reference voltage (high) input. Analog Analog Digital I/O. Analog input reference voltage (low) input. Analog Digital I/O. Analog input Analog Digital I/O. Analog input
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Alternate assignment CCP2 when configuration CCP2MX cleared (all operating modes except Microcontroller mode). Default assignment CCP2 operating modes (CCP2MX set). Alternate assignment CCP2 when CCP2MX cleared (Microcontroller mode only).
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
TABLE 1-3:
Name TQFP
PIC18F8310/8410 PINOUT DESCRIPTIONS (CONTINUED)
Number Type Buffer Type Description PORTB bidirectional port. PORTB software programmed internal weak pull-ups inputs.
RB0/INT0 INT0 RB1/INT1 INT1 RB2/INT2 INT2 RB3/INT3/CCP2 INT3 CCP2(1) RB4/KBI0 KBI0 RB5/KBI1 KBI1 RB6/KBI2/PGC KBI2 RB7/KBI3/PGD KBI3
Digital I/O. Interrupt-on-change pin. In-Circuit Debugger ICSP programming data pin. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger ICSPprogramming clock pin. Digital I/O. Interrupt-on-change pin. Digital I/O. Interrupt-on-change pin. Analog Digital I/O. External interrupt Capture input/Compare output/PWM output. Digital I/O. External interrupt Digital I/O. External interrupt Digital I/O. External interrupt
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Alternate assignment CCP2 when configuration CCP2MX cleared (all operating modes except Microcontroller mode). Default assignment CCP2 operating modes (CCP2MX set). Alternate assignment CCP2 when CCP2MX cleared (Microcontroller mode only).
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
TABLE 1-3:
Name TQFP
PIC18F8310/8410 PINOUT DESCRIPTIONS (CONTINUED)
Number Type Buffer Type Description PORTC bidirectional port.
RC0/T1OSO/T13CKI T1OSO T13CKI RC1/T1OSI/CCP2 T1OSI CCP2(2) RC2/CCP1 CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX1/CK1 RC7/RX1/DT1
Digital I/O. EUSART1 asynchronous receive. EUSART1 synchronous data (see related TX1/CK1). Digital I/O. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1). Digital I/O. data out. Digital I/O. data data I/O. Digital I/O. Synchronous serial clock input/output SPImode. Synchronous serial clock input/output I2Cmode. Digital I/O. Capture input/Compare output/PWM output. CMOS Digital I/O. Timer1 oscillator input. Capture input/Compare output/PWM output. Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input.
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Alternate assignment CCP2 when configuration CCP2MX cleared (all operating modes except Microcontroller mode). Default assignment CCP2 operating modes (CCP2MX set). Alternate assignment CCP2 when CCP2MX cleared (Microcontroller mode only).
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
TABLE 1-3:
Name TQFP
PIC18F8310/8410 PINOUT DESCRIPTIONS (CONTINUED)
Number Type Buffer Type Description PORTD bidirectional port.
RD0/AD0/PSP0 PSP0 RD1/AD1/PSP1 PSP1 RD2/AD2/PSP2 PSP2 RD3/AD3/PSP3 PSP3 RD4/AD4/PSP4 PSP4 RD5/AD5/PSP5 PSP5 RD6/AD6/PSP6 PSP6 RD7/AD7/PSP7 PSP7
Digital I/O. External memory address/data Parallel Slave Port data. Digital I/O. External memory address/data Parallel Slave Port data. Digital I/O. External memory address/data Parallel Slave Port data. Digital I/O. External memory address/data Parallel Slave Port data. Digital I/O. External memory address/data Parallel Slave Port data. Digital I/O. External memory address/data Parallel Slave Port data. Digital I/O. External memory address/data Parallel Slave Port data. Digital I/O. External memory address/data Parallel Slave Port data.
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Alternate assignment CCP2 when configuration CCP2MX cleared (all operating modes except Microcontroller mode). Default assignment CCP2 operating modes (CCP2MX set). Alternate assignment CCP2 when CCP2MX cleared (Microcontroller mode only).
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
TABLE 1-3:
Name TQFP
PIC18F8310/8410 PINOUT DESCRIPTIONS (CONTINUED)
Number Type Buffer Type Description PORTE bidirectional port.
RE0/AD8/RD RE1/AD9/WR RE2/AD10/CS AD10 RE3/AD11 AD11 RE4/AD12 AD12 RE5/AD13 AD13 RE6/AD14 AD14 RE7/CCP2/AD15 CCP2(3) AD15
Digital I/O. Capture input/Compare output/PWM output. External memory address/data Digital I/O. External memory address/data Digital I/O. External memory address/data Digital I/O. External memory address/data Digital I/O. External memory address/data Digital I/O. External memory address/data Chip Select control Parallel Slave Port. Digital I/O. External memory address/data Write control Parallel Slave Port. Digital I/O. External memory address/data Read control Parallel Slave Port.
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Alternate assignment CCP2 when configuration CCP2MX cleared (all operating modes except Microcontroller mode). Default assignment CCP2 operating modes (CCP2MX set). Alternate assignment CCP2 when CCP2MX cleared (Microcontroller mode only).
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
TABLE 1-3:
Name TQFP
PIC18F8310/8410 PINOUT DESCRIPTIONS (CONTINUED)
Number Type Buffer Type Description PORTF bidirectional port.
RF0/AN5 RF1/AN6/C2OUT C2OUT RF2/AN7/C1OUT C1OUT RF3/AN8 RF4/AN9 RF5/AN10/CVREF AN10 CVREF RF6/AN11 AN11 RF7/SS
Digital I/O. slave select input. Analog Digital I/O. Analog input Analog Analog Digital I/O. Analog input Comparator reference voltage output. Analog Digital I/O. Analog input Analog Digital I/O. Analog input Analog Digital I/O. Analog input Comparator output. Analog Digital I/O. Analog input Comparator output. Analog Digital I/O. Analog input
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Alternate assignment CCP2 when configuration CCP2MX cleared (all operating modes except Microcontroller mode). Default assignment CCP2 operating modes (CCP2MX set). Alternate assignment CCP2 when CCP2MX cleared (Microcontroller mode only).
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
TABLE 1-3:
Name TQFP
PIC18F8310/8410 PINOUT DESCRIPTIONS (CONTINUED)
Number Type Buffer Type Description PORTG bidirectional port.
RG0/CCP3 CCP3 RG1/TX2/CK2 RG2/RX2/DT2
Digital I/O. AUSART2 asynchronous receive. AUSART2 synchronous data (see related TX2/CK2). Digital I/O. Digital I/O. RG5/MCLR/VPP pin. PORTH bidirectional port. Digital I/O. AUSART2 asynchronous transmit. AUSART2 synchronous clock (see related RX2/DT2). Digital I/O. Capture input/Compare output/PWM output.
RH0/AD16 AD16 RH1/AD17 AD17 RH2/AD18 AD18 RH3/AD19 AD19
Digital I/O. External memory address/data Digital I/O. Digital I/O. Digital I/O. Digital I/O. Digital I/O. External memory address/data Digital I/O. External memory address/data Digital I/O. External memory address/data
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Alternate assignment CCP2 when configuration CCP2MX cleared (all operating modes except Microcontroller mode). Default assignment CCP2 operating modes (CCP2MX set). Alternate assignment CCP2 when CCP2MX cleared (Microcontroller mode only).
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
TABLE 1-3:
Name TQFP
PIC18F8310/8410 PINOUT DESCRIPTIONS (CONTINUED)
Number Type Buffer Type Description PORTJ bidirectional port.
RJ0/ALE RJ1/OE RJ2/WRL RJ3/WRH RJ4/BA0 RJ5/CE RJ6/LB RJ7/UB AVSS AVDD
Digital I/O. External memory high byte control. Ground reference logic pins. Positive supply logic pins. Ground reference analog modules. Positive supply analog modules. Digital I/O. External memory byte control. Digital External memory chip enable control. Digital I/O. External memory Byte Address control. Digital I/O. External memory write high control. Digital I/O. External memory write control. Digital I/O. External memory output enable. Digital I/O. External memory address latch enable.
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Alternate assignment CCP2 when configuration CCP2MX cleared (all operating modes except Microcontroller mode). Default assignment CCP2 operating modes (CCP2MX set). Alternate assignment CCP2 when CCP2MX cleared (Microcontroller mode only).
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
OSCILLATOR CONFIGURATIONS
Oscillator Types
FIGURE 2-1:
CRYSTAL/CERAMIC RESONATOR OPERATION (XT, HSPLL CONFIGURATION)
OSC1 Internal Logic Sleep
PIC18F6310/6410/8310/8410 devices operated different oscillator modes. user program configuration bits, FOSC3:FOSC0, Configuration Register select these modes: Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator High-Speed Crystal/Resonator with enabled External Resistor/Capacitor with FOSC/4 output RCIO External Resistor/Capacitor with INTIO1 Internal Oscillator with FOSC/4 output INTIO2 Internal Oscillator with External Clock with FOSC/4 output ECIO External Clock with HSPLL
C1(1)
XTAL
RS(2) C2(1) Note OSC2
RF(3)
PIC18FXXXX
Table Table initial values series resistor (RS) required strip crystals. varies with oscillator mode chosen.
TABLE 2-1:
CAPACITOR SELECTION CERAMIC RESONATORS
Typical Capacitor Values Used: Mode Freq 16.0 OSC1 OSC2
Crystal Oscillator/Ceramic Resonators
HSPLL Oscillator modes, crystal ceramic resonator connected OSC1 OSC2 pins establish oscillation. Figure shows connections. oscillator design requires parallel crystal. Note: series crystal give frequency crystal manufacturer's specifications.
Capacitor values design guidance only. These capacitors were tested with resonators listed below basic start-up operation. These values optimized. Different capacitor values required produce acceptable oscillator operation. user should test performance oscillator over expected temperature range application. notes following Table additional information. Resonators Used: 16.0
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
TABLE 2-2: CAPACITOR SELECTION CRYSTAL OSCILLATOR
Crystal Freq Typical Capacitor Values Tested:
Clock from Ext. System Open OSC1
external clock source also connected OSC1 mode, shown Figure 2-2.
FIGURE 2-2:
Type
EXTERNAL CLOCK INPUT OPERATION OSCILLATOR CONFIGURATION)
PIC18FXXXX
OSC2 Mode)
Capacitor values design guidance only. These capacitors were tested with crystals listed below basic start-up operation. These values optimized. Different capacitor values required produce acceptable oscillator operation. user should test performance oscillator over expected temperature range application. notes following this table additional information. Crystals Used:
External Clock Input
ECIO Oscillator modes require external clock source connected OSC1 pin. There oscillator start-up time required after Power-on Reset after exit from Sleep mode. Oscillator mode, oscillator frequency divided available OSC2 pin. This signal used test purposes synchronize other logic. Figure shows connections Oscillator mode.
FIGURE 2-3:
EXTERNAL CLOCK INPUT OPERATION CONFIGURATION)
OSC1/CLKI
Clock from Ext. System
PIC18FXXXX
FOSC/4 OSC2/CLKO
Note Higher capacitance increases stability oscillator, also increases start-up time. When operating below VDD, when using certain ceramic resonators voltage, necessary mode switch crystal oscillator. Since each resonator/crystal characteristics, user should consult resonator/crystal manufacturer appropriate values external components. required avoid overdriving crystals with drive level specification. Always verify oscillator performance over temperature range that expected application.
Clock from Ext. System
ECIO Oscillator mode functions like mode, except that OSC2 becomes additional general purpose pin. becomes PORTA (RA6). Figure shows connections ECIO Oscillator mode.
FIGURE 2-4:
EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION)
OSC1/CLKI
PIC18FXXXX
(OSC2)
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
Oscillator Frequency Multiplier
timing insensitive applications, "RC" "RCIO" device options offer additional cost savings. actual oscillator frequency function several factors: Supply voltage Values external resistor (REXT) capacitor (CEXT) Operating temperature Given same device, operating voltage temperature component values, there will also unit-to-unit frequency variations. These factors such Normal manufacturing variation Difference lead frame capacitance between package types (especially CEXT values) Variations within tolerance limits REXT CEXT Oscillator mode, oscillator frequency divided available OSC2 pin. This signal used test purposes synchronize other logic. Figure shows combination connected. Phase Locked Loop (PLL) circuit provided option users want lower frequency oscillator circuit, clock device highest rated frequency from crystal oscillator. This useful customers concerned with high-frequency crystals, users require higher clock speeds from internal oscillator.
2.5.1
HSPLL OSCILLATOR MODE
HSPLL mode makes Oscillator mode frequencies MHz. then multiplies oscillator output frequency produce internal clock frequency MHz. only available crystal oscillator when FOSC3:FOSC0 configuration bits programmed HSPLL mode 0110).
FIGURE 2-7:
BLOCK DIAGRAM MODE)
Oscillator Enable Enable (from Configuration Register OSC2
Mode Crystal OSC1 Oscillator
FIGURE 2-5:
REXT
OSCILLATOR MODE
FOUT
Phase Comparator
OSC1 CEXT FOSC/4 OSC2/CLKO
Internal Clock
Loop Filter
PIC18FXXXX
SYSCLK
Recommended values: REXT CEXT
RCIO Oscillator mode (Figure 2-6) functions like mode, except that OSC2 becomes additional general purpose pin. becomes PORTA (RA6).
2.5.2
INTOSC
FIGURE 2-6:
REXT
RCIO OSCILLATOR MODE
also available internal oscillator block selected oscillator modes. this configuration, enabled software generates clock output MHz. operation INTOSC with described Section 2.6.4 "PLL INTOSC Modes".
OSC1 CEXT (OSC2)
Internal Clock
PIC18FXXXX
Recommended values: REXT CEXT
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
Internal Oscillator Block
PIC18F6310/6410/8310/8410 devices include internal oscillator block, which generates different clock signals; either used microcontroller's clock source. This eliminate need external oscillator circuits OSC1 and/or OSC2 pins. main output (INTOSC) clock source, which used directly drive device clock. also drives postscaler, which provide range clock frequencies from MHz. INTOSC output enabled when clock frequency from selected. other clock source internal oscillator (INTRC), which provides nominal output. INTRC enabled selected device clock source; also enabled automatically when following enabled: Power-up Timer Fail-Safe Clock Monitor Watchdog Timer Two-Speed Start-up When OSCTUNE register modified, INTOSC INTRC frequencies will begin shifting frequency. INTRC clock will reach frequency within clock cycles (approximately µs). INTOSC clock will stabilize within Code execution continues during this shift. There indication that shift occurred. OSCTUNE register also implements INTSRC PLLEN bits, which control certain features internal oscillator block. INTSRC allows users select which internal oscillator provides clock source when frequency option selected. This covered greater detail Section 2.7.1 "Oscillator Control Register". PLLEN controls operation frequency multiplier, PLL, internal oscillator modes.
2.6.4
INTOSC MODES
frequency multiplier used with internal oscillator block produce faster device clock speeds than normally possible with internal oscillator. When enabled, produces clock speed MHz. Unlike HSPLL mode, controlled through software. control bit, PLLEN (OSCTUNE<6>), used enable disable operation. available when device configured internal oscillator block primary clock source (FOSC3:FOSC0 1001 1000). Additionally, will only function when selected output frequency either (OSCCON<6:4> 110). both these conditions met, disabled. PLLEN control only functional those internal oscillator modes where available. other modes, forced effectively unavailable.
These features discussed greater detail Section 23.0 "Special Features CPU". clock source frequency (INTOSC direct, INTRC direct INTOSC postscaler) selected configuring IRCF bits OSCCON register (Register 2-2).
2.6.1
INTIO MODES
Using internal oscillator clock source eliminates need external oscillator pins, which then used digital I/O. distinct configurations available: INTIO1 mode, OSC2 outputs FOSC/4, while OSC1 functions digital input output. INTIO2 mode, OSC1 functions OSC2 functions RA6, both digital input output.
2.6.5
INTOSC FREQUENCY DRIFT
2.6.2
INTOSC OUTPUT FREQUENCY
internal oscillator block calibrated factory produce INTOSC output frequency MHz. INTRC oscillator operates independently INTOSC source. changes INTOSC across voltage temperature necessarily reflected changes INTRC vice versa.
factory calibrates internal oscillator block output (INTOSC) MHz. However, this frequency drift temperature changes, which affect controller operation variety ways. possible adjust INTOSC frequency modifying value OSTUNE register. This effect INTRC clock source frequency. Tuning INTOSC source requires knowing when make adjustment, which direction should made some cases, large change needed. Three examples follow, other techniques used.
2.6.3
OSCTUNE REGISTER
internal oscillator's output been calibrated factory, adjusted user's application. This done writing OSCTUNE register (Register 2-1). tuning sensitivity constant throughout tuning range.
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
2.6.5.1 Compensating with AUSART
adjustment required when AUSART begins generate framing errors receives data with errors while Asynchronous mode. Framing errors indicate that device clock frequency high; adjust this, decrement value OSTUNE reduce clock frequency. other hand, errors data suggest that clock speed low; compensate, increment OSTUNE increase clock frequency. greater than expected, then internal oscillator block running fast. adjust this, decrement OSCTUNE register.
2.6.5.3
Compensating with Timers
2.6.5.2
Compensating with Timers
This technique compares device clock speed some reference clock. timers used; timer clocked peripheral clock, while other clocked fixed reference source, such Timer1 oscillator. Both timers cleared, timer clocked reference generates interrupts. When interrupt occurs, internally clocked timer read both timers cleared. internally clocked timer value
module free running Timer1 Timer3), clocked internal oscillator block external event with known period (i.e., power frequency). time first event captured CCPRxH:CCPRxL registers recorded. When second event causes capture, time first event subtracted from time second event. Since period external event known, time difference between events calculated. measured time much greater than calculated time, then internal oscillator block running fast; compensate, decrement OSTUNE register. measured time much less than calculated time, then internal oscillator block running slow; compensate, increment OSTUNE register.
REGISTER 2-1:
OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0 INTSRC R/W-0(1) PLLEN(1) R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0
INTSRC: Internal Oscillator Low-Frequency Source Select 31.25 device clock derived from INTOSC source (divide-by-256 enabled) device clock derived directly from INTRC internal oscillator PLLEN: Frequency Multiplier INTOSC Enable bit(1) enabled INTOSC only) disabled Note Available only certain oscillator configurations; otherwise, this unavailable reads `0'. Section 2.6.4 "PLL INTOSC Modes" details.
Unimplemented: Read TUN4:TUN0: Frequency Tuning bits 01111 Maximum frequency 00001 00000 Center frequency. Oscillator module running calibrated frequency. 11111 10000 Minimum frequency Legend: Readable Value Writable Unimplemented bit, read cleared unknown
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
Clock Sources Oscillator Switching
secondary oscillators those external sources connected OSC1 OSC2 pins. These sources continue operate even after controller placed power managed mode. PIC18F6310/6410/8310/8410 devices offer Timer1 oscillator secondary oscillator. This oscillator, power managed modes, often time base functions such real-time clock. Most often, 32.768 watch crystal connected between RC0/T1OSO/T13CKI RC1/T1OSI pins. Like mode oscillator circuit, loading capacitors also connected from each ground. Timer1 oscillator discussed greater detail Section 12.3 "Timer1 Oscillator". addition being primary clock source, internal oscillator block available power managed mode clock source. INTRC source also used clock source several special features, such Fail-Safe Clock Monitor. clock sources PIC18F6310/6410/8310/8410 devices shown Figure 2-8. Section 23.0 "Special Features CPU" configuration register details.
Like previous PIC18 devices, PIC18F6310/6410/8310/8410 family includes feature that allows device clock source switched from main oscillator alternate low-frequency clock source. PIC18F6310/6410/8310/8410 devices offer alternate clock sources. When alternate clock source enabled, various power managed operating modes available. Essentially, there three clock sources these devices: Primary oscillators Secondary oscillators Internal oscillator block primary oscillators include External Crystal Resonator modes, External modes, External Clock modes internal oscillator block. particular mode defined FOSC3:FOSC0 configuration bits. details these modes covered earlier this chapter.
FIGURE 2-8:
PIC18F6310/6410/8310/8410 CLOCK DIAGRAM
PIC18F6X10/8X10
Primary Oscillator
OSC2 Sleep OSC1 Secondary Oscillator T1OSO T1OSCEN Enable Oscillator OSCCON<6:4> Internal Oscillator Block Source INTRC Source OSCTUNE<6>
HSPLL, INTOSC/PLL Peripherals
T1OSI
OSCCON<6:4> Postscaler
Internal Oscillator
T1OSC
IDLEN Clock Control FOSC3:FOSC0 OSCCON<1:0>
(INTOSC)
(INTRC)
OSCTUNE<7>
Clock Source Option other Modules
WDT, PWRT, FSCM Two-Speed Start-up
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
2.7.1 OSCILLATOR CONTROL REGISTER
OSCCON register (Register 2-2) controls several aspects device clock's operation, both full power operation power managed modes. System Clock Select bits, SCS1:SCS0, select clock source. available clock sources primary clock (defined FOSC:FOSC0 configuration bits), secondary clock (Timer1 oscillator) internal oscillator block. clock source changes immediately after more bits written following brief clock transition interval. bits cleared forms Reset. Internal Oscillator Frequency Select bits, IRCF2:IRCF0, select frequency output internal oscillator block drive device clock. choices INTRC source, INTOSC source MHz) frequencies derived from INTOSC postscaler (31.25 MHz). internal oscillator block supplying device clock, changing states these bits will have immediate change internal oscillator's output. When output frequency selected (IRCF2:IRCF0 000), users choose which internal oscillator acts source. This done with INTSRC OSCTUNE register (OSCTUNE<7>). Setting this selects INTOSC 31.25 clock source enabling divide-by-256 output INTOSC postscaler. Clearing INTSRC selects INTRC (nominally kHz) clock source. This option allows users select tunable more precise INTOSC clock source, while maintaining power savings with very clock speed. Regardless setting INTSRC, INTRC always remains clock source features such Watchdog Timer Fail-Safe Clock Monitor. OSTS, IOFS T1RUN bits indicate which clock source currently providing device clock. OSTS indicates that Oscillator Start-up Timer timed primary clock providing device clock primary clock modes. IOFS indicates when internal oscillator block stabilized providing device clock Clock modes. T1RUN (T1CON<6>) indicates when Timer1 oscillator providing device clock secondary clock modes. power managed modes, only these three bits will time. none these bits set, INTRC providing clock, internal oscillator block just started stable. IDLEN determines device goes into Sleep mode Idle modes when SLEEP instruction executed. flag control bits OSCCON register discussed more detail Section "Power Managed Modes". Note Timer1 oscillator must enabled select secondary clock source. Timer1 oscillator enabled setting T1OSCEN Timer1 Control register (T1CON<3>). Timer1 oscillator enabled, then attempt select secondary clock source when executing SLEEP instruction will ignored. recommended that Timer1 oscillator operating stable before executing SLEEP instruction very long delay occur while Timer1 oscillator starts.
2.7.2
OSCILLATOR TRANSITIONS
PIC18F6310/6410/8310/8410 devices contain circuitry prevent clock "glitches" when switching between clock sources. short pause device clock occurs during clock switch. length this pause cycles clock source three four cycles clock source. This formula assumes that clock source stable. Clock transitions discussed greater detail Section 3.1.2 "Entering Power Managed Modes".
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0 IDLEN IDLEN: Idle Enable Device enters Idle mode SLEEP instruction Device enters Sleep mode SLEEP instruction IRCF2:IRCF0: Internal Oscillator Frequency Select bits (INTOSC drives clock directly) MHz(3) (from either INTOSC/256 INTRC directly)(2) OSTS: Oscillator Start-up Time-out Status bit(1) Oscillator Start-up Timer time-out expired; primary oscillator running Oscillator Start-up Timer time-out running; primary oscillator ready IOFS: INTOSC Frequency Stable INTOSC frequency stable INTOSC frequency stable SCS1:SCS0: System Clock Select bits Internal oscillator block Timer1 oscillator Primary oscillator Note Depends state IESO configuration bit. Source selected INTSRC (OSCTUNE<7>), Section 2.6.3 "OSCTUNE Register". Default output frequency INTOSC Reset. Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-1 IRCF2 R/W-0 IRCF1 R/W-0 IRCF0 R(1) OSTS IOFS R/W-0 SCS1 R/W-0 SCS0
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
Effects Power Managed Modes Various Clock Sources Power-up Delays
Power-up delays controlled timers, that external Reset circuitry required most applications. delays ensure that device kept Reset until device power supply stable under normal circumstances primary clock operating stable. additional information power-up delays, Section "Device Reset Timers". first timer Power-up Timer (PWRT), which provides fixed delay power-up (parameter Table 26-12). enabled clearing PWRTEN configuration bit. second timer Oscillator Start-up Timer (OST), intended keep chip Reset until crystal oscillator stable (LP, modes). does this counting 1024 oscillator cycles before allowing oscillator clock device. When HSPLL Oscillator mode selected, device kept Reset additional following mode delay, lock incoming clock frequency. There delay interval TCSD (parameter Table 26-12) following while controller becomes ready execute instructions. This delay runs concurrently with other delays. This only delay that occurs when INTIO modes used primary clock source.
When PRI_IDLE mode selected, designated primary oscillator continues without interruption. other power managed modes, oscillator using OSC1 disabled. OSC1 (and OSC2 pin, used oscillator) will stop oscillating. Secondary Clock modes (SEC_RUN SEC_IDLE), Timer1 oscillator operating providing device clock. Timer1 oscillator also power managed modes required clock Timer1 Timer3. Internal Oscillator modes (RC_RUN RC_IDLE), internal oscillator block provides device clock source. INTRC output used directly provide clock enabled support various special features, regardless power managed mode (see Section 23.2 "Watchdog Timer (WDT)" through Section 23.4 "Fail-Safe Clock Monitor" more information WDT, Fail-Safe Clock Monitor Two-Speed Start-up). INTOSC output used directly clock device, divided down postscaler. INTOSC output disabled clock provided directly from INTRC output. Sleep mode selected, clock sources stopped. Since transistor switching currents have been stopped, Sleep mode achieves lowest current consumption device (only leakage currents). Enabling on-chip feature that will operate during Sleep will increase current consumed during Sleep. INTRC required support operation. Timer1 oscillator operating support real-time clock. Other features operating that require device clock source (i.e., slave, PSP, INTn pins others). Peripherals that significant current consumption listed Section 26.2 Characteristics: Power-Down Supply Current".
TABLE 2-3:
INTIO1 RCIO, INTIO2 ECIO Note:
OSC1 OSC2 STATES SLEEP MODE
OSC1 Floating, external resistor should pull high Floating, external resistor should pull high Floating, pulled external clock Floating, pulled external clock Feedback inverter disabled quiescent voltage level OSC2 logic (clock/4 output) Configured PORTA, Configured PORTA, logic (clock/4 output) Feedback inverter disabled quiescent voltage level
Oscillator Mode
Table Section "Reset" time-outs Sleep MCLR Reset.
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
NOTES:
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
POWER MANAGED MODES
3.1.1 CLOCK SOURCES
PIC18F6310/6410/8310/8410 devices offer total seven operating modes more efficient power management. These modes provide variety options selective power conservation applications where resources limited (i.e., battery-powered devices). There three categories power managed modes: Sleep mode Idle modes modes These categories define which portions device clocked sometimes, what speed. Idle modes three available clock sources (primary, secondary INTOSC multiplexer); Sleep mode does clock source. power managed modes include several power-saving features. these clock switching feature, offered other PIC18 devices, allowing controller Timer1 oscillator place primary oscillator. Also included Sleep mode, offered PICmicro® devices, where device clocks stopped. SCS1:SCS0 bits allow selection three clock sources power managed modes. They are: primary clock, defined FOSC3:FOSC0 configuration bits secondary clock (the Timer1 oscillator) internal oscillator block (for modes)
3.1.2
ENTERING POWER MANAGED MODES
Entering Power Managed mode, switching from power managed mode another, begins loading OSCCON register. SCS1:SCS0 bits select clock source determine which Idle mode being used. Changing these bits causes immediate switch clock source, assuming that running. switch also subject clock transition delays. These discussed Section 3.1.3 "Clock Transitions Status Indicators" subsequent sections. Entry Power Managed Idle Sleep modes triggered execution SLEEP instruction. actual mode that results depends status IDLEN bit. Depending current mode mode being switched change power managed mode does always require setting these bits. Many transitions done changing oscillator select bits, changing IDLEN prior issuing SLEEP instruction. IDLEN already configured correctly, only necessary perform SLEEP instruction switch desired mode.
Selecting Power Managed Modes
Selecting power managed mode requires deciding clocked selecting clock source. IDLEN controls clocking, while SCS1:SCS0 bits select clock source. individual modes, settings, clock sources affected modules summarized Table 3-1.
TABLE 3-1:
Mode
POWER MANAGED MODES
OSCCON bits IDLEN(1) SCS1:SCS0 <1:0> Module Clocking Available Clock Oscillator Source Clocked Clocked Clocked Peripherals Clocked Clocked Clocked Clocked Clocked Clocked None clocks disabled Primary HSPLL, INTRC(2) This normal full power execution mode. Secondary Timer1 Oscillator Internal Oscillator Block(2) Primary HSPLL, Secondary Timer1 Oscillator Internal Oscillator Block(2)
Sleep PRI_RUN SEC_RUN RC_RUN PRI_IDLE SEC_IDLE RC_IDLE Note
IDLEN reflects value when SLEEP instruction executed. Includes INTOSC INTOSC postscaler, well INTRC source.
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
3.1.3 CLOCK TRANSITIONS STATUS INDICATORS
Modes
length transition between clock sources cycles clock source three four cycles clock source. This formula assumes that clock source stable. Three bits indicate current clock source status. They are: OSTS (OSCCON<3>) IOFS (OSCCON<2>) T1RUN (T1CON<6>) general, only these bits will while given power managed mode. When OSTS set, primary clock providing device clock. When IOFS set, INTOSC output providing stable clock source divider that actually drives device clock. When T1RUN set, Timer1 oscillator providing clock. none these bits set, then either INTRC clock source clocking device INTOSC source stable. internal oscillator block configured primary clock source FOSC3:FOSC0 configuration bits, then both OSTS IOFS bits when PRI_RUN PRI_IDLE modes. This indicates that primary clock (INTOSC output) generating stable output. Entering another Power Managed mode same frequency would clear OSTS bit. Note Caution should used when modifying single IRCF bit. less than possible select higher clock speed than supported VDD. Improper device operation result VDD/FOSC specifications violated. Executing SLEEP instruction does necessarily place device into Sleep mode. acts trigger place controller into either Sleep mode Idle modes, depending setting IDLEN bit.
modes, clocks both core peripherals active. difference between these modes clock source.
3.2.1
PRI_RUN MODE
PRI_RUN mode normal full power execution mode microcontroller. This also default mode upon device Reset unless Two-Speed Start-up enabled (see Section 23.3 "Two-Speed Start-up" details). this mode, OSTS set. IOFS internal oscillator block primary clock source (see Section 2.7.1 "Oscillator Control Register").
3.2.2
SEC_RUN MODE
SEC_RUN mode compatible mode "clock switching" feature offered other PIC18 devices. this mode, peripherals clocked from Timer1 oscillator. This gives users option lower power consumption while still using high accuracy clock source. SEC_RUN mode entered setting SCS1:SCS0 bits `01'. device clock source switched Timer1 oscillator (see Figure 3-1), primary oscillator shut down, T1RUN (T1CON<6>) OSTS cleared. Note: Timer1 oscillator should already running prior entering SEC_RUN mode. T1OSCEN when SCS1:SCS0 bits `01', entry SEC_RUN mode will occur. Timer1 oscillator enabled, running, peripheral clocks will delayed until oscillator started; such situations, initial oscillator operation from stable unpredictable operation result.
3.1.4
MULTIPLE SLEEP COMMANDS
power managed mode that invoked with SLEEP instruction determined setting IDLEN time instruction executed. another SLEEP instruction executed, device will enter power managed mode specified IDLEN that time. IDLEN changed, device will enter power managed mode specified setting.
transitions from SEC_RUN mode PRI_RUN, peripherals continue clocked from Timer1 oscillator while primary clock started. When primary clock becomes ready, clock switch back primary clock occurs (see Figure 3-2). When clock switch complete, T1RUN cleared, OSTS primary clock providing clock. IDLEN bits affected wake-up; Timer1 oscillator continues run.
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
FIGURE 3-1: TRANSITION TIMING ENTRY SEC_RUN MODE
T1OSI OSC1 Clock Peripheral Clock Program Counter Clock Transition
FIGURE 3-2:
TRANSITION TIMING FROM SEC_RUN MODE PRI_RUN MODE (HSPLL)
T1OSI OSC1 TOST(1) TPLL(1) Clock Transition
Clock Output
Clock Peripheral Clock Program Counter SCS1:SCS0 bits Changed OSTS
Note TOST 1024 TOSC; TPLL (approx). These intervals shown scale.
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
3.2.3 RC_RUN MODE
RC_RUN mode, peripherals clocked from internal oscillator block using INTOSC multiplexer primary clock shut down. When using INTRC source, this mode provides best power conservation modes, while still executing code. works well user applications which highly timing sensitive, require high-speed clocks times. primary clock source internal oscillator block (either INTRC INTOSC), there distinguishable differences between PRI_RUN RC_RUN modes during execution. However, clock switch delay will occur during entry exit from RC_RUN mode. Therefore, primary clock source internal oscillator block, RC_RUN mode recommended. This mode entered setting SCS1 `1'. Although ignored, recommended that SCS0 also cleared; this maintain software compatibility with future devices. When clock source switched INTOSC multiplexer (see Figure 3-3), primary oscillator shut down OSTS cleared.The IRCF bits modified time immediately change clock speed. Note: Caution should used when modifying single IRCF bit. less than possible select higher clock speed than supported VDD. Improper device operation result VDD/FOSC specifications violated. IRCF bits INTSRC clear, INTOSC output enabled IOFS will remain clear; there will indication current clock source. INTRC source providing device clocks. IRCF bits changed from clear (thus, enabling INTOSC output), INTSRC set, IOFS becomes after INTOSC output becomes stable. Clocks device continue while INTOSC source stabilizes after interval TIOBST. IRCF bits were previously non-zero value, INTSRC before setting SCS1 INTOSC source already stable, IOFS will remain set. transitions from RC_RUN mode PRI_RUN, device continues clocked from INTOSC multiplexer while primary clock started. When primary clock becomes ready, clock switch primary clock occurs (see Figure 3-4). When clock switch complete, IOFS cleared, OSTS primary clock providing device clock. IDLEN bits affected switch. INTRC source will continue either Fail-Safe Clock Monitor enabled.
FIGURE 3-3:
TRANSITION TIMING RC_RUN MODE
Clock Transition
INTRC OSC1 Clock Peripheral Clock Program Counter
FIGURE 3-4:
INTOSC Multiplexer OSC1
TRANSITION TIMING FROM RC_RUN MODE PRI_RUN MODE
TOST(1) Clock Output Clock Peripheral Clock Program Counter SCS1:SCS0 bits Changed
TPLL(1)
Clock Transition
OSTS
Note TOST 1024 TOSC; TPLL (approx). These intervals shown scale.
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
Sleep Mode Idle Modes
Power Managed Sleep mode PIC18F6310/6410/8310/8410 devices identical Legacy Sleep mode offered other PICmicro® devices. entered clearing IDLEN (the default state device Reset) executing SLEEP instruction. This shuts down selected oscillator (see Figure 3-5). clock source status bits cleared. Entering Sleep mode from other mode does require clock switch. This because clocks needed once controller entered Sleep. selected, INTRC source will continue operate. Timer1 oscillator enabled, will also continue run. When wake event occurs Sleep mode interrupt, Reset time-out), device will clocked until primary clock source becomes ready (see Figure 3-6), will clocked from internal oscillator block either Two-Speed Start-up Fail-Safe Clock Monitor enabled (see Section 23.0 "Special Features CPU"). either case, OSTS when primary clock providing device clocks. IDLEN bits affected wake-up. Idle modes allow controller's selectively shut down while peripherals continue operate. Selecting particular Idle mode allows users further manage power consumption. IDLEN when SLEEP instruction executed, peripherals will clocked from clock source selected using SCS1:SCS0 bits; however, will clocked. clock source status bits affected. Setting IDLEN executing SLEEP provides quick method switching from given mode corresponding Idle mode. selected, INTRC source will continue operate. Timer1 oscillator enabled, will also continue run. Since executing instructions, only exits from Idle modes interrupt, time-out Reset. When wake event occurs, execution delayed interval TCSD (parameter Table 26-12), while becomes ready execute code. When begins executing code, resumes with same clock source current Idle mode. example, when waking from RC_IDLE mode, internal oscillator block will clock peripherals other words, RC_RUN mode). IDLEN bits affected wake-up. While Idle mode Sleep mode, time-out will result wake-up mode currently specified SCS1:SCS0 bits.
FIGURE 3-5:
OSC1 Clock Peripheral Clock Sleep Program Counter
TRANSITION TIMING ENTRY SLEEP MODE
FIGURE 3-6:
OSC1 Clock Output Clock Peripheral Clock Program Counter
TRANSITION TIMING WAKE FROM SLEEP (HSPLL)
TOST(1)
TPLL(1)
Wake Event OSTS
Note TOST 1024 TOSC; TPLL (approx). These intervals shown scale.
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
3.4.1 PRI_IDLE MODE
This mode unique among three Low-Power Idle modes, that does disable primary device clock. timing sensitive applications, this allows fastest resumption device operation with more accurate primary clock source, since clock source does have "warm transition from another oscillator. PRI_IDLE mode entered from PRI_RUN mode setting IDLEN executing SLEEP instruction. device another mode, IDLEN first, then clear bits execute SLEEP. Although disabled, peripherals continue clocked from primary clock source specified FOSC3:FOSC0 configuration bits. OSTS remains (see Figure 3-7). When wake event occurs, clocked from primary clock source. delay interval TCSD required between wake event when code execution starts. This required allow become ready execute instructions. After wake-up, OSTS remains set. IDLEN bits affected wake-up (see Figure 3-8).
FIGURE 3-7:
TRANSITION TIMING ENTRY PRI_IDLE MODE
OSC1 Clock Peripheral Clock Program Counter
FIGURE 3-8:
OSC1
TRANSITION TIMING WAKE FROM IDLE MODE
TCSD Clock Peripheral Clock Program Counter Wake Event
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
3.4.2 SEC_IDLE MODE 3.4.3 RC_IDLE MODE
SEC_IDLE mode, disabled, peripherals continue clocked from Timer1 oscillator. This mode entered from SEC_RUN setting IDLEN executing SLEEP instruction. device another mode, IDLEN first, then SCS1:SCS0 `01' execute SLEEP. When clock source switched Timer1 oscillator, primary oscillator shut down, OSTS cleared T1RUN set. When wake event occurs, peripherals continue clocked from Timer1 oscillator. After interval TCSD following wake event, begins executing code being clocked Timer1 oscillator. IDLEN bits affected wake-up; Timer1 oscillator continues (see Figure 3-8). Note: Timer1 oscillator should already running prior entering SEC_IDLE mode. T1OSCEN when SLEEP instruction executed, SLEEP instruction will ignored entry SEC_IDLE mode will occur. Timer1 oscillator enabled, running, peripheral clocks will delayed until oscillator started. such situations, initial oscillator operation from stable unpredictable operation result. RC_IDLE mode, disabled, peripherals continue clocked from internal oscillator block using INTOSC multiplexer. This mode allows controllable power conservation during Idle periods. From RC_RUN, this mode entered setting IDLEN executing SLEEP instruction. device another mode, first IDLEN, then SCS1 execute SLEEP. Although value ignored, recommended that SCS0 also cleared; this maintain software compatibility with future devices. INTOSC multiplexer used select higher clock frequency modifying IRCF bits before executing SLEEP instruction. When clock source switched INTOSC multiplexer, primary oscillator shut down OSTS cleared. IRCF bits non-zero value, INTSRC set, INTOSC output enabled. IOFS becomes after INTOSC output becomes stable, after interval TIOBST (parameter Table 26-12). Clocks peripherals continue while INTOSC source stabilizes. IRCF bits were previously non-zero value, INTSRC before SLEEP instruction executed INTOSC source already stable, IOFS will remain set. IRCF bits INTSRC clear, INTOSC output will enabled; IOFS will remain clear there will indication current clock source. When wake event occurs, peripherals continue clocked from INTOSC multiplexer. After delay TCSD following wake event, begins executing code, being clocked INTOSC multiplexer. IDLEN bits affected wake-up. INTRC source will continue either Fail-Safe Clock Monitor enabled.
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
Exiting Idle Sleep Modes
3.5.3 EXIT RESET
exit from Sleep mode Idle modes triggered interrupt, Reset time-out. This section discusses triggers that cause exits from power managed modes. clocking subsystem actions discussed each power managed modes (see Section "Run Modes" through Section "Idle Modes"). Normally, device held Reset Oscillator Start-up Timer (OST) until primary clock becomes ready. that time, OSTS device begins executing code. internal oscillator block clock source, IOFS instead. exit delay time from Reset start code execution depends both clock sources before after wake-up type oscillator clock source primary clock. Exit delays summarized Table 3-2. Code execution begin before primary clock becomes ready. either Two-Speed Start-up (see Section 23.3 "Two-Speed Start-up") Fail-Safe Clock Monitor (see Section 23.4 "Fail-Safe Clock Monitor") enabled, device begin execution soon Reset source cleared. Execution clocked INTOSC multiplexer driven internal oscillator block. Execution clocked internal oscillator block until either primary clock becomes ready, power managed mode entered before primary clock becomes ready; primary clock then shut down.
3.5.1
EXIT INTERRUPT
available interrupt sources cause device exit from Idle Sleep mode mode. enable this functionality, interrupt source must enabled setting enable INTCON registers. exit sequence initiated when corresponding interrupt flag set. exits from Idle Sleep modes interrupt, code execution branches interrupt vector GIE/GIEH (INTCON<7>) set. Otherwise, code execution continues resumes without branching (see Section "Interrupts"). fixed delay interval TCSD, following wake event, required when leaving Sleep Idle modes. This delay required prepare execution. Instruction execution resumes first clock cycle following this delay.
3.5.4
EXIT WITHOUT OSCILLATOR START-UP DELAY
3.5.2
EXIT TIME-OUT
Certain exits from power managed modes invoke all. There cases: PRI_IDLE mode, where primary clock source stopped; primary clock source HSPLL modes. these instances, primary clock source either does require oscillator start-up delay since already running (PRI_IDLE), normally does require oscillator start-up delay (RC, INTIO Oscillator modes). However, fixed delay interval TCSD, following wake event, still required when leaving Sleep Idle modes allow prepare execution. Instruction execution resumes first clock cycle following this delay.
time-out will cause different actions depending which power managed mode device when time-out occurs. device executing code (all Idle modes Sleep mode), time-out will result exit from power managed mode (see Section "Run Modes" Section "Sleep Mode"). device executing code (all modes), time-out will result Reset (see Section 23.2 "Watchdog Timer (WDT)"). timer postscaler cleared executing SLEEP CLRWDT instruction, losing currently selected clock source Fail-Safe Clock Monitor enabled) modifying IRCF bits OSCCON register internal oscillator block device clock source.
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
TABLE 3-2: EXIT DELAY WAKE-UP RESET FROM SLEEP MODE IDLE MODE CLOCK SOURCES)
Clock Source after Wake-up Primary Device Clock (PRI_IDLE mode) HSPLL INTRC(1) INTOSC(3) T1OSC INTRC
Clock Source before Wake-up
Exit Delay
Clock Ready Status (OSCCON) OSTS
TCSD(2)
IOFS
TOST(4) TOST trc(4) TCSD(2) TIOBST(5) TOST(5) TOST trc(4) TCSD(2) None TOST(4) TOST trc(4) TCSD(2) TIOBST(5)
HSPLL INTRC(1) INTOSC(2) HSPLL INTRC(1) INTOSC(2)
OSTS IOFS OSTS IOFS OSTS IOFS
INTOSC(3)
None (Sleep mode) Note
HSPLL INTRC(1) INTOSC(2)
this instance, refers specifically INTRC clock source. TCSD (parameter required delay when waking from Sleep Idle modes runs concurrently with other required delays (see Section "Idle Modes"). Includes both INTOSC source postscaler derived frequencies. TOST Oscillator Start-up Timer (parameter 32). Lock-out Timer (parameter F12); also designated TPLL. Execution continues during TIOBST (parameter 39), INTOSC stabilization period.
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
NOTES:
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
RESET
RCON Register
PIC18F6310/6410/8310/8410 devices differentiate between various kinds Reset: Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power managed modes Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset Device Reset events tracked through RCON register (Register 4-1). lower five bits register indicate that specific Reset event occurred. most cases, these bits only event must cleared application after event. state these flag bits, taken together, read indicate type Reset that just occurred. This described more detail Section "Reset State Registers". RCON register also control bits setting interrupt priority (IPEN) software control (SBOREN). Interrupt priority discussed Section "Interrupts". covered Section "Brown-out Reset (BOR)".
This section discusses Resets generated MCLR, covers operation various start-up timers. Stack Reset events covered Section 5.1.3.4 "Stack Full Underflow Resets". Resets covered Section 23.2 "Watchdog Timer (WDT)". simplified block diagram On-Chip Reset Circuit shown Figure 4-1.
FIGURE 4-1:
RESET Instruction Stack Pointer
SIMPLIFIED BLOCK DIAGRAM ON-CHIP RESET CIRCUIT
Stack Full/Underflow Reset
External Reset MCLRE MCLR )_IDLE Sleep Time-out Rise Detect Brown-out Reset BOREN OST/PWRT OSC1 INTRC(1) 1024 Cycles 10-bit Ripple Counter Chip_Reset Pulse
PWRT
65.5
11-bit Ripple Counter Enable PWRT Enable OST(2)
Note
This INTRC source from internal oscillator block separate from oscillator CLKI pin. Table time-out situations.
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
REGISTER 4-1: RCON: RESET CONTROL REGISTER
R/W-0 IPEN IPEN: Interrupt Priority Enable Enable priority levels interrupts Disable priority levels interrupts (PIC16CXXX Compatibility mode) SBOREN: Software Enable BOREN1:BOREN0 enabled disabled BOREN1:BOREN0 disabled read `0'. Note SBOREN enabled, Reset state `1'; otherwise, `0'. Unimplemented: Read RESET Instruction Flag RESET instruction executed (set firmware only) RESET instruction executed causing device Reset (must software after Brown-out Reset occurs) Watchdog Timer Time-out Flag power-up, CLRWDT instruction SLEEP instruction time-out occurred Power-Down Detection Flag power-up CLRWDT instruction execution SLEEP instruction POR: Power-on Reset Status Power-on Reset occurred (set firmware only) Power-on Reset occurred (must software after Power-on Reset occurs) BOR: Brown-out Reset Status Brown-out Reset occurred (set firmware only) Brown-out Reset occurred (must software after Brown-out Reset occurs) Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-1(1) SBOREN R/W-1 R/W-0 R/W-0
Note recommended that after Power-on Reset been detected, that subsequent Power-on Resets detected. Brown-out Reset said have occurred when (assuming that software immediately after POR).
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
Master Clear (MCLR)
FIGURE 4-2:
MCLR provides method triggering hard external Reset device. Reset generated holding low. PIC18 Extended devices have noise filter MCLR Reset path which detects ignores small pulses. MCLR driven internal Resets, including WDT. PIC18F6310/6410/8310/8410 devices, MCLR input disabled with MCLRE configuration bit. When MCLR disabled, becomes digital input. Section 10.7 "PORTG, TRISG LATG Registers" more information.
EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW POWER-UP)
MCLR
PIC18FXXXX
Note
Power-on Reset (POR)
Power-on Reset pulse generated on-chip whenever rises above certain threshold. This allows device start initialized state when adequate operation. take advantage circuitry, MCLR through resistor VDD. This will eliminate external components usually needed create Power-on Reset delay. minimum rise rate specified (parameter D004). slow rise time, Figure 4-2. When device starts normal operation (i.e., exits Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must ensure operation. these conditions met, device must held Reset until operating conditions met. events captured (RCON<1>). state whenever occurs; does change other Reset event. reset hardware event. capture multiple events, user manually resets software following POR.
External Power-on Reset circuit required only power-up slope slow. diode helps discharge capacitor quickly when powers down. recommended make sure that voltage drop across does violate device's electrical specification. will limit current flowing into MCLR from external capacitor event MCLR/VPP breakdown, Electrostatic Discharge (ESD) Electrical Overstress (EOS).
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
Brown-out Reset (BOR)
PIC18F6310/6410/8310/8410 devices implement circuit that provides user with number configuration power-saving options. controlled BORV1:BORV0 BOREN1:BOREN0 configuration bits. There total four configurations, which summarized Table 4-1. threshold BORV1:BORV0 bits. enabled (any values BOREN1:BOREN0 except `00'), drop below VBOR (parameter D005) greater than TBOR (parameter will reset device. Reset occur falls below VBOR less than TBOR. chip will remain Brown-out Reset until rises above VBOR. Power-up Timer enabled, will invoked after rises above VBOR; then will keep chip Reset additional time delay, TPWRT (parameter 33). drops below VBOR while Power-up Timer running, chip will back into Brown-out Reset Power-up Timer will initialized. Once rises above VBOR, Power-up Timer will execute additional time delay. Power-up Timer (PWRT) independently configured. Enabling Reset does automatically enable PWRT. Placing under software control gives user additional flexibility tailoring application environment without having reprogram device change configuration. also allows user tailor device power consumption software eliminating incremental current that consumes. While current typically very small, have some impact low-power applications. Note: Even when under software control, Reset voltage level still BORV1:BORV0 configuration bits. cannot changed software.
4.4.2
DETECTING
When enabled, always resets event. This makes difficult determine event occurred just reading state alone. more reliable method simultaneously check state both BOR. This assumes that reset software immediately after event. while `1', reliably assumed that event occurred.
4.4.3
DISABLING SLEEP MODE
4.4.1
SOFTWARE ENABLED
When BOREN1:BOREN0 enabled disabled user software. This done with control bit, SBOREN (RCON<6>). Setting SBOREN enables function previously described. Clearing SBOREN disables entirely. SBOREN operates only this mode; otherwise, read `0'.
When BOREN1:BOREN0 remains under hardware control operates previously described. Whenever device enters Sleep mode, however, automatically disabled. When device returns other operating mode, automatically re-enabled. This mode allows applications recover from brown-out situations, while actively executing code, when device requires protection most. same time, saves additional power Sleep mode eliminating small incremental current.
TABLE 4-1:
CONFIGURATIONS
Status SBOREN (RCON<6>) Unavailable Available Unavailable Unavailable Operation disabled; must enabled reprogramming configuration bits. enabled software; operation controlled SBOREN. enabled hardware active during Idle modes, disabled during Sleep mode. enabled hardware; must disabled reprogramming configuration bits.
Configuration BOREN1 BOREN0
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
Device Reset Timers
4.5.3 LOCK TIME-OUT
PIC18F6310/6410/8310/8410 devices incorporate three separate on-chip timers that help regulate Power-on Reset process. Their main function ensure that device clock stable before code executed. These timers are: Power-up Timer (PWRT) Oscillator Start-up Timer (OST) Lock Time-out With enabled mode, time-out sequence following Power-on Reset slightly different from other oscillator modes. separate timer used provide fixed time-out that sufficient lock main oscillator frequency. This lock time-out (TPLL) typically follows oscillator start-up time-out.
4.5.4
TIME-OUT SEQUENCE
4.5.1
POWER-UP TIMER (PWRT)
power-up, time-out sequence follows: After pulse cleared, PWRT time-out invoked enabled). Then, activated.
Power-up Timer (PWRT) PIC18F6310/6410/8310/8410 devices 11-bit counter which uses INTRC source clock input. This yields approximate time interval 2048 65.6 While PWRT counting, device held Reset. power-up time delay depends INTRC clock will vary from chip chip temperature process variation. parameter details. PWRT enabled clearing PWRTEN configuration bit.
total time-out will vary based oscillator configuration status PWRT. Figure 4-3, Figure 4-4, Figure 4-5, Figure Figure depict time-out sequences power-up, with Power-up Timer enabled device operating Oscillator mode. Figures through also apply devices operating modes. devices mode with PWRT disabled, other hand, there will time-out all. Since time-outs occur from pulse, MCLR kept long enough, time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 4-5). This useful testing purposes synchronize more than PIC18FXXXX device operating parallel.
4.5.2
OSCILLATOR START-UP TIMER (OST)
Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after PWRT delay over (parameter 33). This ensures that crystal oscillator resonator started stabilized. time-out invoked only HSPLL modes only Power-on Reset, exit from most power managed modes.
TABLE 4-2:
TIME-OUT VARIOUS SITUATIONS
Power-up(2) Brown-out PWRTEN ms(1) 1024 TOSC ms(1) ms(1) ms(1) ms(2) ms(1) 1024 TOSC PWRTEN 1024 TOSC ms(2) 1024 TOSC Exit from Power Managed Mode 1024 TOSC ms(2) 1024 TOSC
Oscillator Configuration HSPLL ECIO RCIO INTIO1, INTIO2 Note
(65.5 nominal Power-up Timer (PWRT) delay. nominal time required lock.
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
FIGURE 4-3:
MCLR INTERNAL TPWRT PWRT TIME-OUT
TIME-OUT SEQUENCE POWER-UP (MCLR TIED VDD, RISE TPWRT)
TOST
TIME-OUT
INTERNAL RESET
FIGURE 4-4:
TIME-OUT SEQUENCE POWER-UP (MCLR TIED VDD): CASE
MCLR INTERNAL
TPWRT
PWRT TIME-OUT
TOST
TIME-OUT
INTERNAL RESET
FIGURE 4-5:
TIME-OUT SEQUENCE POWER-UP (MCLR TIED VDD): CASE
MCLR INTERNAL TPWRT PWRT TIME-OUT
TOST
TIME-OUT
INTERNAL RESET
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
FIGURE 4-6: SLOW RISE TIME (MCLR TIED VDD, RISE TPWRT)
MCLR INTERNAL TPWRT PWRT TIME-OUT TOST TIME-OUT INTERNAL RESET
FIGURE 4-7:
TIME-OUT SEQUENCE W/PLL ENABLED (MCLR TIED VDD)
MCLR INTERNAL TPWRT PWRT TIME-OUT
TOST TPLL
TIME-OUT
TIME-OUT INTERNAL RESET
Note: TOST 1024 clock cycles. TPLL max. First three stages PWRT timer.
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
Reset State Registers
Most registers unaffected Reset. Their status unknown unchanged other Resets. other registers forced "Reset state" depending type Reset that occurred. Most registers affected wake-up, since this viewed resumption normal operation. Status bits from RCON register, BOR, cleared differently different Reset situations, indicated Table 4-3. These bits used software determine nature Reset. Table describes Reset states Special Function Registers. These categorized Power-on Brown-out Resets, Master Clear Resets wake-ups.
TABLE 4-3:
STATUS BITS, THEIR SIGNIFICANCE INITIALIZATION CONDITION RCON REGISTER
Program Counter 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 2(1) RCON Register SBOREN u(2) u(2) u(2) u(2) u(2) u(2) u(2) u(2) u(2) u(2) u(2) STKPTR Register STKFUL STKUNF
Condition Power-on Reset RESET Instruction Brown-out Reset MCLR Reset during Power Managed Modes MCLR Reset during Power Managed Idle Modes Sleep Time-out during Full Power Power Managed Modes MCLR Reset during Full Power Execution Stack Full Reset (STVREN Stack Underflow Reset (STVREN Stack Underflow Error (not actual Reset, STVREN Time-out during Power Managed Idle Sleep Modes Interrupt Exit from Power Managed Modes
Legend: unchanged Note When wake-up interrupt GIEH GIEL bits set, loaded with interrupt vector (008h 0018h). Reset state unchanged other Resets when software enabled (BOREN1:BOREN0 configuration bits SBOREN Otherwise, Reset state `0'.
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
TABLE 4-4:
Register
INITIALIZATION CONDITIONS REGISTERS
Applicable Devices 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 Power-on Reset, Brown-out Reset 0000 0000 0000 0000 0000 uu-0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 000x 1111 1111 1100 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 MCLR Resets Reset RESET Instruction Stack Resets 0000 0000 0000 0000 0000 00-0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 000u 1111 1111 1100 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 Wake-up Interrupt uuuu(3) uuuu uuuu(3) uuuu uuuu(3) uu-u uuuu(3) uuuu uuuu uuuu 2(2) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(1) uuuu uuuu(1) uuuu uuuu(1) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TOSU TOSH TOSL STKPTR PCLATU PCLATH TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L
Legend: unchanged, unknown, unimplemented bit, read `0', value depends condition. Shaded cells indicate conditions apply designated device. Note more bits INTCONx PIRx registers will affected cause wake-up). When wake-up interrupt GIEL GIEH set, loaded with interrupt vector (0008h 0018h). When wake-up interrupt GIEL GIEH set, TOSU, TOSH TOSL updated with current value STKPTR modified point next location hardware stack. Table Reset value specific condition. Bits PORTA, LATA TRISA enabled depending oscillator mode selected. When enabled PORTA pins, they disabled read `0'.
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
TABLE 4-4:
Register
INITIALIZATION CONDITIONS REGISTERS (CONTINUED)
Applicable Devices 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 Power-on Reset, Brown-out Reset xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx 1111 1111 0100 q000 0101 0q-1 11q0 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1111 1111 -000 0000 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 0-00 0000 MCLR Resets Reset RESET Instruction Stack Resets uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 1111 1111 0100 00q0 0101 0q-q qquu uuuu uuuu uuuu uuuu u0uu uuuu 0000 0000 1111 1111 -000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 0-00 0000 Wake-up Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuqu uuuu uq-u qquu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 1111 1111 -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu
INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON OSCCON HLVDCON WDTCON RCON(4) TMR1H TMR1L T1CON TMR2 T2CON SSPBUF SSPADD SSPSTAT SSPCON1 SSPCON2 ADRESH ADRESL ADCON0 ADCON1 ADCON2
Legend: unchanged, unknown, unimplemented bit, read `0', value depends condition. Shaded cells indicate conditions apply designated device. Note more bits INTCONx PIRx registers will affected cause wake-up). When wake-up interrupt GIEL GIEH set, loaded with interrupt vector (0008h 0018h). When wake-up interrupt GIEL GIEH set, TOSU, TOSH TOSL updated with current value STKPTR modified point next location hardware stack. Table Reset value specific condition. Bits PORTA, LATA TRISA enabled depending oscillator mode selected. When enabled PORTA pins, they disabled read `0'.
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
TABLE 4-4:
Register
INITIALIZATION CONDITIONS REGISTERS (CONTINUED)
Applicable Devices 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 Power-on Reset, Brown-out Reset xxxx xxxx xxxx xxxx 0000 xxxx xxxx xxxx xxxx 0000 xxxx xxxx xxxx xxxx 0000 000- 0000 0000 0111 xxxx xxxx xxxx xxxx 0000 0000 0000 -0000 0000 0000 0000 0000 0000 0000 0010 0000 000x 1111 0000 0000 1111 1111 0000 0000 0000 0000 0-00 00-0 0000 1111 1111 1111 1111 MCLR Resets Reset RESET Instruction Stack Resets uuuu uuuu uuuu uuuu 0000 uuuu uuuu uuuu uuuu 0000 uuuu uuuu uuuu uuuu 0000 000- 0000 0000 0111 uuuu uuuu uuuu uuuu uuuu uuuu 0000 -0000 0000 0000 0000 0000 0000 0000 0010 0000 000x 1111 0000 0000 1111 1111 0000 0000 0000 0000 0-00 00-0 0000 1111 1111 1111 1111 Wake-up Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -u(1) uuuu uuuu(1) uuuu uuuu uuuu uuuu uuuu(1) uuuu uuuu u-uu uu-u uuuu uuuu uuuu uuuu uuuu
CCPR1H CCPR1L CCP1CON CCPR2H CCPR2L CCP2CON CCPR3H CCPR3L CCP3CON CVRCON CMCON TMR3H TMR3L T3CON PSPCON SPBRG1 RCREG1 TXREG1 TXSTA1 RCSTA1 IPR3 PIR3 PIE3 IPR2 PIR2 PIE2 IPR1 PIR1 PIE1 MEMCON OSCTUNE TRISJ TRISH
Legend: unchanged, unknown, unimplemented bit, read `0', value depends condition. Shaded cells indicate conditions apply designated device. Note more bits INTCONx PIRx registers will affected cause wake-up). When wake-up interrupt GIEL GIEH set, loaded with interrupt vector (0008h 0018h). When wake-up interrupt GIEL GIEH set, TOSU, TOSH TOSL updated with current value STKPTR modified point next location hardware stack. Table Reset value specific condition. Bits PORTA, LATA TRISA enabled depending oscillator mode selected. When enabled PORTA pins, they disabled read `0'.
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
TABLE 4-4:
Register
INITIALIZATION CONDITIONS REGISTERS (CONTINUED)
Applicable Devices 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 6X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 8X10 Power-on Reset, Brown-out Reset 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111(5) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx(5) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xx0x 0000(5) 0000 0000 01-0 0-00 0000 0000 0000 0000 0000 0000 0000 0010 0000 000x MCLR Resets Reset RESET Instruction Stack Resets 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111(5) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(5) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu0u 0000(5) 0000 0000 01-0 0-00 0000 0000 0000 0000 0000 0000 0000 0010 0000 000x Wake-up Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(5) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(5) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(5) uuuu uuuu uu-u u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TRISG TRISF TRISE TRISD TRISC TRISB TRISA(5) LATJ LATH LATG LATF LATE LATD LATC LATB LATA
PORTJ PORTH PORTG PORTF PORTE PORTD PORTC PORTB PORTA(5) SPBRGH1 BAUDCON1 SPBRG2 RCREG2 TXREG2 TXSTA2 RCSTA2
Legend: unchanged, unknown, unimplemented bit, read `0', value depends condition. Shaded cells indicate conditions apply designated device. Note more bits INTCONx PIRx registers will affected cause wake-up). When wake-up interrupt GIEL GIEH set, loaded with interrupt vector (0008h 0018h). When wake-up interrupt GIEL GIEH set, TOSU, TOSH TOSL updated with current value STKPTR modified point next location hardware stack. Table Reset value specific condition. Bits PORTA, LATA TRISA enabled depending oscillator mode selected. When enabled PORTA pins, they disabled read `0'.
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
MEMORY ORGANIZATION
Program Memory Organization
There types memory PIC18 Flash Microcontroller devices: Program Memory Data Harvard architecture devices, data program memories separate busses; this allows concurrent access memory spaces. Additional detailed information operation Flash program memory provided Section "Program Memory". PIC18 microcontrollers implement 21-bit program counter, which capable addressing 2-Mbyte program memory space. Accessing location between upper boundary physically implemented memory 2-Mbyte address will return `0's instruction). PIC18F6310 PIC18F8310 each have Kbytes Flash memory store 4,096 single-word instructions. PIC18F6410 PIC18F8410 each have Kbytes Flash memory store 8,192 single-word instructions. PIC18 devices have interrupt vectors. Reset vector address 0000h interrupt vector addresses 0008h 0018h. program memory maps PIC18F6310/6410/8310/8410 devices shown Figure 5-1.
FIGURE 5-1:
PROGRAM MEMORY STACK PIC18F6310/6410/8310/8410 DEVICES
PIC18FX310 PIC18FX410
PC<20:0> CALL,RCALL,RETURN RETFIE,RETLW Stack Level
PC<20:0> CALL,RCALL,RETURN RETFIE,RETLW Stack Level
Stack Level Reset Vector 0000h
Stack Level Reset Vector 0000h
High Priority Interrupt Vector 0008h Priority Interrupt Vector 0018h On-Chip Program Memory 1FFFh 2000h
High Priority Interrupt Vector 0008h Priority Interrupt Vector 0018h
On-Chip Program Memory User Memory Space User Memory Space
3FFFh 4000h Read
Read
1FFFFFh
1FFFFFh
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
5.1.1 PIC18F8310/8410 PROGRAM MEMORY MODES
addition available on-chip FLASH program memory, 80-pin devices this family also address Mbytes external program memory through external memory interface. There four distinct operating modes available controllers: Microprocessor (MP) Microprocessor with Boot Block (MPBB) Extended Microcontroller (EMC) Microcontroller (MC) Extended Microcontroller Mode allows access both internal external program memories single block. device access entire on-chip Flash memory; above this, device accesses external program memory 2-Mbyte program space limit. with Boot Block mode, execution automatically switches between memories required. Microprocessor Mode permits access only external program memory; contents on-chip Flash memory ignored. 21-bit program counter permits access entire 2-Mbyte linear program memory space. Microprocessor with Boot Block Mode accesses on-chip Flash memory from addresses 000000h 0007FFh. Above this, external program memory accessed 2-Mbyte limit. Program execution automatically switches between memories required. modes, microcontroller complete access data RAM. Figure compares memory maps different program memory modes. differences between on-chip external memory access limitations more fully explained Table 5-1.
program memory mode determined setting Least Significant bits CONFIG3L configuration byte, shown Register 5-1. (See also Section 23.1 "Configuration Bits" additional details device configuration bits.) program memory modes operate follows: Microcontroller Mode accesses only on-chip Flash memory. Attempts read above physical limit on-chip Flash (3FFFh) causes read `0's instruction). Microcontroller mode also only operating mode available PIC18F6310 PIC18F6410 devices.
REGISTER 5-1:
CONFIG3L: CONFIGURATION BYTE REGISTER
R/P-1 WAIT R/P-1 R/P-1 R/P-1
WAIT: External Data Wait Enable Wait selections unavailable, device will wait Wait programmed WAIT1 WAIT0 bits MEMCOM register (MEMCOM<5:4>) External Data Width Select 16-bit external data width 8-bit external data width Unimplemented: Read PM1:PM0: Processor Data Memory Mode Select bits Microcontroller mode Microprocessor mode(1) Microcontroller with Boot Block mode(1) Extended Microcontroller mode(1) Note This mode available only PIC18F8410 devices. Legend: Readable Value after erase Programmable Unimplemented bit, read cleared unknown
DS39635A-page
2004 Microchip Technology Inc.
PIC18F6310/6410/8310/8410
FIGURE 5-2: MEMORY MAPS PIC18FX310/X410 PROGRAM MEMORY MODES
Extended Microcontroller Mode(2) 000000h On-Chip Program Memory (Top Memory) (Top Memory) Reads `0's (Top Memory) (Top Memory) On-Chip Program Memory 000000h Microcontroller Mode(1)
External Program Memory
1FFFFFh On-Chip Flash Microprocessor Mode(2)
1FFFFFh External Memory On-Chip Flash
000000h
On-Chip Program Memory access) External Program Memory
Microprocessor with Boot Block Mode(2) On-Chip Program Memory 000000h 0007FFh 000800h access) (Top Memory) External Program Memory
1FFFFFh External Memory Legend: Note On-Chip Flash
1FFFFFh External Memory On-Chip Flash
(Top Memory) represents upper boundary on-chip program memory space (1FFFh PIC18FX310, 3FFFh PIC18FX410). Shaded areas represent unimplemented inaccessible areas, depending mode. This mode only available mode 64-pin devices default 80-pin devices. These modes only available 80-pin devices.
TABLE 5-1:
Operating Mode Microcontroller Extended Microcontroller Microprocessor Microprocessor Boot Block
MEMORY ACCESS PIC18F8310/8410 PROGRAM MEMORY MODES
Internal Program Memory Execution From Access Table Read From Access Table Write Access External Program Memory Execution From Access Table Read From Access Table Write Access
2004 Microchip Technology Inc.
DS39635A-page
PIC18F6310/6410/8310/8410
5.1.2 PROGRA
Other recent searches
W934PJ - W934PJ W934PJ Datasheet
SP6682UEB - SP6682UEB SP6682UEB Datasheet
SJ-870 - SJ-870 SJ-870 Datasheet
LTC3704 - LTC3704 LTC3704 Datasheet
HER101G - HER101G HER101G Datasheet
HER108G - HER108G HER108G Datasheet
FMM4023KE - FMM4023KE FMM4023KE Datasheet
DS9096P - DS9096P DS9096P Datasheet
BDW83C - BDW83C BDW83C Datasheet
BDW84C - BDW84C BDW84C Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
