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M68HC11 M68HC11 Microcontrollers M68HC11RM/D Rev. 4/200


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M68HC11
M68HC11
Microcontrollers
M68HC11RM/D Rev. 4/2002
WWW.MOTOROLA.COM/SEMICONDUCTORS
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M68HC11
provide most up-to-date information, revision documents World Wide will most current. Your printed copy earlier revision. verify have latest information available, refer following revision history table summarizes changes contained this document. your convenience, page number designators have been linked appropriate location.
Motorola Stylized Logo registered trademarks Motorola, Inc. DigitalDNA trademark Motorola, Inc.
Motorola, Inc., 2002
M68HC11 Rev. MOTOROLA
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Revision History
Revision History
Date June, 2001 February, 2002 Revision Level Index Updated Figure 9-4. Baud Rate Control Register (BAUD) Address designation corrected $102B Instruction -Corrected table head from ADCA ADDA Description Reformatted meet current publications standards Page Number(s)
Instruction Corrected table head from ADCA ANDA Instruction -Corrected table heads ASLA (IMM) ASLA (INH) ASLB (DIR) ASLB (INH) Instruction Corrected table heads ASRA (IMM) ASRA (INH) ASRB (DIR) ASRB (INH) April, 2002 Instruction Corrected second table entry Data under BITA (IND,Y) from under BITB (IND,Y) from Instruction Corrected table head from CLRA (IMM) CLRA (INH) CLRB (DIR) CLRB (INH) Instruction Corrected second table entry Data under (IND,X) Instruction Changed designation from
Reference Manual
M68HC11 Rev. MOTOROLA
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Reference Manual M68HC11
List Sections
Section General Description Section Pins Connections
Section Configuration Modes Operation Section On-Chip Memory Section Resets Interrupts Section Central Processor Unit (CPU) Section Parallel Input/Output. Section Synchronous Serial Peripheral Interface Section Asynchronous Serial Communications Interface. Section Main Timer Real-Time Interrupt Section Pulse Accumulator Section Analog-to-Digital Converter System Appendix Instruction Details Appendix Bootloader Listings Index.
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Reference Manual M68HC11
Table Contents
Section General Description
Contents Introduction General Description MC68HC11A8 Programmer's Model Product Derivatives.
Section Pins Connections
Contents Introduction
Packages Names 2.3.1 MC68HC11A8 2.3.2 MC68HC11D3/MC68HC711D3 2.3.3 MC68HC11E9/MC68HC711E9 2.3.4 MC68HC811E2 2.3.5 MC68HC11F1 2.3.6 MC68HC24 Port Replacement Unit Descriptions 2.4.1 Power-Supply Pins (VDD VSS). 2.4.2 Mode Select Pins (MODB/VSTBY MODA/LIR) 2.4.3 Crystal Oscillator Clock Pins (EXTAL, XTAL, 2.4.4 Crystal Oscillator Application Information. 2.4.4.1 Crystals Parallel Resonance. 2.4.4.2 Using Crystal Oscillator Outputs 2.4.4.3 Using External Oscillator 2.4.4.4 AT-Strip versus AT-Cut Crystals 2.4.5 Reset (RESET)
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2.4.6 2.4.7 2.4.8 2.4.9 2.4.10 Interrupt Pins (XIRQ IRQ) Reference Port Pins (VREFL, VREFH, PE7-PE0) Timer Port Pins Serial Port Pins Ports STRA STRB Pins Termination Unused Pins
Avoidance Damage 2.6.1 Latchup 2.6.2 Protective Interface Circuits 2.6.3 Internal Circuitry Digital Input-Only 2.6.4 Internal Circuitry Analog Input-Only Pin. 2.6.5 Internal Circuitry Digital 2.6.6 Internal Circuitry Input/Open-Drain-Output 2.6.7 Internal Circuitry Digital Output-Only 2.6.8 Internal Circuitry MODB/VSTBY 2.6.9 Internal Circuitry IRQ/VPPBULK Typical Expanded Mode System Connections Typical Single-Chip Mode System Connections.
System Development Debug Features 2.9.1 Load Instruction Register (LIR) 2.9.2 Internal Read Visibility (IRV) 2.9.3 MC68HC24 Port Replacement Unit (PRU)
Section Configuration Modes Operation
Contents Introduction
Hardware Mode Selection 3.3.1 Hardware Mode Select Pins. 3.3.2 Mode Control Bits HPRIO Register EEPROM-Based Configuration (CONFIG) Register. 3.4.1 Operation CONFIG Mechanism 3.4.2 CONFIG Register
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Table Contents
Protected Control Register Bits 3.5.1 Mapping Register (INIT) 3.5.2 Protected Control Bits TMSK2 Register 3.5.3 Protected Control Bits OPTION Register Normal Operating Modes .101 3.6.1 Normal Single-Chip Mode 3.6.2 Normal Expanded Mode. Special Operating Modes .102 3.7.1 Testing Functions Control Register (TEST1) 3.7.2 Test-Related Control Bits BAUD Register 3.7.3 Special Test Mode 3.7.4 Special Bootstrap Mode 3.7.4.1 Loading Programs Bootstrap Mode .110 3.7.4.2 Executing User Programs Bootstrap Mode 3.7.4.3 Using Interrupts Bootstrap Mode 3.7.4.4 Bootloader Firmware Options Test Bootstrap Mode Applications Example 3-1: Programming CONFIG (Uses Special Test Mode)
Section On-Chip Memory
Contents Introduction Read-Only Memory (ROM).
Random-Access Memory (RAM) 4.4.1 Remapping Using INIT Register. 4.4.2 Standby Electrically Erasable Programmable (EEPROM) 4.5.1 Logical Physical Organization .127 4.5.2 Basic Operation EEPROM 4.5.3 Systems Operating Below 2-MHz Speed Clock) 4.5.4 EEPROM Programming Register (PPROG)
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4.5.5 4.5.5.1 4.5.5.2 4.5.5.3 4.5.5.4 4.5.5.5 4.5.6 Programming/Erasing Procedures .137 Programming .138 Bulk Erase Erase Byte Erase CONFIG Register. Optional EEPROM Security Mode .140
EEPROM Application Information. 4.6.1 Conditions Practices Avoid 4.6.2 Using EEPROM Select Product Options 4.6.3 Using EEPROM Setpoint Calibration Information 4.6.4 Using EEPROM during Product Development 4.6.5 Logging Data 4.6.6 Self-Adjusting Systems Using EEPROM 4.6.7 Software Methods Extend Life Expectancy
Section Resets Interrupts
Contents Introduction
Initial Conditions Established During Reset 5.3.1 System Initial Conditions 5.3.1.1 Central Processor Unit (CPU) 5.3.1.2 Memory 5.3.1.3 Parallel Input/Output (I/O) .162 5.3.1.4 Timer 5.3.1.5 Real-Time Interrupt 5.3.1.6 Pulse Accumulator 5.3.1.7 Computer Operating Properly (COP) Watchdog 5.3.1.8 Serial Communications Interface (SCI) 5.3.1.9 Serial Peripheral Interface (SPI) .164 5.3.1.10 Analog-to-Digital (A/D) Converter 5.3.1.11 Other System Controls. 5.3.2 CONFIG Register Allows Flexible Configuration 5.3.3 Mode Operation Established 5.3.4 Program Counter Loaded with Reset Vector
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Table Contents
Causes Reset 5.4.1 Power-On Reset (POR) 5.4.2 Watchdog Timer Reset .170 5.4.3 Clock Monitor Reset 5.4.4 External Reset Interrupt Process 5.5.1 Interrupt Recognition Stacking Registers 5.5.2 Selecting Interrupt Vectors 5.5.3 Return from Interrupt
Non-Maskable Interrupts 5.6.1 Non-Maskable Interrupt Request (XIRQ) .186 5.6.2 Illegal Opcode Fetch 5.6.3 Software Interrupt. Maskable Interrupts .190 5.7.1 Condition Code Register 5.7.2 Special Considerations I-Bit-Related Instructions .192 Interrupt Request 5.8.1 Selecting Edge Triggering Level Triggering 5.8.2 Sharing Vector with Handshake Interrupts Interrupts from Internal Peripheral Subsystems 5.9.1 Inhibiting Individual Sources. 5.9.2 Clearing Interrupt Status Flag Bits .195 5.9.3 Automatic Clearing Mechanisms Some Flags.
Section Central Processor Unit (CPU)
Contents Introduction
Programmer's Model 6.3.1 Accumulators 6.3.2 Index Registers 6.3.3 Stack Pointer (SP) 6.3.4 Program Counter (PC) .203 6.3.5 Condition Code Register (CCR)
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Addressing Modes 6.4.1 Immediate (IMM) .206 6.4.2 Extended (EXT) 6.4.3 Direct (DIR) 6.4.4 Indexed (INDX INDY) 6.4.5 Inherent (INH). 6.4.6 Relative (REL) M68HC11 Instruction 6.5.1 Accumulator Memory Instructions 6.5.1.1 Loads, Stores, Transfers. 6.5.1.2 Arithmetic Operations 6.5.1.3 Multiply Divide 6.5.1.4 Logical Operations 6.5.1.5 Data Testing Manipulation 6.5.1.6 Shifts Rotates 6.5.2 Stack Index Register Instructions 6.5.3 Condition Code Register Instructions. 6.5.4 Program Control Instructions .224 6.5.4.1 Branches 6.5.4.2 Jumps 6.5.4.3 Subroutine Calls Returns (BSR, JSR, RTS) 6.5.4.4 Interrupt Handling (RTI, SWI, WAI). 6.5.4.5 Miscellaneous (NOP, STOP, TEST)
Section Parallel Input/Output
Contents Introduction Parallel Overview
Parallel Register Control Explanations .234 7.4.1 Port Registers. 7.4.2 Data Direction Registers
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Detailed Descriptions 7.5.1 Port 7.5.1.1 PA2-PA0 (IC3-IC1) Logic 7.5.1.2 PA6-PA3 (OC5-OC2) Logic 7.5.1.3 (OC1 PAI) Logic 7.5.1.4 Port Idealized Timing 7.5.2 Port 7.5.2.1 Port Logic 7.5.2.2 Port Idealized Timing 7.5.2.3 Special Considerations Port MC68HC24 7.5.3 (STRB) .248 7.5.3.1 (STRB) Logic 7.5.3.2 Special Considerations STRB MC68HC24 7.5.4 Port 7.5.4.1 Port Logic Expanded Modes .251 7.5.4.2 Summary Port Idealized Expanded Mode Timing 7.5.4.3 Port Single-Chip Mode Logic 7.5.4.4 Port Idealized Single-Chip Mode Timing 7.5.4.5 Special Considerations Port MC68HC24 7.5.5 (STRA) 7.5.5.1 (STRA) Logic 7.5.5.2 Special Considerations STRA MC68HC24 7.5.6 Port 7.5.6.1 (RxD) Logic 7.5.6.2 (TxD) Logic 7.5.6.3 (MISO) Logic 7.5.6.4 (MOSI) Logic 7.5.6.5 (SCK) Logic 7.5.6.6 (SS) Logic 7.5.6.7 Idealized Port Timing 7.5.7 Port 7.5.7.1 Port Logic 7.5.7.2 Idealized Port Timing
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Handshake Subsystem 7.6.1 Simple Strobe Mode. 7.6.1.1 Port Strobe Output 7.6.1.2 Port Simple Latching Input 7.6.2 Full-Input Handshake Mode 7.6.3 Full-Output Handshake Mode 7.6.3.1 Normal Output Handshake 7.6.3.2 Three-State Variation Output Handshake .286 7.6.4 Parallel Control Register (PIOC) 7.6.5 Non-Handshake Uses STRA STRB Pins
Section Synchronous Serial Peripheral Interface
Contents Introduction
Transfer Formats 8.3.1 Clock Phase Polarity Controls 8.3.2 CPHA Equals Zero Transfer Format 8.3.3 CPHA Equals Transfer Format. Block Diagram Signals
Registers .298 8.6.1 Port Data Direction Control Register (DDRD). .298 8.6.2 Control Register (SPCR) .300 8.6.3 Status Register (SPSR) System Errors 8.7.1 Mode-Fault Error 8.7.2 Write-Collision Errors. Beginning Ending Transfers 8.8.1 Transfer Beginning Period (Initiation Delay). 8.8.2 Transfer Ending Period Transfers Peripherals with Word Lengths. 8.9.1 Example 8-1: On-Chip Driving MC144110 8.9.2 Example 8-2: Software Driving MC144110
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Section Asynchronous Serial Communications Interface
Contents Introduction
General Description .318 9.3.1 Transmitter Block Diagram. 9.3.2 Receiver Block Diagram.
Registers Control Bits 9.4.1 Port Related Registers Control Bits (PORTD, DDRD, SPCR) 9.4.2 Baud-Rate Control Register (BAUD) 9.4.3 Control Register (SCCR1) 9.4.4 Control Register (SCCR2) 9.4.5 Status Register (SCSR) .333 9.4.6 Data Register (SCDR). Transmitter. 9.5.1 9-Bit Data Modes 9.5.2 Interrupts Status Flags 9.5.3 Send Break. .341 9.5.4 Queued Idle Character .341 9.5.5 Disabling Transmitter 9.5.6 Buffer Logic Receiver. 9.6.1 Data Sampling Technique 9.6.2 Worst-Case Baud-Rate Mismatch 9.6.3 Double-Buffered Operation 9.6.4 Receive Status Flags Interrupts 9.6.5 Receiver Wakeup Operation .356 9.6.5.1 Idle-Line Wakeup 9.6.5.2 Address-Mark Wakeup Baud-Rate Generator 9.7.1 Timing Chain Block Diagram .358 9.7.2 Baud Rates versus Crystal Frequency.
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Timing Details 9.8.1 Operation Transmitter Enabled 9.8.2 TDRE Transfers from SCDR Transmit Shift Register .361 9.8.3 versus Character Completion 9.8.4 RDRF Flag Setting versus Received Character
Section Main Timer Real-Time Interrupt
10.1 10.2
Contents Introduction
10.3 General Description .368 10.3.1 Overall Timer Block Diagram .369 10.3.2 Input-Capture Concept .371 10.3.3 Output-Compare Concept 10.4 Free-Running Counter Prescaler. .373 10.4.1 Overall Clock Divider Structure 10.4.1.1 Prescaler 10.4.1.2 Overflow .380 10.4.1.3 Counter Bypass (Test Mode) 10.4.2 Real-Time Interrupt (RTI) Function .382 10.4.3 Computer Operating Properly (COP) Watchdog Function .386 10.4.4 Tips Clearing Timer Flags .387 10.5 Input-Capture Functions 10.5.1 Programmable Options 10.5.2 Using Input Capture Measure Period Frequency 10.5.3 Using Input Capture Measure Pulse Width 10.5.4 Measuring Very Short Time Periods 10.5.5 Measuring Long Time Periods with Input Capture Overflow 10.5.6 Establishing Relationship between Software Event .405 10.5.7 Other Uses Input-Capture Pins .406
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10.6 Output-Compare Functions 10.6.1 Normal Input/Output Control Using OC5-OC2 10.6.2 Advanced Input/Output Control Using .415 10.6.2.1 Output Compare Controlling Five Pins 10.6.2.2 Output Compares Controlling Pin. 10.6.3 Forced Output Compares. 10.7 10.8 Timing Details Main Timer System Listing Timer Examples
Section Pulse Accumulator
11.1 11.2 Contents Introduction
11.3 General Description .444 11.3.1 Pulse Accumulator Block Diagram .445 11.3.2 Pulse Accumulator Control Status Registers 11.4 Event Counting Mode 11.4.1 Interrupting after Events 11.4.2 Counting More Than Events 11.5 Gated Time Accumulation Mode 11.5.1 Measuring Times Longer Than Range 8-Bit Counter .454 11.5.2 Configuring Interrupt after Specified Time .455 11.6 11.7 Other Uses Timing Details Pulse Accumulator.
Section Analog-to-Digital Converter System
12.1 12.2 12.3 Contents Introduction Charge-Redistribution
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12.4 Converter Implementation MC68HC11A8 .471 12.4.1 MC68HC11A8 Successive-Approximation Converter .471 12.4.2 Charge Pump Resistor-Capacitor (RC) Oscillator 12.4.3 MC68HC11A8 System Control Logic 12.4.4 Control/Status Register (ADCTL) 12.4.5 Result Registers (ADR4-AD1) .478 12.5 Connection Considerations
Appendix Instruction Details
Contents Introduction Nomenclature .488 M68HC11 Instruction
Appendix Bootloader Listings
Bootloader Listings .603
Index
Index
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Reference Manual M68HC11
List Figures
Figure 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23
Title
Page
Block Diagram M68HC11 Programmer's Model Part Numbering. MC68HC11A8 Assignments. MC68HC11D3/711D3 Assignments MC68HC11E9/711E9 Assignments (52-Pin PLCC) MC68HC811E2 Assignments (48-Pin DIP) MC68HC11F1 Assignments (68-Pin PLCC). MC68HC24 Assignments Reduced MODA/LIR Connections Standby MODB/VSTBY Connections High-Frequency Crystal Connections Low-Frequency Crystal Connections Crystal Layout Example Reset Circuit Example Low-Pass Filter Reference Pins CMOS Inverter Internal Circuitry Digital Input-Only Internal Circuitry Analog Input-Only Internal Circuitry Digital Internal Circuitry Input/Open-Drain-Output Internal Circuitry Output-Only Internal Circuitry MODB/VSTBY Internal Circuitry IRQ/VPPBULK Pin. Basic Expanded Mode Connections. Basic Single-Chip Mode Connections
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List Figures
Figure 4-10 4-11 4-12
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Title
Page
Highest Priority I-Bit Interrupt Miscellaneous Register (HPRIO) System Configuration Register (CONFIG) Mapping Register (INIT) Timer Mask Register (TMSK2) System Configuration Option Register (OPTION) Testing Functions Control Register (TEST1) Testing Functions Control Register (BAUD) .107 Schematic Figure Program Check/Change CONFIG Topological Arrangement EEPROM Bytes (MC68HC11A8) .128 Topological Arrangement Bits EEPROM Byte Condensed Schematic EEPROM Array EEPROM Cell Terminology Erasing EEPROM Byte Programming EEPROM Byte Reading EEPROM Byte. EEPROM Programming Register (PPROG). .136 Erase-Before-Write Programming Method Program-More-Zeros Programming Method. .155 Selective-Write Programming Method .155 Composite Programming Method Typical External Reset Circuit. Highest Priority I-Bit Interrupt Miscellaneous Register (HPRIO) Processing Flow Resets .182 Interrupt Priority Resolution Interrupt Source Resolution within SCI. M68HC11 Programmer's Model .199 Parallel Registers Control Bits Logic Registers Control Bits
M68HC11 Rev. MOTOROLA
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Figure 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28
M68HC11 Rev. MOTOROLA
Title
Page
Special Symbols Used Logic Diagrams PA2-PA0 (IC3-IC1) Logic PA6-PA3 (OC5-OC2) Logic (OC1 PAI) Logic. Idealized Port Timing. Port Logic Idealized Port Timing. (STRB) Logic Port Expanded Mode Logic. Summary Idealized Port Expanded Mode Timing. Port Single-Chip Mode Logic Idealized Port Single-Chip Mode Timing. (STRA) Logic (RxD) Logic. (TxD) Logic (MISO) Logic (MOSI) Logic (SCK) Logic (SS) Logic. .275 Idealized Port Timing Port Logic Idealized Port Timing. Idealized Timing Simple Strobe Operations Idealized Timing Full-Input Handshake Idealized Timing Full-Output Handshake Parallel Control Register (PIOC). CPHA Equals Zero Transfer Format CPHA Equals Transfer Format System Block Diagram. Port Data Direction Register (DDRD) Control Register (SPCR) Status Register (SPSR) Delay from Write SPDR Transfer Start (Master). .307 Transfer Ending Master Transfer Ending Slave
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List Figures
Figure 8-10 8-11 8-12 8-13 8-14 8-15 Title Page
Hardware Hookup Examples Register Definitions Variables Examples Example Software Listing) Timing Analysis Example Example Software Listing Timing Analysis Example Transmitter Block Diagram .320 Receiver Block Diagram Port Related Registers Baud Rate Control Register (BAUD) Control Register (SCCR1) Control Register (SCCR2) Status Register (SCSR). Data Register (SCDR) Logic Block Diagram Start Ideal Case Start Noise Case Start Noise Case Start Noise Case Three Start Noise Case Four Start Noise Case Five Start Noise Case Six. Baud-Rate Frequency Tolerance Baud-Rate Generator Block Diagram .359 Transmitter Enable Timing Details Write SCDR Serial Data Start. .362 Ending Details Transmission .364 RDRF Flag-Setting Details Main Timer System Block Diagram Timer Counter (TCNT) Timing Summary Oscillator Divider Signals Major Clock Divider Chains MC68HC11A8 .377 Prescaler Select Bits (PR1 PR0) .379
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9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 10-1 10-2 10-3 10-4 10-5
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List Figures
Figure 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-31 10-32 10-33 10-34 10-35 11-1 11-2 11-3 11-4 11-5
M68HC11 Rev. MOTOROLA
Title
Page
Timer Overflow Interrupt Enable (TOI) Timer Overflow Flag (TOF) Real-Time Interrupt Enable (RTII) .384 Real-Time Interrupt Flag (RTIF) .384 Real-Time Interrupt Rate Select Bits (RTR1 RTR0) .385 Timer Rate Select Bits (CR1 CR0) Input-Capture Registers Input Capture Interrupt Enable Bits (ICxI). Input Capture Flags (ICxF) Timer Control Register (TCTL2) .392 Measuring Period with Input Capture Timing Analysis Example 10-1 Measuring Pulse Width with Input Capture Timing Analysis Example 10-2 Measuring Long Periods with Input Capture Output-Capture Registers. .408 Output Capture Interrupt Enable Bits (OCxI) Output Capture Flags (OCxF). Simple Output-Compare Example Timer Control Register (TCTL1) Generating Square Wave with Output Compare .413 Timing Analysis Example 10-5 Output Compare Mask Register (OC1M) Output Compare Data Register (OC1D) Producing Outputs with OC1, OC2, OC3. Output Compare Force Register (CFORC) Timer Counter Leaves Reset .422 Timer Counter Read Cycle-by-Cycle Analysis Input-Capture Timing Details Output-Compare Timing Details .424 Pulse Accumulator Operating Modes .444 Block Diagram Pulse Accumulator Subsystem. Timer Interrupt Mask Register (TMSK2) Timer Interrupt Flag Register (TFLG2) Pulse Accumulator Control Register (PACTL)
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List Figures
Figure 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 Title Page
Pulse Accumulator Count Register (PACNT) Pulse Accumulator-Related Bits PACTL. Pulse Accumulator Interrupt Enable Bits Pulse Accumulator Interrupt Flags Edge-Detection Timing .456 Enable versus Counting (Gated Accumulation Mode) Timing Details Pulse Accumulator Counter Overflow .457 PACNT Read Write Basic Charge-Redistribution Charge-Redistribution with ±1/2 Quantization Error MC68HC11A8 Sample Mode. System Configuration Options Register (OPTION) Timing Diagram Sequence Four Conversions. Control/Status Register (ADCTL) .476 Electrical Model Input (Sample Mode) Graphic Estimation Analog Sample Level (Case
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List Tables
Table
Title
Page
M68HC11 Family Members Hardware Mode Select Summary. Ports STRA STRB Pins Hardware Mode Select Summary. Watchdog Rates versus Crystal Frequency .100 Bootstrap Mode Pseudo-Vectors Hardware Mode Select Summary. Reset Vector versus Cause Mode Watchdog Rates versus Crystal Frequency .171 Highest Priority Interrupt versus PSEL3-PSEL0 .180 Load, Store, Transfer Instructions Arithmetic Operation Instructions Multiply Divide Instructions .217 Logical Operation Instructions Data Testing Manipulation Instructions Shift Rotate Instructions. Stack Index Register Instructions .221 Condition Code Register Instructions .223 Branch Instructions .225 Jump Instruction Subroutine Call Return Instructions Interrupt Handling Instructions Miscellaneous Instructions
6-10 6-11 6-12 6-13
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List Tables
Table Title Page
Baud Rate Prescale Selects Baud Rate Selects Baud Rates Crystal Frequency, SCP1, SCP0, SCR2-SCR0.
10-1 Crystal Frequency versus Values 10-2 Rates versus RTR1 RTR0 Various Crystal Frequencies 10-3 Timeout versus Values .387 10-4 Instruction Sequences Clear 10-5 EDGxB EDGxA Encoding 10-6 Encoding 11-1 Pulse Accumulator Timing Periods versus Crystal Rate Channel Assignments
12-1
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Section General Description
Contents
Introduction General Description MC68HC11A8 Programmer's Model Product Derivatives.
Introduction
This reference manual valuable development M68HC11 applications. Detailed descriptions internal subsystems functions have been developed carefully checked against internal Motorola design documentation, making this manual most comprehensive reference available M68HC11 Family microcontroller units (MCU). Practical applications included demonstrate operation each subsystem. These applications treated complete systems, including hardware/software interactions tradeoffs. Interfacing techniques prevent component damage discussed hardware designer. software programmers, Section Central Processor Unit (CPU) Appendix Instruction Details contain examples demonstrating efficient instruction set. This manual intended complement Motorola's official data sheet, replace information data sheet current guaranteed production testing. Although information this manual checked against parts design documentation, accuracy guaranteed like data sheet guaranteed. This manual assumes reader some basic knowledge MCUs
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General Description
assembly-language programming; appropriate instruction manual first-time user. information this manual much more detailed than would usually required normal MCU, user familiar with detailed operation part more likely find solution unexpected system problem. many cases, trick based software on-chip resources used rather than building expensive external circuitry. Data sheets geared toward customary, straightforward on-chip peripherals; whereas, experienced user often uses these on-chip systems very unexpected ways. level detail this manual will help normal user better understand on-chip systems will allow more advanced user make maximum subtleties these systems. addition this manual, data sheet(s) technical data needed specific version(s) M68HC11 being used. pocket reference guide another beneficial source.
General Description MC68HC11A8
high-density complementary metal-oxide semiconductor (HCMOS) MC68HC11A8 advanced 8-bit with highly sophisticated, on-chip peripheral capabilities. design techniques were used achieve nominal speed MHz. addition, fully static design allows operation frequencies down further reducing power consumption. HCMOS technology used MC68HC11A8 combines smaller size higher speeds with low-power high-noise immunity CMOS. On-chip memory systems include: Kbytes read-only memory (ROM) bytes electrically erasable programmable (EEPROM) bytes random-access memory (RAM)
Major peripheral functions provided on-chip. 8-channel analog-to-digital (A/D) converter included with eight bits resolution. asynchronous serial communications interface (SCI) separate
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General Description Programmer's Model
synchronous serial peripheral interface (SPI) included. main 16-bit, free-running timer system three input-capture lines, five output-compare lines, real-time interrupt function. 8-bit pulse accumulator subsystem count external events measure external periods. Self-monitoring circuitry included on-chip protect against system errors. computer operating properly (COP) watchdog system protects against software failures. clock monitor system generates system reset case clock lost runs slow. illegal opcode detection circuit provides non-maskable interrupt illegal opcode detected. software-controlled power-saving modes, wait stop, available conserve additional power. These modes make M68HC11 Family especially attractive automotive battery-driven applications. Figure block diagram MC68HC11A8 MCU. This diagram shows major subsystems they relate pins MCU. lower right-hand corner this diagram, parallel input/output (I/O) subsystem shown inside dashed box. functions this subsystem lost when operated expanded modes, MC68HC24 port replacement unit used regain functions that were lost. functions restored such that software programmer unable tell difference between single-chip system expanded system containing MC68HC24. using expanded system containing MC68HC24 external EPROM, user develop software intended single-chip application.
Programmer's Model
addition executing M6800 M6801 instructions, M68HC11 instruction includes opcodes. nomenclature M68xx used conjunction with specific architecture instruction opposed MC68HC11xx nomenclature, which reference specific member M68HC11 Family MCUs.
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General Description
PULSE ACCUMULATOR BYTES TIMER
PORT
PERIODIC INTERRUPT BYTES WATCHDOG
DATA DIRECTION PORT
EEPROM BYTES
MOSI MISO
REFH REFL PORT CONVERTER
M68HC11
RESET XIRQ PPBULK XTAL EXTAL PORT POWER MODA (LIR) MODB STBY MODE SELECT OSCILLATOR INTERRUPTS
ADDRESS/DATA
HANDSHAKE PARALLEL EQUIVALENT MC68HC24 STRB STRA SINGLE CHIP EXPANDED
DATA DIRECTION PORT
Figure 1-1. Block Diagram
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M68HC11 Rev. MOTOROLA
General Description Programmer's Model
Figure shows seven registers available programmer. 8-bit accumulators used some instructions single 16-bit accumulator called register, which allows 16-bit operations even though technically 8-bit processor. largest group instructions added involve index register. Twelve manipulation instructions that operate memory register location were added. exchange with exchange with instructions used quickly index values into double accumulator where 16-bit arithmetic used. 16-bit 16-bit divide instructions also included.
ACCUMULATOR
ACCUMULATOR
DOUBLE ACCUMULATOR INDEX REGISTER INDEX REGISTER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER
CARRY OVERFLOW ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM INTERRUPT MASK STOP DISABLE
Figure 1-2. M68HC11 Programmer's Model
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General Description Product Derivatives
M68HC11 Family MCUs composed product members listed Table 1-1. Figure explains product part numbers constructed. Table 1-1. M68HC11 Family Members
EPROM/OTP EEPROM (KBytes) (Bytes) (KBytes) (Bytes) Timer Operating Frequency Voltage (Max) (MHz) 3.0, 3.0, 3.0, 3.0, 3.0, 3.0,
Product
Serial
MC68HC11D0 MC68HC11D3 MC68HC11E0 MC68HC11E1 MC68HC11E2 MC68HC11E9 MC68HC11E20 MC68HC11F1
2048
8-CH 8-bit 8-CH 8-bit 8-CH 8-bit 8-CH 8-bit 8-CH 8-bit 8-CH 8-bit
MC68HC11K0
4-CH 8-bit 8-CH 8-bit 2-CH 16-bit 4-CH 8-bit 8-CH 8-bit 2-CH 16-bit 4-CH 8-bit 8-CH 8-bit 2-CH 16-bit
3.0,
MC68HC11K1
SCI+
3.0,
MC68HC11K4
SCI+
3.0,
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General Description Product Derivatives
Table 1-1. M68HC11 Family Members (Continued)
EPROM/OTP EEPROM (KBytes) (Bytes) (KBytes) (Bytes) Timer Operating Frequency Voltage (Max) (MHz)
Product
Serial
MC68HC11KS2
SCI+
8-CH 8-bit
MC68HC11KW1
SCI+
4-CH 8-bit 10-CH 10-bit 2-CH 16-bit 4-CH 8-bit 8-CH 8-bit 2-CH 16-bit 4-CH 8-bit 8-CH 8-bit 2-CH 16-bit 8-CH 8-bit 8-CH 8-bit 8-CH 8-bit
MC68HC11P1
Triple
MC68HC11P2
Triple SCI+
MC68HC711D3 MC68HC711E9 MC68HC711E20 MC68HC711KS2
3.0,
M68HC11s include 8-channel 16-bit timer with real-time interrupt pulse accumulator. timers have three input captures, four output compares, eighth channel that configured fourth input capture fifth output compare.
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General Description
11XX
QUALIFICATION LEVEL FULLY SPECIFIED QUALIFIED PILOT PRODUCTION DEVICE ENGINEERING SAMPLE NUMERIC DESIGNATOR (OPTIONAL) OPERATING TEMPERATURE RANGE HCMOS (VDD 10%) HCMOS (VDD VDC) OPTION (ONLY A-SERIES DEVICES) NONE DISABLED ENABLED MEMORY TYPE BLANK MASKED EPROM/OTPROM EEPROM BASE PART NUMBER 11A8, 11D3, 11E9, 11K4, ETC. MONITOR MASK NONE BLANK BUFFALO TEMPERATURE RANGE NONE 70°C -40°C 85°C -40°C 105°C -40°C 125°C PACKAGE TYPE 44/52/68/84-PIN PLCC 44/52/68/84-PIN CLCC 64/80-PIN 44-PIN 122-PIN TCFP 80/100-PIN TCFP 52-PIN TCFP 40/48-PIN 48-PIN SDIP MAXIMUM SPECIFIED CLOCK SPEED TAPE REEL OPTION NONE STANDARD PACKAGING TAPE REEL PACKAGING
Figure 1-3. Part Numbering
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Reference Manual M68HC11
Section Pins Connections
Contents
Introduction
Packages Names 2.3.1 MC68HC11A8 2.3.2 MC68HC11D3/MC68HC711D3 2.3.3 MC68HC11E9/MC68HC711E9 2.3.4 MC68HC811E2 2.3.5 MC68HC11F1 2.3.6 MC68HC24 Port Replacement Unit Descriptions 2.4.1 Power-Supply Pins (VDD VSS). 2.4.2 Mode Select Pins (MODB/VSTBY MODA/LIR) 2.4.3 Crystal Oscillator Clock Pins (EXTAL, XTAL, 2.4.4 Crystal Oscillator Application Information. 2.4.4.1 Crystals Parallel Resonance. 2.4.4.2 Using Crystal Oscillator Outputs 2.4.4.3 Using External Oscillator 2.4.4.4 AT-Strip versus AT-Cut Crystals 2.4.5 Reset (RESET) 2.4.6 Interrupt Pins (XIRQ IRQ) 2.4.7 Reference Port Pins (VREFL, VREFH, PE7-PE0) 2.4.8 Timer Port Pins 2.4.9 Serial Port Pins 2.4.10 Ports STRA STRB Pins Termination Unused Pins
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Avoidance Damage 2.6.1 Latchup 2.6.2 Protective Interface Circuits 2.6.3 Internal Circuitry Digital Input-Only 2.6.4 Internal Circuitry Analog Input-Only Pin. 2.6.5 Internal Circuitry Digital 2.6.6 Internal Circuitry Input/Open-Drain-Output 2.6.7 Internal Circuitry Digital Output-Only 2.6.8 Internal Circuitry MODB/VSTBY 2.6.9 Internal Circuitry IRQ/VPPBULK Typical Expanded Mode System Connections Typical Single-Chip Mode System Connections.
System Development Debug Features 2.9.1 Load Instruction Register (LIR) 2.9.2 Internal Read Visibility (IRV) 2.9.3 MC68HC24 Port Replacement Unit (PRU)
Introduction
This section discusses functions each MC68HC11A8, typical example M68HC11 Family part. Most pins this microcontroller unit (MCU) serve more functions. Information about practical each presented these descriptions. This section also includes information concerning pins that exposed illegal levels conditions. most common source illegal levels conditions transient noise; however, designer want take precautions against potential misapplication product failures other system components such power supplies. Consideration these factors influence end-product reliability. basic connections single-chip mode expanded mode applications presented Typical Single-Chip Mode System Connections Typical Expanded Mode System Connections. These basic systems used starting point user application minimize time required achieve working prototype system. explanation these basic systems includes
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information concerning additions, such additional memory expanded system. System noise generation susceptibility primarily depend each system environment. MC68HC11A8 designed higher speeds than earlier MCUs. Since high-density complementary metal-oxide semiconductor (HCMOS), signals drive from rail rail, unlike earlier N-channel metal-oxide semiconductor (NMOS) processors. Since these factors significantly affect noise issues, system designer should consider these changes.
Packages Names
Figure through Figure show assignments several members M68HC11 Family. assignments MC68HC24 port replacement unit (PRU) also presented reference although discussed detail this manual. Detailed mechanical data packages located data sheets technical summaries individual parts. Ordering information, which relates part number suffixes package types operating temperature range, also found data sheets technical summaries.
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2.3.1 MC68HC11A8 MC68HC11A8 available either 52-pin plastic leaded chip carrier (PLCC) package 48-pin dual-in-line package (DIP). silicon identical both packages, four analog-to-digital (A/D) converter inputs bonded pins 48-pin DIP. MC68HC11A1 MC68HC11A0 devices also same MC68HC11A8, except that contents nonvolatile configuration (CONFIG) register determine whether internal read-only memory (ROM) and/or electrically erasable programmable (EEPROM) disabled. These downgraded device versions have identical assignments MC68HC11A8. Figure shows assignments MC68HC11A8 52-pin PLCC package 48-pin package.
MODA/LIR MODB/VSTBY
STRB/R/W
STRA/AS
PA7/PAI/OC1 PE7/AN7 PE3/AN3 PE6/AN6 PE2/AN2 PA6/OC2/OC1 PA5/OC3/OC1 PA4/OC4/OC1 PE5/AN5 PE1/AN1 PE4/AN4 PE0/AN0 PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/IC3 PA3/OC5/OC1 PA2/IC1 PA1/IC2 PA0/IC3 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 PE0/AN0 PE1/AN1 PE2/AN2 PE3/AN3 MODB
PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TxD PD0/RxD XIRQ RESET PC7/A7/D7 PC6/A6/D6 PC5/A5/D5 PC4/A4/D4 PC3/A3/D3 PC2/A2/D2 PC1/A1/D1 PC0/A0/D0 XTAL EXTAL STRB/R/W STRA/AS MODA/LIR
XTAL PC0/A0/D0 PC1/A1/D1 PC2/A2/D2 PC3/A3/D3 PC4/A4/D4 PC5/A5/D5 PC6/A6/D6 PC7/A7/D7 RESET XIRQ PD0/RxD
EXTAL
MC68HC11A8
MC68HC11A8
PA3/OC5/OC1
PD1/TxD PD2/MISO
PD3/MOSI PD4/SCK
PD5/SS
PA7/PAI/OC1 PA6/OC2/OC1
PA5/OC3/OC1 PA4/OC4/OC1
PA2/IC1
Figure 2-1. MC68HC11A8 Assignments
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PA1/IC2
Pins Connections Packages Names
2.3.2 MC68HC11D3/MC68HC711D3 MC68HC11D3 available either 44-pin PLCC package 40-pin package. silicon identical both packages, PLCC version additional output compare pins bonded extra named EVSS. MC68HC711D3 functionally equivalent MC68HC11D3 four Kbytes erasable programmable (EPROM) instead mask programmed ROM. MC68HC711D3 available one-time-programmable (OTP) opaque plastic package ceramic windowed package development applications. Figure shows assignments MC68HC11D3/ MC68HC711D3 44-pin PLCC package 40-pin package.
MODB/VSTBY
PC3/A3/D3
PC2/A2/D2
PC1/A1/D1
PC0/A0/D0
MODA/LIR
PC0/A0/D0 PC1/A1/D1 PC2/A2/D2 PC3/A3/D3 PC4/A4/D4 PC5/A5/D5 PC6/A6/D6 PC7/A7/D7 XIRQ/VPP PD7/R/W PD6/AS RESET PD0/RxD PD1/TxD PD2/MISO PD3/MOSI PD4/SCK PD5/SS
MC68HC(7)11D3
XTAL EXTAL MODA/LIR MODB/VSTBY PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/IC3 PA1/IC2 PA2/IC1 PA3/IC4/OC5/OC1 PA5/OC3/OC1 PA7/PAI/OC1
EXTAL
XTAL
EVSS
PC4/A4/D4 PC5/A5/D5 PC6/A6/D6 PC7/A7/D7 XIRQ/VPP PD7/R/W PD6/AS RESET PD0/RxD PD1/TxD
PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/IC3 PA1/IC2
MC68HC(7)11D3
PA4/OC4/OC1
PA3/IC4/OC5/OC1
PA6/OC3/OC1
PA5/OC3/OC1
PA7/PAI/OC1
PD2/MISO
PD5/SS
PD3/MOSI
PD4/SCK
Figure 2-2. MC68HC11D3/711D3 Assignments
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PA2/IC1
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2.3.3 MC68HC11E9/MC68HC711E9 MC68HC11E9 available 52-pin PLCC package only. MC68HC11E1 MC68HC11E0 devices also same MC68HC11E9, except that contents nonvolatile CONFIG register determine whether internal and/or EEPROM disabled. These downgraded device versions have identical assignments MC68HC11E9. MC68HC11E9 upgrade MC68HC11A8. MC68HC11E9 Kbytes mask ROM, bytes EEPROM, bytes RAM. timer system allows output-compare channel reconfigured fourth input-capture channel. MC68HC711E9 functionally equivalent MC68HC11E9 Kbytes EPROM instead mask programmed ROM. MC68HC711E9 available one-time-programmable (OTP) opaque plastic package ceramic windowed package development applications. Figure shows assignments MC68HC11E9 52-pin PLCC package. These assignments same MC68HC11A8, except name PA3/IC4/OC5/OC1 pin.
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Pins Connections Packages Names
MODA/LIR MODB/VSTBY
STRB/R/W
STRA/AS
PE7/AN7 PE3/AN3
PE6/AN6
PE2/AN2 PE5/AN5 PE1/AN1 PE4/AN4 PE0/AN0 PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/IC3 PA1/IC2
XTAL PC0/A0/D0 PC1/A1/D1 PC2/A2/D2 PC3/A3/D3 PC4/A4/D4 PC5/A5/D5 PC6/A6/D6 PC7/A7/D7 RESET XIRQ PD0/RxD
EXTAL
MC68HC11E9
PA3/IC4/OC5/OC1
PD1/TxD PD2/MISO
PD3/MOSI PD4/SCK
PA7/PAI/OC1 PA6/OC2/OC1
Figure 2-3. MC68HC11E9/711E9 Assignments (52-Pin PLCC)
2.3.4 MC68HC811E2 MC68HC811E2 very similar MC68HC11E9 version, except on-chip memory. MC68HC811E2 includes Kbytes EEPROM, which remapped upper half 4-Kbyte page Kbyte map. There masked memory MC68HC811E2. MC68HC811E2 available either 52-pin PLCC package 48-pin DIP. silicon used same both packages, four analog-to-digital (A/D) converter inputs bonded pins 48-pin package. MC68HC811E2 version replaces earlier version called MC68HC811A2. only significant difference between MC68HC811E2 MC68HC811A2 that MC68HC811E2 slightly more flexible timer system, which allows output-compare channel reconfigured fourth input-capture channel.
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PA5/OC3/OC1 PA4/OC4/OC1
PA2/IC1
PD5/SS
Reference Manual
Pins Connections
52-pin PLCC package version MC68HC811E2 identical assignments MC68HC11E9 assignments shown Figure 2-3. Figure illustrates assignments MC68HC811E2 48-pin DIP.
PA7/PAI/OC1 PA6/OC2/OC1 PA5/OC3/OC1 PA4/OC4/OC1
PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TxD PD0/RxD XIRQ RESET PC7/A7/D7 PC6/A6/D6 PC5/A5/D5 PC4/A4/D4 PC3/A3/D3 PC2/A2/D2 PC1/A1/D1 PC0/A0/D0 XTAL EXTAL STRB/R/W STRA/AS MODA/LIR
PA3/IC4/OC5/OC1 PA2/IC1 PA1/IC2 PA0/IC3 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 PE0/AN0 PE1/AN1 PE2/AN2 PE3/AN3 MODB
MC68HC811E2
Figure 2-4. MC68HC811E2 Assignments (48-Pin DIP)
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Pins Connections Packages Names
2.3.5 MC68HC11F1 MC68HC11F1 available only 68-pin PLCC package. MC68HC11F1 first non-multiplexed address/data version M68HC11 Family. addition non-multiplexed bus, this includes Kbyte on-chip intelligent chip selects simple connection external program memory without need external logic chips. Other on-chip peripherals similar MC68HC11E9. Figure shows assignments MC68HC11F1 68-pin PLCC package.
MODB/VSTBY
MODA/LIR
PE7/AN7
PE3/AN3
PE6/AN6
PE2/AN2
PE5/AN5
PC1/D1 PC2/D2 PC3/D3 PC4/D4 PC5/D5 PC6/D6 PC7/D7 RESET XIRQ PG7/CSPROG PG6/CSGEN PG5/CSIO1 PG4/CSIO2
PE1/AN1 PE4/AN4 PE0/AN0 PF0/A0 PF1/A1 PF2/A2 PF3/A3 PF4/A4 PF5/A5 PF6/A6 PF7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14
PC0/D0
4XOUT
EXTAL
XTAL
MC68HC11F1
PA0/IC3
PD3/MOSI
PA6/OC2/OC1
PA5/OC3/OC1
PA7/PAI/OC1
PA4/OC4/OC1
PA3/OC5/OC1
PD2/MISO
PD4/SCK
PD0/RxD
PD1/TxD
Figure 2-5. MC68HC11F1 Assignments (68-Pin PLCC)
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PB7/A15
PA2/IC1
PA1/IC2
PD5/SS
Pins Connections
2.3.6 MC68HC24 Port Replacement Unit Though longer production, MC68HC24 used replace functions data address pins emulators. available either 44-pin PLCC package 40-pin DIP. Figure shows assignments MC68HC24 44-pin PLCC package 40-pin package.
TEST MODE TEST RESET STRA STRB MODE RESET
STRA
MC68HC24
MC68HC24
STRB
Figure 2-6. MC68HC24 Assignments
Descriptions
This section provides pin-by-pin description MCU. general, designer should consider possible functions each when designing into application system. Section Parallel Input/Output contains transistor-level schematics logic associated with each pins. Section Configuration Modes Operation discusses pins that operate multiplexed address/data
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expanded modes operation well functions other pins related mode selection control. reset interrupt pins presented again Section Resets Interrupts. These sections discuss pins related on-chip peripherals presented those sections: Section Synchronous Serial Peripheral Interface
Section Asynchronous Serial Communications Interface Section Main Timer Real-Time Interrupt Section Pulse Accumulator Section Analog-to-Digital Converter System Figure 1-1. Block Diagram pin-function-oriented block diagram MC68HC11A8, which good reference development verification application designs.
2.4.1 Power-Supply Pins (VDD VSS) Power supplied using these pins. positive power input, ground. MC68HC11A8 uses single power supply, some applications, there also optional power supplies reference and/or battery backup on-chip random-access memory (RAM). These additional power sources optional, MCU, including A/D, operate from single (nominal) power supply. Although MC68HC11A8 complementary metal-oxide semiconductor (CMOS) device, very fast signal transitions present many pins. Even when operating slow clock rates, short rise fall times present. Depending loading these fast signals, significant short-duration current demands placed power supply. Special care must taken provide good power-supply bypassing MCU.
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faster edge times MC68HC11A8 generally place greater demands bypassing than earlier NMOS (N-channel MOS) designs. typical expanded-mode system should include 1-µF capacitor separate 0.01-µF capacitor. Both these capacitors should close (physically electrically) possible MC68HC11A8 should have good high-frequency characteristics (for instance, old-technology dipped ceramic disc). 1-µF capacitor primarily supplies charge switching through very low-impedance path (minimum-length runners). Without this bypass, there could very large voltage drops circuit board runners very high (although very short duration) current spike caused several pins simultaneously switching from level other. separate 0.01-µF capacitor included because larger 1-µF capacitor typically good snubbing very high-frequency (low energy) noise. These only general recommendations. Some lightly loaded single-chip systems work quite well with single 0.1-µF bypass capacitor; whereas, more heavily loaded expanded-mode systems require more elaborate bypassing measures. easier less expensive approach power-supply layout bypassing preventive measure from beginning design than locate correct noise problem marginal design. Problems related inadequate power-supply layout bypassing very difficult locate correct, but, reasonable care taken from start design, noise should become problem.
2.4.2 Mode Select Pins (MODB/VSTBY MODA/LIR) mode B/standby supply (MODB/VSTBY) functions both mode select input standby power-supply pin. mode A/load instruction register (MODA/LIR) used select operating mode while reset, operates diagnostic output signal while executing instructions. hardware mode select mechanism starts with logic levels MODA MODB pins while reset state. logic levels MODA MODB pins into clocked
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Pins Connections Descriptions
pipeline path. levels captured those that were present part clock cycle before RESET rose, which ensures there will zero hold-time requirement mode select pins relative rising edge RESET pin. captured levels determine logic state special mode (SMOD) mode select (MDA) control bits highest priority interrupt (HPRIO) register. These control bits actually control logic circuits involved hardware mode selection. Mode selects between single-chip modes expanded modes; mode selects between normal variation special variation chosen operating mode. Bootstrap mode special variation single-chip mode, special test special variation expanded mode. Table summarizes operation mode pins mode control bits. Table 2-1. Hardware Mode Select Summary
Inputs Mode Description MODB MODA Normal single chip Normal expanded Special bootstrap Special test RBOOT SMOD Control Bits HPRIO (Latched Reset)
After RESET released, mode select pins longer influence operating mode. MODA serves alternate function load instruction register (LIR) when reset. open-drain active-low output drives during first cycle each instruction. MODB serves alternate function standby power supply (VSTBY) maintain contents when present. power-saving mode, stop, alternate save contents, which does require separate standby power source. function intended monitoring logic analyzer during debug system. Since this status indicator shows where each instruction begins, programs followed easily. mode select levels status levels were selected prevent interference between shared functions pin. single-chip applications, this
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Pins Connections
simply connected VSS. Since output open-drain, there conflict between direct connection signal that drives during first cycle each instruction. There practical reason monitor during single-chip modes because there visibility internal data address buses. expanded-mode systems, MODA/LIR normally pulled 4.7-k resistor. During reset, pullup resistor instructs MODA select expanded modes. During-program execution, driven during first cycle each instruction signal pulled between signals external 4.7-k pullup. expanded-mode systems where important minimize power-supply current, logic could used drive MODA/LIR rather than just using simple pullup (see Figure 2-7). During reset, MODA would driven high select expanded mode. After reset, would driven logic. logic should operating against pullup, rather should logic-gate-type output with some series resistance protect against unlikely event conflict between active-low signal active-high logic-gate output signal. Such conflict could only occur briefly falling edge reset. Since active about every three cycles during normal execution (average instructions take about three cycles), could reduced about duty cycle).
74HC04 4.7K RESET MODA/LIR M68HC11
Figure 2-7. Reduced MODA/LIR Connections VSTBY function accomplished transistor switch that connects either VSTBY reset logic, depending upon relative levels VSTBY VDD. switch connects unless VSTBY more than threshold higher than VDD. threshold approximately diode drop (0.7 varies from processing variations. During normal operation MCU, supplying power RAM. standby situation, VSTBY should maintained valid level, RESET should activated (pulled low) when drops below legal limits. RESET should always held whenever
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below operating limit. operated special mode (MODB before applying reset) MODB/VSTBY being used back RAM, MODB/VSTBY should driven unless (has returned legal level. Some logic required systems that MODB/VSTBY standby supply want special modes operation. most applications, MODB would connected through pullup resistor normal modes directly ground special modes.
There ways maintain contents on-chip with minimal power consumption battery-based application). preferred method uses stop mode operation. second method uses MODB/VSTBY (see Figure 2-8).
Each these methods advantages. stop mode method preferred because much simpler than separate power-supply method terms hardware costs complexity. STOP method saves power stopping clocks, which reduces current microamps. external logic needed, contents internal registers maintained addition contents internal RAM. MODB/VSTBY method would used cases where there significant amount external circuitry operating from that added complexity supplies added logic justified power savings.
VOUT
4.7K
MODB/V STBY M68HC11
NiCd
BATT
Figure 2-8. Standby MODB/VSTBY Connections
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2.4.3 Crystal Oscillator Clock Pins (EXTAL, XTAL, oscillator pins used with external crystal network externally generated CMOS-compatible clock source. frequency applied these pins four times higher than desired frequency (E-clock rate). clock frequency clock output, which used basic timing reference signal. When clock (address portion cycle), internal process occurring; when high, data being addressed. clock free running one-fourth crystal frequency long oscillator active (stop mode stops clocks). oscillator MC68HC11A8 consists large 2-input NAND gate. inputs this gate driven internal signal that disables oscillator when stop mode. other input EXTAL input MCU. output this NAND gate XTAL output MCU. XTAL normally left unterminated when using external CMOS-compatible clock input EXTAL pin. However, 10-k 100-k load resistor ground used reduce generated radio frequency interference (RFI) noise emission. XTAL output normally intended drive only crystal, XTAL used clock output special care taken avoid undesirable loading. XTAL output buffered with high-impedance buffer such 74HC04, used drive EXTAL input another M68HC11 MCU. cases, circuit-board layout around oscillator pins critical. Load capacitances specified data sheets technical summary include stray layout capacitances. Thus, physical capacitors connected these pins should always less than specified load capacitances estimated interconnection capacitances. Figure Figure 2-10 show internal external components that form crystal oscillator, called Pierce oscillator (also known parallel resonant crystal oscillator). Figure shows connections high-frequency crystals (greater than MHz), Figure 2-10 shows connections low-frequency operation (less than MHz). resistor, provides direct current
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Pins Connections Descriptions
bias input NAND operates linear region. low-frequency designs, provide phase shift. also limits power into crystal, which important many small crystals because they designed very drive levels (typically 1-µW maximum). high-frequency applications (see Figure 2-9), output impedance NAND driver, combined with lower impedance provides same effect low-frequency designs. Higher frequency AT-cut crystals designed much higher drive levels.
Exact values external components function wafer processing parameters, package capacitance, printed circuit board (PCB) capacitance inductance, socket capacitance, operating voltage, crystal technology, frequency. Typical values are: M-20 Higher values sensitive humidity; lower values reduce gain could prevent startup. Value usually fixed. Value varied trim frequency.
pF-25 pF-25
STOP
M68HC11 EXTAL XTAL
XTAL
Figure 2-9. High-Frequency Crystal Connections
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STOP
M68HC11 EXTAL XTAL
XTAL
Figure 2-10. Low-Frequency Crystal Connections tune-up procedure experimentally determining discussed conclusion this subsection. Since circuit layout capacitances effectively values physical capacitances usually smaller than intended capacitances. most high-frequency applications, values equal. low-frequency designs, often desirable make smaller than which provides higher voltage EXTAL input impedance transformation. wider voltage swing this input will result lower power-supply current. crystal oscillator designs, leads should kept short possible. also good practice route paths shown Figure 2-11. These paths isolate oscillator input from output oscillator from adjacent circuitry, only adding capacitance parallel with Potentially noisy lines should kept possible from oscillator components. Ground loops should avoided around oscillator components (note unterminated paths ending under Figure 2-11).
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CRYSTAL
EXTAL
XTAL M68HC11
Figure 2-11. Crystal Layout Example Usually, operation oscillator cannot observed with oscilloscope connected oscillator pins. oscilloscope adds from from VSS, which will usually affect oscillator operation. When oscilloscope connected EXTAL input, (oscilloscope input) forms resistive divider with often disables oscillator biasing circuit linear region EXTAL input. This problem sometimes overcome capacitively coupling oscilloscope with very small capacitor (1-5 between oscilloscope probe oscillator pin. usually better observe E-clock output from since this does alter operation oscillator. low-frequency designs, often possible observe XTAL node with oscilloscope because high-impedance nodes oscillator isolated from XTAL Observe without oscilloscope connected again with oscilloscope connected. unchanged, usually safe assume oscillator unaffected.
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Low-frequency crystal circuits tend very high impedance. Thus, must clean, dry, free conductive material such solder rosin excessive moisture from high humidity. problems occur, value reduced contaminant impedance less significant comparison. course, still best eliminate contaminants. Usually, startup time inversely proportional frequency; thus, low-frequency oscillators start slower than high-frequency oscillators. There many exceptions this rule because there many variables affecting startup time. Observation circuits using MC68HC11A8 with 8-MHz crystal reveals startup from stop mode takes approximately startup from power-up occurs within milliseconds when reaches approximately volt. Power-up performance varies greatly since power-source turn-on characteristics vary greatly. Since MC68HC11A8 fully static design, oscillator required running full speed before processor starts executing instructions (most applications require stable oscillator within first milliseconds after power-up). oscillator running full speed, instructions will take longer execute, unpredictable behavior will result would NMOS processor. oscillator 32-kHz range could require hundreds milliseconds even seconds start stabilize.
NOTE:
following tune-up procedure only meaningful crystal frequencies below MHz. higher frequency applications, because normally this procedure needed. value determined experimentally using final exact type that will used final application. need have final mask program because will held reset throughout experiment. Because number variables involved, components with exact properties those that will used production. example, ceramic-packaged prototype experiment when plastic-packaged will used production. emulator version part will also have slightly different electrical properties than masked version same part.
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determine optimum value observe operating current (IDD) function should held reset throughout this procedure because operating current variations during modes much greater than current variations varying Normally, current will occur. This sharp many circuits instead very broad. shape this curve suggests, exact value critical. Finally, verify that maximum-operating supply voltage does overdrive crystal. Observe output frequency function buffered E-clock output. Under proper operating conditions, frequency should increase parts million supply voltage increases. crystal overdriven, increase supply voltage will cause decrease frequency, frequency will become unstable. frequency problems arise, supply voltage must decreased, values should increased reduce crystal drive.
2.4.4 Crystal Oscillator Application Information Some crystal oscillator application information presented this subsection. 2.4.4.1 Crystals Parallel Resonance Parallel resonance refers Pierce oscillator that crystal parallel with inverter. Almost all) CMOS MCUs this type oscillator. AT-cut crystals available standard devices both series resonant circuits Pierce oscillators. load capacitance specified Pierce version. series resonant versions require this specification more likely listed standard product. type circuit affects oscillating frequency crystal. 8-MHz AT-cut crystal will normally meet requirements M68HC11. However, very accurate oscillator frequency, Pierce version crystal with values match specified load capacitance value crystal. load capacitance approximately equal series combination
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2.4.4.2 Using Crystal Oscillator Outputs crystal oscillator actually (radio frequency) application. Connecting crystal pins other circuitry likely interfere with proper operation oscillator. Modern CMOS inputs very high impedance relatively capacitance; thus, these inputs connected oscillator without disturbing oscillator. data sheet particular part shows examples ways crystal oscillator used drive other circuits crystal frequencies between MHz.
2.4.4.3 Using External Oscillator externally built Pierce oscillator will operate like crystal connected M68HC11. single inverter connect crystal feedback resistor load capacitors external inverter input were EXTAL inverter output were XTAL pin. 74HCU04 this inverter. This device unbuffered HCMOS inverter. Avoid Schmitt-trigger devices because oscillator fail start. Buffer output external Pierce oscillator drive additional logic. 2.4.4.4 AT-Strip versus AT-Cut Crystals AT-strip new-technology low-power crystal. Connecting these crystals M68HC11 cause problems NAND gate overdriving crystal. AT-cut crystal with M68HC11 avoid this problem.
2.4.5 Reset (RESET) This active-low, bidirectional control signal used input initialize MC68HC11A8 known startup state open-drain output indicate that internal failure been detected either clock monitor computer operating properly (COP) watchdog circuit. This RESET signal significantly different from RESET signal used earlier MCUs. More detailed information about this found Section Resets Interrupts.
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reset circuitry specifically designed work with lower levels than other circuitry. Thus, RESET used prevent undesirable performance power applied decays, which important applications which contents on-chip must maintained absence VDD. this situation, reset input logic would powered from standby power source connected MODB/VSTBY whenever support proper operation. Secondly, RESET must controlled when below legal operating limits prevent unintentional corruption EEPROM data. Even application using 512-byte EEPROM, CONFIG register still EEPROM byte must protected from corruption. Virtually MC68HC11A8 systems should include automatic control RESET drive whenever below legal limits. simple, inexpensive, low-voltage inhibit (LVI) device such MC34064 MC34164 used. MC34064 available TO-92 SOT-8 plastic packages provides open-drain output directly drive RESET MC68HC11A8. This device connected VDD, VSS, RESET MCU. pullup resistor from RESET only other component required reset circuit most applications. Figure 2-12 shows typical reset circuit.
MANUAL RESET
RESET MC34064
RESET MC34064
4.7K RESET M68HC11
OPTIONAL DELAY MANUAL RESET SWITCH
Figure 2-12. Reset Circuit Example
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2.4.6 Interrupt Pins (XIRQ IRQ) XIRQ provides means requesting non-maskable interrupts after reset initialization. During reset, condition code register (CCR) set, interrupts masked until software enables them. Since XIRQ input level sensitive, connected multiple-source wired-OR network with external pullup resistor. XIRQ often used power loss detect interrupt. input provides means requesting asynchronous interrupts MC68HC11A8. program selectable (OPTION register), having choice either level-sensitive falling-edge-sensitive triggering. After reset, configured level-sensitive operation default. Whenever XIRQ used with multiple interrupt sources (IRQ must configured level-sensitive operation there more than source interrupt), each source must drive interrupt input with open-drain-type driver avoid contention between outputs. There should single pullup resistor near interrupt input (typically There must also interlock mechanism each interrupt source that source holds interrupt line until recognizes acknowledges interrupt request. more other interrupt sources still pending after services request, interrupt line will still low; thus, will interrupted again soon interrupt mask becomes clear (normally upon return from interrupt). used during factory testing bulk programming voltage source, which allows parallel programming many half bytes EEPROM single programming operation. Since on-chip charge pump does have sufficient drive capability simultaneously program this many EEPROM locations, external 20-V power supply needed supplement on-chip charge pump. switchover mechanism, which decides whether EEPROM powered internal charge pump external voltage source, similar VSTBY logic MODB/VSTBY pin. When external voltage more than charge-pump voltage, switch connects external high-voltage source internal line. added circuitry
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this effect normal functions, does have some effect reacts illegal levels. addition XIRQ IRQ, five other pins MC68HC11A8 also used generate interrupt requests MCU. These pins associated with other on-chip peripherals such timer handshake systems. pins PA0/IC3, PA1/IC2, PA2/lC1, PA7/PAI/OC1, AS/STRA. input-capture pins configured detect rising edges, falling edges, edge. STRA inputs configured detect rising edges falling edges. STRA input only available operating single-chip mode because used address strobe (AS) output when expanded modes. These five pins have advantages over XIRQ pins that each these five interrupts independently maskable with local control well global CCR. Each these five interrupts also readable status indication, pending request cleared without being serviced.
2.4.7 Reference Port Pins (VREFL, VREFH, PE7-PE0) VREFH VREFL pins provide reference voltages converter circuitry. Since converter all-capacitive charge-redistribution converter, there essentially current associated with these pins. Very small dynamic currents caused charge-redistribution switching during conversions (see Section Analog-to-Digital Converter System). These pins normally connected through low-pass filter network (see Figure 2-13) isolate noise logic power supply from relatively sensitive analog measurements. low-noise precision reference supply used alternatively. There should least between VREFL VREFH full accuracy. Lower values will result more inaccuracy, converter will continue operate. system tested across reference supply pins. There inherent diode from VREFL VSS. VREFL goes below more than this diode drop, conversion progress corrupted, permanent physical damage will result until significant current drawn. only documented cases damage have been
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REFH M68HC11 REFL M68HC11
Figure 2-13. Low-Pass Filter Reference Pins
caused blatant misapplication, such connecting directly VREFL pin. Since P-channel devices associated with VREFH pin, there diode clamping VDD. gates analog switches associated with reference input pins controlled signals that switch between about This higher-than-VDD supply output charge pump (separate from charge pump used programming on-chip EEPROM). There special requirement keep VREFH below VDD. fact, converter will continue produce good results approximately VREFH. port input pins used general-purpose inputs and/or analog inputs. These inputs designed that digital input buffers disabled times except part cycle during actual read port thus, analog levels near switch point digital input buffer result high power-supply current drains normal CMOS input buffer. buffers enabled extra N-channel device series with N-channel device input inverter. During digital read port these extra N-channel devices turned part read cycle. Because this special circuitry, necessary terminate unused port pins. analog digital functions port normally interfere with each other; thus, combination pins used digital inputs while remaining port pins used analog inputs. Turning digital buffer during analog sample cause small disturbances input line, which cause small errors sampled analog level. disturbances would caused small gate-to-drain gate-to-source capacitances would have occur very close trailing edge sample period have noticeable effect.
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disturbances small they exist) that they probably would cause measurable inaccuracy. Since easy arrange software avoid this condition, probably easier avoid potential disturbances.
2.4.8 Timer Port Pins Port includes three input-only pins, four output-only pins, that configured operate input output. input-only pins (PA0/IC3, PA1/IC2, PA2/lC1) also serve edge-sensitive timer input-capture pins. four output-only pins (PA3/OC5/OC1, PA4/OC4/OC1, PA5/OC3/OC1, PA6/OC2/OC1) also serve main timer output-compare pins. Whenever output-compare function enabled, that cannot used general-purpose output. These four pins controlled output compare (OC1) and/or another output compare. PA7/PAI/OC1 used general-purpose pin, pulse-accumulator input, output pin.
2.4.9 Serial Port Pins Port includes general-purpose, bidirectional pins that individually configured inputs outputs. When serial communications interface (SCI) receiver enabled, PD0/RxD becomes input dedicated function. When transmitter enabled, PD1/TxD becomes output dedicated function. When serial peripheral interface (SPI) system enabled, PD2/MISO, PD3/MOSI, PD4/SCK, PD5/SS pins become dedicated functions. Even while system enabled, PD5/SS used general-purpose output setting corresponding DDRD5 bit, provided system configured master mode operation. port pins configured (port wired-OR mode (DWOM) control control register (SPCR)) wired-OR operation. This option disables P-channel device output drivers port outputs actively drive high, allowing more such outputs connected without contention. Since P-channel device
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physically present (just turned off), there inherent diode from output cannot pulled level higher than (unlike transistor-transistor logic (TTL) open-collector output). external pullup resistor required port outputs when wired-OR option used. firmware bootloader program configures port wired-OR operation when reset bootstrap mode. application using bootstrap mode, either turn wired-OR option after downloading supply external pullup resistors port output pins.
2.4.10 Ports STRA STRB Pins These pins used general-purpose while operating single-chip mode. When expanded mode used, these pins become multiplexed address/data with address strobe (AS) read/write (R/W) control line. Table summarizes functions these pins related operating mode. Table 2-2. Ports STRA STRB Pins
Port Single-Chip Bootstrap Mode STRA STRB Output Output Output Output Output Output Output Output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input strobe (edge Output strobe A0/D0 A1/D1 A2/D2 A3/D3 A4/D4 A5/D5 A6/D6 A7/D7 Expanded-Multiplexed Special Test Mode Address Address Address Address Address Address Address Address output output output output output output output output
Address/data multiplexed Address/data multiplexed Address/data multiplexed Address/data multiplexed Address/data multiplexed Address/data multiplexed Address/data multiplexed Address/data multiplexed Address strobe (out) Read/write select
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single-chip modes, external address/data needed; thus, these pins available general-purpose I/O. Port 8-bit output-only port; port 8-bit bidirectional port. combination bits port configured outputs; remaining bits used inputs. Several automated handshake functions associated with ports These strobe handshake functions STRA STRB pins strobes handshake controls. STRA edge-detecting input that causes port data latched into special internal latch register. active edge STRA software selectable, port used general-purpose static while other pins being used latched inputs. strobe handshake functions being used, STRA still used edge-detecting interrupt input cannot used general-purpose static input. STRB output strobe associated with handshake functions ports handshake functions being used, STRB still used general-purpose output, though more difficult control than normal port output pin. detailed discussion handshake functions ports refer Section Parallel Input/Output. When operating expanded modes, these pins used address/data allow central processor unit (CPU) access 64-Kbyte memory space. save pins, low-order address 8-bit data time multiplexed eight pins. During first half each cycle, address output signals, A7-A0, present these eight pins; during second half each cycle, these eight pins used bidirectional data bus, D7-D0. signal used active-high latch enable external address latch. Address information allowed through this external transparent latch while high, stable address information latched when low. clock used enable external devices drive data into during second half read cycle clock high). signal indicates direction data high read cycles, write cycles.
NOTE:
AS/STRA output expanded modes input single-chip modes. Remember terminate this unused input single-chip modes.
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Because MC68HC11A8 CMOS device, unused input pins must terminated ensure proper operation reliability. Figure 2-14 shows CMOS inverter, which representative circuitry found CMOS input pins. When input logic P-channel transistor (conducting), N-channel transistor off. When input logic P-channel transistor off, N-channel transistor These transistors actually linear devices with relatively broad switch points. input passes through midsupply, there region where both transistors conduct some degree. Under normal circumstances, input does remain this linear region very long. Once inverter completely switched that only transistors conducting, there virtually current flow. This principle overall current drain CMOS device directly proportional rate switching. Essentially, current gates that linear region during transitions charging discharging internal capacitances. Because input very high impedance, connected, input oscillate float midsupply level. Either these conditions result added power-supply current. oscillation case result coupling noise power supply. older CMOS designs, large currents caused input that floated midsupply could even induce CMOS latchup, which could destroy integrated circuit. Current design techniques MC68HC11A8 have made latchup floating input unlikely, still important terminate unused inputs avoid oscillation, noise, added supply current.
NOTE:
Some inputs (RESET, EXTAL, MODA, MODB) cannot left unterminated system.
Figure 2-14. CMOS Inverter
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port input pins have extra N-channel device between bottom N-channel device input inverter. Since this extra device only enabled half cycle during digital read port less important terminate unused port pins than other unused inputs. cases very slow frequencies, even half cycle might significant length time, unused port pins could terminated. some battery-powered systems where port read often, would desirable eliminate potential added supply current.
Since VREFL VREFH pins connect inputs CMOS gates within MC68HC11A8, these pins need terminating they used. Although termination required, reduce risk damage high-voltage static electricity. Other than pins, there basic types input pins MC68HC11A8 input-only input/output pin. best method terminate unused inputs with pullup pulldown resistor each unused pin. Input-only pins connected each other then common termination point. Although this method less expensive takes less space than individual pullups, much harder separate these pins needed later. Although input-only pins connected directly VSS, better because this connection makes difficult change level that input. pullup pulldown resistor used instead, signal easily connected input later. preferred method terminating pins that configured input output with individual pullup pulldown resistors each unused pin. Some users leave these pins unconnected reconfigure them outputs during initialization. There still brief period during reset initialization where these pins unterminated inputs. There also small risk that defective system might fail reconfigure these pins outputs. capable being configured output should never connected another such directly either power-supply rail. ever became output, there possibility high current drain output conflict. eliminate potential problems, part verification procedure design every system should pin-by-pin review what connected every MCU.
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integrated circuit damaged destroyed exposure illegal voltages conditions. understanding failure mechanisms, designer protect against damaging conditions. some cases, product even designed tolerate common end-user errors designing protective interface circuits. data sheets integrated circuits state conservative limits conditions that will definitely protect integrated circuit. consequences violating specified limits usually discussed because there many variables affecting results. some cases, tolerate significantly worse conditions than stated limits, although almost impossible quantify guarantee this better performance parts conditions. There several basic types interface circuits MC68HC11A8. exact devices connected influence what happens voltage level driven above below VSS. Many other factors, including ambient temperature lot-to-lot process variations, also influence reaction illegal voltage levels conditions. following discussion explains conditions leading actual damage what that damage might This information should used guideline help engineers avoid conditions leading possible damage. Connected substrate silicon die, reference point from which other voltages measured. main positive power supply MCU. Data sheet information tested guaranteed equal percent, but, limited temperature range applications, operate over wider range (some timing drive capability specifications met). operating temperature have significant effect speed CMOS logic. reduced, maximum crystal frequency must also reduced. equal percent, MC68HC11A8 operate with maximum frequency MHz; when maximum frequency about MHz. temperatures, speed increases power-supply current decreases. typically operate with levels without
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damaging MCU, timing drive levels will differ from specified limits. Also, there some adverse effects gate oxides from long-term exposure greater than equal battery-based application could exposed greater than when batteries still expected work properly battery voltage slowly decays some level well below Although MC68HC11A8 could used such application, published specifications cover this range VDD.
2.6.1 Latchup latchup terms familiar failure analysis engineers that work CMOS integrated circuits. refers damage caused very high-voltage static-electricity exposure. Static-electricity (zap) damage usually appears breakdown relatively thin oxide layers that causes leakage shorts. Often secondary damage occurs after initial failure causes short. Latchup refers usually catastrophic condition caused turning unintentional, bipolar, silicon-controlled rectifier (SCR). latchup formed regions layout integrated circuit, which collector, base, emitters unintentional, parasitic transistors. Bulk resistance silicon wells substrate resistors circuit. Application voltages above below VSS, conjunction with enough current develop voltage drops across parasitic resistors unintentional circuit, cause turn Normally, once this turned turned only removing power from integrated circuit. on-impedance overheat destroy integrated circuit. Improvements layout processing techniques have made newer HCMOS devices, such MC68HC11A8, much less likely suffer damage from latchup. Because destructive nature these mechanisms, impossible test every device latchup limits timing drive levels tested. ensure product reliability, sample groups devices destructively tested.
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2.6.2 Protective Interface Circuits applications where pins might exposed detrimental conditions, protective interfaces needed protect from damage. main goals protective interface prevent high currents from flowing prevent illegal voltage levels pin. low-pass filter often satisfy both goals. less common situations, also necessary provide diode clamps prevent high voltages some pins. pins M68HC11 have internal inherent diode clamps VSS, only some pins include clamps VDD. following subsections discuss internal circuits each type note special considerations protection these types. Usually, only pins needing protection those that exposed signals from outside system. example, automobile engine controller, sensors fuel flow connected engine control module ultimately inputs. These signals prime candidates protective interfaces because noise illegal levels could accidentally applied through interface wiring. other hand, buses signals wholly contained within control module probably require sort protective interface because there little chance that these signals would exposed illegal levels. cases, protective interface even interfere with normal operation signal. example, low-pass filter address data line expanded system would introduce significant delays these signals, dramatically limiting maximum operating speed system.
2.6.3 Internal Circuitry Digital Input-Only Figure 2-15 shows circuitry digital input-only pin. gates input buffer very high impedance voltages that would ever applied pin. thick-field protection device normally prevents voltage from reaching levels that could damage gates input buffer. exact circuitry input buffer different different digital inputs (for example, provide hysteresis, etc.), only device gates will connected directly
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pin. Allowing float driven) midsupply level result both P-channel devices input buffer simultaneously being partially which causes excess current noise VDD/VSS power supply. Port inputs exceptions because they specifically designed driven analog levels.
THICK FIELD PROTECTION
INPUT BUFFER
Figure 2-15. Internal Circuitry Digital Input-Only digital input (see Figure 2-15) driven with voltages below VSS, thick-field protection device forms inherent diode junction VSS, which conducts when voltage gets more than diode drop below VSS. voltage driven more negative with respect VSS, current increases. These currents have tendency influence substrate area around protection device, thus affecting electrical characteristics devices vicinity. When current increased very high levels (typically more than specified limit mA), physical damage result. voltage driven above VDD, protection device will begin conduct tend clamp input voltage protect input buffer [3]. voltage which this condition will occur varies significantly from over operating temperature range. room temperature, typically does draw current until approximately 125°C, start conducting slightly lower level. this point, appears function normally will return logic read. voltage increases, thick-field protection device begins conduct more current substrate, which VSS. There should some external series impedance between input voltage source will used detrimental environment. input
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voltage increased even further, protection device will avalanche, voltage will eventually fold back (typically about Under these conditions, parasitic bipolar transistor, which obvious from schematic, turned holding 7-volt level. This avalanche still normally destructive pin. Since foldback clamp level relatively impedance, voltage cannot raised further without supplying large current. offending voltage source increased increase current, circuitry will damaged (specified limit typically takes more than mA). Gate oxides these inputs intended exposed voltages above significant amount time. With HCMOS processing used MC68HC11A8, latchup failure unlikely unless legal drive limits grossly exceeded. 2.6.4 Internal Circuitry Analog Input-Only Figure 2-16 shows circuitry associated with analog input-only pin. This logic similar that digital input-only except addition analog multiplexer extra N-channel device below buffer. N-channel device acts analog multiplexer affects behavior analog input when exposed negative voltages. N-channel device allows analog input pins driven intermediate levels without causing noise current normally associated with input buffer when input midsupply level. This device only turned half E-clock cycle during digital read port Since analog input pins (including VREF pins) only connected N-channel devices high-impedance gates, these pins driven with levels above without usual fear latchup. This aspect important because analog reference supply typically independent supply noise isolation reasons. analog input (see Figure 2-16) responds very much like digital input illegal levels except that negative levels affect operations. analog functions associated with these pins also present some special challenges protective interface circuits. Although N-channel device eliminates need external pullup pulldown resistors unused port pins, conservative designer would still terminate these pins help prevent static damage.
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ANALOG MULTIPLEXER
THICK FIELD PROTECTION
INPUT BUFFER
Figure 2-16. Internal Circuitry Analog Input-Only voltage driven enough relative gate voltage analog multiplexer device, this N-channel device turn conductive path between negative capacitor array discharge capacitors disrupt conversion progress. thick-field protection device other circuit layout measures around N-channel multiplexer device intended prevent voltage from becoming negative enough turn multiplexer device. Even with these internal protective measures, cautious user should avoid negative levels because large negative transient could still disrupt conversion. conversion disrupted this manner experiences serious negative transient; transient need associated with conversion. External diode clamps necessarily good idea analog inputs. Leakage through external diode would significant relationship leakage current; thus, this extra leakage could affect accuracy analog conversion results. Analog input pins usually protected low-pass filter with enough series impedance limit voltage. amount series resistance trade-off between high enough value limit voltage enough value prevent leakage current from adversely affecting conversion
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results. Conversion accuracy specified maximum external series resistance worst-case specified leakage current room temperature, leakage typically much less). acting through causes absolute conversion error minus one-fifth least significant (LSB) when VREF 5.12 leaving only about one-quarter actual circuit errors before results would specified limits. Using larger external resistance series with cause some inaccuracy leakage current acting through this resistance, will still respond predictable manner. There valid system design reasons choosing high external series resistance (for example, minimize power consumption battery-based system). additional detailed information concerning input pins, 12.5 Connection Considerations.
2.6.5 Internal Circuitry Digital Figure 2-17 shows circuitry capable operating input output. Even when configured disable output driver circuitry, transistors still affect reacts illegal levels. P-channel device output driver forms inherent diode VDD, N-channel device forms inherent diode VSS, which parallel with inherent diode thick-field protection device.
OUTPUT BUFFER THICK FIELD PROTECTION
INPUT BUFFER
Figure 2-17. Internal Circuitry Digital
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When configured high-impedance input, input signals clamped within diode drop power-supply rails. When configured output, N-channel device provides low-impedance path VSS, respectively. current into should limited prevent damage. specified current limit although these pins typically withstand transients more than nominal room temperature. port port pins M68HC11 configured open-drain-type outputs. This configuration disables gate signal P-channel device output buffer cannot driven active-high logic level, P-channel device still physically present forms inherent diode VDD. applications, situation will arise where more pins tied same point. Software would arranged that more than these pins configured output time avoid output driver contention. these applications, pins should configured open-drain mode output drivers prevented from high-current contention.
2.6.6 Internal Circuitry Input/Open-Drain-Output pins M68HC11 (RESET MODA/LIR) have high-impedance input functions well open-drain output functions (see Figure 2-18). These pins similar pins except that there P-channel device output driver. Since P-channel output device present, there inherent diode VDD. terms negative illegal levels these pins, diodes clamp diode drop below ground. terms positive levels above VDD, N-channel output device starts conduct before thick-field protection device; thus, typically clamp level these pins will lower than that digital input-only pin. pin, current should limited prevent damage.
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N-CHANNEL ONLY OUTPUT BUFFER THICK FIELD PROTECTION
INPUT BUFFER
Figure 2-18. Internal Circuitry Input/Open-Drain-Output
2.6.7 Internal Circuitry Digital Output-Only Output-only pins react illegal levels exactly like pins. Figure 2-19 shows circuitry digital output-only pin.
OUTPUT BUFFER THICK FIELD PROTECTION
Figure 2-19. Internal Circuitry Output-Only
2.6.8 Internal Circuitry MODB/VSTBY MODB/VSTBY unusual because serves standby voltage source addition acting mode select input (see Figure 2-20). switch automatically connects internal power supply higher VSTBY. illegal high level applied
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MODB/VSTBY pin, this illegal voltage passed into internal system. minor elevation VSTBY relative tolerated during operation, significant elevation result incorrect reads data. When battery other standby voltage source will used maintain contents absence VDD, MODB/VSTBY should driven (rather than standby source) during normal operation. MODB/VSTBY should driven higher level than VDD, except during standby periods; during these periods, RESET should driven low.
MODB/V STBY THICK FIELD PROTECTION
INPUT BUFFER
POWER POWER SWITCH
Figure 2-20. Internal Circuitry MODB/VSTBY
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2.6.9 Internal Circuitry IRQ/VPPBULK used high-voltage power source during factory testing. This high-voltage source supplies power bulk programming operations because internal charge pump designed provide enough current these bulk programming operations. Figure 2-21 shows circuitry IRQ/VPPBULK pin. IRQ/VPPBULK essentially reacts like input-only illegal levels. normal level used during testing very near level where thick-field protection device begins conduct. important limit current power supply into IRQ/VPPBULK with external series resistor (typically because noise overshoot trigger low-impedance foldback mechanism protection device. Without current-limiting resistor, small metal line connecting bonding input circuitry will instantly vaporize. Normal users would encounter this potential problem since function IRQ/VPPBULK only intended Motorola. current-limiting resistor adverse effect bulk programming process since current requirements EEPROM programming very small.
IRQ/V PPBULK THICK FIELD PROTECTION
INPUT BUFFER
Figure 2-21. Internal Circuitry IRQ/VPPBULK
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Pins Connections Typical Expanded Mode System Connections
Typical Expanded Mode System Connections
schematic shown Figure 2-22 fairly straightforward expanded mode system, which operated normal expanded mode special test mode. This circuitry used basis expanded mode application. most cases, circuitry power supply, oscillator, mode selects used exactly shown this system. additional memory peripheral functions added address data buses, loading should reviewed determine whether additional buffering required. Loading generally limited load capacitance before drive capabilities drivers reached. frequencies lower than MHz, more capacitance driven before buffers required. applications where heavy loading occurs, necessary increase power-supply bypass capacitors provide these higher switching demands VDD. address decoding used this example system unusual that external EPROM decoded appear either memory areas. Some commonly used terms describe this type decoding partial decode, redundant mapping, mirroring. this system, external EPROM appears $E000-$FFFF $A000-$BFFF that reset vector fetched this EPROM whether operating normal expanded mode special test mode. This mapping also allows come reset special test mode, check contents EEPROM-based CONFIG register (change CONFIG necessary), then change operating mode normal expanded mode. There several potential advantages starting system this (see 3.7.3 Special Test Mode). 74HC138 decoder provides address-qualified read enable write enable signals 8-Kbyte static RAMs. other four outputs this 74HC138 provide additional chip selects additional peripheral devices. Since signal drives address selects 74HC138, there four active-low read enable outputs four active-low write enable outputs. timing these outputs controlled clock propagation delay through 74HC138 decoder. Address stable long before rising edge clock.
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Pins Connections
MC68HC11A8 SYSTEM POWER 0.01 PA0/IC3 PA1/IC2 PA2/IC0 PA3/OC5/OC1 PA4/OC4/OC1 PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/OC1 4.7K RESET 4.7K XIRQ 4.7K 4.7K CONNECT JUMPER TEST MODE MODA/LIR 4.7K MODB/V STBY PD0/RxD PD1/TxD PD2/MISO PD3/MOSI PD4/SCK PD5/SS PE0/ANO PE1/AN1 PE2/AN2 PE3/AN3 PE4/AN4 PE5/AN5 PE6/AN6 PE7/AN7 CONTROL RESET MC34064 74HC373 DATA
EXTAL XTAL
ADDRESS
Figure 2-22. Basic Expanded Mode Connections (Sheet
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Pins Connections Typical Expanded Mode System Connections
DATA
EPROM 74HC138
ADDRESS
CONTROL
Figure 2-22. Basic Expanded Mode Connections (Sheet
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Pins Connections
MC68HC11A8 SYSTEM POWER PA0/IC3 PA1/IC2 PA2/IC0 PA3/OC5/OC1 PA4/OC4/OC1 PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/OC1
EXTAL XTAL
STRB STRA
4.7K
RESET MC34064
RESET 4.7K XIRQ 4.7K PD0/RxD PD1/TxD PD2/MISO MODB/V STBY MODA/LIR PD3/MOSI PD4/SCK PD5/SS PE0/ANO PE1/AN1
CONNECT JUMPER BOOTSTRAP MODE
4.7K
PE2/AN2 PE3/AN3 PE4/AN4 PE5/AN5 PE6/AN6 PE7/AN7
Figure 2-23. Basic Single-Chip Mode Connections
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Pins Connections Typical Single-Chip Mode System Connections
decoding EPROM done with sections quad NAND gate. Address valid time controls chip select access time EPROM. This chip select decode provides longer access time than chip select arrangement RAMs because EPROMs typically slower than static RAMs. clock controls output enable EPROM, which typically much shorter setup time requirement than chip-select input EPROM. Since address line included decode EPROM, EPROM will appear twice memory map: $A000-$BFFF where $E000-$FFFF where high. potential address conflicts occur this system. on-chip and/or on-chip EEPROM conflict with external EPROM. purposes this example, assumed that internal will used will disabled ROMON control CONFIG register. potential conflict with EEPROM poses concern normal expanded mode because external data high impedance ignored during reads internal EEPROM. special test mode, there potential undesirable conflict EEPROM read while function enabled (see 2.9.2 Internal Read Visibility (IRV). Although normally this conflict would destructive, would increase power consumption generated noise. this example system, special test mode would effect only short time after reset, reads internal EEPROM could avoided easily during this time.
Typical Single-Chip Mode System Connections
Figure 2-23 schematic simple single-chip-mode system, which operated normal single-chip special bootstrap mode. This circuit used basis single-chip-mode application. most cases, circuitry power supply, oscillator, mode selects used exactly shown this system. Only specialized circuitry specific application needs designed from scratch. unused inputs terminated appropriate manner.
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Pins Connections System Development Debug Features
designers M68HC11 carefully considered system development needs user. Since smaller users cannot afford thousands dollars development system, M68HC11 specifically designed accommodate low-cost development tools. M68HC11EVB evaluation board M68HC11EVM evaluation module examples such low-cost tools. Several customers have also built small plug-in modules that emulate MC68HC11A8 product development purposes. small size these plug-in emulators possible because development features designed into M68HC11.
2.9.1 Load Instruction Register (LIR) signal intended debugging aid. This signal driven active first cycle each instruction, making easy reverse assemble (disassemble) instructions from display logic analyzer.
2.9.2 Internal Read Visibility (IRV) During debugging application, useful what being read from internal registers memory locations. feature provides this capability. Usually this feature should disabled during normal operation system possibility conflicts. feature controlled HPRIO register. When data from read internal register memory location driven data monitored logic analyzer. function disabled, data undriven during reads internal address. Special restrictions apply function. When reset normal modes, initially newest derivatives M68HC11 Family, written normal modes. special test bootstrap modes, initially written after which becomes read-only bit.
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M68HC11 Rev. MOTOROLA
Pins Connections System Development Debug Features
careful when function enabled. During reads internal address, data driven even though line indicates that direction toward MCU. Some external device also trying drive data lines, which leads undesirable contention. test debugging situation, special address decode logic used prevent such contention. would expensive inappropriate have this additional decode logic normal mode systems; thus, function only provided special test bootstrap modes. several customer requests function normal modes, logic changed allow function enabled normal modes versions M68HC11. default condition normal modes still equals which disables function. user specifically wants function, written user becomes responsible avoiding contentions. written time unless previously been written written function becomes disabled until next reset sequence.
2.9.3 MC68HC24 Port Replacement Unit (PRU) MC68HC24 gate array that emulates single-chip mode functions ports which lost expansion function when operated expanded modes. expanded mode permits program development external EPROM. system consisting M68HC11 expanded mode, MC68HC24, HC373 octal latch, external EPROM performs like MC68HC11A8 operating single-chip modes, thus allowing application program developed tested before masked pattern ordered. logic M68HC11 specifically designed permit emulation single-chip functions with MC68HC24. First, addresses associated with ports their handshake functions treated external addresses when operating expanded modes. Next, interrupts associated with handshake system vectored same address interrupts. Thus, interrupt output MC68HC24 connected interrupt input MCU, handshake interrupts will treated same internal
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Pins Connections
handshake functions. M68HC11 allows registers and/or internal remapped 4-Kbyte boundary. MC68HC24 copies this logic that registers MC68HC24 will automatically track internal remapping logic. Software written expanded system, including MC68HC24, will operate exactly would internal MC68HC11A8 single-chip mode.
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Reference Manual M68HC11
Section Configuration Modes Operation
Contents
Introduction
Hardware Mode Selection 3.3.1 Hardware Mode Select Pins. 3.3.2 Mode Control Bits HPRIO Register EEPROM-Based Configuration (CONFIG) Register. 3.4.1 Operation CONFIG Mechanism 3.4.2 CONFIG Register Protected Control Register Bits 3.5.1 Mapping Register (INIT) 3.5.2 Protected Control Bits TMSK2 Register 3.5.3 Protected Control Bits OPTION Register Normal Operating Modes .101 3.6.1 Normal Single-Chip Mode 3.6.2 Normal Expanded Mode. Special Operating Modes .102 3.7.1 Testing Functions Control Register (TEST1) 3.7.2 Test-Related Control Bits BAUD Register 3.7.3 Special Test Mode 3.7.4 Special Bootstrap Mode 3.7.4.1 Loading Programs Bootstrap Mode .110 3.7.4.2 Executing User Programs Bootstrap Mode 3.7.4.3 Using Interrupts Bootstrap Mode 3.7.4.4 Bootloader Firmware Options Test Bootstrap Mode Applications Example 3-1: Programming CONFIG (Uses Special Test Mode)
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Configuration Modes Operation Introduction
This section discusses mechanisms that allow MC68HC11A8 conform wide variety applications. These mechanisms include hardware mode selection circuitry, nonvolatile electrically erasable programmable (EEPROM)-based configuration register, protected control register bits. majority control bits MC68HC11A8 accessible time software discussed throughout this manual.
term mode used more than context discussing microcontroller unit (MCU). example, serial peripheral interface (SPI) said either master slave mode, parallel input/output (I/O) system said simple strobed mode, full-input handshake mode, full-output handshake mode. most cases, there confusion about what term mode refers however, term mode conjunction with stop wait often misunderstood. Stop wait actually modes operation central processor unit (CPU) opposed single-chip expanded modes, which modes operation integrated circuit. this section, operating modes other mechanisms controlling basic configuration discussed. Very functions influenced mode operation. example, timers, analog-to-digital converter (A/D), serial functions work same expanded modes they single-chip modes. parallel functions pins lost expanded modes regained with special, external, port-replacement chip called MC68HC24. special modes operation, some special testing functions become accessible, including ability software change mode.
Hardware Mode Selection
There only fundamental modes operation MC68HC11A8 MCU:
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Single-chip mode Expanded mode
M68HC11 Rev. MOTOROLA
Configuration Modes Operation Hardware Mode Selection
Each mode normal variation special variation. These four mode variations selected levels mode (MODA) mode (MODB) pins during reset. special variation single-chip mode called special bootstrap mode; special variation expanded mode called special test mode. special bootstrap mode allows programs downloaded through on-chip serial communications interface (SCI) into internal random-access memory (RAM) executed. bootloaded program used variety tasks such loading calibration values into internal EEPROM performing diagnostics finished module. bootstrap mode special user's mode, factory test mode. special test mode, which intended primarily factory testing, seldom chosen user except emulation, development, other rare circumstances.
3.3.1 Hardware Mode Select Pins hardware mode select mechanism starts with logic levels MODA MODB pins while reset state. logic levels MODA MODB pins into clocked pipeline path. levels captured those that were present part clock cycle before RESET rose, which assures there will zero hold-time requirement mode select pins relative rising edge RESET pin. captured levels determine logic state special mode (SMOD) mode select (MDA) control bits highest priority interrupt (HPRIO) register. These control bits actually control logic circuits involved hardware mode selection. Table summarizes operation mode pins mode control bits. Table 3-1. Hardware Mode Select Summary
Inputs MODB MODA Mode Description Normal single chip Normal expanded Special bootstrap Special test Control Bits HPRIO (Latched Reset) RBOOT SMOD
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Configuration Modes Operation
After RESET rises, mode select pins longer influence operating mode. MODA serves alternate function load instruction register (LIR) when reset. open-drain active-low output drives during first E-clock cycle each instruction. MODB se

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