3.3V CMOS 18-BIT INTERFACE REGISTER WITH VOLT TOLERANT BUS-HOLD T

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3.3V CMOS 18-BIT INTERFACE REGISTER WITH VOLT TOLERANT BUS-HOLD T

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IDT74LVCH162823A 3.3V CMOS 18-BIT INTERFACE REGISTER WITH TOLERANT
3.3V CMOS 18-BIT INTERFACE REGISTER WITH VOLT TOLERANT BUS-HOLD
Typical tSK(o) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range CMOS power levels (0.4µ typ. static) inputs, outputs, tolerant Supports insertion Available SSOP, TSSOP, TVSOP packages
IDT74LVCH162823A
FEATURES:
DESCRIPTION:
DRIVE FEATURES: APPLICATIONS:
Balanced Output Drivers: ±12mA switching noise
3.3V mixed voltage systems Data communication telecommunication systems
LVCH162823A 18-bit interface register built using advanced dual metal CMOS technology. This high-speed, low-power register with clock enable (CLKEN) clear (CLR) controls ideal parity interfacing high-performance synchronous systems. control inputs organized operate device 9-bit registers 18-bit register. Flow-through organization signal pins simplifies layput. inputs designed with hysteresis improved noise margin. pins LVCH162823A driven from either 3.3V devices. This feature allows this device translator mixed 3.3V/5V supply system. LVCH162823A series resistors device output structure which will significantly reduce line noise when used with light loads. This driver been developed drive ±12mA designated threshold levels. LVCH162823A "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
1CLR 1CLK 1CLKEN
2CLR 2CLK 2CLKEN
EIGHT OTHER CHANNELS
EIGHT OTHER CHANNELS
logo registered trademark Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4683/1
IDT74LVCH162823A 3.3V CMOS 18-BIT INTERFACE REGISTER WITH TOLERANT
CONFIGURATION
1CLR
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description
1CLK 1CLKEN
Unit
VTERM TSTG IOUT
Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Current through each
-0.5 +6.5 +150 ±100
NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
CAPACITANCE +25°C, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NOTE: applicable device type.
2CLR
2CLKEN 2CLK
FUNCTION TABLE(1)
Inputs xCLR xCLKEN xCLK Outputs
Function High Clear Hold
SSOP/ TSSOP/ TVSOP VIEW
Load
DESCRIPTION
Names xCLK xCLKEN xCLR Data Inputs
Description
Clock Inputs Clock Enable Inputs (Active LOW) Asynchronous Clear Inputs (Active LOW) Output Enable Input (Active LOW) 3-State Outputs
NOTES: HIGH Voltage Level Voltage Level Don't Care High Impedance LOW-to-HIGH transition Output level before indicated steady-state input conditions were established.
NOTE: These pins have "Bus-Hold". other pins standard inputs, outputs, I/Os.
IDT74LVCH162823A 3.3V CMOS 18-BIT INTERFACE REGISTER WITH TOLERANT
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40°C +85°C
Symbol IOZH IOZL IOFF ICCL ICCH ICCZ High Impedance Output Current (3-State Output pins) Input/Output Power Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 5.5V 2.3V, -18mA 3.3V 3.6V -0.7 -1.2 3.6V 5.5V Parameter Input HIGH Voltage Level Input Voltage Level Input Leakage Current 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 5.5V Test Conditions Min. Typ.(1) Max. Unit
Quiescent Power Supply Current Variation
5.5V(2) input 0.6V, other inputs
NOTES: Typical values 3.3V, +25°C ambient. This applies disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: Pins with Bus-Hold identified description. Typical values 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current 2.3V 3.6V
Test Conditions 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max. ±500
Unit
IDT74LVCH162823A 3.3V CMOS 18-BIT INTERFACE REGISTER WITH TOLERANT
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage 2.3V 2.7V Output Voltage 2.3V 3.6V 2.3V 2.7V Test Conditions(1) 2.3V 3.6V 0.1mA 12mA 0.1mA 12mA Min. Max. 0.55 0.55 Unit
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 3.3V 0.3V, 25°C
Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical Unit
IDT74LVCH162823A 3.3V CMOS 18-BIT INTERFACE REGISTER WITH TOLERANT
SWITCHING CHARACTERISTICS(1)
2.7V Symbol tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ tREM tSK(o) Parameter Propagation Delay xCLK Propagation Delay xCLR Output Enable Time Output Disable Time Set-up Time HIGH LOW, xCLK Hold Time HIGH LOW, xCLK Set-up Time HIGH LOW, xCLKEN xCLK Hold Time HIGH LOW, xCLKEN xCLK xCLK Pulse Width HIGH xCLR Pulse Width Recovery Time xCLR xCLK Output Skew(2) Min. Max. 3.3V 0.3V Min. Max. Unit
NOTES: TEST CIRCUITS WAVEFORMS. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74LVCH162823A 3.3V CMOS 18-BIT INTERFACE REGISTER WITH TOLERANT
TEST CIRCUITS WAVEFORMS TEST CONDITIONS
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
Pulse Generator D.U.T.
Link
VCC(2)= 2.5V±0.2V
Unit
VLOAD Open
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 tPHZ tPLZ DISABLE VLOAD/2 VOL+VLZ VOH-VHZ
Link
VOUT
Test Circuit Outputs
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
Enable Disable Times
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other Tests Switch VLOAD Open
tPLH2 tPHL2
Link
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
tREM
Link
INPUT
Set-up, Hold, Release Times
LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE
Link
tPLH1
tPHL1
OUTPUT
OUTPUT
tSK(x) tPLH2 tPLH1 tPHL2 tPHL1
Pulse Width
Output Skew tSK(X)
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74LVCH162823A 3.3V CMOS 18-BIT INTERFACE REGISTER WITH TOLERANT
ORDERING INFORMATION
Bus-Hold Temp. Range Family XXXX Device Type Package
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package
823A 18-Bit Interface Register Double-Density with Resistors, ±12mA Bus-hold -40°C +85°C
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3.3V CMOS 18-BIT INTERFACE REGISTER WITH VOLT TOLERANT BUS-HOLD T

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