3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER WITH BUS-HOLD VOLT TOLERANT

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3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER WITH BUS-HOLD VOLT TOLERANT

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IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER
3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER WITH BUS-HOLD VOLT TOLERANT
Typical tSK(o) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range CMOS power levels (0.4µ typ. static) inputs, outputs, tolerant Supports insertion Available SSOP, TSSOP, TVSOP packages
IDT74LVCH16276A
FEATURES:
DESCRIPTION:
DRIVE FEATURES: APPLICATIONS:
High Output Drivers: ±24mA Reduced system switching noise
3.3V mixed voltage systems Data communication telecommunication systems
LVCH16276A synchronous exchanger built using advanced dual metal CMOS technology.The LVCH16276A high-speed, bidirectional, 12-bit, registered, multiplexer synchronous memory interleaving applications. registers have common clock clock enable (CExxx) each data register control data sequencing. output enables select (OEA, SEL) also under synchronous control allowing direction changes edge triggered events. tri-port exchanger three 12-bit ports. Data transferred between port either/both ports. clock enable (CE1B, CE2B, CEA1B CEA2B) inputs control data storage. Both ports have common output enable (OEB) synchronously loading registers from port. pins LVCH16276A driven from either 3.3V devices. This feature allows this device translator mixed 3.3V/5V supply system. LVCH16276A been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. LVCH16276A "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
CEA1B
A-1B REGISTER 1B-A REGISTER
1:12
CE1B
1:12
CONTRO REGISTER
CE2B
2B-A REGISTER A-2B REGISTER
CEA2B
1:12
logo registered trademark Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4230/2
IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER
CONFIGURATION
CEA1B CEA2B CE1B CE2B 2B10 2B11 2B12 1B12 1B11 1B10
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description VTERM TSTG IOUT Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Current through each -0.5 +6.5 +150 ±100
Unit
NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
CAPACITANCE +25°C, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NOTE: applicable device type.
SSOP/ TSSOP/ TVSOP VIEW
IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER
DESCRIPTION
Signal A(1:12) 1B(1:12) 2B(1:12) CEA1B CEA2B CE1B CE2B Description Bidirectional Data Port Usually connected CPU's Address/Data bus.(1) Bidirectional Data Port Usually connected even path even bank memory.(1) Bidirectional Data Port Usually connected path bank memory.(1) Clock Input. Clock Enable Input A-1B Register. CEA1B during rising edge CLK, data will clocked into register A-1B (Active LOW). Clock Enable Input A-2B Register. CEA2B during rising edge CLK, data will clocked into register A-2B (Active LOW). Clock Enable Input 1B-A Register. CE1B during rising edge CLK, data will clocked into register 1B-A (Active LOW). Clock Enable Input 2B-A Register. CE2B during rising edge CLK, data will clocked into register 2B-A (Active LOW). Part Selection. When HIGH during rising edge CLK, enables data transfer from Port Port. When during rising edge CLK, enables data transfer from Port Port. Synchronous Output Enable Port (Active LOW). Synchronous Output Enable Port Port (Active LOW).
NOTE: These pins have "Bus-hold". other pins standard inputs, outputs, I/Os.
FUNCTION TABLES(1)
Inputs CE1B CE2B Outputs
Inputs CEA1B CEA2B B(2) B(2)
Outputs B(2) B(2) B(2) Active
NOTES: HIGH Voltage Level Voltage Level Don't Care High-Impedance LOW-to-HIGH Transition Output level before indicated steady-state input conditions were established.
Active
IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40°C +85°C
Symbol IOZH IOZL IOFF ICCL ICCH ICCZ High Impedance Output Current (3-State Output pins) Input/Output Power Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 5.5V 2.3V, -18mA 3.3V 3.6V -0.7 -1.2 3.6V 5.5V Parameter Input HIGH Voltage Level Input Voltage Level Input Leakage Current 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 5.5V Test Conditions Min. Typ.(1) Max. Unit
Quiescent Power Supply Current Variation
5.5V(2) input 0.6V, other inputs
NOTES: Typical values 3.3V, +25°C ambient. This applies disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: Pins with Bus-Hold identified description. Typical values 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current 2.3V 3.6V
Test Conditions 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max. ±500
Unit
IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage 2.3V 2.3V 2.7V Output Voltage 2.3V 3.6V 2.3V 2.7V 24mA 0.1mA 12mA 12mA 24mA Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. Max. 0.55 Unit
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 3.3V 0.3V, 25°C
Symbol Parameter Power Dissipation Capacitance Exchanger Outputs enabled Power Dissipation Capacitance Exchanger Outputs disabled Test Conditions 0pF, 10Mhz Typical Unit
IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER
SWITCHING CHARACTERISTICS(1)
2.7V Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay Propagation Delay Output Enable Time 1Bx, Output Disable Time 1Bx, Set-Up Time, HIGH Data Set-Up Time, CLK, Set-Up Time, Set-Up Time, CEA1B CLK, CE1B CE2B CLK, CEA2B Hold Time, Data Hold Time, OEA, OEB, Hold Time, CEA1B, CE1B, CE2B, CEA2B Pulse Width, HIGH Output Skew(2) stable, CExB Enabled changing, CExB Disabled changing, CExB Enabled Min. Max. 3.3V 0.3V Min. Max. Unit
NOTES: TEST CIRCUITS WAVEFORMS. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER
TEST CIRCUITS WAVEFORMS TEST CONDITIONS
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
Pulse Generator D.U.T.
Link
VCC(2)= 2.5V±0.2V
Unit
VLOAD Open
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 tPHZ tPLZ DISABLE VLOAD/2 VOL+VLZ VOH-VHZ
Link
VOUT
Test Circuit Outputs
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
Enable Disable Times
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other Tests Switch VLOAD Open
tPLH2 tPHL2
Link
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
tREM
Link
INPUT
Set-up, Hold, Release Times
LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE
Link
tPLH1
tPHL1
OUTPUT
OUTPUT
tSK(x) tPLH2 tPLH1 tPHL2 tPHL1
Pulse Width
Output Skew tSK(X)
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER
ORDERING INFORMATION
Bus-Hold Temp. Range Family XXXX Device Type Package
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package
276A 12-Bit Synchronous Exchanger Double-Density, ±24mA Bus-hold -40°C +85°C
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3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER WITH BUS-HOLD VOLT TOLERANT

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