3.3V CMOS 18-BIT IDT74LVCH16501A REGISTERED TRANSCEIVER WITH TOLERANT

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3.3V CMOS 18-BIT IDT74LVCH16501A REGISTERED TRANSCEIVER WITH TOLERANT

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IDT74LVCH16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH VOLT
3.3V CMOS 18-BIT IDT74LVCH16501A REGISTERED TRANSCEIVER WITH TOLERANT BUS-HOLD
Typical tSK(o) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range CMOS power levels (0.4µ typ. static) inputs, outputs, tolerant Supports insertion Available SSOP, TSSOP, TVSOP packages
FEATURES:
DESCRIPTION:
DRIVE FEATURES: APPLICATIONS:
High Output Drivers: ±24mA Reduced system switching noise 3.3V mixed voltage systems Data communication telecommunication systems
This 18-bit registered transceiver built using advanced dual metal CMOS technology. This high-speed, power 18-bit registered transceiver combines D-type latches D-type flip-flops allow data flow transparent latched clocked modes. Data flow each direction controlled output-enable (OEAB OEBA), latch enable (LEAB LEBA) clock (CLKAB CLKBA) inputs. A-to-B data flow, device operates transparent mode when LEAB high. When LEAB low, data latched CLKAB held high logic level. LEAB low, data stored latch/flip-flop low-to-high transition CLKAB. OEAB performs output enable function port. Data flow from port port similar requires using OEBA, LEBA CLKBA. Flow-through organization signal pins simplifies layout. inputs designed with hysteresis improved noise margin. LVCH16501A been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. LVCH16501A "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
OEAB CLKBA LEBA OEBA CLKAB LEAB
OTHER CHANNELS
logo registered trademark Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-3688/1
IDT74LVCH16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH VOLT
CONFIGURATION
OEAB LEAB OEBA LEBA CLKAB CLKBA
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description VTERM TSTG IOUT Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Current through each -0.5 +6.5 +150 ±100
Unit
NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
CAPACITANCE +25°C, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NOTE: applicable device type.
FUNCTION TABLE(1,2)
Inputs OEAB LEAB CLKAB Output B(3) B(4)
SSOP/ TSSOP/ TVSOP VIEW
DESCRIPTION
Names OEAB OEBA LEAB LEBA CLKAB CLKBA Description A-to-B Output Enable Input B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs B-to-A 3-State Outputs(1) B-to-A Data Inputs A-to-B 3-State Outputs(1)
NOTE: These pins have "Bus-Hold". other pins standard inputs, outputs, I/Os.
NOTES: A-to-B data flow shown. B-to-A data flow similar, uses OEBA, LEBA, CLKBA. HIGH Voltage Level Voltage Level Don't Care High-Impedance LOW-to-HIGH Transition Output level before indicated steady-state input conditions were established. Output level before indicated steady-state input conditions were established, provided that CLKAB HIGH before LEAB went LOW.
IDT74LVCH16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH VOLT
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40°C +85°C
Symbol IOZH IOZL IOFF ICCL ICCH ICCZ High Impedance Output Current (3-State Output pins) Input/Output Power Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 5.5V 2.3V, -18mA 3.3V 3.6V -0.7 -1.2 3.6V 5.5V Parameter Input HIGH Voltage Level Input Voltage Level Input Leakage Current 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 5.5V Test Conditions Min. Typ.(1) Max. Unit
Quiescent Power Supply Current Variation
5.5V(2) input 0.6V, other inputs
NOTES: Typical values 3.3V, +25°C ambient. This applies disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: Pins with Bus-Hold identified description. Typical values 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current 2.3V 3.6V
Test Conditions 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max. ±500
Unit
IDT74LVCH16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH VOLT
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage 2.3V 2.3V 2.7V Output Voltage 2.3V 3.6V 2.3V 2.7V 24mA 0.1mA 12mA 12mA 24mA Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. Max. 0.55 Unit
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 3.3V 0.3V, 25°C
Symbol Parameter Power Dissipation Capacitance Transceiver Outputs enabled Power Dissipation Capacitance Transceiver Outputs disabled Test Conditions 0pF, 10Mhz Typical Unit
IDT74LVCH16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH VOLT
SWITCHING CHARACTERISTICS(1)
2.7V Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay Propagation Delay LEBA LEAB Propagation Delay CLKBA CLKAB Output Enable Time OEBA OEAB Output Disable Time OEBA OEAB Set-up Time, HIGH CLKAB, CLKBA Hold Time, HIGH CLKAB, CLKBA Set-up Time, HIGH LEAB, LEBA Hold Time, HIGH LEAB, LEBA Pulse Width HIGH, LEAB LEBA Pulse Width HIGH LOW, CLKAB CLKBA Output Skew(2) HIGH Min. Max. 3.3V 0.3V Min. Max. Unit
NOTES: TEST CIRCUITS WAVEFORMS. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74LVCH16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH VOLT
Link
TEST CIRCUITS WAVEFORMS TEST CONDITIONS
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
Pulse Generator D.U.T.
Link
SAME PHASE INPUT TRANSITION
VCC(2)= 2.5V±0.2V
Unit
VLOAD Open
tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
tPHL
tPHL
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 tPHZ tPLZ DISABLE VLOAD/2
Link
VOUT
Test Circuit Outputs
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
Enable Disable Times
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other Tests Switch VLOAD Open
tPLH2 tPHL2
Link
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
tREM
Link
Set-up, Hold, Release Times
INPUT
tPLH1
tPHL1
LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE
OUTPUT
Link
OUTPUT
Pulse Width
tSK(x) tPLH2 tPLH1 tPHL2 tPHL1
Output Skew tSK(X)
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74LVCH16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH VOLT
ORDERING INFORMATION
Bus-Hold Temp. Range Family XXXX Device Type Package
501A
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package 18-bit Registered Transceiver Double-Density, ±24mA Bus-hold -40°C +85°C
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3.3V CMOS 18-BIT IDT74LVCH16501A REGISTERED TRANSCEIVER WITH TOLERANT

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