DSP96002 32-BIT GENERAL PURPOSE FLOATING-POINT DUAL-PORT PROCESSO
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DSP96002
32-BIT GENERAL PURPOSE FLOATING-POINT DUAL-PORT PROCESSOR
DSP96002 designed support intensive graphic image numeric processing. dual-port, low-power, general purpose floating-point processor. includes 1024 words data (equally divided into data data memory), 1024 words fullspeed on-chip Program RAM, data ROMs, dual-channel Direct Memory Access (DMA) controller, special on-chip bootstrap hardware, On-Chip Emulation (OnCETM) debug circuitry. Central Processing Unit (CPU) consists three 32-bit execution units operating parallel. DSP96002 identical memory expansion ports with control lines facilitate interfacing SRAMs, DRAMs (operating their fast access modes), Video RAMs (VRAMs). Each port configured Host Interface (HI), which facilitates easy interface with other processors multiprocessor applications. Linear arrays DSP96002s implemented without glue logic. MPU-style programming model instruction allow straightforward generation efficient, compact code. high speed DSP96002 makes well-suited high bandwidth numerically intensive applications that require floating-point processing access large memory subsystems.
Control Control
Freescale Semiconductor, Inc.
Control
Address Generation Unit (AGU) Program Data Memory Memory 1024 Bootstrap Instruction Cache Data Memory
Control
Address External Address Switch Dual Channel Controller Internal Switch Manipulation Unit
External Address Address Switch Port Data AA0306
Port
32-bit Host Interface Timer External Data Switch
32-bit Host Interface Timer External Data Switch
Data
Clock Generator
Program Decode Controller
Program Address Generator Program Controller
Program Interrupt Controller
OnCE Data Debug IEEE Floating Point Controller Integer Serial Debug Port
32-bit Buses Dual Access (DMA/Core) 1024 Virtual Locations
MODC/IRQC MODB/IRQB MODA/IRQA RESET
Figure Block Diagram
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TABLE CONTENTS
SECTION SECTION SECTION SECTION SECTION
SIGNAL/CONNECTION DESCRIPTIONS SPECIFICATIONS PACKAGING DESIGN CONSIDERATIONS ORDERING INFORMATION BOOTSTRAP CODE DSP96002. MEMORY TABLES TECHNICAL ASSISTANCE:
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APPENDIX APPENDIX
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Data Sheet Conventions
This data sheet uses following conventions:
OVERBAR "asserted" "deasserted" Examples: Used indicate signal that active when pulled (For example, RESET active when low.) Means that high true (active high) signal high that true (active low) signal Means that high true (active high) signal that true (active low) signal high Signal/Symbol
Note:
Logic State True False True False
Signal State Asserted Deasserted Asserted Deasserted
Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Values VIL, VOL, VIH, defined individual product specifications.
DSP96002/D, Rev.
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DSP96002 Features
FEATURES
Digital signal processing core Efficient 32-bit engine Conforms IEEE 754-1985 standard single precision (32-bit) single extended precision (44-bit) arithmetic Million Instructions Second (MIPS) Parallel operation Data ALU, Address Generation Unit (AGU), program controller within allow more processing instruction cycle Single-cycle parallel multiplier Highly parallel instruction with unique addressing modes Nested hardware loops Instruction cache extended operate byte word) Fast auto-return interrupts Address buses: 32-bit unidirectional internal memory Address (XAB) 32-bit unidirectional internal memory Address (YAB) 32-bit internal Program Address (PAB) 32-bit external address buses
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Data buses: 32-bit bidirectional internal memory Data (XDB) 32-bit bidirectional internal memory Data (YDB) 32-bit bidirectional internal Global memory Data (GDB) 32-bit bidirectional internal Data (DDB) 32-bit bidirectional internal Program Data (PDB) 32-bit external data buses
MCU-like instruction mnemonics make programming easier On-chip 1024 32-bit Program independent on-chip 32-bit data RAMs independent on-chip 32-bit data ROMs (1024 32-bit virtual memory) On-chip 32-bit bootstrap
Memory
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DSP96002 Product Documentation
Off-chip expansion 32-bit words data memory Off-chip expansion 32-bit words program memory
Miscellaneous features expansion ports assignable data, data, program memory spaces combination thereof, effectively doubling off-chip bandwidth. Host interface circuitry each port provides flexible slave interface Direct Memory Access (DMA) controllers external processors easy design multimaster systems Write strobe pins support interface external SRAMs without additional logic programmable timers/counters Three external interrupt/mode control lines external reset line hardware reset 4-pin OnCE port unobtrusive, processor speed-independent debugging HCMOS design operating frequencies from down 223-pin plastic Grid Array (PGA) package 240-pin Ceramic Quad Flat Pack (CQFP) package power supply
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PRODUCT DOCUMENTATION
manuals listed Table required complete description DSP96002 necessary design properly with device. Documentation available from local Motorola distributor, Motorola semiconductor sales office, Motorola Literature Distribution Center, through Motorola home page Internet (the source latest information).
Table Additional Documentation
Document Name DSP96002 User's Manual DSP96002 Data Sheet Description Detailed description DSP96002 core processor peripherals Electrical timing specifications, package descriptions Order Number DSP96002UM/AD DSP96002/D
DSP96002/DRev.
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SECTION SIGNAL/CONNECTION DESCRIPTIONS
SIGNAL GROUPINGS
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input output signals DSP96002 organized into eight functional groups, shown Table illustrated Figure 1-1. Table DSP96002 Functional Signal Groupings
Functional Group Power (VCCN VCCQ) Ground (GNDN GNDQ) Clock (CLK) Interrupt Mode Control Port (Address, Data, Control) Port (Address, Data, Control) Timer/Event Counters OnCE Port Detailed Description Table Table Table Table Table Table Table Table
Figure diagram DSP96002 signals functional group.
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Signal/Connection Descriptions Signal Groupings
Power1 VCCN VCCQ Ground2 GNDN GNDQ Clock Input
DSP96002
Address BA0-BA31 Data BD31 Port Control BR/W
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Interrupt Mode Control MODA/IRQA MODB/IRQB MODC/IRQC RESET
Address AA0-AA31 Data AD0-AD31 Port Control AR/W Note:
Timer/Event Counters TIO0-TIO1
On-Chip Emulation Port (OnCE) DSI/OSO DSCK/OS1
Number power input pins package dependent. Section Number ground connections package dependent. Section
Figure Functional Group Allocations
DSP96002/D, Rev.
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Signal/Connection Descriptions Power
POWER
Table Power Inputs
Power Name VCCN Description Normal Power -VCCN inputs provided general with DSP96002 peripheral circuits. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. Quiet Power-VCCQ inputs provide isolated power internal processing logic. voltage should well-regulated, input should provided with extremely impedance path power rail. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors.
number available power connecctions package-dependent. Section description individual package pinouts.
VCCQ
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Note:
detailed
GROUND
Table Grounds
Ground Name GNDN Description Normal Ground -GNDP connections provide ground return DSP96002 peripheral circuits. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. Quiet Ground -GNDQ isolated ground internal processing logic. connection should provided with extremely low-impedance path ground. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors.
number available ground connecctions package-dependent. Section description individual package pinouts.
GNDQ
Note:
detailed
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Signal/Connection Descriptions Clock
CLOCK
Table Clock Signal
Signal Name Type Input State During Reset Input Signal Description Clock Input-CLK high frequency processor clock input. frequency twice instruction rate. shown Figure 1-2, internal phase generator divides into four phases (t0, t3), which basic instruction execution cycle. Additional phases optionally generated insert Wait States (WS) into instruction execution. Wait State formed pairing phase. should continuous with duty cycle.
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Instruction Cycle Wait States
Instruction Cycle Wait States
Figure Clock Input Instruction Cycle Timing
DSP96002/D, Rev.
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Signal/Connection Descriptions Interrupt Mode Control
INTERRUPT MODE CONTROL
Table Interrupt Mode Control
Signal Name RESET Type State During Reset Signal Description Reset-This input direct hardware reset processor. When RESET asserted low, signal internally synchronized input clock (CLK), placed Reset state, internal phase generator reset. Schmitt trigger input used noise immunity allows slowly rising input (such capacitor charging) reliably reset chip. RESET deasserted synchronous input clock (CLK), exact start-up timing guaranteed, allowing multiple processors start-up synchronously operate together "lock-step." When RESET deasserted, initial chip operating mode latched from MODA, MODB MODC pins. Mode Select A/External Interrupt Request A-This input internally synchronized input clock (CLK). MODA/IRQA selects initial chip operating mode during hardware reset becomes level-sensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB MODC select eight initial chip operating modes latched into Operating Mode Register (OMR) when RESET deasserted. IRQA asserted synchronous input clock (CLK), multiple processors resynchronized using WAIT instruction asserting IRQA exit Wait state. processor Stop standby state IRQA asserted, processor will exit Stop state. Mode Select B/External Interrupt Request B-This input internally synchronized input clock (CLK). MODB/IRQB selects initial chip operating mode during hardware reset becomes level-sensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB MODC select eight initial chip operating modes latched into Operating Mode Register (OMR) when RESET deasserted. IRQB asserted synchronous input clock (CLK), multiple processors resynchronized using WAIT instruction asserting IRQB exit Wait state.
Input Input
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MODA/IRQA
Input Input
MODB/ IRQB
Input Input
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Signal/Connection Descriptions Port Port
Table Interrupt Mode Control (Continued)
Signal Name MODC/IRQC Type State During Reset Signal Description Mode Select C/External Interrupt Request C-This input internally synchronized input clock (CLK). MODC/IRQC selects initial chip operating mode during hardware reset becomes level-sensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB MODC select eight initial chip operating modes latched into Operating Mode Register (OMR) when RESET deasserted. IRQC asserted synchronous input clock (CLK), multiple processors resynchronized using WAIT instruction asserting IRQC exit Wait state.
Input Input
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PORT PORT
Port Port identical pinout function. following descriptions apply both ports. Each port master each port slave Host Interface which accessed demand.
Table Port Port
Signal Name
AA0-AA31 BA0-BA31
Type
Input Output
State During Reset
Tri-stated
Signal Description
Address Bus-A0-A31 specify address external program data memory accesses. there external activity, A0-A31 remain their previous values. Address Enable (AE) input acts output enable control A0-A31. A0-A31 stable whenever transfer strobe asserted change only when deasserted. signal direction depends whether master: Master-A0-A31 tri-state, active high outputs. Master-A2-A5 active high inputs used select Host Interface register. Lines A6-A31 tri-stated. inputs, A2-A5 change asynchronously relative input clock (CLK).
DSP96002/D, Rev.
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Signal/Connection Descriptions Port Port
Table Port Port (Continued)
Signal Name
AD0-AD31 BD0-BD31
Type
Input/ Output
State During Reset
Tri-stated
Signal Description
Data Bus-D0-D31 tri-state, active high, bidirectional input/outputs whether master not. Data Enable (DE) input acts output enable control D0-D31. master, data lines controlled instruction execution controller. also Host Interface data lines. there external activity, D0-D31 tri-stated. Space Select-These signals viewed different ways, depending external memories mapped. They support splitting memory spaces among ports, mapping multiple memory spaces into same physical memory locations. outputs when master tri-stated when master. Timing same address lines A31. Read/Write-R/W output when master input when master. master timing same DSP96002 address lines, giving "early write" signal DRAM interfacing. high read access write access. also Host Interface read/write input. input, change asynchronously relative input clock. goes high external used during instruction cycle. Write Strobe output when master tri-stated when master. supports glueless interface external SRAMs. asserted during external memory write cycles indicate that address lines A0-A32, stable. output data goes data after asserted. requires weak external pull-up resistor connected directly Static RAM. Strobe-BS output when master tri-stated when master. strobe asserted start cycle (providing "early start" signal DRAM interfacing) deasserted cycle. early negation provides "early end" signal useful external control. external used during instruction cycle, remains deasserted until next external cycle.
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AS0-AS1 BS0-BS1
Output
Tri-stated
AR/W BR/W
Input Output
Tri-stated
Output
Tri-stated
Output
Tri-stated
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Signal/Connection Descriptions Port Port
Table Port Port (Continued)
Signal Name
Type
Output
State During Reset
Tri-stated
Signal Description
Transfer Type-TT output when master tri-stated when master. When master, controlled on-chip page circuit. asserted when fast access memory mode (Page, Static Column, Nibble Serial Shift Register) detected. external used during instruction cycle, fault detected page circuit during external access, remains deasserted. parameters page circuit fault detection user programmable. Transfer Strobe-TS output when master input when master. When master, asserted indicate that address lines A0-A31, stable that read write transfer taking place. During read cycle, input data latched inside DSP96002 rising edge During write cycle, output data placed data after asserted. Therefore, used output enable control external data buffers they present. external used during instruction cycle, remains deasserted until next external cycle. external flip-flop delay required, slow devices more address decoding time. also Host Interface transfer strobe input used enable data output drivers during host read operations latch data inside Host Interface during host write operations. input, change asynchronously relative input clock. Write data latched inside Host Interface rising edge When master, combination decoded externally determine status current cycle generate hardware strobes useful latching address data signals.
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Input Output
Tri-stated
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Signal/Connection Descriptions Port Port
Table Port Port (Continued)
Signal Name
Type
Input
State During Reset
Input, ignored during reset
Signal Description
Transfer Acknowledge- input synchronous "DTACK" function that extend external cycle indefinitely. must asserted deasserted synchronously input clock (CLK) proper operation. sampled falling edge input clock (CLK). number wait states infinity) inserted keeping deasserted. typical operation, first deasserted start cycle, then asserted enable completion cycle, finally deasserted before next cycle.The current cycle completes clock period after asserted synchronously CLK. number wait states determined input Control Register (BCR), whichever longer. used minimum number wait states external cycles. tied (asserted) wait states specified BCR, zero wait states will inserted into external cycles.
Note: DSP96002 master there external activity DSP96002 master, then input ignored core.
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Input
Input, ignored during reset
Address Enable-AE input that must asserted deasserted synchronous input clock (CLK) proper operation. master, asserted enable A0-A31 address output drivers. deasserted, address output drivers tri-stated. master, address output drivers tristated regardless whether asserted deasserted. function allow implementation multiplexed systems. example such implementation multiplexed address1/address2 used with dual port memories, such dynamic VRAMs.
Note: There must least undriven period between enables multiplexed buses allow tristate before another enabled. External control responsible this timing. non-multiplexed systems, should tied low.
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Signal/Connection Descriptions Port Port
Table Port Port (Continued)
Signal Name
Type
Input
State During Reset
Input, ignored during reset
Signal Description
Data Enable-DE input that must asserted deasserted synchronous input clock (CLK) proper operation. master Host Interface being read, asserted enable D0-D31 data output drivers. deasserted, data output drivers tri-stated. master, data output drivers tri-stated regardless whether asserted deasserted. Read-only cycles performed even though deasserted. function allow multiplexed systems implemented. example multiplexed data1/data2 used long word transfers with 32-bit wide memory.
Note: There must least undriven period between enables multiplexed buses allow tristate before another enabled. External control responsible this timing. non-multiplexed systems, should asserted (tied low).
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Input
Input
Host Select-HS input that change asynchronous input clock. asserted enable selection Host Interface functions address lines A2-A5. asserted when asserted, data transfer with Host Interface will take place.
Note: Both must tied high disable Host Interface. When asserted, ignored.
1-10
DSP96002/D, Rev.
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Signal/Connection Descriptions Port Port
Table Port Port (Continued)
Signal Name
Type
Input
State During Reset
Input
Signal Description
Host Acknowledge-HA input that change asynchronously input clock. used acknowledge either interrupt request request Host Interface. When Host Interface mode, asserting when asserted will enable contents Host Interface Interrupt Vector Register (IVR) onto data outputs D0-D31. This provides interrupt acknowledge capability compatible with MC68000 family processors. Host Interface mode, used transfer acknowledge input asserted external device transfer data between Host Interface registers external device. read mode, asserted read Host Interface register data outputs D0-D31. Write mode, asserted strobe external data into Host Interface register. Write data latched into register rising edge
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Output
Driven high
Host Request-HR output that never tri-stated. host request asserted indicate that Host Interface requesting service-either interrupt request request-from external device. output connected interrupt request input IRQA, IRQB, IRQC another DSP96002. on-chip Controller channel other DSP96002 select interrupt request input transfer request input. Request-BR output that never tri-stated. asserted when requesting mastership. deasserted when longer needs bus. asserted deasserted independent whether DSP96002 master slave. "parking" allows deasserted even though DSP96002 master (see description "parking" description). Control Register allows asserted under software control even though does need bus. typically sent external arbitrator, which controls priority, parking, tenure each DSP96002 same external bus. only affected requests external bus, never internal bus. During hardware reset, deasserted arbitration reset Slave state.
Output
Driven high
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Signal/Connection Descriptions Port Port
Table Port Port (Continued)
Signal Name
Type
Input
State During Reset
Input, ignored during reset
Signal Description
Grant-BG input that must asserted/ deasserted synchronous input clock (CLK) proper operation. asserted external arbitration circuit indicating DSP96002 become pending master. When asserted, DSP96002 must wait until deasserted before taking mastership. When deasserted, mastership typically given current cycle. This occur middle instruction, which requires more than external cycle execution.
Note: Indivisible read-modify-write instructions (BSET, BCLR, BCHG) will give mastership until current instruction. ignored during hardware reset.
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Signal/Connection Descriptions Port Port
Table Port Port (Continued)
Signal Name
Type
Output
State During Reset
Tri-stated
Signal Description
Acknowledge-BA open drain output. When deasserting DSP96002 drives high during half cycle then disables active pull-up. this way, only weak external pull-up resistor required hold line high. directly connected order obtain same functionality MC68040 pin. When asserted, DSP96002 becomes pending master. waits until negated previous master, indicating that previous master bus. pending master asserts become current master. asserted when either taken master. While asserted, DSP96002 owner (the master). When deasserted, DSP96002 slave. used tri-state enable control external address, data, control signal buffers.
Note: current master keep asserted after ceasing activity, regardless whether asserted deasserted. This called "bus parking" allows current master repeatedly without rearbitration until some other device wants bus.
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current master keeps asserted during indivisible read-modify-write cycles, regardless whether been deasserted external arbitration unit. This form "bus locking" allows current master perform atomic operations shared variables multitasking multiprocessor systems. Current instructions that perform indivisible read-modifywrite cycles BCLR, BCHG BSET.
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Signal/Connection Descriptions Port Port
Table Port Port (Continued)
Signal Name
Type
Input
State During Reset
Input
Signal Description
Busy-BB input that must asserted deasserted synchronous input clock (CLK) proper operation. deasserted when there master external bus. multiple DSP96002 systems, inputs tied together driven logical outputs. asserted when pending master becomes current master (directly indirectly assertion). deasserted current master (directly indirectly deassertion) indicate that longer master. pending master monitors signal until deasserted. Then pending master asserts become current master, which asserts directly indirectly.
Note: pull-up resistors recommended.
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Output
Driven high
Lock-BL output that never tri-stated. Asserted start external indivisible Read-Modify-Write (RMW) cycle (providing "early start" signal DRAM interfacing) deasserted write cycle, remains asserted between read write cycles read-modify-write sequence. used indicate that special memory timing (such timing DRAMs) used "resource lock" external multi-port memory secure semaphore updates. early negation provides "early end" signal useful external control. external used during instruction cycle, remains deasserted until next external indivisible read-modify-write cycle. also remains deasserted external cycle indivisible read-modify-write cycle there internal cycle. only instructions that automatically assert BSET, BCLR BCHG instruction, which accesses external memory. also asserted setting BCR.
1-14
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Signal/Connection Descriptions Timer/Event Counter
TIMER/EVENT COUNTER
Table Timer/Event Counters
Signal Name
TIO0- TIO1
Type
Input Output
State During Reset
Input
Signal Description
Timer/Event Counter -The bidirectional signal connects on-chip Timer/Event Counter. When used input, module functioning external event counter measuring external pulse width/signal period. When used output, module functioning timer, becomes timer pulse. When used timer module, used General Purpose Input/Output (GPIO) pin. timer internal external clocking interrupt processor after number events specified user program, signal external device after counting internal events. timer also used trigger transfers after specified number events (clocks) occurs. When timer disabled, becomes tri-stated. prevent undesired spikes from occurring, should pulled down when use.
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Signal/Connection Descriptions OnCE Port
OnCE PORT
Table On-Chip Emulation Port (OnCE) Signals
Signal Name DSI/OS0 Signal Type Output State during Reset Output Signal Description
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Debug Serial Input/Chip Status 0-Serial data commands provided OnCE controller through DSI/OS0 signal when input. data received signal will recognized only when entered Debug mode operation. Data latched falling edge DSCK serial clock. Data always shifted into OnCE serial port Most Significant (MSB) first. When DSI/OS0 signal output, works conjunction with signal provide chip status information. DSI/OS0 signal output when processor Debug mode. When switching from output input, signal tri-stated.
Note: OnCE interface use, external pull-down resistor should attached this pin. OnCE interface use, resistor required.
DSCK/
Output
Output
Debug Serial Clock/Chip Status 1-The DSCK/OS1 signal supplies serial clock OnCE when input. serial clock provides pulses required shift data into OnCE serial port. (Data clocked into OnCE falling edge clocked OnCE serial port rising edge.) debug serial clock frequency must greater than processor clock frequency. When switching from input output, signal tri-stated. When output, this signal works with signal provide information about chip status. DSCK/OS1 signal output when chip Debug mode.
Note: OnCE interface use, external pull-down resistor should attached this pin. OnCE interface use, resistor required.
1-16
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Signal/Connection Descriptions OnCE Port
Table On-Chip Emulation Port (OnCE) Signals (Continued)
Signal Name Signal Type Output State during Reset Output, pulled high Signal Description
Debug Serial Output-Data contained OnCE controller registers provided through output signal, specified last command received from external command controller. Data always shifted OnCE serial port first. Data clocked OnCE serial port rising edge DSCK. signal also provides acknowledge pulses external command controller. When chip enters Debug mode, signal will pulsed indicate (acknowledge) that OnCE waiting commands. After OnCE receives read command, signal will pulsed indicate that requested data available OnCE serial port ready receive clocks order deliver data. After OnCE receives write command, signal will pulsed indicate that OnCE serial port ready receive data written; after data written, another acknowledge pulse will provided.
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Input
Input
Debug Request-The Debug Request input (DR) allows user enter Debug mode operation from external command controller. When asserted, causes finish current instruction being executed, save instruction pipeline information, enter Debug mode, wait commands entered from line. While Debug mode, signal lets user reset OnCE controller asserting deasserting after receiving acknowledge. necessary reset OnCE controller cases where synchronization between OnCE controller external circuitry lost. must deasserted after OnCE responds with acknowledge signal before sending first OnCE command. Asserting will cause chip exit Stop Wait state. Having asserted during deassertion RESET will cause enter Debug mode.
Note: OnCE interface use, attach external pull-up resistor input.
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Signal/Connection Descriptions OnCE Port
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SECTION SPECIFICATIONS
INTRODUCTION
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digital signal processor (DSP) fabricated using high-density Complementary Metal Oxide Semiconductor (CMOS) with Transistor-TransistorLogic (TTL) compatible inputs outputs. This section covers maximum ratings, thermal characteristics, electrical characteristics DSP96002. Note: Reliability operation enhanced unused inputs tied appropriate logic voltage level (e.g., either VCC).
MAXIMUM RATINGS
CAUTION
This device contains circuitry protecting against damage high static voltage electrical fields; however, normal precautions should taken avoid exceeding maximum voltage ratings. Reliability enhanced unused inputs tied appropriate logic voltage level (e.g., either VCC).
Note: calculation timing requirements, adding maximum value specification minimum value another specification does yield reasonable sum. maximum specification calculated using worst case variation process parameter values direction. minimum specification calculated using worst case same parameters opposite direction. Therefore, "maximum" value specification will never occur same device that "minimum" value another specification; adding maximum minimum represents condition that never exist.
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Specifications Thermal Characteristics
Table Maximum Electrical Ratings
Rating
Supply Voltage Input Voltages Current Drain excluding VSS1 Operating Temperature Range Storage Temperature
Symbol
Tstg
Value
-0.3 +7.0 +100 +150
Unit
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Note:
THERMAL CHARACTERISTICS
Table Thermal Characteristics
Characteristic
Junction Ambient1 Junction Case2 Thermal characterization parameter
Note:
Symbol
Value
CQFP Value
Unit °C/W °C/W °C/W
Junction-to-ambient thermal resistance based measurements horizontal single-sided printed circuit board SEMI G38-87 natural convection. SEMI Semiconductor Equipment Materials International, East Middlefield Road, Mountain View, 94043, (415) 964-5111. Junction-to-case thermal resistance based measurements using cold plate SEMI G30-88 with exception that cold plate temperature used case temperature.
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Specifications Electrical Characteristics
ELECTRICAL CHARACTERISTICS
Table Electrical Characteristics
Characteristic1
Supply Voltage, +10% 33.3 Except CLK, RESET MODA, MODB,MODC Except CLK, MODA, MODB, MODC RESET MODA, MODB, MODC MODA, MODB, MODC @2.4 V/0.5
Symbol
4.75 4.75
Typical
5.25 5.25
Unit
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Input High Voltage Input Voltage Input High Voltage Input Voltage Input High Voltage Input High Voltage Input Voltage Input Leakage Current Tri-State (OffState) Input Current Output High Voltage Output High Voltage Output Voltage
-0.5
VIHC VILC VIHR VIHM VILM
-0.5 -0.5
ITSI -0.4
VOHC VOLC
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Specifications Electrical Characteristics
Table Electrical Characteristics (Continued)
Characteristic1
Output Voltage Power Dissipation Total Supply Current 33.3 MHz2,3 MHz2,3 MHz2,3 33.3 Wait Mode2,3 Stop Mode2,3 Wait Mode2,3 Stop Mode2,3 Wait Mode2,3 Stop Mode2,3 Input Capacitance4
Note:
Symbol
Typical
1.25 1.75
Unit
IDDW IDDS IDDW IDDS IDDW IDDS
Freescale Semiconductor, Inc.
Electrical Characteristics: 33.3 MHz: 10%, -40°C 100°C MHz: -40°C 100°C measured 0.2V. with loads. driven dutycycle oscillator. order obtain these results inputs must terminated (i.e., allowed float). Input capacitance tested production.
DSP96002/D, Rev.
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MOTOROLA
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
ELECTRICAL CHARACTERISTICS
timing waveforms shown this section tested with following values:
maximum minimum pins1
Note: CLK, RESET, MODA, MODB, MODC tested using input levels described Electrical Characteristics page 2-3.
Freescale Semiconductor, Inc.
timing specifications that referenced device input signal measured production with respect VIH/VIL levels respective input signal's transition. timing specifications that referenced device's output levels measured with production test machine reference levels respectively. load capacitances greater than 50pF, drive capability output pins derates linearly additional capacitance from loading, additional capacitance loads greater than
Pulse Width Input Signal midpoint1 Fall Time Note: Rise Time High
midpoint (VIH VIL)/2
Figure Signal Measurement Reference
MOTOROLA
DSP96002/D, Rev.
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Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
Clock Operation
DSP96002 system clock derived from crystal external system clock signal. clock input active high input, high frequency processor clock. frequency twice instruction rate. internal phase generator divides into four phases (t0, t3), which basic instruction execution cycle. Additional phases optionally generated insert Wait States (WS) into instruction execution. wait state formed pairing phase. should continuous with 46-54% duty cycle. Table Clock Operation
Freescale Semiconductor, Inc.
Characteristic
Symb.
33.3 MHz3
MHz4
MHz4
Unit
Instruction Cycle Time Instruction Cycle Time Wait State Wait State
Note:
Icyc
11.5 11.5
13.5 13.5
33.3 16.7 16.7
Cycle Time Cycle Time Rise Time Fall Time High
numbers this column shown circled numbers following figures. Electrical Characteristics: 33.3 MHz: 10%, -40°C 100°C MHz: -40°C 100°C 46%-54% Duty Cycle 46.7%-53.3% Duty Cycle
VIHC Midpoint1 VILC
Note:
midpoint (VCC GND).
Figure Timing Diagram
DSP96002/D, Rev.
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MOTOROLA
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
Arbitration Timing
Table Arbitration Timing
33.3
Characteristic
Unit
High Asserted Deasserted Valid High (Setup) High Invalid (Hold) High Asserted Deasserted Valid High (Setup) High Invalid (Hold) High A0-A31, S0-S1, R/W, Active A0-A31, S0-S1, R/W, tristate Deasserted High A0-A31, S0-S1, R/W, tri-state tri-state
Freescale Semiconductor, Inc.
Note:
numbers this column shown circled numbers following figures. Electrical Characteristics: 33.3 MHz: 10%, -40°C 100°C MHz: -40°C 100°C
MOTOROLA
DSP96002/D, Rev.
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Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
(input) (output) (input)
Freescale Semiconductor, Inc.
(input) (output) A0-A31, R/W, S0-S1, (output) (output) write cycle (Tri-state)
(Tri-state)
(Tri-state)
Figure Acquisition Timing
DSP96002/D, Rev.
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MOTOROLA
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
(input) (output) (input) (output) (Tri-state) A0-A31, R/W, S0-S1 (output) (output) (output) write cycle (Tri-state) (Tri-state) (Tri-state)
Freescale Semiconductor, Inc.
(Tri-state)
Figure Release Timing
MOTOROLA
DSP96002/D, Rev.
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Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
External Relative Timing
Table External Relative Timing
Characteristic
33.3 MHz3
MHz4
MHz4 Unit
A0-A31, S0-S1, Valid Asserted Expression: A0-A31, S0-S1, Valid Deasserted Width Asserted Width Asserted Deasserted R/W, A0-A31 Invalid Deasserted R/W, A0-A31 Invalid Width Deasserted Width Deasserted Asserted D0-D31 Valid (Write Cycle) D0-D31 Valid Deasserted (Write Cycle) D0-D31 Valid Deasserted (Write Cycle) Deasserted D0-D31 Invalid (Write Cycle) Deasserted D0-D31 Invalid (Write Cycle) Asserted D0-D31 Active (Write Cycle) Deasserted D0-D31 Tri-state (Write Cycle) 7.55 13.56 4.05 9.56
Freescale Semiconductor, Inc.
2727 2112 1215 1228 1017
2014 1619
33.58 2227 6.511 1813 8.516 1029 6.511 1018
17.514 13.519
25.08 1527 6.511 1613 6.529 6.511 7.718
1514 1119
2-10
DSP96002/D, Rev.
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MOTOROLA
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
Table External Relative Timing (Continued)
Characteristic
33.3 MHz3
MHz4
MHz4 Unit
Deasserted D0-D31 Three-state (Write Cycle) Deasserted D0-D31 Active (Write Cycle) Asserted D0-D31 Valid (Read Cycle) Deasserted D0-D31 Invalid (Hold) (Read Cycle) A0-A31, S0-S1, Valid D0-D31 Valid (Read Cycle)24 3520 1619 2122 3225 31.521 13.519 17.523 26.526 26.521 1119 1423 2126
Freescale Semiconductor, Inc.
Note:
numbers this column shown circled numbers following figures. Electrical Characteristics: 33.3 MHz: 10%, GND= -40°C 100°C MHz: -40°C 100°C Assuming duty cycle range 46.7%-53.3% wait states Assuming duty cycle range 46%-54% wait states Th-4 1)Tc Th-2 1)Tc 1)Tc (WS)Tc (WS)Tc 1)Tc 1)Tc Using minimum 1)Tc 1)Tc
MOTOROLA
DSP96002/D, Rev.
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2-11
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
A0-A31, S0-S1 (output) (see note) (output) (output) D0-D31 (Tri-state)
DATA (Tri-state) DATA (Tri-state)
Freescale Semiconductor, Inc.
Note: During Read-Modify-Write instructions, A0-A31, S0-S1 change.
Figure External Relative Timing
2-12
DSP96002/D, Rev.
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MOTOROLA
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
External Synchronous Timing
Table External Synchronous Timing
Characteristic
33.3 MHz3
MHz4
MHz4 Unit
High A0-A31, S0-S1, Valid Asserted High A0-A31, S0-S1, Invalid High D0-D31 Valid (Write Cycle) High D0-D31 Invalid (Write Cycle) High D0-D31 Active (Write Cycle) High D0-D31 Three-state (Write Cycle) D0-D31 Valid (Setup) (Read Cycle) D0-D31 Invalid (Hold) (Read Cycle) High Deasserted Width Deasserted Asserted High tri-state Hold Time from Hold Time from Deasserted Deasserted Deasserted Asserted (Two Successive Cycles) Deasserted Asserted (Two Successive Cycles) 6.59 16.57 6.59
Freescale Semiconductor, Inc.
MOTOROLA
DSP96002/D, Rev.
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2-13
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
Table External Synchronous Timing (Continued)
Characteristic
33.3 MHz3
MHz4
MHz4 Unit
Asserted Asserted5. Valid High (Setup)5. High Invalid (Hold)
1510
12.511
9.511
Freescale Semiconductor, Inc.
Note:
numbers this column shown circled numbers following figures. Electrical Characteristics: 33.3 MHz: 10%, -40°C 100°C MHz: -40°C 100°C Assuming duty cycle range 46.7%-53.3% wait states Assuming duty cycle range 46%-54% wait states Timing timing should satisfied. Tc-5 Tc-4 Tl-7 Tl-5 Tc-15 Tc-12.5
2-14
DSP96002/D, Rev.
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MOTOROLA
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
(input) A0-A31, R/W, S0-S1 (output)
(output) (output) (output)
Freescale Semiconductor, Inc.
(input) D0-D31 (output) D0-D31 (input)
Figure External Synchronous Timing-No Wait States
MOTOROLA
DSP96002/D, Rev.
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2-15
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
(input) A0-A31, R/W, S0-S1, (output)
(output)
Freescale Semiconductor, Inc.
(output) (output)
(input)
Figure External Synchronous Timing-One Wait State
2-16
DSP96002/D, Rev.
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MOTOROLA
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
(input) A0-A31, S0-S1 (output)
(output)
Freescale Semiconductor, Inc.
(output) (output) (output) (output)
Figure Read-Modify-Write Cycle Timing-No Wait States
MOTOROLA
DSP96002/D, Rev.
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2-17
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
Multiplexed Timing
Table Multiplexed Timing
Characteristic
Asserted Low5
33.3 MHz3
MHz4
MHz4 Unit
11.56 9.59 11.56 9.59
Asserted A0-A31 Valid Deasserted A0-A31 tri-state Deasserted A0-A31 Invalid Asserted High7 Asserted A0-A31 Active High A0-A31 Active Asserted Low5, Asserted D0-D31 Valid Deasserted D0-D31 Tri-state Deasserted D0-D31 Invalid Asserted High7, Asserted D0-D31 Active
Freescale Semiconductor, Inc.
Note:
numbers this column shown circled numbers following figures. Electrical Characteristics: 33.3 MHz: 10%, -40°C 100°C MHz: -40°C 100°C Assuming duty cycle range 46.7%-53.3% Assuming duty cycle range 46%-54% minimum minimum Tl-4 Tl-2 Host Interface data output, only timings apply.
2-18
DSP96002/D, Rev.
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MOTOROLA
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
(input) (input) A0-A31 (output)
Freescale Semiconductor, Inc.
Figure Address Enable/Disable Timing
(input) (input) D0-D31 (output)
Figure 2-10 Data Enable/Disable Timing
MOTOROLA
DSP96002/D, Rev.
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2-19
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
Host Timing
Table Host Timing
Characteristic
33.3 MHz3
MHz4
MHz4 Unit
A2-A5, Valid Asserted (Setup) Deasserted A2-A5, Invalid (Hold) Asserted D0-D31 Valid Asserted D0-D31 Valid5 Deasserted D0-D31 Invalid (Hold) Asserted D0-D31 Active Deasserted D0-D31 Tri-state A2-A5, Valid D0-D31 Valid D0-D31 Valid A2-A5, Valid D0-D31 Valid D0-D31 Valid5 Asserted D0-D31 Valid (Access Time) Asserted D0-D31 Valid5 D0-D31 Valid Deasserted (Setup) Deasserted D0-D31 Invalid (Hold) Width Asserted5 Width Deasserted Between Consecutive Writes8 Width Deasserted (Others)11 Asserted Deasserted Hold Time After Deasserted 13.5
Freescale Semiconductor, Inc.
64.5
51.5
2-20
DSP96002/D, Rev.
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MOTOROLA
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
Table Host Timing (Continued)
Characteristic
33.3 MHz3
MHz4
MHz4 Unit
Deasserted Asserted (Setup) Width Asserted (DMA Mode) Asserted Asserted Deasserted Asserted After Deassertion12 Deasserted (Setup)14
Freescale Semiconductor, Inc.
Note:
numbers this column shown circled numbers following figures. Electrical Characteristics: 33.3 MHz: 10%, -40°C 100°C MHz: -40°C 100°C Assuming duty cycle range 46.7%-53.3% Assuming duty cycle range 46%-54% When reading status (ICS register), status data guaranteed stable. Assuming both empty Both must deasserted case mixed non-DMA accesses (i.e., after access this recovery time must respected before access.) When deassertion respect timing When timing respected, timing guaranteed respected. Timing required correct operation.
MOTOROLA
DSP96002/D, Rev.
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2-21
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
A2-A5 (input) (input)
(input)
Freescale Semiconductor, Inc.
(input) D0-D31 (output)
Figure 2-11 Host Read Cycle Timing (Non-DMA Mode)
A2-A5 (input) (input) (input) (input) D0-D31 (input)
Figure 2-12 Host Write Cycle Timing (Non-DMA Mode)
2-22
DSP96002/D, Rev.
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MOTOROLA
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
(output) (input) D0-D31 (output)
Freescale Semiconductor, Inc.
Figure 2-13 Host Read Cycle Timing (DMA Mode)
(output) (input) D0-D31 (input)
Figure 2-14 Host Write Cycle Timing (DMA Mode)
(input) (input)
(input)
D0-D31 (output)
Figure 2-15 Host Interrupt Vector Register (IVR) Read Timing (Non-DMA Mode)
MOTOROLA
DSP96002/D, Rev.
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2-23
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
(input) (input) (output)
Freescale Semiconductor, Inc.
Figure 2-16 Host Request Timing
2-24
DSP96002/D, Rev.
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MOTOROLA
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
OnCE Timing
Table 2-10 OnCE Timing
Characteristic
DSCK DSCK High DSCK Cycle Time
33.3 MHz3
MHz4
MHz4 Unit
1525 4011 1015 22217 6812 1266 61.57 67.510 33.513 185.518 5714 1056 5410 14818
Freescale Semiconductor, Inc.
Asserted (ACK) Asserted DSCK High Valid DSCK High Invalid Valid DSCK (Setup) DSCK Invalid (Hold) Last DSCK OS0-OS1, Active (ACK) Asserted First DSCK High8 (ACK) Width Asserted (ACK) Asserted OS0-OS1 Tristate OS0-OS1 Valid High High OS0-OS1 Invalid Last DSCK Read Register First DSCK High Next Command19 Last DSCK Invalid (Hold) DSCK Rise Fall Times
MOTOROLA
DSP96002/D, Rev.
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2-25
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
Table 2-10 OnCE Timing (Continued)
Note:
Characteristic
33.3 MHz3
MHz4
MHz4 Unit
numbers this column shown circled numbers following figures. Electrical Characteristics: 33.3 MHz: 10%, -40°C 100°C MHz: -40°C 100°C Assuming duty cycle range 46.7%-53.3% Assuming duty cycle range 46%-54% maximum. maximum
Freescale Semiconductor, Inc.
DSCK (input)
Figure 2-17 OnCE Serial Clock Timing
(input) (output)
Figure 2-18 OnCE Acknowledge Timing
2-26
DSP96002/D, Rev.
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MOTOROLA
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
DSCK (input) (output)
(Last) (Note
(OS1)
(ACK)
(input)
(OS0)
Freescale Semiconductor, Inc.
Note: Tri-state, external pull-down resistor
Figure 2-19 OnCE Data Status Timing
(output) (Note (output) (ACK) (DSO output) (DSCK input)
(output) (DSI input)
Note: Tri-state, external pull-down resistor
Figure 2-20 OnCE Status Data Timing
(input) OS0-1 (output)
Figure 2-21 OnCE Status Timing
MOTOROLA
DSP96002/D, Rev.
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2-27
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
DSCK (input) (Read Register) (Next Command)
Figure 2-22 OnCE DSCK Next Command After Read Register Timing
Reset, Mode Select, Interrupt Timing
Freescale Semiconductor, Inc.
Table 2-11 Reset, Mode Select, Interrupt Timing
No.1
Characteristic2
RESET Asserted D0-D31, A0-A31, S0-S1, R/W, Threestate RESET Asserted Deasserted RESET Width Asserted5 Asynchronous RESET Deassertion First External Access Synchronous Reset Setup Time from RESET Deassertion High Synchronous Reset Delay from High First External Access7 Mode Select Setup Time Mode Select Hold Time Edge-Triggered Interrupt Request Width Delay from IRQA, IRQB, IRQC assertion External Memory Access Valid Caused First Interrupt Instruction Execution6
33.3 MHz3
MHz4
6010
MHz4 Unit
60013 30014 24218
10011 36515 2517 25419
50013 25014 20218
8512 30516 2017 21220
40013 20014 16218
24516 1617
28421
236.521
18921
2-28
DSP96002/D, Rev.
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MOTOROLA
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
Table 2-11 Reset, Mode Select, Interrupt Timing (Continued)
Characteristic
33.3 MHz3
MHz4
2523
MHz4 Unit
2023
Delay from A0-A31, S0-S1, R/W, Valid Caused First Interrupt Instruction Execution IRQA, IRQB, IRQC Deassertion8
3022
Note:
numbers this column shown circled numbers following figures. Electrical Characteristics: 33.3 MHz: 10%, -40°C 100°C MHz: -40°C 100°C Assuming duty cycle range 46.7%-53.3% wait states Assuming duty cycle range 46%-54%% wait states Assuming stable Assuming single-cycle MOVE instruction first vector location, interrupting stream oneword, single-cycle instructions Assuming asserted deasserted
Freescale Semiconductor, Inc.
This timing necessary prevent multiple interrupt service when interrupt request levelsensitive fast interrupt. avoid this restriction, Edge-triggered mode recommended when using fast interrupts long interrupts recommended when using Level-sensitive mode 20Tc 10Tc 11Tc 11Tc 2)Tc 2)Tc
MOTOROLA
DSP96002/D, Rev.
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2-29
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
RESET (input) (output) D0-D31, A0-A31, S0-S1, R/W, (output)
VIHR
Freescale Semiconductor, Inc.
Figure 2-23 Reset Entry Timing
VIHR
RESET (input) Signals (output)
First Fetch
Figure 2-24 Asynchronous Reset Exit Timing
(input) VIHR RESET (input) Signals (output)
First Fetch
Figure 2-25 Synchronous Reset Exit Timing
2-30
DSP96002/D, Rev.
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MOTOROLA
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
RESET (input)
VIHR
MODA, MODB, MODC (input) VIHM VILM
IRQA, IRQB, IRQC
Figure 2-26 Operating Mode Select Timing
IRQA, IRQB, IRQC (input) A0-A31, S0-S1, R/W, (output)
Freescale Semiconductor, Inc.
First Interrupt Instruction Execution
Note: Reset, Mode Select, Interrupt Figure
Figure 2-27 External Edge-Triggered Interrupt Timing
IRQA, IRQB, IRQC (input) A0-A31, S0-S1, R/W, (output) First Interrupt Instruction Execution
Figure 2-28 External Level-Sensitive Interrupt Timing
MOTOROLA
DSP96002/D, Rev.
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2-31
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
WAIT, STOP, Request Timing
Table 2-12 WAIT, STOP, Request Timing
Characteristic
33.3 MHz3
MHz4
MHz4 Unit
IRQA, IRQB, IRQC Asserted (Setup Time Synchronous Recovery from WAIT State) External Memory Access Valid (First Interrupt Instruction Fetch After Synchronous Recovery from WAIT State)5 IRQA, IRQB, IRQC Width Asserted (Recovery from WAIT State) IRQA, IRQB, IRQC Asserted External Memory Access Valid (First Interrupt Instruction Fetch After Asynchronous Recovery from WAIT State)5 IRQA Asserted (Setup Time Synchronous Recovery from STOP State) External Memory Access Valid (First Instruction Fetch After Synchronous Recovery from STOP State)5 IRQA Width Asserted (Recovery from Stop State) IRQA Asserted External Memory Access Valid (First Instruction Fetch After Asynchronous Recovery from STOP State)5) Asserted (Setup Time Synchronous Recovery from WAIT STOP State)
Freescale Semiconductor, Inc.
4067
4208
338.57 350.59
2717
2819
3510
3010
2010
4067
46611 338.57 388.512 2717
3013
2513
2013
37614
39015 313.514 325.516 25114
3522
3022
2522
37614
43617 313.514 363.518 25114
3013
2513
2013
2-32
DSP96002/D, Rev.
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MOTOROLA
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
Table 2-12 WAIT, STOP, Request Timing (Continued)
Characteristic
33.3 MHz3
MHz4
MHz4 Unit
(ACK) Valid (Enter Debug Mode) After Synchronous Recovery from STOP State After Synchronous Recovery from WAIT State Asserted (ACK) Valid (Enter Debug Mode) After Asynchronous Recovery from STOP State After Asynchronous Recovery from WAIT State Request Asserted (Setup)6 Request Invalid (Hold)6 External Access Valid Assertion Width recover from WAIT/STOP recover from WAIT/STOP enter Debug Mode
54019 51020
45019 42520
30519 29020
Freescale Semiconductor, Inc.
54019 51020
45019 42520
30519 29020
7621
63.521
5021
3522 42025
30023
2924 35025
25023
2324 23525
20023
Note:
numbers this column shown circled numbers following figures. Electrical Characteristics: 33.3 MHz: 10%, -40°C 100°C MHz: -40°C 100°C Assuming duty cycle range 46.7%-53.3% wait states. Assuming duty cycle range 46%-54%% wait states. Assuming ownership. internally defined request. 13Tc 13Tc 13Tc 14Tc 14Tc 12Tc 12Tc 12Tc 13Tc 13Tc 18Tc 17Tc 10Tc 14Tc
MOTOROLA
DSP96002/D, Rev.
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2-33
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
(input) IRQA, IRQB, IRQC (input) A0-A31, S0-S1, R/W, (output)
First Interrupt Instruction Fetch
Freescale Semiconductor, Inc.
Figure 2-29 Recovery from WAIT State Using Synchronous Interrupt Timing
IRQA, IRQB, IRQC (input) A0-A31, S0-S1, R/W, (output)
First Interrupt Instruction Fetch
Figure 2-30 Recovery from WAIT State Using Asynchronous Interrupt Timing
(input) IRQA (input) A0-A31, S0-S1, R/W, (output) First Instruction Fetch
Figure 2-31 Recovery from STOP State Using Synchronous Interrupt Timing
2-34
DSP96002/D, Rev.
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MOTOROLA
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
IRQA (input)
A0-A31, S0-S1, R/W, (output) First Instruction Fetch
Figure 2-32 Recovery from STOP State Using Asynchronous Interrupt Timing
Freescale Semiconductor, Inc.
(input) (input) (output)
Figure 2-33 Recovery from WAIT/STOP State Using Synchronous Timing
(input)
(output)
Figure 2-34 Recovery from WAIT/STOP State Using Asynchronous Timing
MOTOROLA
DSP96002/D, Rev.
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2-35
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
(input)
IRQA, IRQB, IRQC (input) A0-A31, S0-S1, R/W, (output)
Access
Freescale Semiconductor, Inc.
Figure 2-35 External Request Timing
Timer/Event Counter
Table 2-13 Timer Timing
No.1
Note:
Characteristic2
High CKOUT (output) assertion CKOUT (output) deassertion
33.3 MHz3
MHz4
MHz4 Unit
numbers this column shown circled numbers following figures. Electrical Characteristics: 33.3 MHz: 10%, -40°C 100°C MHz: -40°C 100°C Assuming duty cycle range 46.7%-53.3% wait states. Assuming duty cycle range 46%-54%% wait states.
2-36
DSP96002/D, Rev.
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MOTOROLA
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
Figure 2-36 Timer Event Input Restrictions
Freescale Semiconductor, Inc.
CKOUT
(output)
Figure 2-37 External Pulse Generation
MOTOROLA
DSP96002/D, Rev.
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2-37
Freescale Semiconductor, Inc.
Specifications Electrical Characteristics
Freescale Semiconductor, Inc.
2-38
DSP96002/D, Rev.
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MOTOROLA
Freescale Semiconductor, Inc.
SECTION PACKAGING
This section contains package pin-out information DSP96002. There package options: 223-pin Grid Array (PGA) 240-pin Ceramic Quad Flat Pack (CQFP).
Freescale Semiconductor, Inc.
MOTOROLA
DSP96002/D, Rev.
More Information This Product, www.freescale.com
Freescale Semiconductor, Inc.
Packaging Package
PACKAGE
TIO0
BA23 BA27 BA29 BA31 IRQA BA20 BA25 BA28 BA30 IRQB BA17 BA21 BA26 GNDN IRQC BA15 BA18 BA24 BA13 BA16 BA22 GNDN BA12 BA14 BA19 GNDN BA09 BA10 VCCN VCCN BA08 BA11 VCCQ BA07 GNDQ
AR/W
AA02 AA04 AA07 AA10 AA13 AA16
AA00 AA03 AA06 AA09 AA11 AA14 AA18 AA20
AA01 AA05 AA08 AA12 AA15 AA17 AA19 AA21 AA23
Freescale Semiconductor, Inc.
GNDN GNDN GNDN VCCN VCCN VCCQ GNDQ VCCN GNDN GNDN GNDN AA22 AA25 AA26 GNDN AA24 AA28 AA29 GNDN AA27 AA30 AD31
BA04 BA05 BA06 VCCN BA03 BA01 BA02 VCCN BA00 GNDN GNDN GNDN
DSP96002 VIEW
View
GNDN AA31 AD30 AD29 VCCN AD28 AD27 AD26 GNDQ AD24 AD25 AD23 GNDQ AD20 AD21 AD22 VCCQ AD16 AD18 AD19 VCCN VCCN AD17
TIO1
GNDN AD11 AD14 AD15 GNDN AD07 AD12 AD13
BR/W
GNDN GNDN GNDN VCCN GNDQ VCCQ VCCQ VCCN GNDN GNDN GNDN GNDN AD05 AD09 AD10 BD31 GNDN BD26 BD22 BD17 BD14 BD11 BD07 BD04 BD01 AD02 AD06 AD08 BD29 BD27 BD24 BD21 BD18 BD15 BD12 BD09 BD06 BD03 BD00 AD03 AD04
DSCK NC(1)
BD30 BD28 BD25 BD23 BD20 BD19 BD16 BD13 BD10 BD08 BD05 BD02 AD00 AD01
Figure View DSP96002 223-pin Package
DSP96002/D, Rev.
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MOTOROLA
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Packaging Package
BD30 BD28 BD25 BD23 BD20 BD19 BD16 BD13 BD10 BD08 BD05 BD02 AD00 AD01 BD29 BD27 BD24 BD21 BD18 BD15 BD12 BD09 BD06 BD03 BD00 AD03 AD04 BD31 GNDN BD26 BD22 BD17 BD14 BD11 BD07 BD04 BD01 AD02 AD06 AD08
DSCK NC(1)
Freescale Semiconductor, Inc.
GNDN GNDN GNDN VCCN GNDQ VCCQ VCCQ VCCN GNDN GNDN GNDN GNDN AD05 AD09 AD10 GNDN GNDN GNDN GNDN AD07 AD12 AD13 GNDN AD11 AD14 AD15
BR/W TIO1
BA00
BA03 BA01 BA02 VCCN BA04 BA05 BA06 VCCN BA07 GNDQ BA11 VCCQ
DSP96002 PINS BOTTOM VIEW
Bottom View
VCCN VCCN
AD17
VCCQ AD16 AD18 AD19 GNDQ AD20 AD21 AD22 GNDQ AD24 AD25 AD23 VCCN AD28 AD27 AD26 GNDN AA31 AD30 AD29 GNDN AA27 AA30 AD31 GNDN AA24 AA28 AA29
BA08
BA09 BA10 VCCN VCCN BA12 BA14 BA19 GNDN BA13 BA16 BA22 GNDN BA15 BA18 BA24
GNDN GNDN GNDN VCCN VCCN VCCQ GNDQ VCCN GNDN GNDN GNDN AA22 AA25 AA26 TIO0 AA01 AA05 AA08 AA12 AA15 AA17 AA19 AA21 AA23 AA00 AA03 AA06 AA09 AA11 AA14 AA18 AA20 AA02 AA04 AA07 AA10 AA13 AA16
BA17 BA21 BA26 GNDN IRQC BA20 BA25 BA28 BA30 IRQB BA23 BA27 BA29 BA31 IRQA
AR/W
Figure Bottom View DSP96002 223-pin Package
MOTOROLA
DSP96002/D, Rev.
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Freescale Semiconductor, Inc.
Packaging Package
Table DSP96002 List, 223-pin Package
Number
Signal Type
Input/Output Input/Output Input/Output Input/Output Input Input Output Input/Output Input/Output Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Output Output Output Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
Signal Name
BA23 BA27 BA29 BA31 MODA/IRQA TIO0 AR/W AA02 AA04 AA07 AA10 AA13 AA16 BA20 BA25 BA28 BA30 MODB/IRQB AA00 AA03 AA06 AA09 AA11 AA14 AA18
Freescale Semiconductor, Inc.
DSP96002/D, Rev.
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MOTOROLA
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Packaging Package
Table DSP96002 List, 223-pin Package (Continued)
Number
Signal Type
Input/Output Input/Output Input/Output Input/Output Input Input Input Output Output Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Input Input Input Input Input Input Input Input Input/Output Input/Output Input/Output
Signal Name
AA20 BA17 BA21 BA26 GNDN MODC/IRQC RESET AA01 AA05 AA08 AA12 AA15 AA17 AA19 AA21 AA23 BA15 BA18 BA24 GNDN GNDN GNDN VCCN VCCN VCCQ GNDN VCCN GNDN GNDN GNDN AA22 AA25 AA26
Freescale Semiconductor, Inc.
MOTOROLA
DSP96002/D, Rev.
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Freescale Semiconductor, Inc.
Packaging Package
Table DSP96002 List, 223-pin Package (Continued)
Number
Signal Type
Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input Input Input/Output Input/Output Input/Output Input Input Input/Output Input
Signal Name
BA13 BA16 BA22 GNDN GNDN AA24 AA28 AA29 BA12 BA14 BA19 GNDN GNDN AA27 AA30 AD31 BA09 BA10 VCCN VCCN GNDN AA31 AD30 AD29 BA08 BA11 VCCQ VCCN AD28 AD27 AD26 BA07 GNDQ
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DSP96002/D, Rev.
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MOTOROLA
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Packaging Package
Table DSP96002 List, 223-pin Package (Continued)
Number
Signal Type
Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Output Output Input Input Input Input Input/Output Input Output Input/Output Input Input Input/Output Input/Output Input/Output
Signal Name
GNDQ AD24 AD25 AD23 BA04 BA05 BA06 VCCN GNDQ AD20 AD21 AD22 BA03 BA01 BA02 VCCN VCCQ AD16 AD18 AD19 BA00 GNDN VCCN VCCN AD17 TIO1 GNDN GNDN AD11 AD14 AD15
Freescale Semiconductor, Inc.
MOTOROLA
DSP96002/D, Rev.
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Packaging Package
Table DSP96002 List, 223-pin Package (Continued)
Number
Signal Type
Input/Output Input/Output Output Input Input Input/Output Input/Output Input/Output Output Output Input Input Input Input Input Input Input Input Input Input Input Input Input Input/Output Input/Output Input/Output Input Output Output Input Input Input/Output Input Input/Output Input/Output Input/Output
Signal Name
BR/W GNDN GNDN AD07 AD12 AD13 GNDN GNDN GNDN VCCN GNDQ VCCQ VCCQ VCCN GNDN GNDN GNDN GNDN AD05 AD09 AD10 BD31 GNDN BD26 BD22 BD17
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DSP96002/D, Rev.
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MOTOROLA
Freescale Semiconductor, Inc.
Packaging Package
Table DSP96002 List, 223-pin Package (Continued)
Number
Signal Type
Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output
Signal Name
BD14 BD11 BD07 BD04 BD01 AD02 AD06 AD08 DSCK/OS1 BD29 BD27 BD24 BD21 BD18 BD15 BD12 BD09 BD06 BD03 BD00 AD03 AD04 DSI/OS0 BD30 BD28 BD25 BD23
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MOTOROLA
DSP96002/D, Rev.
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Packaging Package
Table DSP96002 List, 223-pin Package (Continued)
Number
Signal Type
Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
Signal Name
BD20 BD19 BD16 BD13 BD10 BD08 BD05 BD02 AD00 AD01
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NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: INCH. INCHES 1.840 1.880 1.840 1.880 0.120 0.150 0.017 0.020 0.100 0.050 0.170 0.190
223X
0.030 0.010
CASE 860C-02 ISSUE
Figure DSP96002 Mechanical Information, 223-pin Package
3-10
DSP96002/D, Rev.
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Packaging CQFP Package
CQFP PACKAGE
GNDN BA27 BA26 BA25 BA24 VCCN BA23 BA22 BA21 BA20 GNDN BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 GNDN BA11 BA10 BA09 BA08 VCCQ GNDQ VCCN BA07 BA06 BA05 BA04 GNDN BA03 BA02 BA01 BA00 TIO1 GNDN VCCN
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BA28 BA29 BA30 BA31 MODC MODB MODA GNDN TIO0 VCCN GNDN AA00 AA01 AA02 AA03 GNDN AA04 AA05 AA06 AA07 GNDQ VCCQ VCCN AA08 AA09 AA10 AA11 GNDN AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 GNDN AA20 AA21
Orientation Mark
(Top View)
GNDN DSCK BD31 BD30 BD29 BD28 GNDN BD27 BD26 BD25 BD24 VCCN BD23 BD22 BD21 BD20 GNDN BD19 BD18 BD17 BD16 VCCQ GNDQ BD15 BD14 BD13 BD12 GNDN BD11 BD10 BD09 BD08 VCCN BD07 BD06 BD05 BD04 GNDN BD03 BD02 BD01 BD00
MOTOROLA
AA22 AA23 VCCN AA24 AA25 AA26 AA27 GNDN AA28 AA29 AA30 AA31 AD31 AD30 AD29 AD28 GNDN AD27 AD26 AD25 AD24 VCCN AD23 AD22 AD21 AD20 GNDN AD19 AD18 AD17 AD16 VCCQ GNDQ AD15 /ADE AD14 AD13 AD12 GNDN AD11 AD10 AD09 AD08 VCCN AD07 AD06 AD05 AD04 GNDN AD03 AD02 AD01 AD00
Figure View DSP96002 240-pin CQFP Package
DSP96002/D, Rev.
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3-11
Freescale Semiconductor, Inc.
Packaging CQFP Package
VCCN GNDN TIO1 BA00 BA01 BA02 BA03 GNDN BA04 BA05 BA06 BA07 VCCN GNDQ VCCQ BA08 BA09 BA10 BA11 GNDN BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 GNDN BA20 BA21 BA22 BA23 VCCN BA24 BA25 BA26 BA27 GNDN
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GNDN DSCK BD31 BD30 BD29 BD28 GNDN BD27 BD26 BD25 BD24 VCCN BD23 BD22 BD21 BD20 GNDN BD19 BD18 BD17 BD16 VCCQ GNDQ BD15 BD14 BD13 BD12 GNDN BD11 BD10 BD09 BD08 VCCN BD07 BD06 BD05 BD04 GNDN BD03 BD02 BD01 BD00
Orientation Mark side)
(Bottom View)
BA28 BA29 BA30 BA31 MODC MODB MODA GNDN TIO0 VCCN GNDN AA00 AA01 AA02 AA03 GNDN AA04 AA05 AA06 AA07 GNDQ VCCQ VCCN AA08 AA09 AA10 AA11 GNDN AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 GNDN AA20 AA21
3-12
AD00 AD01 AD02 AD03 GNDN AD04 AD05 AD06 AD07 VCCN AD08 AD09 AD10 AD11 GNDN AD12 AD13 AD14 /ADE AD15 GNDQ VCCQ AD16 AD17 AD18 AD19 GNDN AD20 AD21 AD22 AD23 VCCN AD24 AD25 AD26 AD27 GNDN AD28 AD29 AD30 AD31 AA31 AA30 AA29 AA28 GNDN AA27 AA26 AA25 AA24 VCCN AA23 AA22
Figure Bottom View DSP96002 240-pin CQFP Package
DSP96002/D, Rev.
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MOTOROLA
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Packaging CQFP Package
Table DSP96002 List, 240-pin CQFP Package
Number
Signal Type
Input/Output Input/Output Input/Output Input/Output Input Input Input Input Input Input Output Output Output Input Input/Output Input Output Output Output Output Input Output Output Input/Output Output Input Input/Output Input/Output Input/Output Input/Output Input
Signal Name
BA28 BA29 BA30 BA31 IRQC/MODC IRQB/MODB IRQA/MODA RESET GNDN TIO0 VCCN AR/W GNDN AA00 AA01 AA02 AA03 GNDN
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MOTOROLA
DSP96002/D, Rev.
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3-13
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Packaging CQFP Package
Table DSP96002 List, 240-pin CQFP Package (Continued)
Number
Signal Type
Input/Output Input/Output Input/Output Input/Output Input Input Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output
Signal Name
AA04 AA05 AA06 AA07 GNDQ VCCQ VCCN AA08 AA09 AA10 AA11 GNDN AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 GNDN AA20 AA21 AA22 AA23 VCCN AA24 AA25 AA26
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3-14
DSP96002/D, Rev.
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Freescale Semiconductor, Inc.
Packaging CQFP Package
Table DSP96002 List, 240-pin CQFP Package (Continued)
Number
Signal Type
Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input Input/Output Input Input/Output Input/Output Input/Output Input Input/Output
Signal Name
AA27 GNDN AA28 AA29 AA30 AA31 AD31 AD30 AD29 AD28 GNDN AD27 AD26 AD25 AD24 VCCN AD23 AD22 AD21 AD20 GNDN AD19 AD18 AD17 AD16 VCCQ GNDQ AD15 AD14 AD13 AD12 GNDN AD11
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MOTOROLA
DSP96002/D, Rev.
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3-15
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Packaging CQFP Package
Table DSP96002 List, 240-pin CQFP Package (Continued)
Number
Signal Type
Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input/Output
Signal Name
AD10 AD09 AD08 VCCN AD07 AD06 AD05 AD04 GNDN AD03 AD02 AD01 AD00 BD00 BD01 BD02 BD03 GNDN BD04 BD05 BD06 BD07 VCCN BD08 BD09 BD10 BD11 GNDN BD12
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3-16
DSP96002/D, Rev.
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Packaging CQFP Package
Table DSP96002 List, 240-pin CQFP Package (Continued)
Number
Signal Type
Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input Input Input Input Input Input/Output Input/Output Output Output Output
Signal Name
BD13 BD14 BD15 GNDQ VCCQ BD16 BD17 BD18 BD19 GNDN BD20 BD21 BD22 BD23 VCCN BD24 BD25 BD26 BD27 GNDN BD28 BD29 BD30 BD31 DSI/OS0 DSK/OS1
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MOTOROLA
DSP96002/D, Rev.
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3-17
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Packaging CQFP Package
Table DSP96002 List, 240-pin CQFP Package (Continued)
Number
Signal Type
Input Output Input Input Output Output Input Output Input/Output Output Input Input/Output Output Output Output Input Output Output Output Output Input Output Output Output Input Input Output Input
Signal Name
GNDN VCCN GNDN TIO1 BR/W BA00 BA01 BA02 BA03 GNDN BA04 BA05 BA06 BA07 VCCN
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3-18
DSP96002/D, Rev.
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Packaging CQFP Package
Table DSP96002 List, 240-pin CQFP Package (Continued)
Number
Signal Type
Input Input Input Output Output Output Output Input Output Output Output Output Output Output Output Output Input Output Output Output Output Input Output Output Output Output Input
Signal Name
GNDQ VCCQ BA08 BA09 BA10 BA11 GNDN BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 GNDN BA20 BA21 BA22 BA23 VCCN BA24 BA25 BA26 BA27 GNDN
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MOTOROLA
DSP96002/D, Rev.
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Packaging CQFP Package
VIEW
PLACES
VIEW
Freescale Semiconductor, Inc.
0.08 SECTION
PLACES NOTES: DIMENSIONS TOLERANCES CONFORM ASME Y14.5M, 1994. CONTROLLING DIMENSION: MILLIMETER. DATUM PLANE LOCATED BOTTOM LEADS WHERE THEY EXIT BODY. DATUMS DETERMINED DATUM PLANE DIMENSIONS DETERMINED SEATING PLANE DATUM DIMENSIONS DEFINE MAXIMUM CERAMIC BODY DIMENSIONS INCLUDING GLASS PROTRUSION BOTTOM MISMATCH.
TIPS
0.30
0.20 VIEW
SEATING PLANE
0.10
(AB) (AA) VIEW
CASE 988-01 ISSUE
MILLIMETERS 30.86 31.75 30.86 31.75 3.75 4.15 0.18 0.30 3.10 3.90 0.17 0.23 0.50 0.13 0.175 0.45 0.55 0.25 0.15 34.60 17.30 34.60 0.04 0.24 17.30 0.12 0.13 1.80 0.95
Figure DSP96002 Mechanical Information, 240-pin CQFP Package
3-20
DSP96002/D, Rev.
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Packaging Package Pin-Out Information
PACKAGE PIN-OUT INFORMATION
Complete mechanical information regarding DSP96002 packaging available facsimile through Motorola's Mfaxsystem. Call following number obtain information facsimile:
(602) 244-6591
Mfax automated system requests following information:
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receiving facsimile telephone number including area code country code caller's Personal Identification Number (PIN)
Note: first time callers, system provides instructions setting PIN, which requires entry name telephone number. type information requested: Instructions using system literature order form Specific part technical information data sheets Other information described system messages
total three documents ordered call. mechanical drawings 223-pin package referenced 860C-02. mechanical drawings 240-pin CQFP package referenced 988-01.
MOTOROLA
DSP96002/D, Rev.
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3-21
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Packaging Package Pin-Out Information
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3-22
DSP96002/D, Rev.
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SECTION DESIGN CONSIDERATIONS
THERMAL DESIGN CONSIDERATIONS
Freescale Semiconductor, Inc.
estimation chip junction temperature, obtained from equation: Equation Where: ambient temperature package junction-to-ambient thermal resistance °C/W power dissipation package Historically, thermal resistance been expressed junction-tocase thermal resistance case-to-ambient thermal resistance: Equation Where: package junction-to-ambient thermal resistance °C/W package junction-to-case thermal resistance °C/W package case-to-ambient thermal resistance °C/W device-related cannot influenced user. user controls thermal environment change case-to-ambient thermal resistance, RCA. example, user change flow around device, heat sink, change mounting arrangement printed circuit board, otherwise change thermal dissipation capability area surrounding device printed circuit board. This model most useful ceramic packages with heat sinks; some heat flow dissipated through case heat sink ambient environment. ceramic packages, situations where heat flow split between path case alternate path through printed circuit board, analysis device thermal performance need additional modeling capability system level thermal simulation tool.
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DSP96002/D, Rev.
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Design Considerations Thermal Design Considerations
thermal performance plastic packages more dependent temperature printed circuit board which package mounted. Again, estimations obtained from satisfactorily answer whether thermal performance adequate, system level model appropriate. complicating factor existence three common ways determining junction-to-case thermal resistance plastic packages: minimize temperature variation across surface, thermal resistance measured from junction outside surface package (case) closest chip mounting area when that surface proper heat sink. define value approximately equal junction-to-board thermal resistance, thermal resistance measured from junction where leads attached case. temperature package case (TT) determined thermocouple, thermal resistance computed using value obtained equation TT)/PD.
Freescale Semiconductor, Inc.
noted above, junction-to-case thermal resistances quoted this data sheet determined using first definition. From practical standpoint, that value also suitable determining junction temperature from case thermocouple reading forced convection environments. natural convection, using junction-to-case thermal resistance estimate junction temperature from thermocouple reading case package will estimate junction temperature slightly hotter than actual temperature. Hence, thermal metric, Thermal Characterization Parameter been defined TT)/PD. This value gives better estimate junction temperature natural convection when using surface temperature package. Remember that surface temperature readings packages subject significant errors caused inadequate attachment sensor surface, errors caused heat loss sensor. recommended technique attach 40-gauge thermocouple wire bead center package with thermally conductive epoxy.
DSP96002/D, Rev.
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Design Considerations Electrical Design Considerations
ELECTRICAL DESIGN CONSIDERATIONS
CAUTION
This device contains protective circuitry guard against damage high static voltage electrical fields. However, normal precautions advised avoid application voltages higher than maximum rated voltages this high-impedance circuit. Reliability operation enhanced unused inputs tied appropriate logic voltage level (e.g., either VCC).
Freescale Semiconductor, Inc.
following list recommendations assure correct operation: Provide low-impedance path from board power supply each DSP, from board ground each pin. least 0.01-0.1 bypass capacitors positioned close possible four sides package connect power source GND. Ensure that capacitor leads associated printed circuit traces that connect chip pins less than 0.5" capacitor lead. least four-layer Printed Circuit Board (PCB) with inner layers GND. Because output signals have fast rise fall times, trace lengths should minimal. This recommendation particularly applies address data buses, well IRQA, IRQB, IRQC, pins. Maximum trace lengths order recommended. Consider device loads, well parasitic capacitance traces when calculating capacitance. This especially critical systems with higher capacitive loads that could create higher transient currents circuits. inputs must terminated (i.e., allowed float) using CMOS levels. Take special care minimize noise levels VCCPLL VSSPLL pins.
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DSP96002/D, Rev.
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Design Considerations Power Consumption Considerations
POWER CONSUMPTION CONSIDERATIONS
Power dissipation issue portable applications. Some factors that affect current consumption described this section. Most current consumed CMOS devices Alternating Current (AC), which charging discharging capacitances pins internal nodes. Current consumption described formula: Equation
Freescale Semiconductor, Inc.
where:
node/pin capacitance voltage swing frequency node/pin toggle Example Current Consumption
loaded with capacitance, operating with clock, toggling maximum possible rate MHz), current consumption
Equation
8.25
Maximum Internal Current (ICCImax) value reflects typical possible switching internal buses best-case operation conditions, which necessarily real application case. Typical Internal Current (ICCItyp) value reflects average switching internal buses typical operating conditions. applications that require very current consumption: Minimize number pins that switching. Minimize capacitive load pins. Connect unused inputs pull-up pull-down resistors. Disable unused peripherals. Disable unused activity.
DSP96002/D, Rev.
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Design Considerations Power-Up Considerations
POWER-UP CONSIDERATIONS
power-up device properly, ensure that following conditions met: Stable power applied device according specifications Table Electrical Characteristics). external clock oscillator active stable. RESET asserted according specifications Table (Reset, Stop, Mode Select, Interrupt Timing).
Freescale Semiconductor, Inc.
Care should taken ensure that maximum ratings input voltages obey restrictions Table (Maximum Ratings), phases powerup procedure. This achieved powering external clock, hardware reset, mode selection circuits from same power supply that connected power supply pins chip. beginning hardware reset procedure, device might consume significantly more current than specified typical supply current. This because contentions among internal nodes being affected hardware reset signal until they reach their final hardware reset state.
MOTOROLA
DSP96002/D, Rev.
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Design Considerations Power-Up Considerations
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DSP96002/D, Rev.
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SECTION ORDERING INFORMATION
Consult Motorola Semiconductor sales office authorized distributor determine product availability place order. Table Ordering Information
Freescale Semiconductor, Inc.
Part
Supply Voltage
Package Type
Count
Frequency (MHz)
Order Number DSP96002RC60 DSP96002RC40 DSP96002RC33 DSP96002FE60 DSP96002FE40
Grid Array (PGA) DSP96002 Ceramic Quad Flat Pack (CQFP)
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DSP96002/D, Rev.
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Ordering Information
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DSP96002/D, Rev.
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APPENDIX BOOTSTRAP CODE DSP96002
BOOTSTRAP CODE DSP96002 Copyright 1988 Motorola Inc. Host algorithm external method. This Bootstrap program contained DSP96002. This program load internal program memory from external sources. program reads bits decide which external source access. MB:MA load from 4,096 consecutive byte-wide memory locations (starting P:$FFFF0000). MB:MA load internal PRAM thru Host Interface Port MB:MA load internal PRAM thru Host Interface Port BOOT $FFFF0000; location memory where external byte-wide EPROM expected mapped M_HCRA $FFFFFFEC; Port Host Control Register M_HSRA $FFFFFFED; Port Host Status Register M_HRXA $FFFFFFEF; Port Host Rec. Data Register M_HCRB $FFFFFFE4; Port Host Control Register M_HSRB $FFFFFFE5; Port Host Status Register M_HRXB $FFFFFFE7; Port Host Rec. Data Register PL:$0; bootstrap code starts P:$0 START MOVE #BOOT,R1; External address bootstrap byte-wide MOVEI #0,R0 starting address internal memory where program will begin loading. this program entered changing bootstrap mode, make certain that registers have been $FFFFFFFF. Make sure appropriate register $xxxxxxFx since EPROMs slow. Make sure that Port Selection Register permit program memory accesses thru required memory expansion port (Port first routine will load 4,096 bytes from external memory space beginning P:$FFFF0000 (bits 7-0). These will condensed into 1,024 32-bit words stored contiguous internal PRAM memory locations starting P:$0. Note that first routine loads data starting with least significant byte P:$0 first. Port Selection Register this program. Reset.
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MOTOROLA
DSP96002/D, Rev.
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Bootstrap Code DSP96002
second routine loads internal PRAM using Host Interface logic. HF1=0, will load 4,096 bytes from external host processor. These will condensed into 1,024 32-bit words stored contiguous internal PRAM memory locations starting P:$0. Note that routine loads data starting with least significant byte P:$0 first. HF1=1, will load 1,024 32-bit words from external host processor. host processor only wants load portion memory, start execution loaded program, Host Interface bootstrap load program routine killed setting
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INLOOP #1024,_LOOP1; Load 1,024 instruction words This context switch JSET #1,OMR,_HOSTLD; Perform load from Host Interface MB=1. This first routine. loads from external memory. #4,_LOOP2; bytes into D0.L #8,D0; Shift previous byte down MOVEM P:(R1)+,D1.L; byte from ext. mem. #24,D1; Shift into upper byte D1,D0; concatenate _LOOP2 <_STORE; Then word memory This second routine. loads thru Host Interface. _HOSTLD JSET #0,OMR,_HOSTB; Port Port Boot thru Host Interface Port _HOSTA BCLR #5,X:M_HCRA; Enable Port Host Interface MOVE #M_HSRA,R2; points HSRA MOVE #M_HRXA,R3; points HRXA <_HOSTR; host routine Boot thru Host Interface Port _HOSTB BCLR #5,X:M_HCRB; Enable Port Host Interface MOVE #M_HSRB,R2; points HSRB MOVE #M_HRXB,R3; points HRXB
DSP96002/D, Rev.
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Freescale Semiconductor, Inc.
Bootstrap Code DSP96002
Host load routine _HOSTR _LBL11 JCLR #3,X:(R2),_LBL22; HF0=1, stop loading data. ENDDO Must terminate loops <_BOOTEND _LBL22 JCLR JCLR MOVE _LBL33 JCLR ENDDO ENDDO JCLR MOVE _LOOP4 _STORE _LOOP1 MOVEM D0.L,P:(R0)+ Store 32-bit result mem. another 32-bit word #0,X:(R2),_LBL11; Wait HRDF high (meaning data present). #4,X:(R2),_LBL33; 8-bit source? X:(R3),D0.L; 32-bit word from host <_STORE #4,_LOOP4; bytes into D0.L #8,D0; Shift previous byte down #3,X:(R2),_LBL2; HF0=1, stop loading data. Must terminate loops <_BOOTEND #0,X:(R2),_LBL1; Wait HRDF high (meaning data present). X:(R3),D1.L; byte from host #24,D1; Shift into upper byte D1,D0; concatenate
Freescale Semiconductor, Inc.
_LBL1
_LBL2
This exit handler that returns execution internal PRAM _BOOTEND ANDI #$F9,OMR operating mode (and trigger exit from bootstrap mode). ANDI #$0,CCR; Clear RESET. Also delay needed Mode change. <$0; Start fetching from PRAM. DSP96002 bootstrap program size words
MOTOROLA
DSP96002/D, Rev.
More Information This Product, www.freescale.com
Freescale Semiconductor, Inc.
Bootstrap Code DSP96002
Freescale Semiconductor, Inc.
DSP96002/D, Rev.
More Information This Product, www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
APPENDIX MEMORY TABLES
Table Memory Contents (full cycle cosine values)
xr:$00000400= $3f800000 $3f7ffec4 $3f7fe129 $3f7f9c18 $3f7f2f9d $3f7e9bc9 $3f7de0b1 $3f7cfe73 $3f7bf531 $3f7ac516 $3f796e4e $3f77f110 $3f764d97 $3f748422 $3f7294f8 $3f708066 $3f6e46be $3f6be858 $3f696591 $3f66becc $3f63f473 $3f6106f2 $3f5df6be $3f5ac450 $3f577026 $3f53fac3 $3f5064af $3f4cae79 $3f48d8b3 $3f44e3f5 $3f40d0da $3f7ffb11 $3f7fd397 $3f7f84ab $3f7f0e58 $3f7e70b0 $3f7dabcc $3f7cbfc9 $3f7baccd $3f7a7302 $3f791298 $3f778bc5 $3f75dec6 $3f740bdd $3f721352 $3f6ff573 $3f6db293 $3f6b4b0c $3f68bf3c $3f660f88 $3f633c5a $3f604621 $3f5d2d53 $3f59f26a $3f5695e5 $3f531849 $3f4f7a1f $3f4bbbf8 $3f47de65 $3f43e200 $3f3fc767 $3f7ff4e6 $3f7fc38f $3f7f6ac7 $3f7eea9d $3f7e4323 $3f7d7474 $3f7c7eb0 $3f7b61fc $3f7a1e84 $3f78b47b $3f772417 $3f756d97 $3f73913f $3f718f57 $3f6f6830 $3f6d1c1d $3f6aab7b $3f6816a8 $3f655e0b $3f628210 $3f5f8327 $3f5c61c7 $3f591e6a $3f55b993 $3f5233c6 $3f4e8d90 $3f4ac77f $3f46e22a $3f42de29 $3f3ebc1b xr:$00000404= $3f7fec43 xr:$00000408= $3f7fb10f xr:$0000040c= $3f7f4e6d xr:$00000410= $3f7ec46d xr:$00000414= $3f7e1324 xr:$00000418= $3f7d3aac xr:$0000041c= $3f7c3b28 xr:$00000420= $3f7b14be xr:$00000424= $3f79c79d xr:$00000428= $3f7853f8 xr:$0000042c= $3f76ba07 xr:$00000430= $3f74fa0b xr:$00000434= $3f731447 xr:$00000438= $3f710908 xr:$0000043c= $3f6ed89e xr:$00000440= $3f6c835e xr:$00000444= $3f6a09a7 xr:$00000448= $3f676bd8 xr:$0000044c= $3f64aa59 xr:$00000450= $3f61c598 xr:$00000454= $3f5ebe05 xr:$00000458= $3f5b941a xr:$0000045c= $3f584853 xr:$00000460= $3f54db31 xr:$00000464= $3f514d3d xr:$00000468= $3f4d9f02 xr:$0000046c= $3f49d112 xr:$00000470= $3f45e403 xr:$00000474= $3f41d870
Freescale Semiconductor, Inc.
MOTOROLA
DSP96002/D, Rev.
More Information This Product, www.freescale.com
Freescale Semiconductor, Inc.
Memory Tables
Table Memory Contents (full cycle cosine values) (Continued)
xr:$00000478= $3f3daef9 xr:$0000047c= $3f396842 xr:$00000480= $3f3504f3 xr:$00000484= $3f3085bb xr:$00000488= $3f2beb4a xr:$0000048c= $3f273656 xr:$00000490= $3f226799 xr:$00000494= $3f1d7fd1 xr:$00000498= $3f187fc0 xr:$0000049c= $3f13682a xr:$000004a0= $3f0e39da xr:$000004a4= $3f08f59b xr:$000004a8= $3f039c3d xr:$000004ac= $3efc5d27 xr:$000004b0= $3ef15aea xr:$000004b4= $3ee63375 xr:$000004b8= $3edae880 xr:$000004bc= $3ecf7bca xr:$000004c0= $3ec3ef15 xr:$000004c4= $3eb8442a xr:$000004c8= $3eac7cd4 xr:$000004cc= $3ea09ae5 xr:$000004d0= $3e94a031 xr:$000004d4= $3e888e93 xr:$000004d8= $3e78cfcc xr:$000004dc= $3e605c13 xr:$000004e0= $3e47c5c2 xr:$000004e4= $3e2f10a2 xr:$000004e8= $3e164083 xr:$000004ec= xr:$000004f0= xr:$000004f4= xr:$000004f8= xr:$000004fc= $3dfab273 $3dc8bd36 $3d96a905 $3d48fb30 $3cc90ab0 $3f3ca003 $3f385216 $3f33e7bc $3f2f61a5 $3f2ac082 $3f26050a $3f212ff9 $3f1c420c $3f173c07 $3f121eb0 $3f0cead0 $3f07a136 $3f0242b1 $3ef9a02d $3eee9479 $3ee363fa $3ed8106b $3ecc9b8b $3ec1071e $3eb554ec $3ea986c4 $3e9d9e78 $3e919ddd $3e8586ce $3e72b651 $3e5a3997 $3e419b37 $3e28defc $3e1008b7 $3dee3876 $3dbc3ac3 $3d8a200a $3d2fe007 $3c96c9b6 $bbc90f88 $bcfb49ba $bd621469 $3f3b8f3b $3f373a23 $3f32c8c9 $3f2e3bde $3f299415 $3f24d225 $3f1ff6cb $3f1b02c6 $3f15f6d9 $3f10d3cd $3f0b9a6b $3f064b82 $3f00e7e4 $3ef6e0cb $3eebcbbb $3ee0924f $3ed53641 $3ec9b953 $3ebe1d4a $3eb263ef $3ea68f12 $3e9aa086 $3e8e9a22 $3e827dc0 $3e6c9a7f $3e541501 $3e3b6ecf $3e22abb6 $3e09cf86 $3de1bc2e $3dafb680 $3d7b2b74 $3d16c32c $3c490e90 $bc490e90 $bd16c32c $bd7b2b74 $3f3a7ca4 $3f36206c $3f31a81d $3f2d1469 $3f286605 $3f239da9 $3f1ebc12 $3f19c200 $3f14b039 $3f0f8784 $3f0a48ad $3f04f484 $3eff17b2 $3ef41f07 $3ee900b7 $3eddbe79 $3ed25a09 $3ec6d529 $3ebb31a0 $3eaf713a $3ea395c5 $3e97a117 $3e8b9507 $3e7ee6e1 $3e667c66 $3e4dee60 $3e354098 $3e1c76de $3e039502 $3dd53db9 $3da3308c $3d621469 $3cfb49ba $3bc90f88 $bc96c9b6 $bd2fe007 $bd8a200a
Freescale Semiconductor, Inc.
xr:$00000500= $248d4000 xr:$00000504= $bcc90ab0 xr:$00000508= $bd48fb30
DSP96002/D, Rev.
More Information This Product, www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Memory Tables
Table Memory Contents (full cycle cosine values) (Continued)
xr:$0000050c= $bd96a905 xr:$00000510= $bdc8bd36 xr:$00000514= $bdfab273 xr:$00000518= $be164083 xr:$0000051c= $be2f10a2 xr:$00000520= $be47c5c2 xr:$00000524= $be605c13 xr:$00000528= $be78cfcc xr:$0000052c= $be888e93 xr:$00000530= $be94a031 xr:$00000534= $bea09ae5 xr:$00000538= $beac7cd4 xr:$0000053c= $beb8442a xr:$00000540= $bec3ef15 xr:$00000544= $becf7bca xr:$00000548= $bedae880 xr:$0000054c= $bee63375 xr:$00000550= $bef15aea xr:$00000554= $befc5d27 xr:$00000558= $bf039c3d xr:$0000055c= $bf08f59b xr:$00000560= $bf0e39da xr:$00000564= $bf13682a xr:$00000568= $bf187fc0 xr:$0000056c= $bf1d7fd1 xr:$00000570= $bf226799 xr:$00000574= $bf273656 xr:$00000578= $bf2beb4a xr:$0000057c= $bf3085bb xr:$00000580= $bf3504f3 xr:$00000584= $bf396842 xr:$00000588= $bf3daef9 xr:$0000058c= $bf41d870 xr:$00000590= $bf45e403 xr:$00000594= $bf49d112 xr:$00000598= $bf4d9f02 xr:$0000059c= $bf514d3d $bda3308c $bdd53db9 $be039502 $be1c76de $be354098 $be4dee60 $be667c66 $be7ee6e1 $be8b9507 $be97a117 $bea395c5 $beaf713a $bebb31a0 $bec6d529 $bed25a09 $beddbe79 $bee900b7 $bef41f07 $beff17b2 $bf04f484 $bf0a48ad $bf0f8784 $bf14b039 $bf19c200 $bf1ebc12 $bf239da9 $bf286605 $bf2d1469 $bf31a81d $bf36206c $bf3a7ca4 $bf3ebc1b $bf42de29 $bf46e22a $bf4ac77f $bf4e8d90 $bf5233c6 $bdafb680 $bde1bc2e $be09cf86 $be22abb6 $be3b6ecf $be541501 $be6c9a7f $be827dc0 $be8e9a22 $be9aa086 $bea68f12 $beb263ef $bebe1d4a $bec9b953 $bed53641 $bee0924f $beebcbbb $bef6e0cb $bf00e7e4 $bf064b82 $bf0b9a6b $bf10d3cd $bf15f6d9 $bf1b02c6 $bf1ff6cb $bf24d225 $bf299415 $bf2e3bde $bf32c8c9 $bf373a23 $bf3b8f3b $bf3fc767 $bf43e200 $bf47de65 $bf4bbbf8 $bf4f7a1f $bf531849 $bdbc3ac3 $bdee3876 $be1008b7 $be28defc $be419b37 $be5a3997 $be72b651 $be8586ce $be919ddd $be9d9e78 $bea986c4 $beb554ec $bec1071e $becc9b8b $bed8106b $bee363fa $beee9479 $bef9a02d $bf0242b1 $bf07a136 $bf0cead0 $bf121eb0 $bf173c07 $bf1c420c $bf212ff9 $bf26050a $bf2ac082 $bf2f61a5 $bf33e7bc $bf385216 $bf3ca003 $bf40d0da $bf44e3f5 $bf48d8b3 $bf4cae79 $bf5064af $bf53fac3
Freescale Semiconductor, Inc.
MOTOROLA
DSP96002/D, Rev.
More Information This Product, www.freescale.com
Freescale Semiconductor, Inc.
Memory Tables
Table Memory Contents (full cycle cosine values) (Continued)
xr:$000005a0= $bf54db31 xr:$000005a4= $bf584853 xr:$000005a8= $bf5b941a xr:$000005ac= $bf5ebe05 xr:$000005b0= $bf61c598 xr:$000005b4= $bf64aa59 xr:$000005b8= $bf676bd8 xr:$000005bc= $bf6a09a7 xr:$000005c0= $bf6c835e xr:$000005c4= $bf6ed89e xr:$000005c8= $bf710908 xr:$000005cc= $bf731447 xr:$000005d0= $bf74fa0b xr:$000005d4= $bf76ba07 xr:$000005d8= $bf7853f8 xr:$000005dc= $bf79c79d xr:$000005e0= $bf7b14be xr:$000005e4= $bf7c3b28 xr:$000005e8= $bf7d3aac xr:$000005ec= xr:$000005f0= xr:$000005f4= xr:$000005f8= xr:$000005fc= $bf7e1324 $bf7ec46d $bf7f4e6d $bf7fb10f $bf7fec43 $bf55b993 $bf591e6a $bf5c61c7 $bf5f8327 $bf628210 $bf655e0b $bf6816a8 $bf6aab7b $bf6d1c1d $bf6f6830 $bf718f57 $bf73913f $bf756d97 $bf772417 $bf78b47b $bf7a1e84 $bf7b61fc $bf7c7eb0 $bf7d7474 $bf7e4323 $bf7eea9d $bf7f6ac7 $bf7fc38f $bf7ff4e6 $bf7ffec4 $bf7fe129 $bf7f9c18 $bf7f2f9d $bf7e9bc9 $bf7de0b1 $bf7cfe73 $bf7bf531 $bf7ac516 $bf796e4e $bf77f110 $bf764d97 $bf748422 $bf5695e5 $bf59f26a $bf5d2d53 $bf604621 $bf633c5a $bf660f88 $bf68bf3c $bf6b4b0c $bf6db293 $bf6ff573 $bf721352 $bf740bdd $bf75dec6 $bf778bc5 $bf791298 $bf7a7302 $bf7baccd $bf7cbfc9 $bf7dabcc $bf7e70b0 $bf7f0e58 $bf7f84ab $bf7fd397 $bf7ffb11 $bf7ffb11 $bf7fd397 $bf7f84ab $bf7f0e58 $bf7e70b0 $bf7dabcc $bf7cbfc9 $bf7baccd $bf7a7302 $bf791298 $bf778bc5 $bf75dec6 $bf740bdd $bf577026 $bf5ac450 $bf5df6be $bf6106f2 $bf63f473 $bf66becc $bf696591 $bf6be858 $bf6e46be $bf708066 $bf7294f8 $bf748422 $bf764d97 $bf77f110 $bf796e4e $bf7ac516 $bf7bf531 $bf7cfe73 $bf7de0b1 $bf7e9bc9 $bf7f2f9d $bf7f9c18 $bf7fe129 $bf7ffec4 $bf7ff4e6 $bf7fc38f $bf7f6ac7 $bf7eea9d $bf7e4323 $bf7d7474 $bf7c7eb0 $bf7b61fc $bf7a1e84 $bf78b47b $bf772417 $bf756d97 $bf73913f
Freescale Semiconductor, Inc.
xr:$00000600= $bf800000 xr:$00000604= $bf7fec43 xr:$00000608= $bf7fb10f xr:$0000060c= $bf7f4e6d xr:$00000610= $bf7ec46d xr:$00000614= $bf7e1324 xr:$00000618= $bf7d3aac xr:$0000061c= $bf7c3b28 xr:$00000620= $bf7b14be xr:$00000624= $bf79c79d xr:$00000628= $bf7853f8 xr:$0000062c= $bf76ba07 xr:$00000630= $bf74fa0b
DSP96002/D, Rev.
More Information This Product, www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Memory Tables
Table Memory Contents (full cycle cosine values) (Continued)
xr:$00000634= $bf731447 xr:$00000638= $bf710908 xr:$0000063c= $bf6ed89e xr:$00000640= $bf6c835e xr:$00000644= $bf6a09a7 xr:$00000648= $bf676bd8 xr:$0000064c= $bf64aa59 xr:$00000650= $bf61c598 xr:$00000654= $bf5ebe05 xr:$00000658= $bf5b941a xr:$0000065c= $bf584853 xr:$00000660= $bf54db31 xr:$00000664= $bf514d3d xr:$00000668= $bf4d9f02 xr:$0000066c= $bf49d112 xr:$00000670= $bf45e403 xr:$00000674= $bf41d870 xr:$00000678= $bf3daef9 xr:$0000067c= $bf396842 xr:$00000680= $bf3504f3 xr:$00000684= $bf3085bb xr:$00000688= $bf2beb4a xr:$0000068c= $bf273656 xr:$00000690= $bf226799 xr:$00000694= $bf1d7fd1 xr:$00000698= $bf187fc0 xr:$0000069c= $bf13682a xr:$000006a0= $bf0e39da xr:$000006a4= $bf08f59b xr:$000006a8= $bf039c3d xr:$000006ac= $befc5d27 xr:$000006b0= $bef15aea xr:$000006b4= $bee63375 xr:$000006b8= $bedae880 xr:$000006bc= $becf7bca xr:$000006c0= $bec3ef15 xr:$000006c4= $beb8442a $bf7294f8 $bf708066 $bf6e46be $bf6be858 $bf696591 $bf66becc $bf63f473 $bf6106f2 $bf5df6be $bf5ac450 $bf577026 $bf53fac3 $bf5064af $bf4cae79 $bf48d8b3 $bf44e3f5 $bf40d0da $bf3ca003 $bf385216 $bf33e7bc $bf2f61a5 $bf2ac082 $bf26050a $bf212ff9 $bf1c420c $bf173c07 $bf121eb0 $bf0cead0 $bf07a136 $bf0242b1 $bef9a02d $beee9479 $bee363fa $bed8106b $becc9b8b $bec1071e $beb554ec $bf721352 $bf6ff573 $bf6db293 $bf6b4b0c $bf68bf3c $bf660f88 $bf633c5a $bf604621 $bf5d2d53 $bf59f26a $bf5695e5 $bf531849 $bf4f7a1f $bf4bbbf8 $bf47de65 $bf43e200 $bf3fc767 $bf3b8f3b $bf373a23 $bf32c8c9 $bf2e3bde $bf299415 $bf24d225 $bf1ff6cb $bf1b02c6 $bf15f6d9 $bf10d3cd $bf0b9a6b $bf064b82 $bf00e7e4 $bef6e0cb $beebcbbb $bee0924f $bed53641 $bec9b953 $bebe1d4a $beb263ef $bf718f57 $bf6f6830 $bf6d1c1d $bf6aab7b $bf6816a8 $bf655e0b $bf628210 $bf5f8327 $bf5c61c7 $bf591e6a $bf55b993 $bf5233c6 $bf4e8d90 $bf4ac77f $bf46e22a $bf42de29 $bf3ebc1b $bf3a7ca4 $bf36206c $bf31a81d $bf2d1469 $bf286605 $bf239da9 $bf1ebc12 $bf19c200 $bf14b039 $bf0f8784 $bf0a48ad $bf04f484 $beff17b2 $bef41f07 $bee900b7 $beddbe79 $bed25a09 $bec6d529 $bebb31a0 $beaf713a
Freescale Semiconductor, Inc.
MOTOROLA
DSP96002/D, Rev.
More Information This Product, www.freescale.com
Freescale Semiconductor, Inc.
Memory Tables
Table Memory Contents (full cycle cosine values) (Continued)
xr:$000006c8= $beac7cd4 xr:$000006cc= $bea09ae5 xr:$000006d0= $be94a031 xr:$000006d4= $be888e93 xr:$000006d8= $be78cfcc xr:$000006dc= $be605c13 xr:$000006e0= $be47c5c2 xr:$000006e4= $be2f10a2 xr:$000006e8= $be164083 xr:$000006ec= xr:$000006f0= xr:$000006f4= xr:$000006f8= xr:$000006fc= $bdfab273 $bdc8bd36 $bd96a905 $bd48fb30 $bcc90ab0 $bea986c4 $be9d9e78 $be919ddd $be8586ce $be72b651 $be5a3997 $be419b37 $be28defc $be1008b7 $bdee3876 $bdbc3ac3 $bd8a200a $bd2fe007 $bc96c9b6 $3bc90f88 $3cfb49ba $3d621469 $3da3308c $3dd53db9 $3e039502 $3e1c76de $3e354098 $3e4dee60 $3e667c66 $3e7ee6e1 $3e8b9507 $3e97a117 $3ea395c5 $3eaf713a $3ebb31a0 $3ec6d529 $3ed25a09 $3eddbe79 $3ee900b7 $3ef41f07 $3eff17b2 $3f04f484 $bea68f12 $be9aa086 $be8e9a22 $be827dc0 $be6c9a7f $be541501 $be3b6ecf $be22abb6 $be09cf86 $bde1bc2e $bdafb680 $bd7b2b74 $bd16c32c $bc490e90 $3c490e90 $3d16c32c $3d7b2b74 $3dafb680 $3de1bc2e $3e09cf86 $3e22abb6 $3e3b6ecf $3e541501 $3e6c9a7f $3e827dc0 $3e8e9a22 $3e9aa086 $3ea68f12 $3eb263ef $3ebe1d4a $3ec9b953 $3ed53641 $3ee0924f $3eebcbbb $3ef6e0cb $3f00e7e4 $3f064b82 $bea395c5 $be97a117 $be8b9507 $be7ee6e1 $be667c66 $be4dee60 $be354098 $be1c76de $be039502 $bdd53db9 $bda3308c $bd621469 $bcfb49ba $bbc90f88 $3c96c9b6 $3d2fe007 $3d8a200a $3dbc3ac3 $3dee3876 $3e1008b7 $3e28defc $3e419b37 $3e5a3997 $3e72b651 $3e8586ce $3e919ddd $3e9d9e78 $3ea986c4 $3eb554ec $3ec1071e $3ecc9b8b $3ed8106b $3ee363fa $3eee9479 $3ef9a02d $3f0242b1 $3f07a136
Freescale Semiconductor, Inc.
xr:$00000700= $a48d4000 xr:$00000704= $3cc90ab0 xr:$00000708= $3d48fb30 xr:$0000070c= $3d96a905 xr:$00000710= $3dc8bd36 xr:$00000714= $3dfab273 xr:$00000718= $3e164083 xr:$0000071c= $3e2f10a2 xr:$00000720= $3e47c5c2 xr:$00000724= $3e605c13 xr:$00000728= $3e78cfcc xr:$0000072c= $3e888e93 xr:$00000730= $3e94a031 xr:$00000734= $3ea09ae5 xr:$00000738= $3eac7cd4 xr:$0000073c= $3eb8442a xr:$00000740= $3ec3ef15 xr:$00000744= $3ecf7bca xr:$00000748= $3edae880 xr:$0000074c= $3ee63375 xr:$00000750= $3ef15aea xr:$00000754= $3efc5d27 xr:$00000758= $3f039c3d
DSP96002/D, Rev.
More Information This Product, www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Memory Tables
Table Memory Contents (full cycle cosine values) (Continued)
xr:$0000075c= $3f08f59b xr:$00000760= $3f0e39da xr:$00000764= $3f13682a xr:$00000768= $3f187fc0 xr:$0000076c= $3f1d7fd1 xr:$00000770= $3f226799 xr:$00000774= $3f273656 xr:$00000778= $3f2beb4a xr:$0000077c= $3f3085bb xr:$00000780= $3f3504f3 xr:$00000784= $3f396842 xr:$00000788= $3f3daef9 xr:$0000078c= $3f41d870 xr:$00000790= $3f45e403 xr:$00000794= $3f49d112 xr:$00000798= $3f4d9f02 xr:$0000079c= $3f514d3d xr:$000007a0= $3f54db31 xr:$000007a4= $3f584853 xr:$000007a8= $3f5b941a xr:$000007ac= $3f5ebe05 xr:$000007b0= $3f61c598 xr:$000007b4= $3f64aa59 xr:$000007b8= $3f676bd8 xr:$000007bc= $3f6a09a7 xr:$000007c0= $3f6c835e xr:$000007c4= $3f6ed89e xr:$000007c8= $3f710908 xr:$000007cc= $3f731447 xr:$000007d0= $3f74fa0b xr:$000007d4= $3f76ba07 xr:$000007d8= $3f7853f8 xr:$000007dc= $3f79c79d xr:$000007e0= $3f7b14be xr:$000007e4= $3f7c3b28 xr:$000007e8= $3f7d3aac xr:$000007ec= $3f7e1324 $3f0a48ad $3f0f8784 $3f14b039 $3f19c200 $3f1ebc12 $3f239da9 $3f286605 $3f2d1469 $3f31a81d $3f36206c $3f3a7ca4 $3f3ebc1b $3f42de29 $3f46e22a $3f4ac77f $3f4e8d90 $3f5233c6 $3f55b993 $3f591e6a $3f5c61c7 $3f5f8327 $3f628210 $3f655e0b $3f6816a8 $3f6aab7b $3f6d1c1d $3f6f6830 $3f718f57 $3f73913f $3f756d97 $3f772417 $3f78b47b $3f7a1e84 $3f7b61fc $3f7c7eb0 $3f7d7474 $3f7e4323 $3f0b9a6b $3f10d3cd $3f15f6d9 $3f1b02c6 $3f1ff6cb $3f24d225 $3f299415 $3f2e3bde $3f32c8c9 $3f373a23 $3f3b8f3b $3f3fc767 $3f43e200 $3f47de65 $3f4bbbf8 $3f4f7a1f $3f531849 $3f5695e5 $3f59f26a $3f5d2d53 $3f604621 $3f633c5a $3f660f88 $3f68bf3c $3f6b4b0c $3f6db293 $3f6ff573 $3f721352 $3f740bdd $3f75dec6 $3f778bc5 $3f791298 $3f7a7302 $3f7baccd $3f7cbfc9 $3f7dabcc $3f7e70b0 $3f0cead0 $3f121eb0 $3f173c07 $3f1c420c $3f212ff9 $3f26050a $3f2ac082 $3f2f61a5 $3f33e7bc $3f385216 $3f3ca003 $3f40d0da $3f44e3f5 $3f48d8b3 $3f4cae79 $3f5064af $3f53fac3 $3f577026 $3f5ac450 $3f5df6be $3f6106f2 $3f63f473 $3f66becc $3f696591 $3f6be858 $3f6e46be $3f708066 $3f7294f8 $3f748422 $3f764d97 $3f77f110 $3f796e4e $3f7ac516 $3f7bf531 $3f7cfe73 $3f7de0b1 $3f7e9bc9
Freescale Semiconductor, Inc.
MOTOROLA
DSP96002/D, Rev.
More Information This Product, www.freescale.com
Freescale Semiconductor, Inc.
Memory Tables
Table Memory Contents (full cycle cosine values) (Continued)
xr:$000007f0= xr:$000007f4= xr:$000007f8= xr:$000007fc= $3f7ec46d $3f7f4e6d $3f7fb10f $3f7fec43 $3f7eea9d $3f7f6ac7 $3f7fc38f $3f7ff4e6 $3f7f0e58 $3f7f84ab $3f7fd397 $3f7ffb11 $3f7f2f9d $3f7f9c18 $3f7fe129 $3f7ffec4
Table Memory Contents (full cycle sine values)
yr:$00000400= $00000000 $3bc90f88 $3cfb49ba $3d621469 $3da3308c $3dd53db9 $3e039502 $3e1c76de $3e354098 $3e4dee60 $3e667c66 $3e7ee6e1 $3e8b9507 $3e97a117 $3ea395c5 $3eaf713a $3ebb31a0 $3ec6d529 $3ed25a09 $3eddbe79 $3ee900b7 $3ef41f07 $3eff17b2 $3f04f484 $3f0a48ad $3f0f8784 $3f14b039 $3f19c200 $3f1ebc12 $3f239da9 $3f286605 $3c490e90 $3d16c32c $3d7b2b74 $3dafb680 $3de1bc2e $3e09cf86 $3e22abb6 $3e3b6ecf $3e541501 $3e6c9a7f $3e827dc0 $3e8e9a22 $3e9aa086 $3ea68f12 $3eb263ef $3ebe1d4a $3ec9b953 $3ed53641 $3ee0924f $3eebcbbb $3ef6e0cb $3f00e7e4 $3f064b82 $3f0b9a6b $3f10d3cd $3f15f6d9 $3f1b02c6 $3f1ff6cb $3f24d225 $3f299415 $3c96c9b6 $3d2fe007 $3d8a200a $3dbc3ac3 $3dee3876 $3e1008b7 $3e28defc $3e419b37 $3e5a3997 $3e72b651 $3e8586ce $3e919ddd $3e9d9e78 $3ea986c4 $3eb554ec $3ec1071e $3ecc9b8b $3ed8106b $3ee363fa $3eee9479 $3ef9a02d $3f0242b1 $3f07a136 $3f0cead0 $3f121eb0 $3f173c07 $3f1c420c $3f212ff9 $3f26050a $3f2ac082 yr:$00000404= $3cc90ab0 yr:$00000408= $3d48fb30 yr:$0000040c= $3d96a905 yr:$00000410= $3dc8bd36 yr:$00000414= $3dfab273 yr:$00000418= $3e164083 yr:$0000041c= $3e2f10a2 yr:$00000420= $3e47c5c2 yr:$00000424= $3e605c13 yr:$00000428= $3e78cfcc yr:$0000042c= $3e888e93 yr:$00000430= $3e94a031 yr:$00000434= $3ea09ae5 yr:$00000438= $3eac7cd4 yr:$0000043c= $3eb8442a yr:$00000440= $3ec3ef15 yr:$00000444= $3ecf7bca yr:$00000448= $3edae880 yr:$0000044c= $3ee63375 yr:$00000450= $3ef15aea yr:$00000454= $3efc5d27 yr:$00000458= $3f039c3d yr:$0000045c= $3f08f59b yr:$00000460= $3f0e39da yr:$00000464= $3f13682a yr:$00000468= $3f187fc0 yr:$0000046c= $3f1d7fd1 yr:$00000470= $3f226799 yr:$00000474= $3f273656
Freescale Semiconductor, Inc.
DSP96002/D, Rev.
More Information This Product, www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Memory Tables
Table Memory Contents (full cycle sine values) (Continued)
yr:$00000478= $3f2beb4a yr:$0000047c= $3f3085bb yr:$00000480= $3f3504f3 yr:$00000484= $3f396842 yr:$00000488= $3f3daef9 yr:$0000048c= $3f41d870 yr:$00000490= $3f45e403 yr:$00000494= $3f49d112 yr:$00000498= $3f4d9f02 yr:$0000049c= $3f514d3d yr:$000004a0= $3f54db31 yr:$000004a4= $3f584853 yr:$000004a8= $3f5b941a yr:$000004ac= $3f5ebe05 yr:$000004b0= $3f61c598 yr:$000004b4= $3f64aa59 yr:$000004b8= $3f676bd8 yr:$000004bc= $3f6a09a7 yr:$000004c0= $3f6c835e yr:$000004c4= $3f6ed89e yr:$000004c8= $3f710908 yr:$000004cc= $3f731447 yr:$000004d0= $3f74fa0b yr:$000004d4= $3f76ba07 yr:$000004d8= $3f7853f8 yr:$000004dc= $3f79c79d yr:$000004e0= $3f7b14be yr:$000004e4= $3f7c3b28 yr:$000004e8= $3f7d3aac yr:$000004ec= $3f7e1324 yr:$000004f0= yr:$000004f4= yr:$000004f8= yr:$000004fc= $3f7ec46d $3f7f4e6d $3f7fb10f $3f7fec43 $3f2d1469 $3f31a81d $3f36206c $3f3a7ca4 $3f3ebc1b $3f42de29 $3f46e22a $3f4ac77f $3f4e8d90 $3f5233c6 $3f55b993 $3f591e6a $3f5c61c7 $3f5f8327 $3f628210 $3f655e0b $3f6816a8 $3f6aab7b $3f6d1c1d $3f6f6830 $3f718f57 $3f73913f $3f756d97 $3f772417 $3f78b47b $3f7a1e84 $3f7b61fc $3f7c7eb0 $3f7d7474 $3f7e4323 $3f7
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