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SWITCHING REGULATOR OUTPUT CURRENT 5.1V OUTPUT VOLTAGE RANGE DUTY
Top Searches for this datasheetL4972A L4972AD SWITCHING REGULATOR OUTPUT CURRENT 5.1V OUTPUT VOLTAGE RANGE DUTY CYCLE RANGE INTERNAL FEED-FORWARD LINE REG. INTERNAL CURRENT LIMITING PRECISE 5.1V CHIP REFERENCE RESET POWER FAIL FUNCTIONS INPUT/OUTPUT SYNC UNDER VOLTAGE LOCK WITH HYSTERETIC TURN-ON LATCH SINGLE PULSE PERIOD VERY HIGH EFFICIENCY SWITCHING FREQUENCY 200KHz THERMAL SHUTDOWN CONTINUOUS MODE OPERATION MULTIPOWER TECHNOLOGY POWERDIP SO20 ORDERING NUMBERS L4972A (Powerdip) L4972AD (SO20) DESCRIPTION L4972A stepdown monolithic power switching regulator delivering voltage variable from 40V. Realized with mixed technology, device uses DMOS output transistor obtain very high efficiency very fast switching times. Features BLOCK DIAGRAM L4972A include reset power fail microprocessors, feed forward line regulation, soft start, limiting current thermal protection. device mounted Powerdip SO20 large plastic packages requires external components. Efficient operation switching frequencies 200KHz allows reduction size cost external filter component. June 2000 1/23 This advanced information product development undergoing evaluation. Details subject change without notice. L4972A-L4972AD ABSOLUTE MAXIMUM RATINGS Symbol Ptot Tstg SO-20 Parameter Input Voltage Input Operating Voltage Output Voltage Output Peak Voltage 0.1µs 200khz Maximum Output Current Boostrap Voltage Boostrap Operating Voltage Input Voltage Pins Reset Output Voltage Reset Output Sink Current Input Voltage Reset Delay Sink Current Error Amplifier Output Sink Current Soft Start Sink Current Total Power Dissipation TPINS 90°C Tamb 70°C copper area PCB) Junction Storage Temperature Value Internally Limited 3.75(*) 1.3/1 Unit CONNECTION (top view) THERMAL DATA Symbol j-pins j-amb Parameter Thermal Resistance Junction-Pins Thermal Resistance Junction-ambient Powerdip 12°C/W 60°C/W SO-20 16°C/W 80°C/W 2/23 L4972A-L4972AD FUNCTIONS Name BOOTSTRAP RESET DELAY RESET RESET INPUT Function Cboot capacitor connected between this terminal output allows drive properly internal D-MOS transistor. capacitor connected between this terminal ground determines reset signal delay time. Open Collector Reset/power Fail Signal Output. This output high when supply output voltages safe. Input Power Fail Circuit. threshold 5.1V. connected divider input power fail function. must connected external resistor when power fail signal required. Common Ground Terminal series network connected between this terminal ground determines regulation loop gain characteristics. Soft Start Time Constant. capacitor connected between sterminal ground define soft start time constant. Feedback Terminal Regulation Loop. output connected directly this terminal 5.1V operation; connected divider higher voltages. Multiple L4972A's synchronized connecting inputs together external syncr. pulse. Unregulated Input Voltage. Connected. 5.1V Vref Device Reference Voltage. Internal Start-up Circuit Drive Power Stage. Rosc. External resistor connected ground determines constant charging current Cosc. Cosc. External capacitor connected ground determines (with Rosc) switching frequency. Regulator Output. GROUND FREQUENCY COMPENSATION SOFT START FEEDBACK INPUT SYNC INPUT SUPPLY VOLTAGE N.C. Vref Vstart OSCILLATOR OSCILLATOR OUTPUT 3/23 L4972A-L4972AD CIRCUIT OPERATION L4972A monolithic stepdown switching regulator working continuous mode realized Technology. This technology allows integration isolated vertical DMOS power transistors plus mixed CMOS/Bipolar transistors. device deliver output voltage adjustable from 5.1V contains diagnostic control functions that make particularly suitable microprocessor based systems. BLOCK DIAGRAM block diagram shows DMOS power transistors control loop. Integrated functions include reference voltage trimmed 5.1V soft start, undervoltage lockout, oscillator with feedforward control, pulse pulse current limit, thermal shutdown finally reset power fail circuit. reset power fail circuit provides output signal microprocessor indicating status system. Device turn around with typical hysterysis, this threshold porvides correct voltage driving stage DMOS gate hysterysis prevents instabilities. external bootstrap capacitor charge internal voltage reference needed provide correct gate drive power DMOS. driving circuit able source sink peak currents around 0.5A gate DMOS transistor. typical switching time current DMOS transistor 50ns. fast commutation switching frequencies 200kHz possible. control loop consists sawtooth oscillator, error amplifier, comparator, latch output stage. error signal produced comparing output voltage with precise 5.1V chip reference. This error signal then compared with sawtooth oscillator order generate frixed frequency pulse width modulated drive output stage. latch included eliminate multiple pulsing within period even noisy environments. gain stability loop adjusted external network connected output error amplifier. voltage feedforward control been added oscillator, this maintains superior line regulation over wide input voltage range. Closing loop directly gives output voltage 5.1V, higher voltages obtained inserting voltage divider. turn output overcurrents prevented soft start function (fig. error amplifier initially clamped external capacitor, Css, allowed rise linearly under charge internal constant current source. Output overload protection provided current limit circuit. load current sensed internal metal resistor connected comparator. When load current exceeds preset threshold, output comparator sets flip flop which turns power DMOS. next clock pulse, from internal 40kHz oscillator, will reset flip flop power DMOS will again conduct. This current protection method, ensures constant current output when system overloaded short circuited limits switching frequency, this condition, 40kHz. Reset Power fail circuit (fig. generates output signal when supply voltage exceeds threshold programmed external voltage divider. reset signal, generated with delay time programmed external capacitor delay pin. When supply voltage falls below threshold output voltage goes below reset output goes immediately. reset output open drain. Fig. shows case when supply voltage higher than threshold, output voltage Fig. shows case when output 5.1V, supply voltage higher than fixed threshold. thermal protection disables circuit operation when junction temperature reaches about 150°C hysterysis prevent unstable conditions. 4/23 L4972A-L4972AD Figure Feedforward Waveform. Figure Soft Start Function. Figure Limiting Current Function. 5/23 L4972A-L4972AD Figure Reset Power Fail Functions. 6/23 L4972A-L4972AD ELECTRICAL CHARACTERISTICS (refer test circuit, 25°C, 35V, 30K, 2.7nF, 100KHz typ, unless otherwise specified) DYNAMIC CHARACTERISTICS Symbol I20L Parameter Input Volt. Range (pin Output Voltage Line Regulation Load Regulation Dropout Voltage between Limiting Current Efficiency Test Conditions Vref (**) =15V Vref 0.5A; Vref Vref 0.5A Vref 100KHz Vref 2VRMS; 100Hz; Vref Min. 0.25 Typ. Max. Unit Fig. f/Vi Supply Voltage Ripple Rejection Switching Frequency Voltage Stability Switching Frequency Temperature Stability Switching Frequency Maximum Operating Switching Frequency f/Tj fmax 125°C Vref 2.2nF Only version (**) Pulse testing with duty cycle Vref SECTION (pin Symbol short Parameter Reference Voltage Line Regulation Load Regulation Average Temperature Coefficient Reference Voltage Short Circuit Current Limit 125°C Test Condition Min. Typ. Max. Unit mV/°C Fig. VSTART SECTION (pin Symbol short Parameter Reference Voltage Line Regulation Load Regulation Short Circuit Current Limit Test Condition Min. 11.4 Typ. Max. 12.6 Unit Fig. 7/23 L4972A-L4972AD ELECTRICAL CHARACTERISTICS (continued) CHARACTERISTICS Symbol V11on Hyst I11Q I11OQ I20L Parameter Turn-on Threshold Turn-off Hysteresys Quiescent Current Operating Supply Current Leak Current 55V; Test Condition Min. Typ. Max. Unit Fig. SOFT START (pin Symbol Parameter Soft Start Source Current Output Saturation Voltage Test Condition 20mA; 200µA; Min. Typ. Max. Unit Fig. ERROR AMPLIFIER Symbol -I7L Parameter High Level Voltage Level Voltage Source Output Current Sink Output Current Input Bias Current Open Loop Gain Supply Voltage Rejection Input Offset Voltage Test Condition 100µA; 4.7V 100µA; 5.3V; 4.7V 5.3V Min. Typ. Max. Unit Fig. RAMP GENERATOR (pin Symbol Parameter Ramp Valley Ramp Peak Min. Ramp Current Max. Ramp Current Test Condition 100µA Min. Typ. Max. Unit Fig. SYNC FUNCTION (pin Symbol I10L I10H Parameter Input Voltage High Input voltage Test Condition 50V; Min. -0.3 Typ. Max. Unit Fig. Sync Input Current with 0.9V; Input Voltage Input Current with High 2.5V Input Voltage Output Amplitude Output Pulse Width Vthr 2.5V 8/23 L4972A-L4972AD ELECTRICAL CHARACTERISTICS (continued) RESET POWER FAIL FUNCTIONS Symbol I2SO I2SI Parameter Rising Thereshold Voltage (pin Falling Thereshold Voltage (pin Delay High Threshold Volt. Delay Threshold Volt. Delay Source Current Delay Source Sink Current Output Saturation Voltage Output Leak Current Rising Threshold Voltage Hysteresis Input Bias Current Test Conditions 5.3V 5.3V 5.3V 4.7V 5.3V; 4.7V; 15mA; 4.7V 50V; 4.95 Min. Vref -130 4.77 4.95 5.25 Typ. Vref -100 Vref -200 Max. Vref Vref -160 5.25 Unit Fig. TYPICAL PERFORMANCES (using evaluation board) VREF 100KHz) RIPPLE 30mV Line regulation 12mV 50V) Load regulation component values Refer fig. (Part list). 9/23 L4972A-L4972AD Figure Component Layout fig.5 scale). Evaluation Board Available (only version) PART LIST 4.7K table OPTION 4.7K 1000µF (ROE) 2,2µF 390pF Film 22nF 1837 (ERO) 2.7nF 1830 (ERO) 0.33µF Film 100µF (ROE) Film EQUIVALENT) 150µH core 58310 MAGNETICS TURNS 0.91mm (AWG COGEMA 949181 capacitors parallel increase input current capability. capacitors parallel reduce total output ESR. Table 4.7k 4.7k 4.7k 4.7k 6.2kW 9.1k Note: Test Application Circuit L4972D mounted Table SUGGESTED BOOSTRAP CAPACITORS Operating Frequency 20KHz 50KHz 100KHz 200KHz 500KHz Boostrap Cap.c10 680nF 470nF 330nF 220nF 100nF 10/23 L4972A-L4972AD Figure P.C. Board Component Layout Circuit Fig. (1:1 scale) Figure Test Circuits. 11/23 L4972A-L4972AD Figure Figure Figure 12/23 L4972A-L4972AD Figure Figure Quiescent Drain Current Supply Voltage duty cycle fig. 7A). Figure Quiescent Drain Current Junction Temperature duty cycle). 13/23 L4972A-L4972AD Figure Quiescent Drain Current Duty Cycle. Figure Reference Voltage (pin (see fig. Figure Reference Voltage (pin Junction Temperature (see fig. Figure Reference Voltage (pin (see fig. Figure Reference Voltage (pin Junction Temperature (see fig. Figure Reference Voltage 5.1V (pin Supply Voltage Ripple Rejection FreSVR (dB) 14/23 L4972A-L4972AD Figure Switching Frequency Input Voltage (see fig. Figure Switching Frequency Junction Temperature (see fig. Figure Switching Frequency (see fig.5). Figure Maximum Duty Cycle Frequency. Figure Supply Voltage Ripple Rejection Frequency (see fig. Figure Efficiency Output Voltage. 15/23 L4972A-L4972AD Figure Line Transient Response (see fig. Figure Load Transient Response (see fig. Figure Dropout Voltage between Current Figure .Dropout Voltage between Junction Temperature. Figure Power Dissipation (device only) Input Voltage. Figure Power Dissipation (device only) Input Voltage. 16/23 L4972A-L4972AD Figure Power Dissipation (device only) Output Voltage. Figure Power Dissipation (device only) Output Voltage. Figure Power Dissipation (device only) Output Current. Figure Power Dissipation (device only) Output Current. Figure Efficiency Output Current. Figure Test Thermal Characteristic. 17/23 L4972A-L4972AD Figure Junction Ambient Thermal Resistance Area Board Heatsink (DIP 16+2+2) Figure Junction Ambient Thermal Resistance Area Board Heatsink (SO20) Figure Maximum Allowable Power Dissipation Ambient Temperature (Powerdip) Figure Maximum Allowable Power Dissipation Ambient Temperature (SO20) Figure Open Loop Frequency Phase Error Amplifier (see fig. 7C). 18/23 L4972A-L4972AD Figure 5.1V Cost Application Circuit. Figure 5.1V/12V Multiple Supply. Note Synchronization between L4972A L4970A. 19/23 L4972A-L4972AD Figure L4972A's Sync. Example. Figure 1A/24V Multiple Supply. Note synchronization between L4972A L4962 20/23 L4972A-L4972AD DIM. MIN. 0.38 0.51 0.85 TYP. MAX. MIN. 0.020 1.40 0.50 0.50 24.80 8.80 2.54 22.86 7.10 5.10 3.30 1.27 0.015 0.033 inch TYP. MAX. OUTLINE MECHANICAL DATA 0.055 0.020 0.020 0.976 0.346 0.100 0.900 0.280 0.201 0.130 Powerdip 0.050 21/23 L4972A-L4972AD DIM. MIN. 0.25 2.35 0.33 0.23 12.6 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.51 0.32 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 inch TYP. MAX. 0.104 0.012 0.020 0.013 0.512 0.299 0.050 0.419 0.030 0.050 OUTLINE MECHANICAL DATA SO20 (min.)8° (max.) SO20MEC 22/23 L4972A-L4972AD Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specification mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. 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