3.3V CMOS 18-BIT UNIVERSAL IDT74ALVCHR16501 TRANSCEIVER WITH 3-STATE O

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3.3V CMOS 18-BIT UNIVERSAL IDT74ALVCHR16501 TRANSCEIVER WITH 3-STATE O

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IDT74ALVCHR16501 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS
3.3V CMOS 18-BIT UNIVERSAL IDT74ALVCHR16501 TRANSCEIVER WITH 3-STATE OUTPUTS BUS-HOLD
MICRON CMOS Technology Typical tSK(o) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range 2.5V 0.2V CMOS power levels (0.4µ typ. static) Rail-to-Rail output swing increased noise margin Available SSOP, TSSOP, TVSOP packages
FEATURES:
DESCRIPTION:
DRIVE FEATURES: APPLICATIONS:
Balanced Output Drivers: ±12mA Switching Noise 3.3V high speed systems 3.3V lower voltage computing systems
This 18-bit universal transceiver built using advanced dual metal CMOS technology. Data flow each direction controlled output-enable (OEAB OEBA), latch enable (LEAB LEBA) clock (CLKAB CLKBA) inputs. A-to-B data flow, device operates transparent mode when LEAB high. When LEAB low, data latched CLKAB held high logic level. LEAB low, data stored latch/ flip-flop low-to-high transition CLKAB. When OEAB high, outputs active. When OEAB low, outputs high-impedance state. Data flow from similiar that uses OEBA, LEBA, CLKBA. output enables complementary (OEAB active high OEBA active low). ALVCHR16501 series resistors device output structure which will significantly reduce reduce line noise when used with light loads. This driver been designed drive ±12mA designated threshold levels. ALVCHR16501 "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
OEAB CLKAB
LEAB LEBA CLKBA OEBA
OTHER CHANNELS
logo registered trademark Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
APRIL 1999
DSC-4613/1
IDT74ALVCHR16501 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS
CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description VTERM(2) Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Clamp Current, Continuous Current through each -0.5 +4.6 -0.5 VCC+0.5 +150 ±100 VTERM(3)
CLKAB CLKBA
Unit
OEAB LEAB OEBA LEBA
TSTG IOUT
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
CAPACITANCE +25°C, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NOTE: applicable device type.
DESCRIPTION
Names Description A-to-B Output Enable Input B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs B-to-A 3-State Outputs(1) B-to-A Data Inputs A-to-B 3-State Outputs(1) OEAB OEBA LEAB LEBA CLKAB CLKBA
SSOP/ TSSOP/ TVSOP VIEW
NOTE: These pins have "Bus-Hold". other pins standard inputs, outputs, I/Os.
IDT74ALVCHR16501 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS
FUNCTION TABLE(1,2)
Inputs OEAB LEAB CLKAB Output B(3) B(4)
NOTES: A-to-B data flow shown. B-to-A data flow similar, uses OEBA, LEBA, CLKBA. HIGH Voltage Level Voltage Level Don't Care High-Impedance LOW-to-HIGH Transition Output level before indicated steady-state input conditions were established Output level before indicated steady-state input conditions were established, provided that CLKAB before LEAB went LOW.
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40°C +85°C
Symbol IOZH IOZL ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input HIGH Current Input Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 2.3V, -18mA 3.3V 3.6V input 0.6V, other inputs 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 3.6V Test Conditions Min. Typ.(1) -0.7 Max. -1.2 Unit
Quiescent Power Supply Current Variation
NOTE: Typical values 3.3V, +25°C ambient.
IDT74ALVCHR16501 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: Pins with Bus-Hold identified description. Typical values 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current 2.3V 3.6V
Test Conditions 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max. ±500
Unit
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage 2.3V 2.7V Output Voltage 2.3V 3.6V 2.3V 2.7V Test Conditions(1) 2.3V 3.6V 0.1mA 12mA 0.1mA 12mA Min. Max. 0.55 0.55 Unit
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 25°C
2.5V 0.2V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical 3.3V 0.3V Typical Unit
IDT74ALVCHR16501 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS
SWITCHING CHARACTERISTICS(1)
2.5V 0.2V Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tSK(o) Parameter Propagation Delay Propagation Delay LEBA LEAB Propagation Delay CLKBA CLKAB Output Enable Time OEBA Output Enable Time OEAB Output Disable Time OEBA Output Disable Time OEAB Set-up Time, data before Hold Time, data after Set-up Time, data before HIGH Hold Time, data after HIGH Pulse Width, HIGH Pulse Width, HIGH Output Skew(2) Min. Max. 2.7V Min. Max. 3.3V 0.3V Min. Max. Unit
NOTES: TEST CIRCUITS WAVEFORMS. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74ALVCHR16501 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS
TEST CIRCUITS WAVEFORMS TEST CONDITIONS
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
ALVC Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 tPHZ tPLZ DISABLE VLOAD/2
ALVC Link
Pulse Generator
VLOAD Open
D.U.T.
VOUT
ALVC Link
Test Circuit Outputs
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 1.0MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 1.0MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
Enable Disable Times
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other Tests Switch VLOAD Open
tREM
ALVC Link
INPUT
tPLH1
tPHL1
Set-up, Hold, Release Times
OUTPUT
LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE
OUTPUT tPLH2 tPHL2
ALVC Link
Pulse Width
ALVC Link
tSK(x) tPLH2 tPLH1 tPHL2 tPHL1
Output Skew tSK(X)
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74ALVCHR16501 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS
ORDERING INFORMATION
ALVC Bus-Hold Temp. Range Family Device Type Package
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package 18-Bit Universal Transceiver with 3-State Outputs Double-Density, ±12mA Bus-Hold 40°C +85°C
CORPORATE HEADQUARTERS 2975 Stender Santa Clara, 95054
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Tech Support: logichelp@idt.com (408) 654-6459

3.3V CMOS 18-BIT UNIVERSAL IDT74ALVCHR16501 TRANSCEIVER WITH 3-STATE O

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