IDT74LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS, VOLT
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IDT74LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
IDT74LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS, VOLT TOLERANT BUS-HOLD
Typical tSK(o) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range CMOS power levels (0.4µ typ. static) inputs, outputs, tolerant Supports insertion Available SSOP, TSSOP, TVSOP packages
FEATURES:
DRIVE FEATURES: APPLICATIONS:
Balanced Output Drivers: ±12mA switching noise
3.3V mixed voltage systems Data communication telecommunication systems
This 20-bit flip-flop built using advanced dual metal CMOS technology. flip-flops LVCH162721A edge-triggered D-type flip-flops with qualified clock storage. positive transition clock (CLK) input, device provides true data outputs clock-enable (CLKEN) input low. CLKEN high, data stored. buffered output-enable (OE) input places outputs either normal logic state (high low) high-impedance state. highimpedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without need interface pullup components. does affect internal operation flip-flops. data retained data entered while outputs high-impedance state. LVCH162721A series resistors device output structure which will significantly reduce line noise when used with light loads. This driver been designed drive ±12mA designated threshold levels. LVCH162721A "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
DESCRIPTION:
FUNCTIONAL BLOCK DIAGRAM
CLKEN
Other Channels
logo registered trademark Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4940/1
IDT74LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
CONFIGURATION
CLKEN
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description VTERM TSTG IOUT Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Current through each -0.5 +6.5 +150 ±100
Unit
NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
CAPACITANCE +25°C, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NOTE: applicable device type.
DESCRIPTION
Names CLKEN Data Inputs(1) 3-State Outputs Clock Input Clock Enable Input (Active LOW) Internal Connection Description 3-State Output Enable Input (Active LOW)
NOTE: These pins have "Bus-Hold". other pins standard inputs, outputs, I/Os.
FUNCTION TABLE (EACH FLIP-FLOP)(1)
Inputs CLKEN Outputs Q(2) Q(2)
SSOP/ TSSOP/ TVSOP VIEW
NOTES: HIGH Voltage Level Don't Care Voltage Level High-Impedance LOW-to-HIGH transition Output level before indicated steady-state input conditions were established.
IDT74LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40°C +85°C
Symbol IOZH IOZL IOFF ICCL ICCH ICCZ High Impedance Output Current (3-State Output pins) Input/Output Power Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 5.5V 2.3V, -18mA 3.3V 3.6V -0.7 -1.2 3.6V 5.5V Parameter Input HIGH Voltage Level Input Voltage Level Input Leakage Current 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 5.5V Test Conditions Min. Typ.(1) Max. Unit
Quiescent Power Supply Current Variation
5.5V(2) input 0.6V, other inputs
NOTES: Typical values 3.3V, +25°C ambient. This applies disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: Pins with Bus-Hold identified description. Typical values 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current 2.3V 3.6V
Test Conditions 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max. ±500
Unit
IDT74LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage 2.3V 2.7V Output Voltage 2.3V 3.6V 2.3V 2.7V Test Conditions(1) 2.3V 3.6V 0.1mA 12mA 0.1mA 12mA Min. Max. 0.55 0.55 Unit
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 3.3V 0.3V, 25°C
Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical Unit
SWITCHING CHARACTERISTICS(1)
2.7V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay Output Enable Time Output Disable Time Set-up Time, data before Set-up Time, CLKEN before Hold Time, data after Hold Time, CLKEN after Pulse Duration, HIGH Output Skew(2) Min. Max. 3.3V 0.3V Min. Max. Unit
NOTES: TEST CIRCUITS WAVEFORMS. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
Link
TEST CIRCUITS WAVEFORMS TEST CONDITIONS
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
Pulse Generator D.U.T.
Link
SAME PHASE INPUT TRANSITION
VCC(2)= 2.5V±0.2V
Unit
VLOAD Open
tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
tPHL
tPHL
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 tPHZ tPLZ DISABLE VLOAD/2
Link
VOUT
Test Circuit Outputs
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
Enable Disable Times
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other Tests Switch VLOAD Open
tPLH2 tPHL2
Link
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
tREM
Link
Set-up, Hold, Release Times
INPUT
tPLH1
tPHL1
LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE
OUTPUT
Link
OUTPUT
Pulse Width
tSK(x) tPLH2 tPLH1 tPHL2 tPHL1
Output Skew tSK(X)
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
ORDERING INFORMATION
Bus-Hold Temp. Range Family Device Type Package
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package
721A 20-Bit Flip-Flop with 3-State Outputs Double-Density with Resistors, ±12mA Bus-hold -40°C +85°C
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