3.3V CMOS 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS VOLT

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3.3V CMOS 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS VOLT

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IDT74LVC841A 3.3V CMOS 10-BIT BUS-INTERFACE D-TYPE LATCH
3.3V CMOS 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS VOLT TOLERANT
MICRON CMOS Technology 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range CMOS power levels (0.4µ typ. static) Rail-to-rail output swing increased noise margin inputs, outputs, tolerant Supports insertion Available SOIC, SSOP, QSOP, TSSOP packages
IDT74LVC841A
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
High Output Drivers: ±24mA Reduced system switching noise
APPLICATIONS:
3.3V high speed systems 3.3V lower voltage computing systems
LVC841A 10-bit bus-interface D-type latch built using advanced dual metal CMOS technology. LVC841A designed specifically driving highly capacitive relatively low-impedance loads. particularly suitable implementing buffer registers, ports, bidirectional drivers, working registers. latches transparent D-type latches. device noninverting data inputs provides true data outputs. buffered output-enable input used place outputs either normal logic state (high logic levels) high-impedance state. high-impedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without interface pullup components. does affect internal operations latch. Previously stored data retained data entered while outputs highimpedance state. LVC841A been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. ensure high-impedance state during power power down, should tied through pullup resistor; minimum value resistor determined current-sinking capability driver. Inputs driven from either 3.3V devices. This feature allows this device translator mixed 3.3V/5V system environment.
FUNCTIONAL BLOCK DIAGRAM
NINE OTHER CHANNELS
logo registered trademark Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4695/1
IDT74LVC841A 3.3V CMOS 10-BIT BUS-INTERFACE D-TYPE LATCH
CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description VTERM TSTG Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Current through each -0.5 +6.5 +150 ±100
Unit
IOUT
NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
CAPACITANCE +25°C, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NOTE: applicable device type.
SOIC/ SSOP/ QSOP/ TSSOP VIEW
DESCRIPTION
Names Description Output Enable Control (Active LOW) Latch Enable Input Latch Data Inputs 3-State Latch Data Outputs
FUNCTION TABLE(1)
Inputs Outputs Q(2)
NOTES: HIGH Voltage Level Voltage Level Don't Care High Impedance Output level before indicated steady-state input conditions were established.
IDT74LVC841A 3.3V CMOS 10-BIT BUS-INTERFACE D-TYPE LATCH
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40°C +85°C
Symbol IOZH IOZL IOFF ICCL ICCH ICCZ High Impedance Output Current (3-State Output pins) Input/Output Power Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 5.5V 2.3V, -18mA 3.3V 3.6V -0.7 -1.2 3.6V 5.5V Parameter Input HIGH Voltage Level Input Voltage Level Input Leakage Current 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 5.5V Test Conditions Min. Typ.(1) Max. Unit
Quiescent Power Supply Current Variation
5.5V(2) input 0.6V, other inputs
NOTES: Typical values 3.3V, +25°C ambient. This applies disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage 2.3V 2.3V 2.7V Output Voltage 2.3V 3.6V 2.3V 2.7V 24mA 0.1mA 12mA 12mA 24mA Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. Max. 0.55 Unit
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
IDT74LVC841A 3.3V CMOS 10-BIT BUS-INTERFACE D-TYPE LATCH
OPERATING CHARACTERISTICS, 3.3V 0.3V, 25°C
Symbol Parameter Power Dissipation Capacitance Latch Outputs enabled Power Dissipation Capacitance Latch Outputs disabled Test Conditions 0pF, 10Mhz Typical Unit
SWITCHING CHARACTERISTICS(1)
2.7V Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay Propagation Delay Output Enable Time Output Disable Time Pulse Duration Set-up Time, data before Hold Time, data after Output Skew(2) Min. Max. 3.3V 0.3V Min. Max. Unit
NOTES: TEST CIRCUITS WAVEFORMS. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74LVC841A 3.3V CMOS 10-BIT BUS-INTERFACE D-TYPE LATCH
TEST CIRCUITS WAVEFORMS TEST CONDITIONS
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
Link
Pulse Generator D.U.T. VOUT
VLOAD Open CONTROL INPUT
Propagation Delay
ENABLE DISABLE VLOAD/2 VOL+VLZ VOH-VHZ
Link
tPZL OUTPUT SWITCH NORMALLY VLOAD tPZH OUTPUT SWITCH NORMALLY HIGH VLOAD/2 tPHZ
tPLZ
Link
Test Circuit Outputs
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
Enable Disable Times
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other Tests Switch VLOAD Open
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
tREM
Link
INPUT
Set-up, Hold, Release Times
tPLH1
tPHL1
OUTPUT
LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE
OUTPUT tPLH2 tPHL2
Pulse Width
Link
Link
tSK(x) tPLH2 tPLH1 tPHL2 tPHL1
Output Skew tSK(X)
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74LVC841A 3.3V CMOS 10-BIT BUS-INTERFACE D-TYPE LATCH
ORDERING INFORMATION
Temp. Range Bus-Hold XXXX Device Type Package
841A
Small Outline (gull wing) Shrink Small Outline Package Quarter Size Small Outline Package Thin Shrink Small Outline Package 10-Bit Bus-Interface D-Type Latch with 3-State Outputs, ±24mA Bus-hold -40°C +85°C
Blank
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3.3V CMOS 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS VOLT

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