Hynix HYMD264G726D(L)F4N-D43/J series registered 184-pin double data r
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64Mx72 bits Registered SDRAM DIMM HYMD264G726D(L)F4N-D43/J
Hynix HYMD264G726D(L)F4N-D43/J series registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which organized 64Mx72 high-speed memory arrays. Hynix HYMD264G726D(L)F4ND43/J series consists eighteen 64Mx4 SDRAM FBGA packages 184pin glass-epoxy substrate. Hynix HYMD264G726D(L)F4N-D43/J series provide high performance 8-byte interface 5.25" width form factor industry standard. suitable easy interchange addition. Hynix HYMD264G726D(L)F4N-D43/J series designed high speed 166/200MHz offers fully synchronous operations referenced both rising falling edges differential clock inputs. While addresses control inputs latched rising edges clock, Data, Data strobes Write data masks inputs sampled both rising falling edges data paths internally pipelined 2-bit prefetched achieve very high bandwidth. input output voltage levels compatible with SSTL_2. High speed frequencies, programmable latencies burst lengths allow variety device operation high performance memory system. Hynix HYMD264G726D(L)F4N-D43/J series incorporates SPD(serial presence detect). Serial presence detect function implemented serial 2,048-bit EEPROM. first bytes serial data programmed Hynix identify DIMM type, capacity other information DIMM last bytes available customer.
FEATURES
512MB (64M Registered DIMM based 64Mx4 SDRAM JEDEC Standard 184-pin dual in-line memory module (DIMM) Error Check Correction (ECC) Capability Registered inputs with one-clock delay Phase-lock loop (PLL) clock driver reduce loading 2.6V 0.1V VDDQ Power supply DDR400, 2.5V 0.2V VDDQ DDR333 supported inputs outputs compatible with SSTL_2 interface Fully differential clock operations /CK) with 166/200MHz Programmable Latency DDR400, DDR333 supported Programmable Burst Length with both sequential interleave mode tRAS Lock-out function supported Internal four bank operations with single pulsed Auto refresh self refresh supported 8192 refresh cycles 64ms
ORDERING INFORMATION
Part
HYMD264G726D(L)F4N-D43 HYMD264G726D(L)F4N-J
Power Supply
VDD=2.6V VDDQ=2.6V VDD=2.5V VDDQ=2.5V
Clock Frequency
200MHz (*DDR400)
Interface
Form Factor
SSTL_2 166MHz (*DDR333)
184pin Registered DIMM 5.25 1.125 0.15 inch
JEDEC Defined Specifications compliant
This document general product description subject change without notice. Hynix Semiconductor does assume responsibility circuits described. patent licenses implied. Rev. June 2004
HYMD264G726D(L)F4N-D43/J
CK0, /CK0 CS0, CKE0 /RAS, /CAS, BA0, DQ0~DQ64 CB0~CB7 DQS0~DQS7 DM0~8 /RESET Description Differential Clock Inputs Chip Select Input Clock Enable Input Commend Sets Inputs Address Bank Address Data Inputs/Outputs Data Strobe Inputs/Outputs Data Strobe Inputs/Outputs Data-in Mask Power Supply Reset Enable VDDQ VREF VDDSPD SA0~SA2 VDDID FETEN Description Power Supply Ground Reference Power Supply Power Supply E2PROM Address Inputs E2PROM Clock E2PROM Data Write Protect Flag Identification Flag Connection Enable
ASSIGNMENT
Name VREF DQS0 /RESET DQS1 VDDQ DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 DQ18 VDDQ DQ19 DQ32 VDDQ DQ33 DQS4 DQ34 DQ35 DQ40 Name DQ24 DQ25 DQS3 DQ26 DQ27 DQS8 Name VDDQ DQ41 /CAS DQS5 DQ42 DQ43 DQ48 DQ49 VDDQ DQS6 DQ50 DQ51 VDDID DQ56 DQ57 DQS7 DQ58 DQ59 Name VDDQ VDDQ DQ12 DQ13 DQ14 DQ15 CKE1* VDDQ BA2* DQ20 DQ21 DQ22 DQ23 DQ36 DQ37 DQ38 DQ39 DQ44 Name DQ28 DQ29 VDDQ DQ30 DQ31 VDDQ /CK0 VDDQ Name /RAS DQ45 VDDQ /CS0 /CS1* DQ46 DQ47 VDDQ DQ52 DQ53 A13,FETEN* DQ54 DQ55 VDDQ DQ60 DQ61 DQ62 DQ63 VDDQ VDDSPD
These used this module used other module 184pin DIMM family
Rev. June 2004
HYMD264G726D(L)F4N-D43/J
FUNCTIONAL BLOCK DIAGRAM
/RS0 DQS0
I/O0 I/O1 I/O2 I/O3
DM0/DQS9
I/O0 I/O1 I/O2 I/O3
DQS1
DQ10 DQ11 I/O0 I/O1 I/O2 I/O3
DM1/DQS10
DQ12 DQ13 DQ14 DQ15
I/O0 I/O1 I/O2 I/O3
DQS2
DQ16 DQ17 DQ18 DQ19 I/O0 I/O1 I/O2 I/O3
DM2/DQS11
DQ20 DQ21 DQ22 DQ23
I/O0 I/O1 I/O2 I/O3
DQS3
DQ24 DQ25 DQ26 DQ27 I/O0 I/O1 I/O2 I/O3
DM3/DQS12
DQ28 DQ29 DQ30 DQ31
I/O0 I/O1 I/O2 I/O3
DQS4
DQ32 DQ33 DQ34 DQ35 I/O0 I/O1 I/O2 I/O3
DM4/DQS13
DQ36 DQ37 DQ38 DQ39
I/O0 I/O1 I/O2 I/O3
DQS5
DQ40 DQ41 DQ42 DQ43 I/O0 I/O1 I/O2 I/O3
DM5/DQS14
DQ44 DQ45 DQ46 DQ47
I/O0 I/O1 I/O2 I/O3
DQS6
DQ48 DQ49 DQ50 DQ51 I/O0 I/O1 I/O2 I/O3
DM6/DQS15
DQ52 DQ53 DQ54 DQ55
VDDSPD
Serial DO-D8 DO-D8 DO-D8
I/O0 I/O1 I/O2 I/O3
VDDQ
VREF
DQS7
DQ56 DQ57 DQ58 DQ59 I/O0 I/O1 I/O2 I/O3
DM7/DQS16
DQ60 DQ61 DQ62 DQ63
I/O0 I/O1 I/O2 I/O3
DO-D8
Strap:see Note
VDDID
DQS8
I/O0 I/O1 I/O2 I/O3
DM8/DQS17
Serial
I/O0 I/O1 I/O2 I/O3
SA1SA2
BA0-BA1
A0-A13 /RAS /CAS
/PCK
/RS->/CS SDRAMs D0-D17 RBA0-RBA1-> BA0->BA1 SDRAMs D0-D17
RA0-RA13-> A0->A13 SDRAMs D0-D17 /RRAS->/RAS SDRAMs D0-D17 /RCAS->/CAS SDRAMs D0-D17 RCKEA->CKE SDRAMs D0-D17 /RWE->WE SDRAMs D0-D17
Note DQ-to-I/O wiring changed within byte. DQ/DQS/DM/CKE/S relationships must maintained shown. DQ/DQS resistors should Ohms. DDID strap connections (for memory device STRAP (OPEN) STRAP Address control resistors should Ohms.
/RESET
CKO, /CKO-PLL* Wire Clock Loading Table /Wiring Diagram
Rev. June 2004
HYMD264G726D(L)F4N-D43/J
ABSOLUTE MAXIMUM RATINGS
Parameter Operating Temperature (Ambient) Storage Temperature Voltage relative Voltage relative Voltage VDDQ relative Output Short Circuit Current Power Dissipation Soldering Temperature Time TSTG VIN, VOUT VDDQ TSOLDER Symbol -0.5 -0.5 -0.5 Components Rating
Unit
Note Operation above absolute maximum rating adversely affect device reliability
OPERATING CONDITIONS (TA=0 Voltage referenced VSS=
Parameter Power Supply Voltage Power Supply Voltage Power Supply Voltage Power Supply Voltage Input High Voltage Input Voltage Termination Voltage Reference Voltage VDDQ VDDQ VREF Symbol VREF 0.15 -0.3 VREF 0.04 0.49*VDDQ Typ. VREF 0.5*VDDQ VDDQ VREF 0.15 VREF 0.04 0.51*VDDQ Unit Note
Note VDDQ must exceed level VDD. (min) acceptable -1.5V pulse width with duration. value VREF approximately equal 0.5VDDQ. DDR400, VDD=2.6V 0.1V, VDDQ=2.6V+/-0.1V
OPERATING CONDITIONS (TA=0 Voltage referenced
Parameter Input High (Logic Voltage, signals Input (Logic Voltage, signals Input Differential Voltage, inputs Input Crossing Point Voltage, inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.5*VDDQ-0.2 VREF 0.31 VREF 0.31 VDDQ 0.5*VDDQ+0.2 Unit Note
Note magnitude difference between input level input /CK. value expected equal 0.5*V transmitting device must track variations level same. Rev. June 2004
HYMD264G726D(L)F4N-D43/J
OPERATING TEST CONDITIONS (TA=0 70oC, Voltage referenced
Parameter Reference Voltage Termination Voltage Input High Level Voltage (VIH, min) Input Level Voltage (VIL, max) Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Input Signal maximum peak swing Input minimum Signal Slew Rate Termination Resistor (RT) Series Resistor (RS) Output Load Capacitance Access Time Measurement (CL) Value VDDQ VDDQ VREF 0.31 VREF 0.31 VREF Unit V/ns
Rev. June 2004
HYMD264G726D(L)F4N-D43/J
CAPACITANCE (TA=25oC, f=100MHz
Parameter Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance Data Input Output Capacitance Data Input Output Capacitance A12, BA0, /RAS, /CAS, CKE0, CKE1 CS0, CK0, /CK0 DQ63, DQS0 DQS8 Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIO1 CIO2 Unit
Note min. max., VDDQ 2.3V 2.7V, VODC VDDQ/2, VOpeak-to-peak 0.2V Pins under test tied GND. These values guaranteed design tested sample basis only.
OUTPUT LOAD CIRCUIT
RT=50
Output
Zo=50 VREF
CL=30pF
Rev. June 2004
HYMD264G726D(L)F4N-D43/J
CHARACTERISTICS (TA=0 Voltage referenced
Parameter Input Leakage Current
Add, CMD, /CS, /CKE
Symbol
Min. 0.76
0.76
Unit
Note -15.2mA +15.2mA
Output Leakage Current Output High Voltage Output Voltage
Note 3.6V, other pins tested under DOUT disabled, VOUT=0 2.7V
Rev. June 2004
HYMD264G726D(L)F4N-D43/J
CHARACTERISTICS (TA=0 70oC, Voltage referenced
Parameter Symbol Test Condition
bank; Active Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM inputs changing twice clock cycle address control inputs changing once clock cycle bank; Active Read Precharge; Burst Length tRC=tRC(min); tCK=tCK(min); address control inputs changing once clock cycle banks idle; Power down mode; CKE=Low, tCK= tCK(min) /CS=High, banks idle; tCK=tCK(min); CKE= High; address control inputs changing once clock cycle. VIN=VREF bank active Power down mode; CKE=Low, tCK=tCK(min) /CS=HIGH; CKE=HIGH; bank; ActivePrecharge; tRC=tRAS(max); tCK=tCK(min); inputs changing twice clock cycle; Address other control inputs changing once clock cycle Burst=2; Reads; Continuous burst; bank active; Address control inputs changing once clock cycle; tCK=tCK(min); IOUT=0mA Burst=2; Writes; Continuous burst; bank active; Address control inputs changing once clock cycle; tCK=tCK(min); inputs changing twice clock cycle tRC=tRFC(min) 8*tCK DDR200 100Mhz, 10*tCK DDR266A DDR266B 133Mhz; distributed refresh CKE=<0.2V; External clock =tCK(min) Normal Power Sort J(DDR333@CL=2.5), D43(DDR400@CL=3)
Speed -D43
Unit
Note
Operating Current
IDD0
2270
2090
Operating Current
IDD1
2450
2450
Precharge Power Down Standby Current Idle Standby Current Active Power Down Standby Current
IDD2P
IDD2F
1730
1550
IDD3P
Active Standby Current
IDD3N
1550
1460
Operating Current
IDD4R
3530
3350
Operating Current
IDD4W
3530
3350
Auto Refresh Current
IDD5
3050
3050
Self Refresh Current Operating Current Four Bank Operation
IDD6
5150
4970
IDD7
Four bank interleaving with BL=4 Refer following page detailed test condition
Rev. June 2004
HYMD264G726D(L)F4N-D43/J
CHARACTERISTICS operating conditions unless otherwise noted)
Sort J(DDR333@CL=2.5), D43(DDR400@CL=3) -D43 Parameter Cycle Time Auto Refresh Cycle Time Active Time Active Read with Auto Precharge Delay Address Column Address Delay Active Active Delay Column Address Column Address Delay Precharge Time Write Recovery Time Write Read Command Delay Auto Precharge Write Recovery Precharge Time Symbol tRFC tRAS tRAP tRCD tRRD tCCD tWTR tDAL tRCD tRPmin (tWR/tCK) (tRP/tCK) 0.45 0.45 -0.65 -0.55 -tQHS (tCL,tCH) 0.55 0.55 0.65 0.55 tAC(Max) tAC(min) tAC(Max) -tQHS (tCL,tCH) -0.7 -0.7 0.75 0.75 (tWR/tCK) (tRP/tCK) 0.45 0.45 -0.7 -0.6 0.55 0.55 2,3,5,6 2,3,5,6 2,4,5,6 2,4,5,6
Unit Note
System Clock Cycle Time Clock High Level Width Clock Level Width Data-Out edge Clock edge Skew DQS-Out edge Clock edge Skew
tDQSCK tDQSQ tQHS
DQS-Out edge Data-Out edge Skew Data-Out hold time from Clock Half Period Data Hold Skew Factor Data-out high-impedance window from Data-out low-impedance window from Input Setup Time (fast slew rate) Input Hold Time (fast slew rate) Input Setup Time (slow slew rate) Input Hold Time (slow slew rate)
Rev. June 2004
HYMD264G726D(L)F4N-D43/J
CHARACTERISTICS operating conditions unless otherwise noted)
-D43 Parameter Input Pulse Width Write High Level Width Write Level Width Clock First Rising edge DQS-In falling edge setup time falling edge hold time from Data-In Setup Time DQS-In Data-in Hold Time DQS-In Input Pulse Width Read Preamble Time Read Postamble Time Write Preamble Setup Time Write Preamble Hold Time Write Postamble Time Mode Register Delay Exit self refresh non-READ command Exit self refresh READ command Average Periodic Refresh Interval Symbol tIPW tDQSH tDQSL tDQSS tDSS tDSH tDIPW tRPRE tRPST tWPRES tWPREH tWPST tMRD tXSNR tXSRD tREFI 0.35 0.35 0.72 0.25 1.28 0.35 0.35 0.75 0.45 0.45 1.75 0.25 1.25 6,7,11~13 Sort J(DDR333@CL=2.5), D43(DDR400@CL=3)
Unit Note
continued
Note This calculation accounts tDQSQ(max), pulse width distortion on-chip circuit jitter. Data sampled rising edges clock A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE. command/address input slew rate >=1.0V/ns command/address input slew rate >=0.5V/ns <1.0V/ns This derating table used increase tIS/tIH case where input slew-rate below 0.5V/ns. Input Setup Hold Slew-rate Derating Table. Input Setup Hold Slew-rate V/ns slew rates >=1.0V/ns These parameters quarantee device timing, they necessarily tested each device, they quaranteed design tester correlation. Data latched both rising falling edges Data Strobes(LDQS/UDQS) LDM/UDM. Delta +100 Delta
Rev. June 2004
HYMD264G726D(L)F4N-D43/J
Minimum cycles stable input clocks after Self Refresh Exit command, where held high, required complete Self Refresh Exit lock internal circuit SDRAM. (tCL, tCH) refers smaller actual clock time actual clock high time provided device (i.e. this value greater than minimum specification limits tCH). minimum half clock period given cycle defined clock high clock (tCH, tCL). tQHS consists tDQSQmax, pulse width distortion on-chip clock circuits, data skew output pattern effects p-channel n-channel variation output drivers.
This derating table used increase tDS/tDH case where input slew-rate below 0.5V/ns. Input Setup Hold Slew-rate Derating Table. Input Setup Hold Slew-rate V/ns Delta +150 Delta +150
Setup/Hold Plateau Derating. This derating table used increase tDS/tDH case where input level flat below VREF +/-310mV duration 2ns. Input Level +280 Delta Delta
Setup/Hold Delta Inverse Slew Rate Derating. This derating table used increase tDS/tDH case where slew rates differ. Delta Inverse Slew Rate calculated (1/SlewRate1)-(1/SlewRate2). example, slew rate 1=0.5V/ns Slew Rate2 0.4V/n then Delta Inverse Slew Rate -0.5ns/V. (1/SlewRate1)-(1/SlewRate2) ns/V +/-0.25 Delta +100 Delta +100
DQS, input slew rate specified prevent double clocking data preserve setup hold times. Signal transi tions through region must monotonic. tDAL (tDPL (tRP each terms above, already integer, round next highest integer. equal actual system clock cycle time. Example: DDR266B CL=2.5 tDAL (2.00) (2.67) Round each non-integer next highest integer: (3), tDAL clock parts which internal lockout circuit, Active Read with Auto precharge delay should tRAS BL/2 tCK. transitions occur same access time windows valid data trasitions. These parameters referenced specific voltage level specify when device output longer driving (HZ), begins driving (LZ).
Rev. June 2004
HYMD264G726D(L)F4N-D43/J
SIMPLIFIED COMMAND TRUTH TABLE
Command Extended Mode Register Mode Register Device Deselect Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self Refresh Exit CKEn-1 CKEn /RAS /CAS
ADDR
A10/ code code
Note
Entry Precharge Power Down Mode Exit
Active Power Down Mode
Entry Exit
H=Logic High Level, L=Logic Level, X=Don't Care, V=Valid Data Input, Code=Operand Code, NOP=No Operation Note states Don't Care. Refer below Write Mask Truth Table. Code(Operand Code) consists A0~A12 BA0~BA1 used Mode Registering duing Extended MRS. Before entering Mode Register mode, banks must precharge state command issued after period from Prechagre command. Read with Autoprecharge command detected memory component CK(n), then there will command presented activated bank until CK(n+BL/2+tRP). Write with Autoprecharge command detected memory component CK(n), then there will command presented activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In Prechage delay(tDPL) which also called Write Recovery Time (tWR) needed guarantee that last data been completely written. A10/AP High when Precharge command being issued, BA0/BA1 ignored banks selected precharged.
Rev. June 2004
HYMD264G726D(L)F4N-D43/J
PACKAGE DIMENSIONS
Front
133.35 5.25
131.35 5.171
128.95
Register
(2X)4.00 0.157
5.077
28.575
1.125
2.50 0.098
0.118
Back
3.99 0.157max
1.27+/-0.10 0.05+/-0.004
Note) dimension typical unless otherwise stated.
Millimeters Inches
Rev. June 2004
4.00 0.157
Register
17.80 0.700
Side
SERIAL PRESENCE DETECT
SPECIFICATION
(64Mx72 Registered DIMM)
Rev. June 2004
HYMD264G726D(L)F4N-D43/J
SERIAL PRESENCE DETECT
Byte# 36~40 46~61 Function Description Number Bytes written into serial memory module manufacturer Total number Bytes device Fundamental memory type Number address this assembly Number column address this assembly Number physical banks DIMM Module data width Module data width (continued) Module voltage Interface levels(VDDQ) SDRAM cycle time Latency=2.5(tCK) SDRAM access time from clock CL=2.5 (tAC) Module configuration type Refresh rate type Primary SDRAM width Error checking SDRAM data width Minimum clock delay back-to-back random column address(tCCD) Burst lengths supported Number banks each SDRAM latency supported latency latency SDRAM module attributes SDRAM device attributes General SDRAM cycle time CL=2.0(tCK) SDRAM access time from clock CL=2.0(tAC) SDRAM cycle time CL=1.5(tCK), 2.0(tCK) SDRAM access time from clock CL=1.5(tAC) Minimum precharge time(tRP) Minimum activate active delay(tRRD) Minimum delay(tRCD) Minimum active precharge time(tRAS) Module density Command address signal input setup time(tIS) Command address signal input hold time(tIH) Data signal input setup time(tDS) Data signal input hold time(tDH) Reserved VCSDRAM Minimum active auto-refresh time tRC) Minimum auto-refresh active/auto-refresh command period(tRFC) Maximum cycle time (tCK max) Maximim DQS-DQ skew time(tDQSQ) Maximum read data hold skew factor(tQHS) Superset information(may used future) Revision code Checksum Bytes 0~62 55ns 70ns 10ns 0.4ns 0.5ns Undefined Initial release 0.60ns 0.60ns 0.40ns 0.40ns Undefined 60ns 72ns 12ns 7.5ns +/-0.75ns 15ns 10ns 15ns 40ns 512MB 0.75ns 0.75ns 0.45ns 0.45ns 2.5, Registered, +/-0.2Voltage tolerance, Concurrent Auto Precharge tRAS Lock 6.0ns +/-0.7ns 18ns 12ns 18ns 42ns 7.5ns 5.0ns +/-0.7ns 7.8us Self refresh 2,4,8 Banks
Sort J(DDR333@CL=2.5), D43(DDR400@CL=3) Function Supported -D43
Bytes Bytes SDRAM 1Bank Bits SSTL 2.5V 6.0ns
Hexa Value -D43
Note
Rev. June 2004
HYMD264G726D(L)F4N-D43/J
SERIAL PRESENCE DETECT
Byte# 65~71 Function Description Manufacturer JEDEC Code Manufacturer JEDEC Code
Sort J(DDR333@CL=2.5), D43(DDR400@CL=3) Function Supported -D43
Hynix(Korea Area) HSA(United States Area) HSE(Europe Area) HSJ(Japan Area) Singapore Asia Area 6(8K refresh,4Bank) Undefined Undefined
continued
Hexa Value -D43
Note
Hynix JEDEC
Manufacturing location
95~98 99~127
Manufacture part number(Hynix Memory Module) Manufacture part number(Hynix Memory Module) Manufacture part number(Hynix Memory Module) Manufacture part number (DDR SDRAM) Manufacture part number(Memory density) Manufacture part number(Module Depth) Manufacture part number(Module Depth) Manufacture part number(Module type) Manufacture part number(Data width) -Manufacture part number(Data width) Manufacture part number(Refresh, Bank.) Manufacture part number(Component Generation) Manufacture part number(Component Package Type) Manufacture part number(Component configuration) Manufacture part number(Module Revision) Manufacture part number(Minimum cycle time) Manufacture part number(Minimum cycle time) Manufacture part number(Minimum cycle time) Manufacture revision code(for Component) Manufacture revision code (for PCB) Manufacturing date(Year) Manufacturing date(Week) Module serial number Manufacturer specific data (may used future)
128~255 Open customer Note bank address excluded This value based component specification These bytes programmed code date week date year These bytes apply Hynix's Module Serial Number System These bytes undefined coded `00h' Refer Hynix Site
Byte 85~86, power part
Byte Function Description Manufacture part number(Low power part) Manufacture part number(Component configuration) Function Supported -D43 Hexa Value -D43 Note
Rev. June 2004
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