MCF5407UM/D Rev. 0.1, 11/2001 ColdFire registered trademark Digit
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MCF5407 ColdFire® Integrated Microprocessor User's Manual
MCF5407UM/D Rev. 0.1, 11/2001
ColdFire registered trademark DigitalDNA trademark Motorola, Inc. registered trademark Philips Semiconductors
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. reach USA/EUROPE/Locations Listed: Motorola Literature Distribution; P.O. 5405, Denver, Colorado 80217. 1-303-675-2140 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, King Street, Industrial Estate, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: Document Comments: (512) 895-2638, Attn: TECD Applications Engineering
Motorola Inc., 2001. rights reserved.
Overview Part MCF5407 Processor Core ColdFire Core Hardware Multiply/Accumulate (MAC) Unit Local Memory Debug Support Part System Integration Module (SIM) Overview Phase-Locked Loop (PLL) Module
Part Part Part
Interrupt Controller Chip-Select Module Synchronous/Asynchronous DRAM Controller Module Part III: Peripheral Module Controller Module Timer Module UART Modules
Parallel Port (General-Purpose I/O)
Part Hardware Interface Mechanical Data Signal Descriptions Operation IEEE 1149.1 Test Access Port (JTAG) Electrical Specifications Appendix Migration Appendix Memory Glossary Terms Abbreviations Index
Part
Part Part Part
Overview Part MCF5407 Processor Core ColdFire Core Hardware Multiply/Accumulate (MAC) Unit Local Memory Debug Support Part System Integration Module (SIM) Overview Phase-Locked Loop (PLL) Module Interrupt Controller Chip-Select Module Synchronous/Asynchronous DRAM Controller Module Part III: Peripheral Module Controller Module Timer Module UART Modules
Part
Parallel Port (General-Purpose I/O)
Part Hardware Interface Mechanical Data Signal Descriptions Operation IEEE 1149.1 Test Access Port (JTAG) Electrical Specifications Appendix Migration Appendix Memory Glossary Terms Abbreviations Index
CONTENTS
Paragraph Number Title Page Number
Chapter Overview
1.2.1 1.3.1 1.3.1.1 1.3.1.2 1.3.1.3 1.3.1.4 1.3.2 1.3.2.1 1.3.2.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 1.3.8 1.3.8.1 1.3.8.2 1.3.8.3 1.3.8.4 1.3.8.5 1.3.9 1.3.10 1.4.1 1.4.2 Features MCF5407 Features. Process ColdFire Module Description ColdFire Core Instruction Fetch Pipeline (IFP). Operand Execution Pipeline (OEP) Module. Integer Divide Module. Harvard Architecture 16-Kbyte Instruction Cache/8-Kbyte Data Cache Internal 2-Kbyte SRAMs DRAM Controller Controller. UART Modules. 1-10 Timer Module 1-11 Module 1-11 System Interface 1-11 External Interface 1-11 Chip Selects 1-11 16-Bit Parallel Port Interface 1-12 Interrupt Controller 1-12 JTAG. 1-12 System Debug Interface. 1-12 Module. 1-13 Programming Model, Addressing Modes, Instruction Set. 1-13 Programming Model 1-15 User Registers 1-15
Contents
CONTENTS
Paragraph Number 1.4.3 1.4.4 Title Page Number Supervisor Registers 1-16 Instruction 1-16
Part MCF5407 Processor Core Chapter ColdFire Core
2.1.1 2.1.2 2.1.2.1 2.1.2.1.1 2.1.2.2 2.1.2.2.1 2.1.2.2.2 2.1.2.2.3 2.1.2.3 2.1.3 2.2.1 2.2.1.1 2.2.1.2 2.2.1.3 2.2.1.4 2.2.1.5 2.2.1.6 2.2.2 2.2.2.1 2.2.2.2 2.2.2.3 2.2.2.4 2.2.2.5 2.2.2.6 2.4.1 2.4.2 2.6.1 Features Enhancements. Clock-Multiplied Microprocessor Core. Enhanced Pipelines Instruction Fetch Pipeline (IFP). Branch Acceleration Operand Execution Pipeline (OEP) Illegal Opcode Handling. Hardware Multiply/Accumulate (MAC) Unit Hardware Divide Unit. Harvard Memory Architecture Debug Module Enhancements Programming Model User Programming Model Data Registers (D0-D7) Address Registers (A0-A6) Stack Pointer (A7, Program Counter (PC) Condition Code Register (CCR) Programming Model. 2-10 Supervisor Programming Model. 2-10 Status Register (SR). 2-11 Vector Base Register (VBR) 2-12 Cache Control Register (CACR) 2-12 Access Control Registers (ACR0-ACR3). 2-12 Base Address Registers (RAMBAR0 RAMBAR1) 2-12 Module Base Address Register (MBAR) 2-12 Integer Data Formats. 2-13 Organization Data Registers. 2-13 Organization Integer Data Formats Registers 2-13 Organization Integer Data Formats Memory 2-14 Addressing Mode Summary 2-15 Instruction Summary. 2-15 Additions Instruction Architecture 2-18
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Paragraph Number 2.6.2 2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 2.8.1 2.8.2 Title Page Number 2-19 2-23 2-25 2-26 2-27 2-29 2-30 2-31 2-32 2-34 2-36
Instruction Summary Execution Timings MOVE Instruction Execution Timing Execution Timings-One-Operand Instructions Execution Timings-Two-Operand Instructions. Miscellaneous Instruction Execution Times. Branch Instruction Execution Times Exception Processing Overview Exception Stack Frame Definition. Processor Exceptions ColdFire Instruction Architecture Enhancements.
Chapter Hardware Multiply/Accumulate (MAC) Unit
3.1.0.1 3.1.0.2 3.1.0.3 3.1.0.4 Overview. Programming Model. General Operation. Instruction Summary Data Representation. Instruction Execution Timings.
Chapter Local Memory
4.4.1 4.5.1 4.8.1 4.8.2 4.9.1 4.9.1.1 4.9.1.2 4.9.1.3 Interactions between Local Memory Modules SRAM Overview SRAM Operation SRAM Programming Model. SRAM Base Address Registers (RAMBAR0/RAMBAR1). SRAM Initialization. SRAM Initialization Code Power Management Cache Overview. Cache Organization. Cache Line States: Invalid, Valid-Unmodified, Valid-Modified. Cache Start-Up. Cache Operation. 4-11 Caching Modes 4-13 Cacheable Accesses 4-14 Write-Through Mode (Data Cache Only). 4-14 Copyback Mode (Data Cache Only). 4-14
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Paragraph Number 4.9.2 4.9.3 4.9.3.1 4.9.3.2 4.9.3.3 4.9.3.4 4.9.4 4.9.5 4.9.5.1 4.9.5.2 4.9.5.2.1 4.9.5.2.2 4.9.6 4.10 4.10.1 4.10.2 4.11 4.12 4.12.1 4.12.2 4.13 Title Page Number 4-14 4-15 4-16 4-16 4-16 4-17 4-17 4-17 4-17 4-18 4-18 4-18 4-19 4-21 4-21 4-23 4-24 4-27 4-27 4-28 4-32 Cache-Inhibited Accesses Cache Protocol. Read Miss Write Miss (Data Cache Only) Read Write (Data Cache Only) Cache Coherency (Data Cache Only). Memory Accesses Cache Maintenance. Cache Filling. Cache Pushes Push Store Buffers Push Store Buffer Operation. Cache Locking Cache Registers. Cache Control Register (CACR) Access Control Registers (ACR0-ACR3). Cache Management. Cache Operation Summary Instruction Cache State Transitions Data Cache State Transitions. Cache Initialization Code.
Chapter Debug Support
5.2.1 5.3.1 5.3.2 5.3.3 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 Overview. Signal Descriptions Processor Status/Debug Data (PSTDDATA[7:0]) Real-Time Trace Support. Begin Execution Taken Branch (PST 0x5) Processor Stopped Breakpoint State Change (PST 0xE) Processor Halted (PST 0xF) Programming Model Address Attribute Trigger Registers (AATR, AATR1). 5-10 Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1) 5-12 Address Attribute Register (BAAR). 5-12 Configuration/Status Register (CSR). 5-13 Data Breakpoint/Mask Registers (DBR/DBR1, DBMR/DBMR1) 5-15 Program Counter Breakpoint/Mask Registers (PBR, PBR1, PBR2, PBR3, PBMR) 5-16 Trigger Definition Register (TDR) 5-18 Extended Trigger Definition Register (XTDR) 5-19
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Paragraph Number 5.4.9 5.5.1 5.5.2 5.5.2.1 5.5.2.2 5.5.3 5.5.3.1 5.5.3.1.1 5.5.3.2 5.5.3.3 5.5.3.3.1 5.5.3.3.2 5.5.3.3.3 5.5.3.3.4 5.5.3.3.5 5.5.3.3.6 5.5.3.3.7 5.5.3.3.8 5.5.3.3.9 5.5.3.3.10 5.5.3.3.11 5.5.3.3.12 5.5.3.3.13 5.6.1 5.6.1.1 5.6.2 5.8.1 5.8.2 Title Page Number 5-21 5-22 5-22 5-24 5-25 5-26 5-26 5-27 5-28 5-28 5-30 5-30 5-31 5-32 5-33 5-35 5-37 5-39 5-40 5-41 5-42 5-43 5-44 5-45 5-45 5-46 5-48 5-48 5-49 5-49 5-50 5-53
Resulting Possible Trigger Combinations. Background Debug Mode (BDM) Halt. Serial Interface. Receive Packet Format Transmit Packet Format. Command Set. ColdFire Command Format. Extension Words Required. Command Sequence Diagrams. Command Descriptions Read Register (RAREG/RDREG) Write Register (WAREG/WDREG). Read Memory Location (READ). Write Memory Location (WRITE) Dump Memory Block (DUMP) Fill Memory Block (FILL) Resume Execution (GO). Operation (NOP) Synchronize PSTDDATA Lines (SYNC_PC) Read Control Register (RCREG) Write Control Register (WCREG) Read Debug Module Register (RDMREG) Write Debug Module Register (WDMREG) Real-Time Debug Support Theory Operation. Emulator Mode Concurrent Processor Operation Motorola-Recommended Pinout. Debug Definition PSTDDATA Outputs. User Instruction Supervisor Instruction Set.
Part System Integration Module (SIM) Chapter Overview
6.2.1 Features Programming Model Register Memory Map.
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CONTENTS
Paragraph Number 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.2.10.1 6.2.10.1.1 6.2.10.1.2 Title Page Number Module Base Address Register (MBAR) Reset Status Register (RSR) Software Watchdog Timer. System Protection Control Register (SYPCR) Software Watchdog Interrupt Vector Register (SWIVR). Software Watchdog Service Register (SWSR). Clock Control STOP Instruction 6-10 Assignment Register (PAR) 6-10 Arbitration Control 6-11 Default Master Park Register (MPARK) 6-11 Arbitration Internally Generated Transfers (MPARK[PARK]). 6-12 Arbitration between Internal External Masters Accessing Internal Resources 6-14
Chapter Phase-Locked Loop (PLL)
7.1.1 7.2.1 7.2.2 7.2.3 7.2.4 7.4.1 7.4.2 Overview. PLL:PCLK Ratios. Operation Reset/Initialization Normal Mode. Reduced-Power Mode. Control Register (PLLCR). Port List. Timing Relationships PCLK, PSTCLK, BCLKO RSTI Timing Power Supply Filter Circuit
Chapter Module
8.4.1 8.4.2 8.4.3 8.4.4 Overview. Interface Features. System Configuration. Protocol Arbitration Procedure Clock Synchronization. Handshaking Clock Stretching Programming Model
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Paragraph Number 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 8.6.6 8.6.7 Title Page Number Address Register (IADR) Frequency Divider Register (IFDR). Control Register (I2CR) Status Register (I2SR). Data Register (I2DR) Programming Examples 8-10 Initialization Sequence. 8-10 Generation START. 8-10 Post-Transfer Software Response. 8-11 Generation STOP. 8-12 Generation Repeated START. 8-12 Slave Mode 8-13 Arbitration Lost. 8-13
Chapter Interrupt Controller
9.2.1 9.2.2 9.2.3 9.2.4 Overview. Interrupt Controller Registers Interrupt Control Registers (ICR0-ICR9) Autovector Register (AVR) Interrupt Pending Mask Registers (IPR IMR). Interrupt Port Assignment Register (IRQPAR)
Chapter Chip-Select Module
10.1 10.2 10.3 10.3.1 10.3.1.1 10.3.1.2 10.4 10.4.1 10.4.1.1 10.4.1.2 10.4.1.3 10.4.1.4 Overview. Chip-Select Module Signals Chip-Select Operation. General Chip-Select Operation. 16-, 32-Bit Port Sizing. Global Chip-Select Operation. Chip-Select Registers. Chip-Select Module Registers Chip-Select Address Registers (CSAR0-CSAR7) Chip-Select Mask Registers (CSMR0-CSMR7). Chip-Select Control Registers (CSCR0-CSCR7) Code Example. 10-1 10-1 10-2 10-3 10-4 10-4 10-5 10-6 10-6 10-7 10-8 10-9
Chapter Synchronous/Asynchronous DRAM Controller Module
Contents
CONTENTS
Paragraph Number 11.1 11.1.1 11.1.2 11.2 11.2.1 11.3 11.3.1 11.3.2 11.3.2.1 11.3.2.2 11.3.2.3 11.3.3 11.3.3.1 11.3.3.2 11.3.3.3 11.3.3.4 11.3.3.5 11.4 11.4.1 11.4.2 11.4.3 11.4.3.1 11.4.3.2 11.4.3.3 11.4.4 11.4.4.1 11.4.4.2 11.4.4.3 11.4.4.4 11.4.4.5 11.4.4.6 11.4.5 11.4.5.1 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 Title Page Number Overview. 11-1 Definitions 11-2 Block Diagram Major Components 11-2 DRAM Controller Operation 11-3 DRAM Controller Registers 11-3 Asynchronous Operation 11-4 DRAM Controller Signals Asynchronous Mode. 11-4 Asynchronous Register Set. 11-4 DRAM Control Register (DCR) Asynchronous Mode 11-4 DRAM Address Control Registers (DACR0/DACR1) 11-5 DRAM Controller Mask Registers (DMR0/DMR1) 11-7 General Asynchronous Operation Guidelines 11-8 Non-Page-Mode Operation. 11-11 Burst Page-Mode Operation 11-12 Continuous Page Mode. 11-13 Extended Data (EDO) Operation. 11-15 Refresh Operation 11-16 Synchronous Operation. 11-16 DRAM Controller Signals Synchronous Mode. 11-17 Using Edge Select (EDGESEL) 11-18 Synchronous Register 11-19 DRAM Control Register (DCR) Synchronous Mode. 11-19 DRAM Address Control Registers (DACR0/DACR1) Synchronous Mode 11-20 DRAM Controller Mask Registers (DMR0/DMR1) 11-22 General Synchronous Operation Guidelines. 11-23 Address Multiplexing 11-23 Interfacing Example. 11-27 Burst Page Mode. 11-27 Continuous Page Mode. 11-29 Auto-Refresh Operation. 11-31 Self-Refresh Operation 11-32 Initialization Sequence. 11-32 Mode Register Settings. 11-33 SDRAM Example 11-34 SDRAM Interface Configuration. 11-34 Initialization. 11-35 DACR Initialization. 11-35 Initialization. 11-37 Mode Register Initialization 11-38 Initialization Code. 11-39
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Paragraph Number Title Page Number
Part Peripheral Module Chapter Controller Module
12.1 12.1.1 12.2 12.3 12.4 12.4.1 12.4.2 12.4.3 12.4.4 12.4.5 12.4.6 12.5 12.5.1 12.5.2 12.5.2.1 12.5.2.2 12.5.3 12.5.3.1 12.5.3.2 12.5.4 12.5.4.1 12.5.4.2 12.5.4.3 12.5.5 Overview. 12-1 Module Features 12-2 Signal Description 12-2 Transfer Overview. 12-4 Controller Module Programming Model. 12-5 Source Address Registers (SAR0-SAR3) 12-7 Destination Address Registers (DAR0-DAR3) 12-7 Byte Count Registers (BCR0-BCR3). 12-7 Control Registers (DCR0-DCR3). 12-8 Status Registers (DSR0-DSR3) 12-10 Interrupt Vector Registers (DIVR0-DIVR3) 12-11 Controller Module Functional Description. 12-11 Transfer Requests (Cycle-Steal Continuous Modes) 12-12 Data Transfer Modes 12-12 Dual-Address Transfers 12-12 Single-Address Transfers. 12-13 Channel Initialization Startup 12-13 Channel Prioritization 12-13 Programming Controller Module 12-13 Data Transfer 12-14 External Request Acknowledge Operation 12-14 Auto-Alignment 12-17 Bandwidth Control. 12-18 Termination. 12-18
Chapter Timer Module
13.1 13.1.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 Overview. Features General-Purpose Timer Units General-Purpose Timer Programming Model Timer Mode Registers (TMR0/TMR1) Timer Reference Registers (TRR0/TRR1) Timer Capture Registers (TCR0/TCR1). Timer Counters (TCN0/TCN1) 13-1 13-2 13-2 13-2 13-3 13-4 13-4 13-5
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Paragraph Number 13.3.5 13.4 13.5 Title Page Number Timer Event Registers (TER0/TER1). 13-5 Code Example. 13-6 Calculating Time-Out Values 13-7
Chapter UART Modules
14.1 14.2 14.3 14.3.1 14.3.2 14.3.3 14.3.4 14.3.5 14.3.6 14.3.7 14.3.8 14.3.9 14.3.10 14.3.11 14.3.12 14.3.13 14.3.14 14.3.15 14.3.16 14.3.17 14.3.18 14.3.19 14.4 14.5 14.5.1 14.5.1.1 14.5.1.2 14.5.1.2.1 14.5.1.2.2 14.5.2 14.5.2.1 14.5.2.2 14.5.2.2.1 14.5.2.3 14.5.2.4 Overview. 14-1 Serial Module Overview 14-2 Register Descriptions 14-3 UART Mode Registers (UMR1n). 14-5 UART Mode Register (UMR2n) 14-7 FIFO Threshold Register (RXLVL). 14-8 Modem Control Register (MODCTL). 14-9 FIFO Threshold Register (TXLVL) 14-10 UART Status Registers (USRn) 14-10 UART Clock-Select Registers (UCSRn). 14-12 Receive Samples Available Register (RSMP). 14-12 Transmit Space Available Register (TSPC) 14-13 UART Command Registers (UCRn) 14-13 UART Receiver Buffers (URBn) 14-15 UART Transmitter Buffers (UTBn) 14-16 UART Input Port Change Registers (UIPCRn). 14-17 UART Auxiliary Control Register (UACRn). 14-17 UART Interrupt Status/Mask Registers (UISRn/UIMRn). 14-18 UART Divider Upper/Lower Registers (UDUn/UDLn) 14-19 UART Interrupt Vector Register (UIVRn). 14-20 UART Input Port Register (UIPn) 14-20 UART Output Port Data Registers (UOP1n/UOP0n). 14-21 UART Module Signal Definitions 14-21 Operation. 14-23 Transmitter/Receiver Clock Source. 14-23 Programmable Divider. 14-24 Calculating Baud Rates. 14-24 CLKIN Baud Rates. 14-24 External Clock 14-25 Transmitter Receiver Operating Modes. 14-25 Transmitting UART Mode 14-26 Transmitter Modem Mode (UART1) 14-27 Low-Power Mode 14-29 Receiver 14-29 UART1 UART Mode 14-31
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Paragraph Number 14.5.2.4.1 14.5.2.5 14.5.2.6 14.5.3 14.5.3.1 14.5.3.2 14.5.3.3 14.5.4 14.5.5 14.5.5.1 14.5.5.2 14.5.5.3 14.5.6 14.5.6.1 Title Page Number 14-31 14-32 14-33 14-34 14-34 14-34 14-35 14-35 14-37 14-37 14-37 14-37 14-37 14-38
Receiver Modem Mode (UART1). FIFO Stack UART0. FIFOs UART1 Looping Modes Automatic Echo Mode Local Loop-Back Mode Remote Loop-Back Mode. Multidrop Mode. Operation Read Cycles Write Cycles Interrupt Acknowledge Cycles Programming UART Module Initialization Sequence
Chapter Parallel Port (General-Purpose I/O)
15.1 15.1.1 15.1.2 15.1.3 15.1.4 Parallel Port Operation. Assignment Register (PAR) Port Data Direction Register (PADDR). Port Data Register (PADAT) Code Example. 15-1 15-1 15-2 15-2 15-4
Part Hardware Interface Chapter Mechanical Data
16.1 16.2 16.3 16.4 Package Pinout Mechanical Diagram. Case Drawing. 16-1 16-1 16-8 16-9
Chapter Signal Descriptions
17.1 17.2 17.2.1 Overview. 17-1 MCF5407 Signals 17-7 Address 17-7
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Paragraph Number 17.2.1.1 17.2.1.2 17.2.2 17.2.3 17.2.4 17.2.5 17.2.6 17.2.7 17.2.8 17.2.9 17.2.10 17.3 17.3.1 17.4 17.4.1 17.4.2 17.4.3 17.5 17.5.1 17.5.2 17.5.3 17.5.4 17.5.5 17.5.5.1 17.5.5.2 17.5.5.3 17.5.5.4 17.5.6 17.5.6.1 17.6 17.6.1 17.6.2 17.6.3 17.7 17.7.1 17.7.2 17.7.3 17.7.4 17.7.5 17.7.6 17.7.7 17.8 17.8.1
Title
Page Number
Address (A[23:0]). 17-7 Address (A[31:24]/PP[15:8]) 17-7 Data (D[31:0]) 17-8 Read/Write (R/W). 17-8 Size (SIZ[1:0]) 17-8 Transfer Start (TS) 17-9 Address Strobe (AS) 17-9 Transfer Acknowledge (TA) 17-9 Transfer Progress (TIP/PP7). 17-10 Transfer Type (TT[1:0]/PP[1:0]) 17-10 Transfer Modifier (TM[2:0]/PP[4:2]/DACK[1:0]). 17-10 Interrupt Control Signals. 17-12 Interrupt Request (IRQ1/IRQ2, IRQ3/IRQ6, IRQ5/IRQ4, IRQ7). 17-12 Arbitration Signals. 17-12 Request (BR) 17-12 Grant (BG). 17-12 Driven (BD). 17-13 Clock Reset Signals. 17-13 Reset (RSTI). 17-13 Clock Input (CLKIN). 17-13 Clock Output (BCLKO) 17-13 Reset (RSTO). 17-13 Data/Configuration Pins (D[7:0]) 17-14 D[7:5,3]-Boot Chip-Select (CS0) Configuration 17-14 D7-Auto Acknowledge Configuration (AA_CONFIG) 17-14 D[6:5]-Port Size Configuration (PS_CONFIG[1:0]) 17-14 D3-Byte-Enable Configuration (BE_CONFIG) 17-15 D4-Address Configuration (ADDR_CONFIG) 17-15 D[2:0]-Divide Control (DIVIDE[2:0]) 17-15 Chip-Select Module Signals 17-15 Chip-Select (CS[7:0]) 17-15 Byte Enables/Byte Write Enables (BE[3:0]/BWE[3:0]) 17-16 Output Enable (OE) 17-16 DRAM Controller Signals 17-16 Address Strobes (RAS[1:0]). 17-16 Column Address Strobes (CAS[3:0]) 17-16 DRAM Write (DRAMW). 17-16 Synchronous DRAM Column Address Strobe (SCAS) 17-17 Synchronous DRAM Address Strobe (SRAS). 17-17 Synchronous DRAM Clock Enable (SCKE) 17-17 Synchronous Edge Select (EDGESEL) 17-17 Controller Module Signals. 17-17 Request (DREQ[1:0]/PP[6:5]). 17-17
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Paragraph Number 17.8.2 17.9 17.9.1 17.9.2 17.9.3 17.9.4 17.10 17.10.1 17.10.2 17.11 17.12 17.12.1 17.12.2 17.13 17.13.1 17.13.2 17.13.3 17.13.4 17.14 17.14.1 17.14.2 17.14.3 17.14.4 17.14.5 Title Page Number 17-18 17-18 17-18 17-19 17-19 17-19 17-19 17-19 17-19 17-19 17-20 17-20 17-20 17-20 17-20 17-20 17-20 17-21 17-21 17-21 17-21 17-22 17-22 17-22
Transfer Modifier/DMA Acknowledge (TM[2:0]/DACK[1:0]) Serial Module Signals Transmitter Serial Data Output (TxD). Receiver Serial Data Input (RxD). Clear Send (CTS). Request Send (RTS) Timer Module Signals. Timer Inputs (TIN[1:0]). Timer Outputs (TOUT1, TOUT0) Parallel Port (PP[15:0]) Module Signals. Serial Clock (SCL) Serial Data (SDA) Debug Test Signals Test Mode (MTMOD[3:0]) High Impedance (HIZ). Processor Clock Output (PSTCLK). Processor Status Debug Data (PSTDDATA[7:0]). Debug Module/JTAG Signals. Test Reset/Development Serial Clock (TRST/DSCLK) Test Mode Select/Breakpoint (TMS/BKPT) Test Data Input/Development Serial Input (TDI/DSI) Test Data Output/Development Serial Output (TDO/DSO). Test Clock (TCK)
Chapter Operation
18.1 18.2 18.3 18.4 18.4.1 18.4.2 18.4.3 18.4.4 18.4.5 18.4.6 18.4.7 18.4.7.1 18.4.7.2 18.4.7.3 Features 18-1 Control Signals. 18-1 Characteristics. 18-2 Data Transfer Operation 18-2 Cycle Execution. 18-4 Data Transfer Cycle States 18-5 Read Cycle. 18-7 Write Cycle 18-8 Fast-Termination Cycles. 18-9 Back-to-Back Cycles 18-10 Burst Cycles. 18-11 Line Transfers 18-12 Line Read Cycles. 18-12 Line Write Cycles. 18-14
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Paragraph Number 18.4.7.4 18.5 18.6 18.7 18.7.1 18.7.2 18.8 18.8.1 18.9 18.9.1 18.9.2 18.10 18.10.1 18.10.2 Title Page Number 18-15 18-16 18-17 18-17 18-18 18-19 18-20 18-21 18-21 18-25 18-29 18-33 18-34 18-35 Transfers Using Mixed Port Sizes Misaligned Operands Errors Interrupt Exceptions. Level Interrupts. Interrupt-Acknowledge Cycle. Arbitration. Arbitration Signals. General Operation External Master Transfers. Two-Device Arbitration Protocol (Two-Wire Mode) Multiple External Device Arbitration Protocol (Three-Wire Mode). Reset Operation. Master Reset Software Watchdog Reset.
Chapter IEEE 1149.1 Test Access Port (JTAG)
19.1 19.2 19.3 19.4 19.4.1 19.4.2 19.4.3 19.4.4 19.5 19.6 19.7 Overview. 19-1 JTAG Signal Descriptions 19-2 Controller. 19-3 JTAG Register Descriptions 19-4 JTAG Instruction Shift Register 19-5 IDCODE Register 19-6 JTAG Boundary-Scan Register 19-7 JTAG Bypass Register. 19-10 Restrictions 19-10 Disabling IEEE Standard 1149.1 Operation 19-10 Obtaining IEEE Standard 1149.1. 19-11
Chapter Electrical Specifications
20.1 20.1.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 General Parameters 20-1 Supply Voltage Sequencing Separation Cautions. 20-3 Clock Timing Specifications. 20-4 Input/Output Timing Specifications. 20-6 Reset Timing Specifications 20-15 Debug Timing Specifications. 20-16 Timer Module Timing Specifications 20-17 Input/Output Timing Specifications. 20-18 UART Module Timing Specifications 20-19
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Paragraph Number 20.9 20.10 20.11 Title Page Number
Parallel Port (General-Purpose I/O) Timing Specifications 20-22 Timing Specifications. 20-23 IEEE 1149.1 (JTAG) Timing Specifications 20-24
Appendix Migrating from ColdFire MCF5307 MCF5407
A.6.1 A.6.2 A.8.1 A.8.2 A.8.2.1 A.8.3 A.8.3.1 A.8.3.2 A.8.3.3 A.8.3.4 A.8.3.5 A.8.4 A.8.5 A.8.6 A.10 A.11 Overview. Instruction Additions Enhanced Memories. On-Chip Modifications. UART Enhancements Timing Differences Phase-Locked Loop (PLL). Timing Relationships. Reset Initialization Modifications. Revision Debug A-10 Debug Interrupts Interrupt Requests Emulator Mode A-10 On-Chip Breakpoint Registers. A-12 Write Debug Module Register (wdmreg) A-12 Debug Programming Model A-14 Address Breakpoint Registers (ABLR1, ABHR1) A-14 Address Attribute Breakpoint Register (AATR1) A-14 Program Counter Breakpoint Registers (PBR1-PBR3) A-14 Data Breakpoint Register (DBR1, DBMR1) A-15 Extended Trigger Definition Register (XTDR) A-15 Debug Interrupt Exception Vectors A-15 Processor Status Debug Data Output Signals A-16 Debug Summary. A-17 Voltage Input Changes. A-17 Power Supply Filter Circuit A-18 Pin-Assignment Compatibility. A-18
Appendix List Memory Maps
Contents
CONTENTS
Paragraph Number Title Page Number
MCF5407 User's Manual
ILLUSTRATIONS
Figure Number Title Page Number
4-10 4-11 4-12 4-13 4-14
MCF5407 Block Diagram. UART Module Block Diagram. 1-10 Module 1-13 ColdFire MCF5407 Programming Model 1-15 ColdFire Enhanced Pipeline ColdFire Multiply-Accumulate Functionality Diagram ColdFire Programming Model. Condition Code Register (CCR) Status Register (SR). 2-11 Vector Base Register (VBR). 2-12 Organization Integer Data Formats Data Registers. 2-13 Organization Integer Data Formats Address Registers 2-14 Memory Operand Addressing. 2-14 Exception Stack Frame Form. 2-33 ColdFire Multiplication Accumulation. Programming Model SRAM Base Address Registers (RAMBARn) Data Cache Organization Data Cache Organization Line Format Data Cache-A: Reset, after Invalidation, Loading Pattern. 4-10 Data Caching Operation. 4-11 Write-Miss Copyback Mode. 4-16 Data Cache Locking. 4-20 Cache Control Register (CACR) 4-21 Access Control Register Format (ACRn) 4-24 Format (Data Cache). 4-25 Format (Instruction Cache) 4-25 Instruction Cache Line State Diagram. 4-27 Data Cache Line State Diagram-Copyback Mode 4-28 Data Cache Line State Diagram-Write-Through Mode 4-29 Processor/Debug Module Interface. PSTCLK Timing. PSTDDATA: Single-Cycle Instruction Timing. Example Instruction Output PSTDDATA. Debug Programming Model Address Attribute Trigger Registers (AATR, AATR1). 5-11
Illustrations
ILLUSTRATIONS
Figure Page Title Number Number Address Breakpoint Registers (ABLR, ABHR, ABLR1, ABHR1). 5-12 Address Attribute Register (BAAR). 5-13 Configuration/Status Register (CSR). 5-13 5-10 Data Breakpoint/Mask Registers (DBR/DBR1 DBMR/DBMR1). 5-16 5-11 Program Counter Breakpoint Registers (PBR, PBR1, PBR2, PBR3) 5-17 5-12 Program Counter Breakpoint Mask Register (PBMR) 5-17 5-13 Trigger Definition Register (TDR) 5-18 5-14 Extended Trigger Definition Register (XTDR) 5-20 5-15 Serial Interface Timing 5-24 5-16 Receive Packet. 5-25 5-17 Transmit Packet 5-26 5-18 Command Format 5-27 5-19 Command Sequence Diagram. 5-29 RAREG/RDREG Command Sequence. 5-30 5-21 RAREG/RDREG Command Format 5-30 5-20 WAREG/WDREG Command Sequence 5-31 5-23 WAREG/WDREG Command Format. 5-31 5-22 READ Command Sequence. 5-32 5-25 5-24 read Command/Result Formats. 5-32 WRITE Command Format 5-33 5-26 WRITE Command Sequence 5-34 5-27 DUMP Command/Result Formats 5-35 5-28 DUMP Command Sequence 5-36 5-29 FILL Command Format. 5-37 5-30 FILL Command Sequence. 5-38 5-31 Command Sequence. 5-39 5-33 Command Format. 5-39 5-32 Command Sequence 5-40 5-35 Command Format. 5-40 5-34 SYNC_PC Command Sequence 5-41 5-37 SYNC_PC Command Format. 5-41 5-36 RCREG Command Sequence. 5-42 5-39 RCREG Command/Result Formats. 5-42 5-38 WCREG Command Sequence 5-43 5-41 WCREG Command/Result Formats. 5-43 5-40 RDMREG Command Sequence. 5-44 5-43 RDMREG Command/Result Formats. 5-44 5-42 WDMREG Command Sequence 5-45 5-45 WDMREG Command Format. 5-45 5-44 5-46 Recommended Connector. 5-49 Block Diagram. Module Base Address Register (MBAR) Reset Status Register (RSR)
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Figure Number 6-10 6-11 6-12 6-13 8-10 10-1 10-2 10-3 10-4 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 Title Page Number
MCF5407 Embedded System Recovery from Unterminated Access. System Protection Control Register (SYPCR) Software Watchdog Interrupt Vector Register (SWIVR). Software Watchdog Service Register (SWSR). Assignment Register (PAR) 6-10 Default Master Register (MPARK) 6-11 Round Robin Arbitration (PARK 00). 6-12 Park Master Core Priority (PARK 6-13 Park Module Priority (PARK 10). 6-13 Park Current Master Priority (PARK 6-14 Module Block Diagram Control Register (PLLCR). CLKIN, PCLK, PSTCLK, BCLKO Timing Reset Initialization Timing. Power Supply Filter Circuit Module Block Diagram Standard Communication Protocol Repeated START Synchronized Clock SCL. Address Register (IADR) Frequency Divider Register (IFDR). Control Register (I2CR) I2CR Status Register (I2SR) Data Register (I2DR) 8-10 Flow-Chart Typical Interrupt Routine. 8-14 Interrupt Controller Block Diagram. Interrupt Control Registers (ICR0-ICR9) Autovector Register (AVR) Interrupt Pending Register (IPR) Interrupt Mask Register (IMR) Interrupt Port Assignment Register (IRQPAR) Connections External Memory Port Sizes 10-4 Chip Select Address Registers (CSAR0-CSAR7) 10-6 Chip Select Mask Registers (CSMRn) 10-7 Chip-Select Control Registers (CSCR0-CSCR7) 10-8 Asynchronous/Synchronous DRAM Controller Block Diagram 11-2 DRAM Control Register (DCR) (Asynchronous Mode) 11-5 DRAM Address Control Registers (DACR0/DACR1). 11-6 DRAM Controller Mask Registers (DMR0 DMR1). 11-7 Basic Non-Page-Mode Operation RNCN (4-4-4-4) 11-11 Basic Non-Page-Mode Operation RNCN (5-5-5-5) 11-12 Burst Page-Mode Read Operation (4-3-3-3). 11-13 Burst Page-Mode Write Operation (4-3-3-3). 11-13 Continuous Page-Mode Operation. 11-14
Illustrations xxiii
ILLUSTRATIONS
Figure Page Title Number Number 11-10 Write Continuous Page Mode. 11-15 11-11 Read Operation (3-2-2-2) 11-15 11-12 DRAM Access Delayed Refresh 11-16 11-13 MCF5407 SDRAM Interface. 11-18 11-14 Using EDGESEL Change Signal Timing. 11-19 11-15 DRAM Control Register (DCR) (Synchronous Mode) 11-19 11-16 DACR0 DACR1 Registers (Synchronous Mode). 11-20 11-17 DRAM Controller Mask Registers (DMR0 DMR1). 11-22 11-18 Burst Read SDRAM Access 11-28 11-19 Burst Write SDRAM Access 11-29 11-20 Synchronous, Continuous Page-Mode Access-Consecutive Reads. 11-30 11-21 Synchronous, Continuous Page-Mode Access-Read after Write. 11-31 11-22 Auto-Refresh Operation. 11-32 11-23 Self-Refresh Operation 11-32 11-24 Mode Register (mrs) Command 11-34 11-25 Initialization Values 11-35 11-26 SDRAM Configuration. 11-36 11-27 DACR Register Configuration. 11-36 11-28 DMR0 Register 11-37 11-29 Mode Register Mapping MCF5407 A[31:0] 11-38 12-1 Signal Diagram 12-1 12-2 MCF5307/MCF5407 TM[2:0] Remapping 12-4 12-3 Dual-Address Transfer. 12-4 12-4 Single-Address Transfers. 12-5 12-6 Destination Address Registers (DARn) 12-7 12-5 Source Address Registers (SARn) 12-7 12-7 Byte Count Registers (BCRn). 12-8 12-8 Control Registers (DCRn) 12-8 12-9 Status Registers (DSRn) 12-10 12-10 Interrupt Vector Registers (DIVRn) 12-11 12-11 DREQ Timing Constraints, Dual-Address Transfer. 12-15 12-12 Dual-Address, Peripheral-to-SDRAM, Lower-Priority Transfer 12-16 12-13 Single-Address Transfer 12-17 13-1 Timer Block Diagram 13-1 13-2 Timer Mode Registers (TMR0/TMR1) 13-3 13-3 Timer Reference Registers (TRR0/TRR1) 13-4 13-4 Timer Capture Register (TCR0/TCR1) 13-5 13-5 Timer Counters (TCN0/TCN1). 13-5 13-6 Timer Event Registers (TER0/TER1). 13-5 14-1 Simplified Block Diagram 14-1 14-2 UART Mode Registers (UMR1n). 14-6 14-3 UART Mode Register (UMR2n) 14-7 14-4 FIFO Threshold Register (RXLVL). 14-8
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Figure Number 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 14-17 14-18 14-19 14-20 14-21 14-22 14-24 14-23 14-25 14-26 14-27 14-28 14-29 14-30 14-31 14-32 14-33 14-34 14-35 14-36 14-37 14-38 14-39 15-1 15-2 15-3 16-1 16-2 16-3 17-1 17-2 Title Page Number
Modem Control Register (MODCTL) 14-9 FIFO Threshold Register (TXLVL) 14-10 UART Status Register (USRn) 14-10 UART Clock-Select Register (UCSRn). 14-12 Receive Samples Available Register (RSMP). 14-13 Space Available Register (TSPC) 14-13 UART Command Register (UCRn). 14-14 UART Receiver Buffer UART0 (URB0). 14-16 UART Receiver Buffer UART1 (URB1). 14-16 UART Transmitter Buffer UART0 (UTB0) 14-16 UART Transmitter Buffer UART1 (UTB1) 14-17 UART Input Port Change Register (UIPCRn). 14-17 UART Auxiliary Control Register (UACRn) 14-18 UART Interrupt Status/Mask Registers (UISRn/UIMRn). 14-18 UART Divider Upper Register (UDUn). 14-19 UART Divider Lower Register (UDLn). 14-19 UART Interrupt Vector Register (UIVRn) 14-20 UART Input Port Register (UIPn) 14-20 UART Block Diagram Showing External Internal Interface Signals 14-21 UART Output Port Data Register (UOP1/UOP0) 14-21 UART/RS-232 Interface 14-23 UART1/CODEC Interface. 14-23 UART1/AC Interface 14-23 Clocking Source Diagram. 14-24 Transmitter Receiver Functional Diagram. 14-25 Transmitter Timing Diagram 14-27 16-Bit CODEC Interface Timing (lsb First) 14-27 8-Bit CODEC Interface Timing (msb First) 14-28 Interface Timing. 14-28 Receiver Timing. 14-30 Automatic Echo 14-34 Local Loop-Back 14-34 Remote Loop-Back 14-35 Multidrop Mode Timing Diagram 14-36 UART Mode Programming Flowchart 14-39 Parallel Port Assignment Register (PAR) 15-1 Port Data Direction Register (PADDR). 15-2 Port Data Register (PADAT) 15-3 Mechanical Diagram. 16-9 MCF5407 Case Drawing (General View) 16-10 Case Drawing (Details). 16-11 MCF5407 Block Diagram with Signal Interfaces 17-2 MCF5307 MCF5407 TM[2:0] Remapping 17-18
Illustrations
ILLUSTRATIONS
Figure Page Title Number Number 18-1 Signal Relationship CLKIN Non-DRAM Access. 18-2 18-2 Connections External Memory Port Sizes 18-4 18-3 Chip-Select Module Output Timing Diagram 18-4 18-4 Data Transfer State Transition Diagram 18-6 18-5 Read Cycle Flowchart. 18-7 18-6 Basic Read Cycle. 18-8 18-7 Write Cycle Flowchart. 18-9 18-8 Basic Write Cycle 18-9 18-9 Read Cycle with Fast Termination 18-10 18-10 Write Cycle with Fast Termination. 18-10 18-11 Back-to-Back Cycles 18-11 18-12 Line Read Burst (2-1-1-1), External Termination 18-12 18-13 Line Read Burst (2-1-1-1), Internal Termination 18-13 18-14 Line Read Burst (3-2-2-2), External Termination 18-13 18-15 Line Read Burst-Inhibited, Fast, External Termination. 18-14 18-16 Line Write Burst (2-1-1-1), Internal/External Termination. 18-14 18-17 Line Write Burst (3-2-2-2) with Wait State, Internal Termination 18-15 18-18 Line Write Burst-Inhibited, Internal Termination 18-15 18-19 Longword Read from 8-Bit Port, External Termination. 18-16 18-20 Longword Read from 8-Bit Port, Internal Termination 18-16 18-21 Example Misaligned Longword Transfer (32-Bit Port) 18-17 18-22 Example Misaligned Word Transfer (32-Bit Port) 18-17 18-23 Interrupt-Acknowledge Cycle Flowchart 18-20 18-24 Basic No-Wait-State External Master Access 18-22 18-25 External Master Burst Line Access 32-Bit Port. 18-24 18-26 MCF5407 Two-Wire Mode Arbitration Interface. 18-25 18-27 Two-Wire Arbitration with Request Asserted. 18-26 18-28 Two-Wire Implicit Explicit Mastership. 18-27 18-29 MCF5407 Two-Wire Arbitration Protocol State Diagram. 18-28 18-30 Three-Wire Implicit Explicit Mastership. 18-30 18-31 Three-Wire Arbitration. 18-31 18-32 Three-Wire Arbitration Protocol State Diagram 18-32 18-33 Master Reset Timing. 18-34 18-34 Software Watchdog Reset Timing 18-35 19-1 JTAG Test Logic Block Diagram 19-2 19-2 JTAG Controller State Machine. 19-4 19-3 IDCODE Register 19-6 19-4 Disabling JTAG JTAG Mode 19-11 19-5 Disabling JTAG Debug Mode 19-11 20-1 Supply Voltage Sequencing Separation Cautions. 20-3 20-2 Example Circuit Control Supply Sequencing. 20-4 20-3 CLKIN-to-Core Clock Frequency Ranges. 20-4 20-4 Clock Timing 20-5
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Figure Number 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 20-16 20-17 20-18 20-19 20-20 20-21 20-22 20-23 20-24 Title Page Number
PSTCLK Timing. 20-6 Timings-Normal Read Write Cycles 20-8 SDRAM Read Cycle with EDGESEL Tied Buffered CLKIN 20-9 SDRAM Write Cycle with EDGESEL Tied Buffered CLKIN 20-10 SDRAM Read Cycle with EDGESEL Tied High. 20-11 SDRAM Write Cycle with EDGESEL Tied High. 20-12 SDRAM Read Cycle with EDGESEL Tied 20-13 SDRAM Write Cycle with EDGESEL Tied 20-14 Output Timing-High Impedance. 20-14 Reset Timing. 20-15 Real-Time Trace Timing 20-16 Serial Port Timing 20-16 Timer Module Timing 20-17 Input/Output Timings 20-19 UART0 UART1 Module Timing-UART Mode 20-20 UART1 16-bit CODEC Mode 20-21 UART1 Mode 20-21 General-Purpose Timing. 20-22 Timing 20-23 IEEE 1149.1 (JTAG) Timing 20-25 MCF5307 MCF5407 TM[2:0] Remapping Simplified Block Diagram Module. Exception Stack Frame Form A-11 Write Debug Module Register Command (WDMREG). A-12 WDMREG Command Sequence. A-13 Power Supply Filter Circuit. A-18
Illustrations
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ILLUSTRATIONS
Figure Number Title Page Number
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TABLES
Table Number Title Page Number
2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22
User-Level Registers. 1-15 Supervisor-Level Registers. 1-16 Field Descriptions 2-10 MOVEC Register 2-11 Status Field Descriptions 2-11 Integer Data Formats. 2-13 ColdFire Effective Addressing Modes. 2-15 Notational Conventions 2-16 ColdFire ISA_B Extension Summary. 2-19 User-Level Instruction Summary. 2-19 Supervisor-Level Instruction Summary. 2-23 Misaligned Operand References 2-24 Move Byte Word Execution Times. 2-25 Move Long Execution Times. 2-25 Miscellaneous Move Execution Times. 2-26 One-Operand Instruction Execution Times 2-27 Two-Operand Instruction Execution Times. 2-27 Miscellaneous Instruction Execution Times. 2-29 Branch Instruction Execution Times 2-30 Instruction Execution Times. 2-30 Exception Vector Assignments. 2-32 Format Field Encoding 2-33 Fault Status Encodings. 2-33 MCF5407 Exceptions 2-34 Instruction Summary. Two-Operand Instruction Execution Times Move Instruction Execution Times. RAMBARn Field Description Examples Typical RAMBAR Settings Valid Modified Settings CACR Field Descriptions 4-21 ACRn Field Descriptions. 4-24 Instruction Cache Line State Transitions. 4-27 Data Cache Line State Transitions. 4-29 Data Cache Line State Transitions (Current State Invalid) 4-30 Data Cache Line State Transitions (Current State Valid). 4-31
Tables xxix
TABLES
Table Number 4-10 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 Title Page Number Data Cache Line State Transitions (Current State Modified). 4-31 Debug Module Signals. PSTDDATA: Sequential Execution Single-Cycle Instructions PSTDDATA: Data Operand Captured. Processor Status Encoding. Status Posting BDM/Breakpoint Registers. AATR AATR1 Field Descriptions. 5-11 ABLR ABLR1 Field Description. 5-12 ABHR ABHR1 Field Description. 5-12 BAAR Field Descriptions 5-13 Field Descriptions. 5-14 DBRn Field Descriptions. 5-16 DBMRn Field Descriptions 5-16 Access Size Operand Data Location 5-16 PBR, PBR1, PBR2, PBR3 Field Descriptions. 5-17 PBMR Field Descriptions 5-17 Field Descriptions 5-19 XTDR Field Descriptions 5-20 Receive Packet Field Description 5-25 Transmit Packet Field Description 5-26 Command Summary 5-26 Field Descriptions 5-27 Control Register Map. 5-42 Definition Encoding-Read. 5-44 PSTDDATA Nibble/CSR[BSTAT] Breakpoint Response. 5-46 Exception Vector Assignments. 5-47 PSTDDATA Specification User-Mode Instructions. 5-50 PSTDDATA Specification Supervisor-Mode Instructions 5-54 Registers MBAR Field Descriptions Field Descriptions. SYPCR Field Descriptions PLLIPL Settings. 6-10 MPARK Field Descriptions. 6-11 Divide Ratio Encodings PLLCR Field Descriptions. Module Input SIgnals. Module Output Signals Interface Memory Map. Address Register Field Descriptions IFDR Field Descriptions I2CR Field Descriptions.
MCF5407 User's Manual
TABLES
Table Number 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-23 11-24 Title Page Number I2SR Field Descriptions. Interrupt Controller Registers Interrupt Control Registers ICRn Field Descriptions Interrupt Priority Scheme. Field Descriptions. Autovector Register Assignments. Field Descriptions. IRQPAR Field Descriptions Chip-Select Module Signals 10-1 Byte Enables/Byte Write Enable Signal Settings 10-2 Accesses Matches CSCRs DACRs 10-3 D7/AA, Automatic Acknowledge Boot CS0. 10-4 D[6:5]/PS[1:0], Port Size Boot 10-5 D3/BE_CONFIG0, BE[3:0] Boot Configuration 10-5 Chip-Select Registers. 10-5 CSARn Field Description 10-7 CSMRn Field Descriptions 10-7 CSCRn Field Descriptions. 10-8 DRAM Controller Registers 11-3 SDRAM Signal Summary 11-4 Field Descriptions (Asynchronous Mode). 11-5 DACR0/DACR1 Field Description 11-6 DMR0/DMR1 Field Descriptions. 11-7 Generic Address Multiplexing Scheme 11-8 DRAM Addressing Byte-Wide Memories. 11-10 DRAM Addressing 16-Bit Wide Memories. 11-10 DRAM Addressing 32-Bit Wide Memories. 11-11 SDRAM Commands 11-17 Synchronous DRAM Signal Connections 11-17 Field Descriptions (Synchronous Mode) 11-19 DACR0/DACR1 Field Descriptions (Synchronous Mode). 11-21 DMR0/DMR1 Field Descriptions. 11-23 MCF5407 SDRAM Interface (8-Bit Port, 9-Column Address Lines). 11-24 MCF5407 SDRAM Interface (8-Bit Port,10-Column Address Lines). 11-24 MCF5407 SDRAM Interface (8-Bit Port,11-Column Address Lines). 11-24 MCF5407 SDRAM Interface (8-Bit Port,12-Column Address Lines). 11-24 MCF5407 SDRAM Interface (8-Bit Port,13-Column Address Lines). 11-25 MCF5407 SDRAM Interface (16-Bit Port, 8-Column Address Lines). 11-25 MCF5407 SDRAM Interface (16-Bit Port, 9-Column Address Lines). 11-25 MCF5407 SDRAM Interface (16-Bit Port, 10-Column Address Lines). 11-25 MCF5407 SDRAM Interface (16-Bit Port, 11-Column Address Lines). 11-25 MCF5407 SDRAM Interface (16-Bit Port, 12-Column Address Lines). 11-26
Tables
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Table Number 11-25 11-26 11-27 11-28 11-29 11-30 11-31 11-32 11-33 11-34 11-35 11-36 11-37 12-1 12-2 12-3 12-4 12-5 13-1 13-2 13-3 13-4 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 14-17 14-18 14-19 15-1 15-2 Title Page Number MCF5407 SDRAM Interface (16-Bit Port, 13-Column-Address Lines) 11-26 MCF5407 SDRAM Interface (32-Bit Port, 8-Column Address Lines). 11-26 MCF5407 SDRAM Interface (32-Bit Port, 9-Column Address Lines). 11-26 MCF5407 SDRAM Interface (32-Bit Port, 10-Column Address Lines). 11-26 MCF5407 SDRAM Interface (32-Bit Port, 11-Column Address Lines). 11-27 MCF5407 SDRAM Interface (32-Bit Port, 12-Column Address Lines). 11-27 SDRAM Hardware Connections. 11-27 SDRAM Example Specifications 11-34 SDRAM Hardware Connections. 11-35 Initialization Values. 11-35 DACR Initialization Values. 11-36 DMR0 Initialization Values. 11-37 Mode Register Initialization 11-38 Signals 12-2 MCF5407 Signal Configurations PP[4:2]/TM[2:0]/DACK[1:0] 12-3 Memory Controller Module Registers. 12-6 DCRn Field Descriptions. 12-8 DSRn Field Descriptions 12-10 General-Purpose Timer Module Memory 13-3 TMRn Field Descriptions 13-4 TERn Field Descriptions. 13-6 Time-Out Values Seconds)-TRR[REF] 0xFFFF(162-MHz Processor Clock) 13-7 UART Module Programming Model. 14-4 UMR1n Field Descriptions 14-6 UMR2n Field Descriptions 14-7 RXLVL Field Descriptions. 14-8 Modem Control Register (MODCTL) Field Descriptions. 14-9 TXLVL Field Descriptions 14-10 USRn Field Descriptions 14-11 UCSRn Field Descriptions. 14-12 RSMP Field Descriptions 14-13 TSPC Field Descriptions. 14-13 UCRn Field Descriptions. 14-14 UIPCRn Field Descriptions 14-17 UACRn Field Descriptions 14-18 UISRn/UIMRn Field Descriptions 14-19 UIVRn Field Descriptions 14-20 UIPn Field Descriptions. 14-20 UOP1/UOP0 Field Descriptions 14-21 UART Module Signals 14-22 UART Module Initialization Sequence 14-38 Parallel Port Descriptions 15-2 PADDR Field Description 15-2
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Table Number 15-3 16-1 16-2 16-3 16-4 16-5 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 17-12 17-13 17-14 17-15 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 19-1 19-2 19-3 19-4 20-1 20-2 20-3 20-4 20-5 20-6 Title Page Number Relationship between PADAT Register Parallel Port (PP) 15-3 Pins 1-52 (Left, Top-to-Bottom) 16-1 Pins 53-104 (Bottom, Left-to-Right). 16-3 Pins 105-156 (Right, Bottom-to-Top). 16-5 Pins 157-208 (Top, Right-to-Left) 16-6 Dimensions 16-11 MCF5407 Signal Index. 17-3 MCF5407 Alphabetical Signal Index 17-5 Data Configuration 17-8 Cycle Size Encoding. 17-9 Cycle Transfer Type Encoding. 17-10 TM[2:0] Encodings (Normal Access). 17-10 Encoding Master 17-11 TM[1:0] Encoding Master 17-11 TM[2:0] Encodings (Emulator Access) 17-11 TM[2:0] Encodings (Interrupt Level) 17-12 Data Configuration 17-14 Selection Automatic Acknowledge 17-14 Selection Port Size 17-14 D3/BE_CONFIG, BE[3:0] Boot Configuration 17-15 D4/ADDR_CONFIG, Address Assignment. 17-15 ColdFire Signal Summary 18-1 Cycle Size Encoding. 18-3 Accesses Matches CSCRs DACRs 18-5 Cycle States 18-6 Allowable Line Access Patterns 18-12 MCF5407 Arbitration Protocol States 18-20 ColdFire Arbitration Signal Summary. 18-21 Cycles Basic No-Wait-State External Master Access. 18-23 Cycles External Master Burst Line Access 32-Bit Port 18-24 MCF5407 Two-Wire Arbitration Protocol Transition Conditions. 18-28 Three-Wire Arbitration Protocol Transition Conditions 18-32 Data Configuration 18-35 JTAG Descriptions 19-3 JTAG Instructions. 19-5 IDCODE Assignments. 19-6 Boundary-Scan Definitions. 19-7 Absolute Maximum Ratings 20-1 Operating Temperatures. 20-1 Electrical Specifications 20-2 Divide Ratio Encodings 20-4 Clock Timing Specification 20-5 Input Timing Specification. 20-6
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TABLES
Table Number 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 20-16 A-10 A-11 A-12 A-13 B-10 Title Page Number Output Timing Specification 20-6 Reset Timing Specification. 20-15 Debug Timing Specification 20-16 Timer Module Timing Specification. 20-17 Input Timing Specifications between SDA. 20-18 Output Timing Specifications between 20-18 UART Module Timing Specifications 20-19 General-Purpose Port Timing Specifications. 20-22 Timing Specifications 20-23 IEEE 1149.1 (JTAG) Timing Specifications 20-24 Differences between MCF5307 MCF5407. MOVEC Space Register TM[2:1] Encoding MCF5307 Internal Master Encoding MCF5307 Internal Master Divide Ratio Encodings D[7:0] Multiplexing D7/AA, Automatic Acknowledge Boot CS0. D[6:5]/PS[1:0], Port Size Boot D4/ADDR_CONFIG, Address Assignment. D3/BE_CONFIG, BE[3:0] Boot Configuration Definition Encoding-Write A-13 Debug Exception Vector Assignments A-16 Version Debug Processor Status Encodings A-17 Registers.B-1 Interrupt Controller Registers .B-1 Chip-Select Registers.B-2 DRAM Controller Registers .B-3 General-Purpose Timer Registers .B-4 UART0 Control Registers.B-4 UART1 Control Registers.B-6 Parallel Port Memory Map.B-7 Interface Memory Map.B-8 Controller Registers.B-8
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About This Book
primary objective this user's manual define functionality MCF5407 processors software hardware developers. information this book subject change without notice, described disclaimers title page this book. with technical documentation, readers' responsibility sure they using most recent version documentation. locate published errata updates this document, refer world-wide
Audience
This manual intended system software hardware developers applications programmers want develop products MCF5407. assumed that reader understands operating systems, microprocessor system design, basic principles software hardware, basic details ColdFire architecture.
Organization
Following summary brief description major sections this manual: Chapter "Overview," includes general descriptions modules features incorporated MCF5407, focussing particular features defined Version (V4) programming model, such Harvard memory architecture implementation, instructions, registers. Part intended system designers need understand operation MCF5407 ColdFire core multiply/accumulate (MAC) execution unit. describes programming exception models, Harvard memory implementation, debug module. Chapter "ColdFire Core," provides overview microprocessor core MCF5407. chapter begins with description enhancements from ColdFire core, then fully describes programming model implemented MCF5407. also includes full description exception handling, data formats, instruction summary, table instruction timings.
About This Book
xxxv
Organization
Chapter "Hardware Multiply/Accumulate (MAC) Unit," describes MCF5407 multiply/accumulate unit, which executes integer multiply, multiply-accumulate, miscellaneous register instructions. integrated into operand execution pipeline (OEP). Chapter "Local Memory." This chapter describes MCF5407 implementation ColdFire local memory specification. consists following major sections. Section 4.2, "SRAM Overview," describes MCF5407 on-chip static (SRAM) implementation. covers general operations, configuration, initialization. also provides information examples showing minimize power consumption when using SRAM. Section 4.7, "Cache Overview," describes MCF5407 cache implementation, including organization, configuration, coherency. describes cache operations cache interacts with other memory structures. Chapter "Debug Support," describes Revision enhanced hardware debug support MCF5407. This revision ColdFire debug architecture encompasses earlier revisions. Part "System Integration Module (SIM)," describes system integration module, which provides overall control serves interface between ColdFire core processor complex internal peripheral devices. includes general description individual chapters that describe components SIM, such phase-lock loop (PLL) timing source, interrupt controller peripherals, configuration operation chip selects, SDRAM controller. Chapter "SIM Overview," describes programming model, arbitration, system-protection functions MCF5407. Chapter "Phase-Locked Loop (PLL)," describes configuration operation module. describes detail registers signals that support implementation. Chapter "I2C Module," describes MCF5407 module, including protocol, clock synchronization, registers programing model. also provides extensive programming examples. Chapter "Interrupt Controller," describes operation interrupt controller portion SIM. Includes descriptions registers interrupt controller memory interrupt priority scheme. Chapter "Chip-Select Module," describes MCF5407 chip-select implementation, including operation programming model, which includes chip-select address, mask, control registers. Chapter "Synchronous/Asynchronous DRAM Controller Module," describes configuration operation synchronous/asynchronous DRAM
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Organization
controller component SIM. begins with general description brief glossary, includes description signals involved DRAM operations. remainder chapter divided between descriptions asynchronous synchronous operations. Part III, "Peripheral Module," describes operation configuration MCF5407 DMA, timer, UART, parallel port modules, describes they interface with system integration unit, described Part Chapter "DMA Controller Module," provides overview controller module describes detail signals registers. latter sections this chapter describe operations, features, supported data transfer modes detail, showing timing diagrams various operations. Chapter "Timer Module," describes configuration operation general-purpose timer modules, timer timer includes programming examples. Chapter "UART Modules," describes universal asynchronous/synchronous receiver/transmitters (UARTs) implemented MCF5407 includes programming examples. Particular attention given UART1 implementation synchronous interface that provides controller 16-bit CODEC interface audio CODEC '97) digital interface. Chapter "Parallel Port (General-Purpose I/O)," describes operation programming model parallel port assignment, direction-control, data registers. includes code example setting parallel port. Part "Hardware Interface," provides pinout both electrical functional descriptions MCF5407 signals. also describes these signals interact support variety operations shown timing diagrams. Chapter "Mechanical Data," provides functional listing package diagram MCF5407. Chapter "Signal Descriptions," provides alphabetical listing MCF5407 signals. This chapter describes MCF5407 signals. particular, shows which inputs outputs, they multiplexed, which signals require pull-up resistors, state each signal reset. Chapter "Bus Operation," describes data transfers, error conditions, arbitration, reset operations. describes transfers initiated MCF5407 external master, includes detailed timing diagrams showing interaction signals supported operations. Note that Chapter "Synchronous/Asynchronous DRAM Controller Module," describes DRAM cycles. Chapter "IEEE 1149.1 Test Access Port (JTAG)," describes configuration operation MCF5407 JTAG test implementation. describes JTAG instructions disable JTAG functionality.
About This Book xxxvii
Suggested Reading
Chapter "Electrical Specifications," describes electrical specifications thermal characteristics MCF5407. Because additional speeds have become available since publication this book, consult Motorola's ColdFire page, confirm that this latest information. This manual includes following appendixes: Appendix "Migrating from ColdFire MCF5307 MCF5407," highlights differences between MCF5307B MCF5407. Users MCF5307 MCF5307A should this document conjunction with MCF5307 User's Manual Mask Addendum. additional information, MCF5407 Integrated ColdFire Microprocessor Product Brief. Appendix "List Memory Maps," lists entire address-map MCF5407 memory-mapped registers.
This manual also includes glossary index.
Suggested Reading
This section lists additional reading that provides background information this manual well general information about ColdFire architecture.
General Information
following documentation provides useful information about ColdFire architecture computer architecture general:
ColdFire Documentation
ColdFire documentation available from sources listed back cover this manual. Document order numbers included parentheses ease ordering. ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD) User's manuals-These books provide details about individual ColdFire implementations intended used conjunction with ColdFire Programmers Reference Manual. These include following: ColdFire MCF5102 User's Manual (MCF5102UM/AD) ColdFire MCF5202 User's Manual (MCF5202UM/AD) ColdFire MCF5204 User's Manual (MCF5204UM/AD) ColdFire MCF5206 User's Manual (MCF5206EUM/AD) ColdFire MCF5206E User's Manual (MCF5206EUM/AD) ColdFire MCF5307 User's Manual (MCF5307UM/AD) ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD)
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Conventions
Using Microprocessors Microcomputers: Motorola Family, William Wray, Ross Bannatyne, Joseph Greenfield
Additional literature ColdFire implementations being released processors become available. current list ColdFire documentation, refer World Wide
Conventions
This document uses following notational conventions: MNEMONICS mnemonics italics REG[FIELD] text, instruction mnemonics shown uppercase. code tables, instruction mnemonics shown lowercase. Italics indicate variable command parameters. Book titles text italics. Prefix denote hexadecimal number Prefix denote binary number Abbreviations registers shown uppercase. Specific bits, fields, ranges appear brackets. example, RAMBAR[BA] identifies base address field base address register. 4-bit data unit 8-bit data unit 16-bit data unit 32-bit data unit some contexts, such signal encodings, indicates don't care. Used express undefined numerical value logical operator logical operator logical operator
nibble byte word longword
Acronyms Abbreviations
Table lists acronyms abbreviations used this document.
Table Acronyms Abbreviated Terms
Term AVEC Analog-to-digital conversion Arithmetic logic unit Autovector Meaning
About This Book
xxxix
Acronyms Abbreviations
Table Acronyms Abbreviated Terms (Continued)
Term BIST BSDL CODEC FIFO GPIO IEEE JEDEC JTAG LIFO MBAR PCLK PLRU Background debug mode Built-in self test Boundary-scan description language Code/decode Digital-to-analog conversion Direct memory access Digital signal processing Effective address Extended data output (DRAM) First-in, first-out General-purpose Inter-integrated circuit Institute Electrical Electronics Engineers Instruction fetch pipeline Interrupt priority level Joint Electron Device Engineering Council Joint Test Action Group Last-in, first-out Least recently used Least-significant byte Least-significant Multiple accumulate unit Memory base address register Most-significant byte Most-significant Multiplex operation Operand execution pipeline Program counter Processor clock Phase-locked loop Pseudo least recently used Meaning
MCF5407 User's Manual
Terminology Notational Conventions
Table Acronyms Abbreviated Terms (Continued)
Term PQFP RISC UART Power-on reset Plastic quad flat pack Reduced instruction computing Receive System integration module Start frame Test access port Transistor-to-transistor logic Transmit Universal asynchronous/synchronous receiver transmitter Meaning
Terminology Notational Conventions
Table shows notational conventions used throughout this document.
Table Notational Conventions
Instruction Operand Syntax Opcode Wildcard Logical condition (example: equal) Register Specifications Ay,Ax Dy,Dx Ry,Rx address register (example: address register Source destination address registers, respectively data register (example: data register Source destination data registers, respectively control register (example vector base register) registers (ACC, MAC, MASK) address data register Destination register (used instructions only) source destination registers, respectively index register (can address data register:
About This Book
Terminology Notational Conventions
Table Notational Conventions (Continued)
Instruction Operand Syntax Register Names MACSR MASK accumulator register Condition code register (lower byte status register mask register Program counter Status register Port Name PSTDDATA Processor status/debug data port Miscellaneous Operands #<data> <ea> <ea>y,<ea>x <label> <list> <shift> <size> <vector> <xxx> Immediate data following 16-bit operation word instruction Effective address Source destination effective addresses, respectively Assembly language program label List registers MOVEM instruction (example: D3-D0) Shift operation: shift left (<<), shift right (>>) Operand data size: byte (B), word (W), longword Both instruction data caches Data cache Instruction cache Identifies 4-bit vector number trap instructions identifies indirect data address referencing memory identifies absolute address referencing memory Signal displacement value, bits wide (example: 16-bit displacement) Scale factor (x1, indexed addressing mode, <<1n>> operations) Operations Arithmetic addition postincrement indicator Arithmetic subtraction predecrement indicator Arithmetic multiplication
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Table Notational Conventions (Continued)
Instruction sign-extended <condition> then <operations> else <operations> Arithmetic division Invert; operand logically complemented Logical Logical Logical exclusive Shift left (example: shift left bits) Shift right (example: shift right bits) Source operand moved destination operand operands exchanged bits upper portion made equal high-order lower portion Test condition. true, operations after `then' performed. condition false optional `else' clause present, operations after `else' performed. condition false else omitted, instruction performs operation. Refer instruction description example. Subfields Qualifiers Address Optional operation Identifies indirect address Displacement value, n-bits wide (example: 16-bit displacement) Calculated effective address (pointer) selection (example: Least significant (example: Least significant byte Least significant word Most significant Most significant byte Most significant word Condition Code Register Names Carry Negative Overflow Extend Zero Operand Syntax
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Terminology Notational Conventions
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MCF5407 User's Manual
Chapter Overview
This chapter overview MCF5407 ColdFire® processor. includes general descriptions modules features incorporated MCF5407, focusing particular features defined Version (V4) programming model, such Harvard memory architecture implementation, instructions, registers.
Features
MCF5407 integrated microprocessor combines ColdFire processor core with following components, shown Figure 1-1: Harvard architecture memory system with 16-Kbyte instruction cache 8-Kbyte data cache Two, 2-Kbyte on-chip SRAMs Integer/fractional multiply-accumulate (MAC) unit Divide unit System debug interface DRAM controller synchronous asynchronous DRAM Four-channel controller general-purpose timers UARTs, that supports synchronous operations I2Cinterface Parallel interface System integration module (SIM)
Designed embedded control applications, MCF5407 delivers Dhrystone MIPS while minimizing system costs.
Chapter Overview
Features
COLDFIRE PROCESSOR COMPLEX Instruction Unit
Branch Logic
JTAG
8-Entry Branch Cache
Instruction Fetch Pipeline (IFP)
128-Entry Prediction Table
Ten-Instruction FIFO Buffer Operand Execution Pipeline (OEP)
LIFO Return Stack
Debug Module
PSTCLK
GeneralPurpose Registers A0-A7 D0-D7
Local Memory SRAM Controller RAMBAR0 RAMBAR1 2-Kbyte SRAM0 CLKIN on-chip peripherals) Local Memory Instruction 2-Kbyte SRAM1 Local Memory Data
Harvard Cache Controller CACR ACR2 ACR3 ACR0 ACR1 8-Kbyte Data Cache
CLKIN RSTI
PCLK RSTO
16-Kbyte Instruction Cache
4-Entry Store Buffer
SYSTEM INTEGRATION MODULE (SIM) Control
Parallel Port
System Control
SWIVR SYPCR SWSR
Base Address
MBAR
Master Park
MPARK
Four Channels Software Watchdog
DRAM Controller DRAM Control
Chip-Select Module
CSARs CSCRs CSMRs
External Interface
Interrupt Controller
ICRs IRQPAR
Module UARTs GeneralPurpose Timers
Addr/Cntrl Mask
DACR0/1 DMR0/1
DRAM Controller Outputs CS[7:0]
32-Bit Address 32-Bit Data Control Signals
IRQ[1,3,5,7]
Figure 1-1. MCF5407 Block Diagram
MCF5407 User's Manual
Features
Features common many embedded applications, such DMAs, various DRAM controller interfaces, on-chip memories, integrated using advanced process technologies. MCF5407 extends legacy Motorola's family providing compatible path ColdFire customers which development tools customer code leveraged. fact, customers moving from ColdFire code translation emulation tools that facilitate modifying assembly code ColdFire architecture. package, pinout, integration MCF5407 create especially simple upgrade current MCF5307 designs with over triple system performance. Based concept variable-length RISC technology, ColdFire family combines architectural simplicity conventional 32-bit RISC with memory-saving, variable-length instruction set. defining ColdFire architecture embedded processing applications, 68K-code compatible core combines performance advantages RISC architecture with optimum code density streamlined, variable-length M68000 instruction set. using variable-length instruction architecture, embedded system designers using ColdFire RISC processors enjoy significant advantages over conventional fixed-length RISC architectures. denser binary code ColdFire processors consumes less memory than many fixed-length instruction RISC processors available. This improved code density means more efficient system memory given application allows slower, less costly memory help achieve target performance level. MCF5407 first standard product implement Version ColdFire microprocessor core. microarchitecture implements number advanced techniques, including Harvard memory architecture, branch cache acceleration logic, limited superscalar support (dual-instruction issue), which contribute Dhrystone MIPS performance level. Increasing internal speed core also allows higher performance while providing system designer with easy-to-use lower speed system interface. processor complex frequency integer multiple, times, external frequency. core clock stopped support low-power mode. Serial communication channels provided interface module programmable full-duplex UARTs, which provides synchronous communications soft-modem applications. Four channels allow fast data transfer using programmable burst mode independent processor execution. 16-bit general-purpose multimode timers provide separate input output signals. system protection, processor includes programmable 16-bit software watchdog timer. addition, common system functions such chip selects, interrupt control, arbitration, IEEE 1149.1 JTAG module included.A sophisticated debug interface supports background-debug mode plus real-time trace debug with expanded on-chip breakpoint registers. This interface present ColdFire standard products allows common emulator support across entire family microprocessors.
Chapter Overview
MCF5407 Features
MCF5407 Features
following list summarizes MCF5407 features: ColdFire processor core Variable-length RISC, clock-multiplied Version microprocessor core Implementation Revision ColdFire instruction architecture (ISA), which leverages programming model independent decoupled pipelines: four-stage instruction fetch pipeline (IFP) five-stage operand execution pipeline (OEP) Ten-instruction FIFO buffer provides decoupling between pipelines Limited superscalar design achieves performance levels close dual-issue performance Programmable two-level branch acceleration mechanism with 8-entry branch cache plus 128-entry prediction table increased performance 32-bit internal address supporting Gbytes linear address space 32-bit data user-accessible, 32-bit-wide, general-purpose registers Supervisor/user modes system protection Vector base register relocate exception-vector table Optimized high-level language constructs Multiply accumulate unit (MAC) High-speed, complex arithmetic processing applications Tightly coupled Three-stage execute pipeline with clock issue rate operations multiplies support, with 32-bit accumulate Signed unsigned integer support, plus signed fractional operands Hardware integer divide unit Unsigned signed integer divide support Tightly coupled 32/16 32/32 operation support producing quotient and/or remainder results 16-Kbyte instruction cache, 8-Kbyte data cache Four-way set-associative organization Operates higher processor core frequency Provides pipelined, single-cycle access critical code data Data cache supports write-through copyback modes Four-entry, 32-bit store buffer improve performance operand writes
MCF5407 User's Manual
MCF5407 Features
Two, 2-Kbyte SRAMs Programmable location anywhere within 4-Gbyte linear address space Higher core-frequency operation Pipelined, single-cycle access critical code data Each block mappable either instruction data operand controller Four fully programmable channels: support external requests external acknowledges Dual-address single-address transfer support with 16-, 32-bit data capability Source/destination address pointers that increment remain constant 24-bit transfer counter channel Operand packing unpacking supported Auto-alignment transfers supported efficient block movement Bursting cycle steal support Two-bus-clock internal access Automatic transfers from on-chip UARTs using internal interrupts DRAM controller Synchronous DRAM (SDRAM), extended-data-out (EDO) DRAM, fast page mode support Mbytes DRAM Programmable timer provides CAS-before-RAS refresh asynchronous DRAMs Support separate memory blocks UARTs UART offers synchronous mode with expanded buffers soft modem support Full-duplex operation Programmable clock Modem control signals available (CTS, RTS) Processor-interrupt capability Dual 16-bit general-purpose multiple-mode timers 8-bit prescaler Timer input output pins Processor-interrupt capability 18.5-nS resolution
Chapter Overview
MCF5407 Features
module Interchip interface EEPROMs, controllers, converters, keypads Fully compatible with industry-standard Master slave modes support multiple masters Automatic interrupt generation with programmable level System interface module (SIM) Chip selects provide direct interface 16-, 32-bit SRAM, ROM, FLASH, memory-mapped devices Eight fully programmable chip selects, each with base address register Programmable wait states port sizes chip select User-programmable processor clock/input clock frequency ratio Programmable interrupt controller interrupt latency Four external interrupt request inputs Programmable autovector generator Software watchdog timer 16-bit general-purpose interface IEEE 1149.1 test (JTAG) module System debug support Real-time trace determining dynamic execution path while emulator mode Background debug mode (BDM) debug features while halted Real-time debug support, including user-visible hardware breakpoint registers supporting separate breakpoints Supports servicing critical, real-time interrupt requests while emulator mode Supports comprehensive emulator functions through trace breakpoint logic On-chip Accepts various clock input (CLKIN) frequencies between Supports core frequencies between Supports low-power mode Product offerings Dhrystone MIPS Implemented 0.22 quad-layer-metal process technology with 1.8-V operation (3.3-V compliant pads) 208-pin plastic package 0°-70° operating temperature
MCF5407 User's Manual
ColdFire Module Description
1.2.1 Process
MCF5407 manufactured 0.22-µ CMOS process with quad-layer-metal routing technology. This process combines high performance power needed embedded system applications. Inputs 3.3-V tolerant; outputs CMOS open-drain CMOS with outputs operating from with guaranteed TTL-level specifications.
ColdFire Module Description
following sections provide overviews various modules incorporated MCF5407.
1.3.1 ColdFire Core
Version ColdFire core consists independent decoupled pipelines maximize performance-the instruction fetch pipeline (IFP) operand execution pipeline (OEP).
1.3.1.1 Instruction Fetch Pipeline (IFP)
four-stage instruction fetch pipeline (IFP) designed prefetch instructions operand execution pipeline (OEP). Because fetch execution pipelines decoupled ten-instruction FIFO buffer, fetch mechanism prefetch instructions advance their OEP, thereby minimizing time stalled waiting instructions. maximize performance conditional branch instructions, Version implements sophisticated two-level acceleration mechanism. first level 8-entry, direct-mapped branch cache with 2-bit prediction state (strongly/weakly, taken/not-taken) each entry. branch cache implements instruction folding techniques. These allow conditional branch instructions that predicted correctly taken execute zero cycles. those conditional branches with information branch cache, second-level, direct-mapped prediction table containing entries accessed. Again, each entry uses same 2-bit prediction state definition branch cache. This branch prediction state then used predict direction prefetched conditional branch instructions. Other change-of-flow instructions, including unconditional branches, jumps, subroutine calls, similar mechanism where calculates target address. performance subroutine return instructions improved through four-entry, LIFO return stack. cases, these mechanisms allow redirect fetch stream down path predicted taken well advance actual instruction execution. result significantly improved performance.
Chapter Overview
ColdFire Module Description
1.3.1.2 Operand Execution Pipeline (OEP)
prefetched instruction stream gated from FIFO buffer into five-stage OEP. consists two, traditional two-stage RISC compute engines with register file access feeding arithmetic/logic unit (ALU). compute engine located typically used operand memory address calculations (the address ALU), while compute engine located bottom pipeline used instruction execution (the execution ALU). resulting structure provides Gbytes/S data operand bandwidth compute engines supports single-cycle execution speeds most instructions, including load, store, most embedded-load operations. response users developers' comments, design supports execution ColdFire Revision instruction set, which adds small number instructions improve performance code density. also implements advanced performance features. dynamically determines appropriate location instruction execution (either address execution ALU) based pipeline state. address compute engine, conjunction with register renaming resources, used execute number heavily-used opcodes forward results subsequent instructions without pipeline stalls. Additionally, implements instruction folding techniques involving MOVE instructions that instructions issued single machine cycle. resulting microarchitecture approaches performance full superscalar implementation, much lower silicon cost.
1.3.1.3 Module
unit provides signal processing capabilities MCF5407 variety applications including digital audio servo control. Integrated execution unit processor's OEP, unit implements three-stage arithmetic pipeline optimized multiplies. Both 32-bit input operands supported this design addition full extensions signed unsigned integers, plus signed, fixed-point fractional input operands.
1.3.1.4 Integer Divide Module
Integrated into OEP, divide module performs operations using signed unsigned integers. module supports word longword divides producing quotients and/or remainders.
1.3.2 Harvard Architecture
Harvard memory architecture implements separate instruction data buses processor-local memories, removing conflicts between instruction fetches operand accesses.
MCF5407 User's Manual
ColdFire Module Description
1.3.2.1 16-Kbyte Instruction Cache/8-Kbyte Data Cache
MCF5407 Harvard architecture includes 16-Kbyte instruction cache 8-Kbyte data cache. These four-way, set-associative caches provide pipelined, single-cycle access cached instructions operands. with ColdFire caches, cache controllers implement non-lockup, streaming design. processor-local memories decouples performance from external memory speeds increases available bandwidth external devices on-chip 4-channel DMA. Both caches implement line-fill buffers optimize 16-byte line burst accesses. Additionally, data cache supports copyback, write-through, cache-inhibited modes. 4-entry, 32-bit buffer used cache line push operations configured deferred write buffering write-through cache-inhibited modes. INTOUCH instruction used prefetch instructions that, when used with cache locking feature, cannot displaced from instruction cache instruction cache misses. This function desirable systems where deterministic real-time performance critical.
1.3.2.2 Internal 2-Kbyte SRAMs
2-Kbyte on-chip SRAM modules also connected Harvard memory architecture provide pipelined, single-cycle access memory regions mapped these devices. Each memory independently mapped 0-modulo-2K location 4-Gbyte address space configured either instruction data accesses. Time-critical functions mapped onto instruction memory bus, while system stack heavily-referenced data operands mapped onto data bus.
1.3.3 DRAM Controller
MCF5407 DRAM controller provides direct interface blocks DRAM. controller supports 16-, 32-bit memory widths easily interface PC-100 DIMMs. unique addressing scheme allows increases system memory size without rerouting address lines rewiring boards. controller operates normal mode page mode supports SDRAMs DRAMs.
1.3.4 Controller
MCF5407 provides four fully programmable channels quick data transfer. Dual- single-address modes support bursting cycle steal. Data transfers bits long with packing unpacking supported along with auto-alignment option efficient block transfers. Automatic block transfers from on-chip serial UARTs also supported through channels.
Chapter Overview
ColdFire Module Description
1.3.5 UART Modules
MCF5407 contains UARTs, which function independently. UART been enhanced provide synchronous operation CODEC interface soft modem support. Either UART clocked system clock, eliminating need external crystal. Each UART module interfaces directly CPU, shown Figure 1-2.
UART Internal Channel Control Logic Serial Communications Channel System Integration Module (SIM) Interrupt Controller Interrupt Control Logic Programmable Clock Generation CLKIN External clock (TIN)
Figure 1-2. UART Module Block Diagram
Each UART module consists following major functional areas: Serial communication channel 16-bit divider clock generation Internal channel control logic Interrupt control logic
UART1 enhanced provide CODEC interface soft modem support. UART1 programmed function like UART0 following modem modes: 8-bit CODEC interface 16-bit CODEC interface audio CODEC (AC97) digital interface controller
Each UART contains programmable clock-rate generator. Data formats bits with even, odd, parity, stop bits 1/16 increments. UARTs include following transmit receive FIFO buffers: UART0 4-byte FIFO receive buffer 2-byte FIFO transmit buffer. UART1, FIFOs hold following: 1-byte samples when programmed UART 8-bit CODEC interface 2-byte samples when programmed 16-bit CODEC interface 20-bit samples when programmed Digital Controller
UART modules also provide several error-detection maskable-interrupt capabilities. Modem support includes request-to-send (RTS) clear-to-send (CTS) lines. CLKIN provides time base through programmable prescaler. UART time scale also sourced from timer input. Full-duplex, auto-echo loopback, local loopback,
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ColdFire Module Description
remote loopback modes allow testing UART connections. programmable UARTs interrupt various normal error-condition events.
1.3.6 Timer Module
timer module includes general-purpose timers, each which contains free-running 16-bit timer three modes. mode captures timer value with external event. Another mode triggers external signal interrupts when timer reaches value, while third mode counts external events. timer unit 8-bit prescaler that allows programming clock input frequency, which derived from system cycle external clock input (TIN). programmable timer-output generates either active-low pulse toggles output.
1.3.7 Module
interface two-wire, bidirectional serial used quick data exchanges between devices. minimizes interconnection between devices system best suited applications that need occasional bursts rapid communication over short distances among several devices. operate master, slave, multiple-master modes.
1.3.8 System Interface
MCF5407 processor provides direct interface 16-, 32-bit FLASH, SRAM, ROM, peripheral devices through fully programmable chip selects write enables. Support burst ROMs also included. Through on-chip PLL, users input slower clock MHz) that internally multiplied create faster processor clock (100 MHz).
1.3.8.1 External Interface
interface controller transfers information between ColdFire core memory, peripherals, other devices external bus. external interface provides bits address space, 32-bit data bus, associated control signals. This interface implements extended synchronous protocol that supports bursting operations. Simple two-wire request/acknowledge arbitration between MCF5407 processor another master, such external device, glueless with arbitration logic internal MCF5407 processor. Multiple-master arbitration also available with some simple external arbitration logic.
1.3.8.2 Chip Selects
Eight fully programmable chip select outputs support external memory peripheral circuits with user-defined wait-state insertion. These signals interface 16-,
Chapter Overview 1-11
ColdFire Module Description
32-bit ports. base address, access permissions, internal transfer terminations programmable with configuration registers each chip select. also provides global chip select functionality boot upon reset initializing MCF5407.
1.3.8.3 16-Bit Parallel Port Interface
16-bit general-purpose programmable parallel port serves either input output pin-by-pin basis.
1.3.8.4 Interrupt Controller
interrupt controller provides user-programmable control internal peripheral interrupts implements four external fixed interrupt-request pins. Each internal interrupt programmed seven interrupt levels four priority levels within each these levels. Additionally, external interrupt request pins mapped levels levels Autovector capability available both internal external interrupts.
1.3.8.5 JTAG
help with system diagnostics manufacturing testing, MCF5407 processor includes dedicated user-accessible test logic that complies with IEEE 1149.1a standard boundary-scan testability, often referred Joint Test Action Group, JTAG. more information, refer IEEE 1149.1a standard.
1.3.9 System Debug Interface
ColdFire processor core debug interface provided support system debugging conjunction with low-cost debug emulator development tools. Through standard debug interface, users access real-time trace debug information. This allows processor system debugged full speed without need costly in-circuit emulators. debug unit MCF5407 compatible upgrade MCF52xx MCF53xx debug modules with added breakpoint registers support interrupt request servicing while emulator mode. on-chip breakpoint resources include total programmable registers-two sets address registers (each with 32-bit registers), sets data registers (each with 32-bit data register plus 32-bit data mask register), 32-bit register plus 32-bit mask register three additional 32-bit registers. These registers accessed through dedicated debug serial communication channel from processor's supervisor mode programming model. breakpoint registers configured generate triggers combining address, data, conditions variety single dual-level definitions. trigger event programmed generate processor halt initiate debug interrupt exception. MCF5407's interrupt servicing options during emulator mode allow real-time critical interrupt service routines serviced while processing debug interrupt event, thereby ensuring that system continues operate even during debugging.
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Programming Model, Addressing Modes, Instruction
support program trace, Version debug module combined processor status debug data outputs into single 8-bit (PSTDDATA[7:0]). This PSTCLK output provide execution status, captured operand data, branch target addresses defining processor activity one-half CPU's clock rate.
1.3.10 Module
MCF5407 module shown Figure 1-3.
CLKIN on-chip peripherals) BCLKO
CLKIN DIVIDE[2:0] RSTI
PCLK core)
Debug Module
RSTO PSTCLK PCLK/2)
Figure 1-3. Module
module's three modes operation described follows. Reset mode-When RSTI asserted, enters reset mode. reset, asserts RSTO from MCF5407. core:bus frequency ratio other MCF5407 configuration information sampled during reset. Normal mode-In normal mode, input frequency programmed reset clock-multiplied provide processor clock (PCLK). Reduced-power mode-In reduced-power mode, PCLK disabled executing sequence that includes programming control system configuration register (SCR) then executing STOP instruction. Register contents retained reduced-power mode, system reenabled quickly when unmasked interrupt reset detected.
Programming Model, Addressing Modes, Instruction
ColdFire programming model privilege levels-supervisor user. status register (SR) indicates privilege level. processor identifies logical address that differentiates between supervisor user modes accessing either supervisor user address space.
Chapter Overview
1-13
Programming Model, Addressing Modes, Instruction
User mode-When processor user mode (SR[S] only subset registers accessed, privileged instructions cannot executed. Typically, most application processing occurs user mode. User mode usually entered executing return from exception instruction (RTE, assuming value SR[S] saved stack MOVE, instruction (assuming SR[S] Supervisor mode-This mode protects system resources from uncontrolled access users. supervisor mode, complete access provided registers entire ColdFire instruction set. Typically, system programmers supervisor programming model implement operating system functions provide control. supervisor programming model provides access same registers user model, plus additional registers configuring on-chip system resources, described Section 1.4.3, "Supervisor Registers." Exceptions (including interrupts) handled supervisor mode.
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Programming Model, Addressing Modes, Instruction
1.4.1 Programming Model
Figure shows MCF5407 programming model.
Data registers
User Registers
Address registers
Stack pointer Program counter Condition code register status register accumulator mask register Status register Vector base register Cache control register Access control register (data) Access control register (data) Access control register (instruction) Access control register (instruction) base address register base address register Module base address register
MACSR MASK
Supervisor Registers
(CCR) Must zeros
CACR ACR0 ACR1 ACR2 ACR3 RAMBAR0 RAMBAR1 MBAR
Figure 1-4. ColdFire MCF5407 Programming Model
1.4.2 User Registers
user programming model shown Figure summarized Table 1-1.
Table 1-1. User-Level Registers
Register Data registers (D0-D7) Address registers (A0-A7) Description These 32-bit registers bit, byte, word, longword operands. They also used index registers. These 32-bit registers serve software stack pointers, index registers, base address registers. base address registers used word longword operations. functions hardware stack pointer during stacking subroutine calls exception handling.
Chapter Overview
1-15
Programming Model, Addressing Modes, Instruction
Table 1-1. User-Level Registers (Continued)
Register Program counter (PC) Condition code register (CCR) status register (MACSR) Accumulator (ACC) Mask register (MASK) Description Contains address instruction currently being executed MCF5407 processor lower byte contains indicator flags that reflect result previous operation used conditional instruction execution. Defines operating configuration unit contains indicator flags from results instructions. General-purpose register used accumulate results operations General-purpose register provides optional address mask instructions that fetch operands from memory. useful implementation circular queues operand memory.
1.4.3 Supervisor Registers
Table summarizes MCF5407 supervisor-level registers.
Table 1-2. Supervisor-Level Registers
Register Status register (SR) Description upper byte provides interrupt information addition variety mode indicators signaling operating state ColdFire processor. lower byte CCR, shown Figure 1-4. Defines upper bits base address exception vector table used during exception processing. low-order bits forced zero, locating vector table 0-modulo-1 Mbyte address. Defines operating modes Version cache memories. Control fields configuring instruction, data, branch cache provided this register, along with default attributes 4-Gbyte address space. Define address ranges attributes associated with various memory regions within 4-Gbyte address space. Each defines location given memory region assigns attributes such write-protection cache mode (copyback, write-through, cacheability). ACR0 ACR1 support data memory; ACR2 ACR3 support instruction memory. Additionally, CACR fields assign default attributes instruction data memory spaces. Provide logical base address 2-Kbyte SRAM modules define attributes access types allowed corresponding SRAM. Defines logical base address memory-mapped space containing control registers on-chip peripherals.
Vector base register (VBR) Cache configuration register (CACR) Access control registers (ACR0/1, ACR2/3)
base address registers (RAMBAR0, RAMBAR1) Module base address register (MBAR)
1.4.4 Instruction
Version ColdFire core implements Revision instruction set, which adds opcodes enhance support byte- word-sized operands position-independent code. ColdFire instruction supports high-level languages optimized those instructions most commonly generated compilers embedded applications. Table provides alphabetized listing ColdFire instruction opcodes, supported
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Programming Model, Addressing Modes, Instruction
operation sizes, assembler syntax. two-operand instructions, first operand generally source operand second destination. Because ColdFire architecture provides upgrade path customers, instruction supports most common opcodes. majority instructions binary compatible optimized opcodes. This feature, when coupled with code conversion tools from third-party developers, generally minimizes software porting issues customers with applications. following list summarizes enhanced instructions Revision ISA: instructions: INTOUCH loads blocks instructions locked instruction cache. MOV3Q.L moves 3-bit immediate data destination location. MVS.{B,W} sign-extends source operand moves destination register. MVZ.{B,W} zero-fills source operand moves destination register. SATS.L updates destination register depending overflow bit. TAS.B tests byte operand being addressed. Enhancements existing Revision instructions: Longword support branch instructions (Bcc, BRA, BSR) Byte word support compare instructions (CMP, CMPI) Byte longword support MOVE.x where source type #<data> destination type d16(Ax); that move.b #<data>, d16(Ax)
Chapter Overview
1-17
Programming Model, Addressing Modes, Instruction
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MCF5407 User's Manual
Part MCF5407 Processor Core
Intended Audience
Part intended system designers need general understanding functionality supported MCF5407. also describes operation MCF5407 ColdFire core multiply/accumulate (MAC) execution unit. describes programming exception models, Harvard memory implementation, debug module.
Contents
Chapter "ColdFire Core," provides overview microprocessor core MCF5407. chapter begins with description enhancements from ColdFire core, then fully describes programming model implemented MCF5407. also includes full description exception handling, data formats, instruction summary, table instruction timings. Chapter "Hardware Multiply/Accumulate (MAC) Unit," describes MCF5407 multiply/accumulate unit, which executes integer multiply, multiply-accumulate, miscellaneous register instructions. integrated into operand execution pipeline (OEP). Chapter "Local Memory." This chapter describes MCF5407 implementation ColdFire local memory specification. consists following major sections. Section 4.2, "SRAM Overview," describes MCF5407 on-chip static (SRAM) implementation. covers general operations, configuration, initialization. also provides information examples showing minimize power consumption when using SRAM. Section 4.7, "Cache Overview," describes MCF5407 cache implementation, including organization, configuration, coherency. describes cache operations cache interacts with other memory structures.
Part MCF5407 Processor Core
I-xix
Chapter "Debug Support," describes Revision enhanced hardware debug support MCF5407. This revision ColdFire debug architecture encompasses earlier revisions.
Suggested Reading
following literature helpful with respect topics Part ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD) Using Microprocessors Microcomputers: Motorola Family, William Wray, Ross Bannatyne, Joseph Greenfield
Acronyms Abbreviations
Table contains acronyms abbreviations used Part
Table I-i. Acronyms Abbreviated Terms
Term BIST BSDL CODEC FIFO GPIO IEEE JEDEC JTAG LIFO Analog-to-digital conversion Arithmetic logic unit Background debug mode Built-in self test Boundary-scan description language Code/decode Digital-to-analog conversion Direct memory access Digital signal processing Effective address Extended data output (DRAM) First-in, first-out General-purpose Inter-integrated circuit Institute Electrical Electronics Engineers Instruction fetch pipeline Interrupt priority level Joint Electron Device Engineering Council Joint Test Action Group Last-in, first-out Meaning
I-xx
MCF5407 User's Manual
Table I-i. Acronyms Abbreviated Terms (Continued)
Term MBAR PCLK PLRU PQFP RISC UART Least recently used Least-significant byte Least-significant Multiple accumulate unit Memory base address register Most-significant byte Most-significant Multiplex operation Operand execution pipeline Program counter Processor clock Phase-locked loop Pseudo least recently used Power-on reset Plastic quad flat pack Reduced instruction computing Receive System integration module Start frame Test access port Transistor-to-transistor logic Transmit Universal asynchronous/synchronous receiver transmitter Meaning
Part MCF5407 Processor Core
I-xxi
I-xxii
MCF5407 User's Manual
Chapter ColdFire Core
This chapter provides overview microprocessor core MCF5407. chapter begins with description enhancements from Version (V3) ColdFire core, then fully describes programming model implemented MCF5407. also includes full description exception handling, data formats, instruction summary, table instruction timings.
Features Enhancements
MCF5407 first standard product contain Version ColdFire microprocessor core. create this next-generation, high-performance core, many advanced microarchitectural techniques were implemented. Most notable Harvard memory architecture, branch cache acceleration logic, limited superscalar dual-instruction issue capabilities, which together provide (Dhrystone 2.1) MIPS performance MHz. MCF5407 core design emphasizes performance backward compatibility, represents next step ColdFire performance roadmap. following list summarizes MCF5407 features: Variable-length RISC, clock-multiplied Version microprocessor core Revision ColdFire instruction architecture provides instructions improve performance code density independent, decoupled pipelines-four-stage instruction fetch pipeline (IFP) five-stage operand execution pipeline (OEP) increased performance conditional branch instructions Ten-instruction FIFO buffer provides decoupling between pipelines Limited superscalar design approaches dual-issue performance Sophisticated two-level branch acceleration mechanism with branch cache plus prediction table increased performance conditional instructions 32-bit internal address supporting Gbytes linear address space 32-bit data user-accessible, 32-bit-wide, general-purpose registers Supervisor/user modes system protection
Chapter ColdFire Core
Features Enhancements
Vector base register relocate exception-vector table Optimized high-level language constructs
2.1.1 Clock-Multiplied Microprocessor Core
MCF5407 incorporates clock-multiplying phase-locked loop (PLL). Increasing internal speed core also allows higher performance while providing system designer with easy-to-use lower speed system interface. frequency processor complex integer multiple external speed. Chapter "Electrical Specifications," lists supported clock ratios. processor, instruction data caches, integrated SRAMs, misalignment module operate higher speed clock (PCLK); other system integrated modules operate speed input clock (CLKIN). When combined with enhanced pipeline structure Version ColdFire core, processor local memories provide high level performance today's demanding embedded applications. PCLK disabled minimize dissipation when low-power mode entered. This described Section 7.2.3, "Reduced-Power Mode."
2.1.2 Enhanced Pipelines
prefetches instructions. decodes instructions, fetches required operands, then executes specified function. independent, decoupled pipeline structures maximize performance while minimizing core size. Pipeline stages shown Figure summarized follows: Four-stage (plus optional instruction buffer stage) Instruction address generation (IAG) calculates next prefetch address. Instruction fetch cycle (IC1) initiates prefetch processor's local instruction bus. Instruction fetch cycle (IC2) completes prefetch processor's instruction local bus. Instruction early decode (IED) generates time-critical decode signals needed OEP. Instruction buffer (IB) optional stage uses FIFO queue minimize effects fetch latency. Five-stage with optional processor write cycles. Decode stage (DS/secDS) decodes selects sequential instructions. Operand address generation (OAG) generates address data operand. Operand fetch cycle (OC1 OC2) fetch data operands. Execute (EX) performs prescribed operations previously fetched data operands.
MCF5407 User's Manual
Features Enhancements
Write data available (DA) makes data available operand write operations only. Store data (ST) updates memory element operand write operations only.
Instruction Fetch Pipeline Branch Cache Branch Accel. Instruction Memory
Operand Execution Pipeline
Internal
secDS
Misalignment Module Data (Operand) Memory
Debug
DDATA
DSCLK
PSTDDATA PSTCLK
Figure 2-1. ColdFire Enhanced Pipeline
Chapter ColdFire Core
Features Enhancements
2.1.2.1 Instruction Fetch Pipeline (IFP)
Because fetch execution pipelines decoupled ten-instruction FIFO buffer, prefetch instructions before needs them, minimizing stalls. 2.1.2.1.1 Branch Acceleration maximize performance conditional branch instructions, implements sophisticated two-level acceleration mechanism. first level 8-entry, direct-mapped branch cache with bits indicating four prediction states (strongly/weakly taken/not-taken) each entry. branch cache also provides association between instruction addresses corresponding target address. event branch cache hit, branch predicted taken, branch cache sources target address from stage back into redirect prefetch stream location. branch cache implements instruction folding, conditional branch instructions correctly predicted taken execute zero cycles. conditional branches with information branch cache, second-level, direct-mapped prediction table accessed. Each entries uses same 2-bit prediction mechanism branch cache. branch predicted taken, branch acceleration logic stage generates target address. Other change-of-flow instructions, including unconditional branches, jumps, subroutine calls, similar mechanism where calculates target address. performance subroutine return instruction (RTS) improved through four-entry, LIFO hardware return stack. cases, these mechanisms allow redirect fetch stream down predicted path well ahead instruction execution.
2.1.2.2 Operand Execution Pipeline (OEP)
instruction registers decode stage (DS) loaded from FIFO instruction buffer bypassed directly from instruction early decode (IED). consists two, traditional two-stage RISC compute engines with dual-ported register file access feeding arithmetic logic unit (ALU). compute engine (the address ALU) used typically operand address calculations; execution bottom used instruction execution. resulting structure provides Gbytes/S operand bandwidth MHz) compute engines supports single-cycle execution speeds most instructions, including load store operations most embedded-load operations. supports ColdFire Revision instruction set, which adds instructions improve performance code density. also implements following advanced performance features: Stalls minimized dynamically basing choice between address execution instruction execution pipeline state. address register renaming resources together execute heavily used opcodes forward results subsequent instructions with pipeline stalls.
MCF5407 User's Manual
Features Enhancements
Instruction folding involving MOVE instructions allows instructions issued cycle. resulting microarchitecture approaches full superscalar performance much lower silicon cost.
2.1.2.2.1 Illegal Opcode Handling conversion from M68000 code, every 16-bit operation word decoded ensure that each instruction valid. processor attempts execution illegal unsupported instruction, illegal instruction exception (vector taken. 2.1.2.2.2 Hardware Multiply/Accumulate (MAC) Unit optional unit Version that provides hardware support limited digital signal processing (DSP) operations used embedded code, while supporting integer multiply instructions ColdFire microprocessor family. features three-stage execution pipeline, optimized multiplies. tightly coupled OEP, which issue multiply with 32-bit accumulation plus fetch 32-bit operand single cycle. multiply with 32-bit accumulation requires three cycles before next instruction issued. Figure shows basic functionality MAC. full instructions provided signed unsigned integers plus signed, fixed-point fractional input operands.
Operand Operand
Shift 0,1,-1
Accumulator
Figure 2-2. ColdFire Multiply-Accumulate Functionality Diagram
provides functionality following three related areas, which described detail Chapter "Hardware Multiply/Accumulate (MAC) Unit." Signed unsigned integer multiplies Multiply-accumulate operations with signed unsigned fractional operands Miscellaneous register operations
Chapter ColdFire Core
Features Enhancements
2.1.2.2.3 Hardware Divide Unit hardware divide unit performs following integer division operations: 32-bit operand/16-bit operand producing 16-bit quotient 16-bit remainder 32-bit operand/32-bit operand producing 32-bit quotient 32-bit operand/32-bit operand producing 32-bit remainder
2.1.2.3 Harvard Memory Architecture
Harvard memory architecture supports increased bandwidth requirements processor pipelines providing separate configuration, access control, protection resources data (operand) instruction memory. MCF5407 separate instruction data buses processor-local memories, eliminating conflicts between instruction fetches operand accesses.
2.1.3 Debug Module Enhancements
ColdFire processor core debug interface supports system integration conjunction with low-cost development tools. Real-time trace debug information accessed through standard interface, which allows processor system debugged full speed without costly in-circuit emulators. MCF5407 debug unit compatible upgrade MCF52xx MCF53xx debug modules with added breakpoint registers support interrupt request servicing while emulator mode. On-chip breakpoint resources include following: Configuration/status register (CSR) Background debug mode (BDM) address attributes register (BAAR) attributes mask registers (AATR AATR1) Breakpoint registers. These used define triggers combining address, data, conditions single- dual-level definitions. They include following: Four breakpoint registers (PBR, PBR1, PBR2, PBR3) breakpoint mask register (PBMR) pairs data operand address breakpoint registers (ABHR/ABLR ABLR1/ABHR1) Data breakpoint registers (DBR DBR1) Data breakpoint mask registers (DBMR DBMR1) Trigger event registers. These programmed generate processor halt initiate debug interrupt exception. They include following: Trigger definition register (TDR) Extended trigger definition register (XTDR)
MCF5407 User's Manual
Programming Model
These registers accessed through dedicated debug serial communication channel, from processor's supervisor programming model, using WDEBUG instruction. MCF5407's interrupt servicing options during emulator mode allow real-time critical interrupt service routines serviced while processing debug interrupt event, thereby ensuring that system continues operate even during debugging. support program trace, Version debug module combines processor status debug data outputs into single 8-bit bus, PSTDDATA[7:0]. This along with PSTCLK output provide execution status, captured operand data, branch target addresses defining processor activity one-half CPU's clock rate. enhancements Revision debug specification fully backward-compatible with revisions. more information, Chapter "Debug Support."
Programming Model
MCF5407 programming model consists three instruction register groups-user, (also user-mode), supervisor, shown Figure 2-2. User mode programs restricted user instructions programming models. Supervisor-mode system software reference user-mode instructions registers additional supervisor instructions control registers. user supervisor programming model selected based SR[S]. following sections describe registers user, MAC, supervisor programming models.
Chapter ColdFire Core
Programming Model
Data registers
Address registers
User Registers
Stack pointer Program counter Condition code register status register accumulator mask register Status register Vector base register Cache control register Access control register (data) Access control register (data) Access control register (instruction) Access control register (instruction) base address register base address register Module base address register
MACSR MASK
Supervisor Registers
(CCR) Must zeros
CACR ACR0 ACR1 ACR2 ACR3 RAMBAR0 RAMBAR1 MBAR
Figure 2-3. ColdFire Programming Model
2.2.1 User Programming Model
Figure shows, user programming model consists following registers: general-purpose 32-bit registers, D0-D7 A0-A7 32-bit program counter 8-bit condition code register
2.2.1.1 Data Registers (D0-D7)
Registers D0-D7 used data registers bit, byte (8-bit), word (16-bit), longword (32-bit) operations. They also used index registers.
MCF5407 User's Manual
Programming Model
2.2.1.2 Address Registers (A0-A6)
address registers (A0-A6) used software stack pointers, index registers, base address registers used word longword operations.
2.2.1.3 Stack Pointer (A7,
processor core supports single hardware stack pointer (A7) used during stacking subroutine calls, returns, exception handling. stack pointer implicitly referenced certain operations explicitly referenced instruction specifying address register. initial value loaded from reset exception vector, address 0x0000. same register used user supervisor modes, used word longword operations. subroutine call saves program counter (PC) stack return restores from stack. status register (SR) saved stack during exception interrupt processing. return from exception instruction restores values from stack.
2.2.1.4 Program Counter (PC)
holds address executing instruction. sequential instructions, processor automatically increments When program flow changes, updated with target instruction. some instructions, specifies base address PC-relative operand addressing modes.
2.2.1.5 Condition Code Register (CCR)
CCR, Figure 2-4, occupies SR[7-0], shown Figure 2-3. CCR[4-0] indicator flags based results generated arithmetic operations.
Field Reset
Undefined
Figure 2-4. Condition Code Register (CCR)
Table describes fields.
Chapter ColdFire Core
Programming Model
Table 2-1. Field Descriptions
Bits Name Reserved, should cleared. Extend condition code bit. Assigned value carry arithmetic operations; otherwise affected specified result. Also used input operand multiple-precision arithmetic. Negative condition code bit. result set; otherwise cleared. Zero condition code bit. result equals zero; otherwise cleared. Overflow condition code bit. arithmetic overflow occurs, implying that result cannot represented operand size; otherwise cleared. Carry condition code bit. carry-out data operand occurs addition borrow occurs subtraction; otherwise cleared. Description
2.2.1.6 Programming Model
Figure shows registers portion user programming model. These registers described follows: Accumulator (ACC)-This 32-bit, read/write, general-purpose register used accumulate results operations. Mask register (MASK)-This 16-bit general-purpose register provides optional address mask instructions that fetch operands from memory. useful implementation circular queues operand memory. status register (MACSR)-This 8-bit register defines configuration unit contains indicator flags affected instructions. Unless noted otherwise, MACSR indicator flag settings based final result, that result final operation involving product accumulator.
2.2.2 Supervisor Programming Model
MCF5407 supervisor programming model shown Figure 2-3. Typically, system programmers supervisor programming model implement operating system functions provide
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