81200 Data Generator/Analyzer Platform Data Sheet Release Corresp

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Agilent 81200
81200 Data Generator/Analyzer Platform
Data Sheet Release Corresponds Release 3.5x)
Simplify your verification characterization process Push devices limit with comprehensive signal testing
Agilent 81200 data generator/analyzer platform right choice engineer manufacturing performing functional parametric tests digital subsystems, ICs, boards. 81200 allows thorough verification characterization digital devices throughout development cycle, thus reducing risks, costs time-to-market. 81200 modular system offering stimulus analyzer channels speed classes 200/330/675/2.700Mb/s.
Create virtually test signal need
Today's devices require very complex stimuli. With sequencing looping million vectors memory channel, create infinite variety stimulus signals. Choose from return-to-zero (RZ), non-return to-zero (NRZ) return-to-one (R1) formats. Create even more complex signals with Boolean channel addition including return-to-complement. internal editor includes memory-based PRBS/PRWS (pseudo-random binary/word sequence) stimulate traffic. 81200 ideal performing parallel error ratio measurements 2.7Gb/s stimulating digital port DAC.
Features Flexible real-time stimulus
response system Easy integration into standard environments 1Kb/s 2.7Gb/s Mbit memory channel 2-128 channels (doubles channels Mbit/s) Scaleable upgradeable through modules frontends timing resolution, edge placement accuracy Pattern formats: NRZ, DNRZ PRBS (Pseudo-Random-BitSequence) PRWS (PseudoRandom-Word-Sequence) 215- Sequencing with looping levels (nested loops) Branching internal external events Variable delays, levels transition times independently each channel Semi-automatic deskew eases test setup Measurement modes: capture, error capture, error count Measurement result displays: state list, waveform viewer, bit-error-rate Intuitive, Windows 4.0-based Remote Interfaces: LAN, GPIB SCPI,with based language, Plug Play drivers easy programming Agilent VEE, C/C++/Visual basic.
Figure 81200 data generator/analyzer platform
Platform Description
Agilent 81200 Data Generator/Analyzer Platform modular platform which tailored your specific needs, example, pulse generator, single multi-phase clock generator, data generator, data generator/analyzer system. indicated block diagram (Figure each input stimulated generator channel with independent data memory, timing output. device outputs sampled analyzer channel with individual input threshold, sampling point delay, memory, captured expected data. data generator analyzer channels synchronized common system clock pattern sequence. Initial easy because 81200 supplied ready- to-use. software hardware fully installed. only need connect computer peripherals (keyboard, mouse, monitor) mainframe. integration into standard test system required, please refer mainframes described next section configurating standalone system 81200. advantage standalone system that system arrives fully installed ready
Data Generator Generator data Timing, Clock Sequence
Comprehensive Characterization
Characterizing digital components usually very time-consuming task. make this task faster easier with 81200, consider wide range accessories Agilent 81200, which include:
Data Analyzer
Expected data
Captured data Timing, demux State list error rate
Clock
Sequence
Clock generation, central start stop sequence
External clock, ext. start stop, ext. reference
Figure Block Diagram 81200 functional layout
Easy Integration into Your Test Environment
81200 data generator/analyzer modules integrated easily into other VXI-based test platforms, C-size module configured work with 81200 system. Plug Play drivers facilitate easy programming test system integration. details integrating 81200 modules into standard test system, consult 81200 Data Generator/Analyzer Platform configuration guide, publication number 5965-3417E.
E4839A Test Fixture (see 59683580E more details) E4805B line trigger input signals (useful when branching external events (hardware signals) other then VXI-ECL trigger lines compare errors) E4805B De-skew probe (Comprises Agilent 1144A 880MHz active probe adapter (part number 12501200)). Agilent general accessories (cable kits, adapters etc). table Product Description Model Number Cable Kit: 4*SMA(m) SMA(m) meter Cable Kit: 10*SMA(m) Connector coax. cable, Torque wrench, SMA. Adapter Kit: SMA(m) Adapter Adapter (m)/BNC (f). Adapter right-angle (m-f). Adapter right-angle (m-m). Adapter SMA. Pulse adder/splitter, SMA. transition converter. transition converter. transition converter. Cable, GPIB. Agilent 15443A Agilent 15442A Agilent 15441A Agilent 8120-4948 Agilent 8710-1582 Agilent 15440A Agilent 1250-1200 Agilent 1250-1249 Agilent 1250-1397 Agilent 1250-1698 Agilent 11667B Agilent 15433B Agilent 15434B Agilent 15438B Agilent 10833B
General Accessories Cable (m), matched pair
Scaleable Upgradeable
81200 modular instrument, which tailored your specific needs. idea that system which configured such that matches your measurement task perfectly front-ends determine speed input/output capabilities your instrument. After have chosen front-ends, they placed data modules, which responsible sequencing, generation analysis data patterns. These modules plus least clock module, which generates system frequency instrument, installed mainframe (see figure more channels needed expander frames system, reach maximum number channels channels Gb/s, channels MHz, channels 200/330 Mb/s).
E4849C Mainframe
mainframe (figure offers eleven twelve slots 81200 modules, depending controller option which chosen. Controller options 2-slot (E4803A), IEEE 1394 link slot) control system from external (E4849C#013) offers empty slots clock module data modules. When 2-slot chosen system comes installed with Windows operating system E4873A user software. controller option, IEEE 1394.PC link (firewire) chosen, E4849C#013 should selected. There external offered, preinstalled with Windows 81200 (E4860AS#014) This configuration offers empty slots 81200 modules.
Figure E4949C mainframe
more modules expansion frames (E4860A#152) added house 22/23 data modules. E4849C#002 Option provides extender module (E1482B) that expander frames (E4848B) connected, order total data modules housed.
Data Modules determine -signal generation/analysis capabilities-speed channels Front-Ends determine -type (generator/analyzer) -speed channels
Clock module generates system clock distributes clock Data Modules
Figure Front-Ends, modules mainframe.
Front-End Module Overview
Each system needs least clock module E4805B) generate system clock and, least data generator/analyzer module E4841A, E4861A E4832A.
E4832A Data Generator/Analyzer Module
This module provides four slots generator analyzer front-ends, E4838A,E4835A. This module allows independant channles with PRBS/PRWS measurements 215-1 memory depth Mbit channel.
E4846A
Mbit/s, NRZ, dual channel, single ended, Vpp.
Analyzer Front-ends
E4863A
GSa/s, single channel,
E4805B Central Clock Module
This module provides clock sequence data flow control signals Data Modules: frequency resolution (instead four digits) synchronizes analyzer channels well generator channels drives E4841A, E4832A E4861A modules.
E4835A
MSa/s, this pair channels, bandwidth. fills adjacent slots E4832A provides independant channels.
E4861A Gb/s Data Generator/Analyzer Module
This module provides slots generator analyzer front-ends E4862A, E4863A. module provides independant channels.
E4847A
MSa/s, dual channel, Ohm/high-impedance selectable, bandwidth. mixed-logic requirements, slower faster frontends provide economic generatating control signals well data.
E4841A 333Mb/s Data Generator/Analyzer Module
This module provides four slots generator analyzer dual front-ends E4846A E4847A. With dual frontends module provide independant channels Mbit memory each.
Generator Front-ends E4862A
Gb/s, data 2.7GHz clock single channel, differential, Vpp.
E4838A
MHz, RZ/NRZ, single channel, differential, variable transition times, Vpp.
Table Module/Front-End Compatibility Modules Mb/s 675Mb/s Front-Ends E4841A E4832A E4835A E4838A E4846A E4847A E4862A E4863A
Gb/s E4861A
Technical Specifications
These specifications describe instrument's warranted performance. Non-warranted values described typical. specifications valid from ambient temperature after minute warm phase, with outputs inputs leves terminated with ground. Segment Types: pattern, pause, PRBS/PRWS*. Pause Segments: "PAUSE "PAUSE"1" levels selectable generator. PAUSE segment analyzer. Pattern Formats: NRZ, DNRZ, patterns selected, shown Figure facilitate complete pattern setup there different editing tools: Sequence Editor: (defines sequence) Data Editing: (defines segment content) fill pattern, complement, copy, cut, paste, move, insert, append, delete. Binary, octal, hexadecimal, decimal formats. Masking: single bits complete segments masked expected data memory. This allows specific areas ignored Compare Data mode.
Data Flow with nested loops Data Flow with Event handling
Channels Grouping
Number Channels: Powerful Sequencing: sequence channels depending succession segments, front-end type. shown Figure segment flow defined -Loops (finite, Grouping: connections infite,nested) events (branch, grouped named according goto, trigger). sequence applies requirements deviceto channels, different segunder- test facilitate setup. ment types different modules. Port Types: individual channels assigned data pulse Note: Generating segment ports. Pulse ports indepentypes PRBS pattern (userdent data sequence. Easy defined) same time setup clock possible requires different E4841A data generator/analyzer modules. Pattern Sequencing module generates PRBS Segment: memory pattern, other userdivided into loopable segments. defined pattern.
Block
Event
Block
Block
Infinite Event
Block
Block
Block
Block
Figure Sequencing capabilities
Figure Connection Window helps create virtual model your measurement set-up Figure Sequence Editor lets data segments, different looping levels, events
Figure 81200 Pattern Formats
Input/output Specifications
Front-ends: choose between three generator frontends (outputs) three analyzer front-ends (inputs) speed classes MHz, MHz, GHz. individual specifications following pages. Enable/connect: Each output/input switched individually, connect/ disconnect function allows disable/enable respectively, outputs inputs time. Connectors:
Channel Addition (for E4832A with E4838A only) Outputs logically combined, shown Figure This feature useful applications such clock/data recovery tests that need different pulse widths single channel return complement logic. With Analog channel adding -level- signal possible, Auxiliary Output: analyzer front-end E4863 provides auxilary output. differential signal from device-under- test single-endedthrough analyzer further usage, e.g. input jitter analyzer oscilloscope. Auxiliary output works input modes.
Figure Channel addition
Analog channel setupthe E4838A
signal
normal yellow complement green
signal
from waveform memory
added signal
normal complement blue
Analog channel Agilent E4838A Frontend
Lol+Lo2-Hil
Measurement Modes
Agilent 81200 Data Generator/ Analyzer Platform provides measurement modes when: more analyzer frontends fitted E4805B provides clock conditions case external clock). measurement modes detailed below. Capture mode: data bits sampled stored. Results displayed state list viewed using waveform viewer. Captured data edited, filed, exported, copied generator channels regeneration. Error Capture Mode: data bits sampled compared with expected pattern real time. total least 65,504 bytes captured before after error occurs. Masking possible individual bits pattern segments whole segments, that only bits interest captured. results stored viewed using state list waveform viewer. Errors highlighted. Error Count Mode: same Error Capture mode, except that errors counted instead being stored. possible watch result display real time while measurement running stimulus parameters varied. result displayed count (number bits), error count (number errors), bit-error-rate (BER).
Figure Bit-Error-Rate display shows actual error rate real-time.
Figure Waveform View
Waveform Viewer waveform viewer display Analyzer Data graphical way.
Signal Waveforms
following waveforms taken from different speed classes 81200 Family. pictures taken showing once Generator output scope second Analyzer Inputs connected idealsource with help opening measurement ParBERT 81250 measurement software) performance Analyzer recorded Frequency: Mb/s used E4805A+E4832A E4838A E4835A 2.5Gb/s used for: E4805A+ E4861A E4862A +E4863A Data :PRBS (stimulus expected) data Generator levels: Level -.4V, High levels Analyzer/ Opening: Single ended, terminated grd. Compared Bits Threshold Trigger Out: clock mode (625 MHz), levels O/1V
Scope settings:
Agilent 81600 with 83484A module -connected with cables -ext trigger from 81200 trigger -signal adjusted with Auto scale every measurement events
ParBERT Settings:
Generator Analyzer single ended mode, normal in/out used.
Ideal source:
transistion time 30ps, jitter <10ps levels -.5V/
Figure Signals E4832A with E4838A Generator E4835A Analyzer
Figure 13a) Signal E4861A with E4862A E4863A Analyzer
Technical specifications 2.7Gb/s
E4861A Generator Analyzer Module
This module holds combination analyzer front-end (E4863A generator front-end E4862A,).
Table E4861A Data Generator Timing Specifications amplitude, Frequency range* Clock/Data mode 333.334 MHz/Mb/s 2.70 Delay (between specified leading edge delay channels) fraction bits each channel Range (not limited period) Resolution Accuracy relative zero-delay placement. (From 20°C 35°C without autocal) typ. relative zerodelay placement temperature change within after autocalibration Skew between modules same typ. after deskewing customer type levels unchanged system frequency Pulse width period typ. clock mode
*See tables frontend deratings
Clock Module/Data Mode
generator operate clock mode data mode. Clock mode achieved when generator assigned Pulse Port. Data mode achieved when using Data Port. Clock mode there fixed duty cycle 50%. data mode there format with variable delay. analyzer works Data Port always with variable sampling delay. sampling delay analyzer consists elements: start delay fine delay. fine delay varied within period without stopping. Data Capabilities PRBS/PRWS memory based data defined segments. Segments assigned generator stimulating pattern, analyzer defines expected pattern where incoming data compared expected pattern setup with mask bits. segment length resolution resolution which length pattern segment mask set. maximum memory channel E4861A steps bits length 8192 kbits. segment length resolution coarse, memory depth frequency traded shown table
Table E4861A Analyzer Timing timing parameters meaW sured levels, terminated with Sample delay:= start delay fine delay, fine delay change without stopping Sampling rate* Same generator Fine delay range period Sampling delay range Same generator Sampling delay range Same generator Accuracy Same generator Resolution Same generator Skew Same generator
*See tables frontend deratings
E4861A Generator/Analyzer 2.7Gb/s Module
slots front-ends E4862A, E4863A
Figure E4861A Module
Table E4861A Pattern Sequencing Patterns: Memory based PRBS/PRWS Marker Density Errored Extended ones Clock patterns User 8Mbit table 2n-1, n=7, 1/8, 1/4, 1/2, 3/4, PRBS/PRWS 2n-1, n=7, 11,15 2n-1, n=7, 2n-1, n=7, Divide multiplied Data editor, file import
Sub-frequencies
applications requiring different frequencies fraction system clock, rate divided multiplied This influences dependency between segment length resolution maximum memory depth (see table
Table Data rate range, segment length resolution, available memory fine delay operation Data rate range Segment length Maximum memory Mbit/s resolution depth, bits 333.334.666.666 bits 2,097,152 666.667.1,333.333 bits 4,194,304 1,333.334.2,666.667 bits 8,388,608
general possible higher values segment length resolution also lower frequencies than indicated table
Table Parameters Analyzer Front-Ends E4863A GSa/s Number channels differential single ended Impedance typ. differential termination voltage switched Internal termination voltage -2.0 +3.0 (can switched Threshold voltage range -2.0 Threshold resolution Threshold accuracy Input sensitivity (single-ended 50mV differential) Minimum detectable typ. levels pulse width Maximum input voltage range Three ranges selectable: Maximum differential voltage 1.8V operating max. Phase Margin, with ideal input signal >1UI with generator E4862A 1UI-75 Auxiliary Swing: typ., coupled
Table Parameters Generator Front-ends E4862A 2.67Gbit/s (E4864A 1.33 GHZ) Outputs differential single ended Impedance Typ. Formats Clock: Duty cycle 50%±10% typ. Data: NRZ, DNRZ Output voltage window -2.00 3.00 3.00 4.5(terminated only) Maximum external voltage +4.7 External termination voltage Amplitude Resolution voltage CMOS 0.05 Vpp* Accuracy HiLevel/Amplitude ±2%±10 Short circuit current Transition times (20%-80%) 90ps typ@ ECL,LVDS 110ps Overshooting/ringing 20mV Jitter, Data mode <50ps peak-to-peak Clock mode <5ps, *does double into open, outputs switch off.
Input/Output
Addressable technologies
LVDS, (terminated with V/-2 PECL (terminated Analyzer input requires Bias Tee)
Generator Output
Generator output used single ended differential. Enable/Disable relays provide on/off switching. Switched will provide internal termination. recommended either turn externally terminate unused outputs. Generator outputs work into centre tapped termination differential termination. proper termination scheme chosen from editor adapt proper level programming.
Analyzer Input
analyzer channel operated -single ended normal -Single ended complement -differential termination there always connected programmable termination voltage. differential mode there additionally differential termination selectable. Independantly selected termination, select anaylsis incoming signal shall performed input, inverted input true differentially. connecting PECL recommended Bias Tee. Gb/s analyzer offers auxillary output, where differential input signal available single ended signal. bandwidth Output limited 2GHz.
Protection
Input Output Relays switch automatically, when maximum voltages will exceeded.
Compatibility
E4861A module will work also with front-ends E4864A E4865A 1.35Gb/s.
Technical specifications
E4832A Generator/Analyzer Module
This module holds combination analyzer front-ends (E4835A) four generator front-ends (E4838A),
E4832A Generator/Analyzer Module
Clock Module/Data Mode
generator operate clock mode data mode. Clock mode achieved when generator assigned Pulse Part. Data mode achieved with assigning data part. Clock mode there fixed duty cycle type 50%. data mode there NRZ,RZ,R1 formats with variable delay. analyzer works data part always with variable sampling delay. sampling delay consists elements: start delay fine delay. fine delay varied within period without stopping. Data Capabilities PRBS/PRWS memory based data defined segments. Segments assigned generator stimulating pattern, analyzer defines expected pattern where incoming data compared expected pattern setup with mask bits. segment length resolution resolution which length pattern segment set. maximum memory channel E4832A steps bits length 2048 Kbit. 16-bit segment length resolution coarse, memory depth frequency traded shown table Sub-frequencies: applications requiring different frequencies fraction system clock, ratio divided multiplied 2,4,8, This influences dependency between segment length resolution maximum memory depth (see table 12).
slots front-ends E4835A*, E4838A E4843A
Note:*occupy front-end slots E4832A
Figure E4832A Module
Table E4832A Data Generator Timing Specifications amplitude, fastest transition times) Frequency range 333.334 Delay range (not limited period) Resolution Accuracy relative zero-delay Placement*. Skew typ. after deskewing customer levels Pulse width specified width duty cycle Range 750ps (Period-750ps) Resolution Accuracy Duty Cycle 99%, subject width limits *Valid 15.35°C room temperature
Table E4832A Analyzer Timing timing parameters measured levels, terminated with Sample delay:= start delay fine delay, Fine delay changed without stopping** Sampling rate* Same generator Fine delay range period Sampling delay range Same generator Accuracy Same generator Resolution Same generator Skew Same generator
*See tables frontend deratings
**Conditions: frequency 20.8 using finest segment length resolution.
Table Pattern Sequencing features E4832A Patterns: Memory based 2Mbit table PRBS/PRWS 2n-1, n=7, Marker Density Errored Extended ones Clock patterns User 1/8, 1/4, 1/2, 3/4, PRBS/PRWS 2n-1, n=7, 2n-1, n=7, 2n-1, n=7, Divide multiplied Data editor, file import
Input/Output
Addressable technologies
LVDS, (P)ECL, TTL, CMOS
Analyzer Input
analyzer channel operated -single ended normal -Single ended complement -differential termination there always connected programmable termination voltage. differential mode there additionally differential termination selectable. Independantly selected termination, select anaylsis incoming signal shall performed input inverted input true differentially.
Table Data rate range, segment length resolution, available memory fine delay operation Data rate range Segment length Maximum memory Mbit/s resolution depth, bits 20.834.41.666 bits 131,008 41.667.83.333 bits 262,016 83.334.166.666 bits 524,032 166.667.333.333 bits 1,048,064 333.334.666.667 bits 2,097,152
general possible higher values segment length resolution also lower frequencies than indicated table. this case fine delay function auto-sychronisation function unavailable.
Table Level Parameters Differential Generator Front-end E4838A Number channels differential Impedance typ. Data formats NRZ, DNRZ Output voltage window -2.2 +4.4 (doubles into open max. 5Vpp) Amplitude /Resolution 0.1V 3.50 10mV Level accuracy \25mV typ. after settling time LVDS/(P)ECL typ. after settling time Variable transition time range (10-90% amplitude) Accuracy \100 LVDS /(P)ECL (20-80% amplitude) 0.35 Overshoot/ringing (|5% typ). Jitter Data mode |100 peak peak typ) Clock mode typ. Channel addition analog
Generator Output
Generator output used single ended differential. Enable/Disable realys provide on/off switching. Switched will provide internal termination. recommended either turn externally terminate unused outputs. Generator outputs work into centre tapped termination differential termination. proper termination scheme chosen from editor adapt proper level programming.
Table Differential Analyzer Front-Ends E4835A1, MSa/s Number channels differential single ended (switchable) Impedance typ. differential termination voltage switched Termination voltage (can switched off) -2.0 Threshold voltage range/Threshold accuracy -2.00 +4.50 \20mV Threshold resolution Input sensitivity Differential Single-ended Minimum detectable pulsewidth typ. levels Input voltage range ranges selectable: Phase Margin, with ideal input signal }1UI with E4838A Generator }1UI -180
1occupy front-end slots E4832A. E4835A contains front-ends (E4835AZ) common data back end. this document refer front-end E4835A.
Compatibility
E4832A module also equipped with E4843A generator frontend.
Technical specifications 333Mb/s
E4841A Mb/s Generator/Analyzer Module
Table E4841A Data Generator Timing Specifications amplitude, fastest transition times) Frequency range* 1.000 333.333 This module holds Delay range (not limited period). combination four f<333.334 kHz" max. delay period. analyzer front-ends (E4847A) Resolution f<170 0.05% period generator front-ends Accuracy relative zero delay (E4846A). These dual channel placement. f<170 tolerance increases front-ends make channels 0.1% each slot, eight chanSkew typ. after deskewing customer levels nels module. E4841A Pulse width specified width duty cycle orignally module, Range* 750ps [Period-750ps] with dual fronResolution tends maximum data rate Accuracy* limited Mb/s. Duty Cycle subject width limits Mb/s operation E4832A tables front-end deratings recommended. Segment length resolution: This resolution which length pattern segment set. maximum memory channel E4841A steps bits length Kbit. 8-bit segment length resolution coarse, memory depth frequency traded shown table Sub-frequencies: applications requiring different frequencies fraction system clock, ratio divided multiplied 2,4,8. This influences dependency between segment length resolution maximum memory depth (see table 18). Using Analyzer, error capture mode memory half value shown. (table Table E4841A Analyzer Timing timing parameters measured levels, terminated with Sampling rate* Same generator Sampling delay range* Same generator limited system period within front-end. Accuracy Same generator Resolution Same generator Skew* Same generator *See tables front-end deratings
E4841A Generator/Analyzer Module
DATA GEN./ANALYZER
Failed
Access
FRONT-END
FRONT-END
FRONT-END
FRONT-END
slots frontends E4846A E4847A
E4841A
Figure
Table Pattern Sequencing features E4841A Patterns: Memory based Mbit) table PRBS/PRWS 2n-1,n=7,9,10,11,15 Clock patterns User Divide multiple 2,4,8, (16) Data editor, file import
Input/Output Addressable technolgies TTL, 3.3V CMOS, (P)ECL Analyzer Output -single-ended -High impedence (10K) sampling point dual channel analyzer input individually adjusted within system period. Generator output -single ended outputs -enable/disable realais Delay range channels within front-end sued over full range. output into open. Into open voltage range doubles Compatibilty E4841A used with E4843A, E4844A, E4837A, frontends 667MHz with memory. Stimulation/Measurement E4847A high-impedance analyzer front-end assists measurements bidirectional ports. parallel with generator front-end, impedance presented connector 15440A Parts) required.
Table Data rate range, segment length resolution, available memory synchronisation fine delay operation Data rate range Segment length Maximum memory Mbit/s resolution depth, bits 20.834.41.666 bits 65,504 41.667.83.333 bits 131,008 83.334.166.666 bits 262,016 166.667.333.333 bits 524,032
general possible higher values segment length resolution lower frequency than indicated table
Table Level Parameters dual Generator Front-End E4846A Mbit/s E4846A Outputs/Source Resistance single-ended Maximum Frequency Mbit/s (and Data Formats) (NRZ, DNRZ) Output Voltage Window -1.75 +3.50 doubles into open Addressable Technologies TTL, (terminated with V/-2 PECL (terminated Amplitude/Resolution 0.30 3.50 Vpp/10mV doubles into open Accuracy Levels Short Circuit Current 70mA max., max. Maximum External Voltage termination Voltage Range Transition Times Constant slew rate 20-80% levels |1.2 typ. 10-90% ampl |2.5 typ. Overshoot/Ringing Droop |20%, |10% Minimum Pulsewidth ELC:| typ. Vpp: |4.0
Table Parameters Analyzer Front-End E4847A MSa/s, dual channel Analog Bandwidth typ. Number Channels independent levels Typical Impedance parallel Termination Voltage -2.1 +3.1 selected) Number thresholds input Threshold voltage Range (into -2.10 +5.10 Threshold Resolution Threshold Accuracy \20mV Input Sensitivity mVpp Minimum Detectable Pulsewidth typ. levels
Module Descriptions
Each system consists least clock module (E4805B) clock data generator module (E4831A), which generates system clock least generator/ analyzer module (E4832A) 2.67 generator/analyzer module (E4861A) which houses frontends. module E4831A intended generator only systems.
Table E4805B Central Clock Specifications Frequency range(1) (can entered period frequency)
Resolution Accuracy
limited modules front-ends resolution From Gb/s resolution From Gb/s resolution
1kHz 666.66700 E4861A will with Clock module range 2.67GHz, E4832A range MHz. with internal reference
E4805B Central Clock Module/E4831A Clock Data Generator Module
E4805B E4831A include (Phase-Lock-Loop) frequency generator provide system clock. Depending frequency chosen data module E4841A clocked ratio 1,2,4, times higher lower than system clock. External start/stop: E4805B started, stopped gated selected active input level. With E4861A there only start mode. Ext. Clock/Ext. Reference: This input runs 81200 synchronously with ext. clock, when more accurate reference needed than internal oscillator. Usage continuous clock necessary. Burst clock cannot used external clock. Maximum external clock 2.67 GHz. (Note: improvement jitter specifications will achieved). Guided deskew: Individual semi-automatic deskew channel. deskew probe E4805B #003 allows deskew DUT's (Device Under Test) pins with connected. Deskew range 20ns. Interaction with External Environment (Instruments DUTs) (only with E4805B Central Clock Module): Agilent 81200 react user-defined events, which result simply trigger pulse, example, also change pattern sequence, details table Figure
Table External input ext.clock/ext.ref. Input E4805B Zin/Termination voltage /-2.10 3.30 Sensitivity/max levels mVpp Coupling Ext. Input: -1.40 +3.70 Ext. Clock/Ext. Input transitions/slope Ext. Input active edge selectable Input frequency/period Ext. Clock kHz-2.67 Ext. 1*,2*,5, Required duty cycle Latency(typical): trigger Output channel output Ext. input 16ns clock** 46ns clock** Ext. clock 15ns 45ns Ext.colck Input multiplier 1,2.255 expander frame used *Jitter performance degraded
E4805B Central Clock Module
Clock outputs modules
Clock Expander Frame E4848B
Clock/Ref. Input External input Trigger output
Deskew Probe
Table Trigger output characteristics E4805B Trigger output signals Clock mode sequence mode MHz). sequence mode pulse mark start segment Output impedance Output level (frequency |180 MHz), GND, GND/-2 PECL Trigger advance typ. between trigger output data output/sampling point (delay zero both cases) Maximum input voltage +3.3 Jitter (int.reference/int. (typ. 5ps) clock, measured TRIGGER OUTPUT).
Table E4805B Sequencing Number Segments (every segment looped once) segment looped) Looping levels nested loops plus optional infinite loop Loops independently from repetitions Start/stop External input, manual, programmed Event handling React internal external events. Details table
Table Event handling E4805B Usage events Description Stop data Very useful production tests during interaction with other test sequences: equipment Data segment switching: Based events. Certain portions overall sequence executed Trigger external devices: External instruments like oscilloscope triggered, sample waveform error location. integration: 81200 started from platform like test system complementing missing tester functionalities. result: pass/fail information returned back platform. Match loop: Repetition data segment long defined event occurs. Useful device sychronization, PLL-based device. Event trigger sources Events defined combination following sources. maximum events defined. option 8-line trigger input signals trigger lines capture error/or error detected analyzer channels command control: event trigger command issued locally remotely. Reactions event data segment immediately deferred combination segment jump trigger pulse trigger output E4805B Central Clock Module trigger lines
General Characteristics
Mainframes: table Save/recall: Pattern segments, settings complete settings plus segments saved recalled. number settings that stored limited only internal disk space. Vector import/export: Pattern files imported/exported inch floppy disk, GPIB (IEEE 488.2). File format ASCII using STIL subset. Programming interface: GP-IB (IEEE 488.2) LAN. interface applications such Visual Basic, must installed. Agilent 81200 Plug Play drivers easy programming available. Programming language: SCPI 1992.0 Programming times: Vector transfer from memory hardware depends amount data. Also table On-line help: Context-sensitive. Table Programming Times 81200 Programming time Change levels typ. Change delay ms.typ. applicable mode. Change period mstyp. E4805B with E4832A. applicable mode. Increases with number modules less than proportional. Stop start Download values: System with channels, <1.5 100,000 each System with channels, 1Mbit each System with channels, Mbit each Print-on-demand: Getting started programming guides printed from .pdf files included 81200 software. Self-test: Module system selftests initiated. Agilent Technologies Quality Standards 81200 produced 9001 international quality system standard part Agilent Technologies commitment continually increase customer satisfaction through improved quality control.
Modules
Module size: C-size, slot. Module type: Register-based; requires 81200 user software E4873A supplied with mainframes. Weight: (including front-ends) Net: 2kg. Shipping: Re-calibration period: years recommended.
Table General Mainframe Characteristics E4849C mainframe Factory-installed items E8403A 13-slot C-size frame, Controller options:
E4848B expander frame E8403A 13-slot C-size frame, E1482B extender module, meter INTX cable
2-slot E9851A
with additional memory (total with Windows 4.0, E4873A Agilent 81200 UserSoftware installed IEEE 1394 link (E8491B) with installation License CD-ROM E4873A 81200 User Software Number slots 11(for controller option 012) 81200 modules 12(for controller option 013) (subtract expander frame connected) Operating temperature 10°C 40°C Storage temperature -20°C 60°C Humidity rel. humidity 40°C Power requirements 90-264 Vac, \10%, 44-66 90-264 Vac, \10%, 300-440 (not recommended, leakage current exceed safety limits }132 Vac) Power available modules 90-110 supplies 1000 110-264 supplies Electromagnetic compatibility 55011/CISPR group class Acoustic noise (56) sound pressure (high) speed Safety 348, 1244, 22.2 #231, CE-mark Physical dimensions W:424.5mm H:352 Weight (Net) 26.8 25.3kg Weight (shipping max.)
Table Volts +24V +12V -5.2V -12V Modules (These specifications take already power specifications front-ends into account) E4805 Current 0.15A 0.2A 1.8A 1.4A 3.8A 0.2A Central Clock Dynamic Current 0.015A 0.02A 0.18A 0.14A 0.38A 0.02A Module E4861A 2.67 Gb/s Current Gen./An. Module Dynamic Current 0.10A 0.01A 0.50A 0.05A 5.20A 0.52A 1.80A 0.18A 4.00A 0.40A 0.90A 0.09A
Note: module E4841A E4832A power specifications chosen front-ends E4846A, E4847A, E4835A E4838A have added power specifications E4841A E4832A module overall value power specifications E4841A Gen./An. Module E4832A Gen./An. Module Front-Ends E4835A Differential Analyzer Msa/s Current Dynamic Current 0.03 0.003A 2.90A 0.290A 0.85A 0.085A 4.20A 0.420A 0.04A 0.004A
Current Dynamic Current
0.10A 0.010A
0.10A 0.01A
2.60A 0.26A
0.60A 0.06A
3.60A 0.36A
0.10A 0.01A
Current Dynamic current
0.2A 0.02A
1.2A 0.12A
0.2A 0.02A
0.3A 0.03A
0.3A 0.03A
E4838A Current Differential Dynamic Current Generator MHz, var. Slopes E4846A Mbit/s Dual Generator E4847A MSa/s Dual Analyzer Current Dynamic Current
0.45 0.045
0.18 0.018
0.07 0.007
0.38 0.038
0.41 0.041
0.210A 0.021A
0.025A 0.003A
0.050A 0.005A
0.120A 0.300A 0.0120A 0.030A
Current Dynamic Current
0.1A 0.01A
0.9A 0.09A
0.06A 0.006A
0.05A 0.005A
0.06A 0.006A
Table Cooling requirements modules E4805B E4861A with front-ends installed Flow Modules rise Liter/s E4850B 0.25 E4861A
Table Cooling requirements module E4841A with front-ends installed Flow Module 15°C rise Liter/s E4841A E4832A
Related Literature Agilent 81200 Data Generator/Analyzer Platform,
brochure Agilent 81200 Data Generator/Analyzer Platform configuration guide Agilent E4839A Test Fixture 5968-3580E transfer Data between Design, Simulation Agilent 81200 Data Generator Analyzer Flat Panel Display Link Test 5968-8028E Agilent Data Generator/Analyzer Platform Together with signal Integrity Analysis Agilent 81200 Data Generator/Analyzer Platform, Start Assistance
Pub. Number
5980-0488E 5965-3417E
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Agilent Technologies, Inc. 2004 Printed Netherlands, 29th April 2004 5965-3415E
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