3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE WITH VOLT TOLERANT

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3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE WITH VOLT TOLERANT

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IDT74LVC86A 3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE WITH VOLT TOLERANT
MICRON CMOS Technology 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range CMOS power levels (0.4µ typ. static) Rail-to-Rail output swing increased noise margin inputs, outputs, I/Os tolerant Supports insertion Available SOIC, SSOP, TSSOP packages
IDT74LVC86A
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
This quadruple 2-input exclusive-OR gate built using advanced dual metal CMOS technology. LVC86A performs Boolean function positive logic. common application true/ complement element. inputs low, other input reproduced true form output. inputs high, signal other input reproduced inverted output. LVC86A been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. Inputs driven from either 3.3V devices. This feature allows this device translator mixed 3.3V/5V system environment.
High Output Drivers: ±24mA Reduced system switching noise
APPLICATIONS:
3.3V mixed voltage systems Data communication telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
CONFIGURATION
FUNCTION TABLE (EACH GATE)(1)
Inputs
NOTE: HIGH Voltage Level Voltage Level
SOIC/ SSOP/ TSSOP VIEW
Outputs
DESCRIPTION
Names Data Inputs Data Outputs Description
logo registered trademark Integrated Device Technology, Inc.
©1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4725/1
IDT74LVC86A 3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TSTG IOUT Description Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Current through each -0.5 +6.5 +150 ±100 Unit
CAPACITANCE +25°C, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NOTE: applicable device type.
NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40°C +85°C
Symbol IOZH IOZL IOFF ICCL ICCH ICCZ High Impedance Output Current (3-State Output pins) Input/Output Power Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 5.5V 2.3V, -18mA 3.3V 3.6V, -0.7 -1.2 3.6V 5.5V Parameter Input HIGH Voltage Level Input Voltage Level Input Leakage Current 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 5.5V Test Conditions Min. Typ.(1) Max. Unit
Quiescent Power Supply Current Variation
input 0.6V, other inputs
NOTE: Typical values 3.3V, +25°C ambient.
IDT74LVC86A 3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage 2.3V 2.3V 2.7V Output Voltage 2.3V 3.6V 2.3V 2.7V 24mA 0.1mA 12mA 12mA 24mA Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. Max. 0.55 Unit
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 3.3V 0.3V, 25°C
Symbol Parameter Power Dissipation Capacitance Gate Test Conditions 0pF, 10Mhz Typical Unit
SWITCHING CHARACTERISTICS(1)
2.7V Symbol tPLH tPHL tSK(o) Parameter Propagation Delay Output Skew(2) Min. Max. 3.3V 0.3V Min. Max. Unit
NOTES: TEST CIRCUITS WAVEFORMS. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74LVC86A 3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
TEST CIRCUITS WAVEFORMS TEST CONDITIONS
Symbol VLOAD VCC(1)= 2.5V±0.2V VCC(2)= 3.3V±0.3V 2.7V Unit
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
Propagation Delay
QUAD Link
Pulse Generator
VLOAD Open ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 tPHZ tPLZ DISABLE VLOAD/2
QUAD Link
D.U.T.
VOUT
QUAD Link
Test Circuit Outputs
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns. Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
Enable Disable Times
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other Tests Switch VLOAD Open
DATA INPUT TIMING INPUT SYNCHRONOUS CONTROL ASYNCHRONOUS CONTROL
tREM
INPUT
tPLH1
tPHL1
QUAD Link
Set-up, Hold, Release Times
LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE
QUAD Link
OUTPUT
OUTPUT tPLH2 tPHL2
tSK(x) tPLH2 tPLH1 tPHL2 tPHL1
QUAD Link
Output Skew tSK(X)
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
Pulse Width
IDT74LVC86A 3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
ORDERING INFORMATION
Device Type Package Temp. Range
Small Outline Shrink Small Outline Package Thin Shrink Small Outline Package Quadruple 2-Input Exclusive-OR Gate, ±24mA -40°C +85°C
CORPORATE HEADQUARTERS 2975 Stender Santa Clara, 95054
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Tech Support: logichelp@idt.com (408) 654-6459

3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE WITH VOLT TOLERANT

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