This Hynix unbuffered Slim Outline Dual In-Line Memory Module(DIMM) se
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200pin Unbuffered DDR2 SDRAM SO-DIMMs based ver.
This Hynix unbuffered Slim Outline Dual In-Line Memory Module(DIMM) series consists ver. DDR2 SDRAMs Fine Ball Grid Array(FBGA) packages 200pin glass-epoxy substrate. This Hynix ver. based Unbuffered DDR2 SO-DIMM series provide high performance byte interface 67.60mm width form factor industry standard. suitable easy interchange addition.
JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V 0.1V Power Supply inputs outputs compatible with SSTL_1.8 interface Posted Programmable Latency (Off-Chip Driver Impedance Adjustment) (On-Die Termination) Fully differential clock operations Programmable Burst Length with both sequential interleave mode Auto refresh self refresh supported 8192 refresh cycles 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: ball FBGA 67.60 30.00 form factor Lead-free Products RoHS compliant
ORDERING INFORMATION
Part Name HYMP112S648-E3/C4 HYMP325S64M8-E3/C4 HYMP112S64P8-E3/C4 HYMP325S64MP8-E3/C4 Density Organization 128Mx64 256Mx64 128Mx64 256Mx64 DRAMs ranks Materials Leaded Leaded Lead free Lead free
This document general product description subject change without notice. Hynix Semiconductor does assume responsibility circuits described. patent licenses implied. Rev. Feb. 2005
1200pin Unbuffered DDR2 SDRAM SO-DIMMs SPEED GRADE PARAMETERS
(DDR2-400) Speed@CL3 Speed@CL4 Speed@CL5 CL-tRCD-tRP 3-3-3 (DDR2-533) 4-4-4 Unit Mbps Mbps Mbps
ADDRESS TABLE
Density Organization Ranks 128M 256M SDRAMs 128Mb 128Mb DRAMs row/bank/column Address 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 14(A0~A13)/3(BA0~BA2)/10(A0~A9) Refresh Method 64ms 64ms
Rev. Feb. 2005
1200pin Unbuffered DDR2 SDRAM SO-DIMMs DESCRIPTION
Symbol Type Polarity Cross Point Description system clock inputs. adress commands lines sampled cross point CK[1:0], CK[1:0] Input rising edge falling edge Delay Locked Loop(DLL) circuit driven from clock inputs output timing read operations synchronized input clock. CKE[1:0] Input Active High Activates DDR2 SDRAM signal when high deactivates signal when low. deactivating clocks, initiates Power Down mode Self Refresh mode. Enables associated DDR2 SDRAM command decoder when disables S[1:0] Input Active Active command decoder when high. When command decoder disabled, commands ignored previous operations continue. Rank selected Rank selected RAS, CAS, BA[2:0] ODT[1:0] Input Input Input Active High When sampled cross point rising edge falling edge CAS, define operation excecuted SDRAM. Selects which DDR2 SDRAM internal bank four eight activated. Asserts on-die termination signals enabled DDR2 SDRAM mode register. During Bank Activate command cycle, difines address when sampled cross point rising edge falling edge During Read Write command cycle, defines column address when sampled cross point rising edge falling edge addition column address, used A[9:0], A10/AP, A[15:11] Input invoke autoprecharge operation burst read write cycle. high., autoprecharge selected BA0-BAn defines bank precharged. low, autoprecharge disabled. During Precharge command cycle., used conjunction with BA0-BAn control which bank(s) precharge. high, banks will precharged regardless state BA0-BAn inputs. low, then BA0-BAn used define which bank precharge. DQ[63:0] DM[7:0] In/Out Input Active High Data Input/Output pins. data write masks, associated with data byte. Write mode, operates byte mask allowing input data written blocks write operation high. Read mode, lines have effect. data strobe, associated with data byte, sourced whit data transfers. Write mode, data strobe sourced controller centered data window. DQS[7:0], DQS[7:0] In/Out Cross point Read mode, data strobe sourced DDR2 SDRAMs sent leading edge data window. signals complements, timing relative crosspoint respective DQS. module operated single ended strobe mode, signals must tied system board DDR2 SDRAM mode registers programmed approriately. VDD, VDDSPD,VSS SA[1:0] TEST Supply In/Out Input Input In/Out Power supplies core, I/O, Serial Presense Detect, ground module. This bidirectional used transfer data into EEPROM. resister must connected pull This signals used clock data into EEPROM. resistor connected from pull Address pins used select Serial Presence Detect base address. TEST reserved analysis tools connected normal memory modules(SODIMMs).
Rev. Feb. 2005
1200pin Unbuffered DDR2 SDRAM SO-DIMMs ASSIGNMENT
Front Side VREF DQS0 DQS0 DQS1 DQS1 DQ10 DQ11 DQ16 DQ17 DQS2 Back Side DQ12 DQ13 DQ14 DQ15 DQ20 DQ21 Front Side DQS2 DQ18 DQ19 DQ24 DQ25 DQ26 DQ27 CKE0 Back Side DQ22 DQ23 DQ28 DQ29 DQS3 DQS3 DQ30 DQ31 NC/A15 NC/A14 Front Side A10/AP NC/S1 DQ32 DQ33 DQS4 DQS4 DQ34 DQ35 DQ40 DQ41 Back Side ODT0 DQ36 DQ37 DQ38 DQ39 DQ44 DQ45 DQS5 DQS5 Front Side DQ42 DQ43 DQ48 DQ49 DQS6 DQS6 DQ50 DQ51 DQ56 DQ57 DQ58 DQ59 VDDSPD Back Side DQ46 DQ47 DQ52 DQ53 DQ54 DQ55 DQ60 DQ61 DQS7 DQS7 DQ62 DQ63
NC,TEST
NC/ODT1
NC/CKE1
Location
Front
Back
Rev. Feb. 2005
1200pin Unbuffered DDR2 SDRAM SO-DIMMs FUNCTIONAL BLOCK DIAGRAM
1GB(128Mbx64) HYMP112S648-E3/C4
ODT1
CKE1
CKE0 DQS0
DQS0
DQS1
DQ15
DQS2
DQ23
DQS3
DQ31
DQS4
DQS5
DQS6
DQS0
SDRAMS SDRAMS SDRAMS SDRAMS SDRAMS
Rev. Feb. 2005
1200pin Unbuffered DDR2 SDRAM SO-DIMMs FUNCTIONAL BLOCK DIAGRAM
2GB(256Mbx64) HYMP351S64M8-E3/C4
10+/-5
SDRAM SDRAM SDRAM SDRAM SDRAM
Serial
loads
Serial SDRAM
/CK0
loads loads
SDRAM SDRAM
Notes Resistor values
/CK1
loads
Rev. Feb. 2005
1200pin Unbuffered DDR2 SDRAM SO-DIMMs ABSOLUTE MAXIMUM RATINGS
Parameter Voltage relative Voltage VDDQ relative Voltage relative Storage Temperature Storage Humidity(without condensation) Notes: Stress greater than those listed cause permanent damage device. This stress rating only, device functional operation above conditions indicated implied. Expousure absolute maximum rating ditions extended periods affect reliablility. Symbol VDDQ VIN, VOUT TSTG HSTG Value +100 Unit
Note
OPERATING CONDITIONS
Parameter DIMM Operating temperature(ambient) DIMM Barometric Pressure(operating storage) DRAM Component Case Temperature Range Notes: 9850 DRAM case temperature Above 85oC, Auto-Refresh command interval reduced tREFI=3.9us. Measurement conditions TCASE, please refer JEDEC document JESD51-2. Symbol TOPR PBAR TCASE Rating ~+95 Units
Notes
Pascal
OPERATING CONDITIONS (SSTL_1.8)
Parameter Power Supply Voltage Input Reference Voltage EEPROM Supply Voltage Termination Voltage Symbol VDDQ VREF VDDSPD 0.49 VDDQ VREF-0.04 0.51 VDDQ VREF+0.04 Unit Note
Notes: VDDQ must less than equal VDD. Peak peak noise VREF exeed +/-2% VREF(dc) transmitting device must track VREF receiving device.
Rev. Feb. 2005
1200pin Unbuffered DDR2 SDRAM SO-DIMMs INPUT LOGIC LEVEL
Parameter Input High Voltage Input Voltage Symbol VIH(DC) VIL(DC) VREF 0.125 -0.30 VDDQ VREF 0.125 Unit Note
INPUT LOGIC LEVEL
Parameter Input logic High Input logic Symbol VIH(AC) VIL(AC) VREF 0.250 VREF 0.250 Unit Note
INPUT TEST CONDITIONS
Symbol VREF VSWING(MAX) SLEW Notes: Input waveform timing referenced input signal crossing through VREF level applied device under test. input signal minimum slew rate maintained over range from VREF VIH(ac) rising edges range from VREF VIL(ac) falling edges shown below figure. timings referenced with input waveforms switching from VIL(ac) VIH(ac) positive transitions VIH(ac) VIL(ac) negative transitions. Condition Input reference voltage Input signal maximum peak peak swing Input signal minimum slew rate Value VDDQ Units V/ns Notes
VSWING(MAX)
VDDQ VIH(ac) VIH(dc) VREF VIL(dc) VIL(ac)
delta Falling Slew VREF VIL(ac) delta
delta Rising Slew VIH(ac)min VREF delta
Figure Input Test Signal Waveform>
Rev. Feb. 2005
1200pin Unbuffered DDR2 SDRAM SO-DIMMs Differential Input logic Level
Symbol (ac) (ac) Parameter differential input voltage differential cross point voltage Min. VDDQ 0.175 Max. VDDQ VDDQ 0.175 Units Note
VIN(DC) specifies allowable execution each input differential pair such DQS, DQS, LDQS, LDQS, UDQS UDQS. VID(DC) specifies input differential voltage |VTR -VCP required switching, where true input (such DQS, LDQS UDQS) level complementary input (such DQS, LDQS UDQS) level. minimum value equal VIH(DC) VIL(DC).
VDDQ VSSQ
Differential signal levels
Notes: VID(AC) specifies input differential voltage |VTR -VCP required switching, where true input signal (such DQS, LDQS UDQS) complementary input signal (such DQS, LDQS UDQS). minimum value equal IH(AC) VIL(AC). typical value VIX(AC) expected about VDDQ transmitting device VIX(AC) expected track variations VDDQ VIX(AC) indicates voltage whitch differential input signals must cross.
Crossing point
DIFFERENTIAL OUTPUT PARAMETERS
Symbol (ac) Parameter differential cross point voltage Min. VDDQ 0.125 Max. VDDQ 0.125 Units Note
Notes: typical value VOX(AC) expected about VDDQ transmitting device VOX(AC) expected track variations VDDQ VOX(AC) indicates voltage whitch differential output signals must cross.
Rev. Feb. 2005
1200pin Unbuffered DDR2 SDRAM SO-DIMMs OUTPUT BUFFER LEVELS OUTPUT TEST CONDITIONS
Symbol VOTR Notes: VDDQ device under test referenced. Parameter Output Timing Measurement Reference Level SSTL_18 VDDQ Units Notes
OUTPUT CURRENT DRIVE
Symbol IOH(dc) IOL(dc) Parameter Output Minimum Source Current Output Minimum Sink Current SSTl_18 13.4 13.4 Units Notes
Notes: VDDQ VOUT 1420 (VOUT VDDQ)/IOH must less than values VOUT between VDDQ VDDQ VDDQ VOUT VOUT/IOL must less than values VOUT between value VREF applied receiving device values IOH(dc) IOL(dc) based conditions given Notes They used test device drive current capability ensure plus noise margin minus noise margin delivered SSTL_18 receiver. actual current values derived shifting desired driver operating point along load line define convenient driver current measurement.
Rev. Feb. 2005
1200pin Unbuffered DDR2 SDRAM SO-DIMMs Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25. f=1MHz HYMP112S64[P]8
CKE, ODT,CS Address, RAS, CAS, DQS, Symbol Unit
HYMP351S64M[P]8
CKE, ODT,CS Address, RAS, CAS, DQS, Notes: Pins under test tied GND. These value guaranteed design tested sample basis only. Symbol Unit
Rev. Feb. 2005
1200pin Unbuffered DDR2 SDRAM SO-DIMMs SPECIFICATIONS
(TCASE 95oC)
1GB, 128M DIMM HYMP112S64[P]8
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4R IDD4W IDD5B IDD6 IDD6(L) IDD7 E3(DDR2 400@CL3) 1040 1120 2160 1920 C4(DDR2 533@CL 1360 1440 2160 2400 Unit note
2GB, 256M DIMM HYMP325S64M[P]8
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4R IDD4W IDD5B IDD6 IDD6(L) IDD7 Notes: IDD6 current values guaranted Tcase max. E3(DDR2 400@CL 1280 1360 1520 1600 2640 2400 C4(DDR2 533@CL 1440 1520 1120 1920 2000 2720 2960 Unit note
Rev. Feb. 2005
1200pin Unbuffered DDR2 SDRAM SO-DIMMs Meauarement Conditions
Symbol IDD0 Conditions Operating bank active-precharge current; tCK(IDD), tRC(IDD), tRAS tRASmin(IDD);CKE HIGH, HIGH between valid commands;Address inputs SWITCHING;Data inputs SWITCHING Operating bank active-read-precharge curren IOUT 0mA;BL CL(IDD), tCK(IDD), (IDD), tRAS tRASmin(IDD), tRCD tRCD(IDD) HIGH, HIGH between valid commands Address inputs SWITCHING Data pattern same IDD4W Precharge power-down current banks idle tCK(IDD) Other control address inputs STABLE; Data inputs FLOATING Precharge quiet standby current;All banks idle; tCK(IDD);CKE HIGH, HIGH; Other control address inputs STABLE; Data inputs FLOATING Precharge standby current; banks idle; tCK(IDD); HIGH, HIGH; Other control address inputs SWITCHING; Data inputs SWITCHING Active power-down current; banks open; tCK(IDD); LOW; Fast Exit MRS(12) Other control address inputs STABLE; Data inputs FLOATSlow Exit MRS(12) Active standby current; banks open; tCK(IDD), tRAS tRASmax(IDD), =tRP(IDD); HIGH, HIGH between valid commands; Other control address inputs SWITCHING; Data inputs SWITCHING Operating burst write current; banks open, Continuous burst writes; CL(IDD), tCK(IDD), tRAS tRASmax(IDD), tRP(IDD); HIGH, HIGH between valid commands; Address inputs SWITCHING; Data inputs SWITCHING Operating burst read current; banks open, Continuous burst reads, IOUT 0mA; CL(IDD), tCK(IDD), tRAS tRASmax(IDD), tRP(IDD); HIGH, HIGH between valid commands; Address inputs SWITCHING;; Data pattern same IDD4W Burst refresh current; tCK(IDD); Refresh command every tRFC(IDD) interval; HIGH, HIGH between valid commands; Other control address inputs SWITCHING; Data inputs SWITCHING Self refresh current; 0.2V; Other control address inputs FLOATING; Data inputs FLOATING. IDD6 current values guaranted Tcase max. Operating bank interleave read current; bank interleaving reads, IOUT 0mA; CL(IDD), tRCD(IDD)-1*tCK(IDD); tCK(IDD), tRC(IDD), tRRD tRRD(IDD), tRCD 1*tCK(IDD); HIGH, HIGH between valid commands; Address inputs STABLE during DESELECTs; Data pattern same IDD4R; Refer following page detailed timing conditions Units
IDD1
IDD2P IDD2Q IDD2N
IDD3P
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
IDD7
Notes: specifications tested after device properly initialized Input slew rate specified Parametric Test Condition parameters specified with disabled. Data consists DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, UDQS. values must with combinations EMRS bits Definitions defined VILAC(max) HIGH defined VIHAC(min) STABLE defined inputs stable HIGH level FLOATING defined inputs VREF VDDQ/2 SWITCHING defined inputs changing between HIGH every other clock cycle (once clocks) address control signals, inputs changing between HIGH every other data transfer (once clock) signals including masks strobes. Rev. Feb. 2005
1200pin Unbuffered DDR2 SDRAM SO-DIMMs Electrical Characteristics Timings
Speed Bins CL,tRCD,tRP,tRC tRAS Corresponding
Speed Bin(CL-tRCD-tRP) Parameter Latency tRCD tRAS DDR2-533 (C4) 4-4-4 DDR2-400 (E3) 3-3-3 Unit
Timing Parameters Speed Grade
Parameter Data-Out edge Clock edge Skew DQS-Out edge Clock edge Skew Clock High Level Width Clock Level Width Clock Half Period System Clock Cycle Time input setup time input hold time input setup time(single-ended strobe) input hold time(single-ended strobe) Control Address input Pulse Width each input input pulse witdth each input pulse width each input Data-out high-impedance window from Symbol tDQSCK tDS1 tDH1 tIPW tDIPW DDR2-400 -600 -500 0.45 0.45 (tCL,tCH) 5000 0.35 2*tAC tQHS -0.25 0.35 0.35 0.35 -600 0.55 0.55 8000 +0.25 DDR2-533 -500 -500 0.45 0.45 (tCL,tCH) 3750 0.35 2*tAC tQHS -0.25 0.35 0.35 0.35 -500 0.55 0.55 8000 +0.25 Unit Note
low-impedance time from CK/CK tLZ(DQS) low-impedance time from CK/CK tLZ(DQ) DQS-DQ skew associated signals tDQSQ hold skew factor tQHS DQ/DQS output hold time from First latching transition associated clock edge tDQSS input high pulse width tDQSH input pulse width tDQSL falling edge setup time tDSS falling edge hold time from tDSH Mode register command cycle time tMRD Write postamble tWPST Write preamble tWPRE Data-Out edge Clock edge Skew Address control input setup time
Rev. Feb. 2005
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
Continued Parameter Address control input hold time Read preamble Read postamble Auto-Refresh Active/Auto-Refresh command period Active Active Delay page size Active Active Delay page size Four Activate Window page size Four Activate Window page size command delay Write recovery time Auto Precharge Write Recovery Precharge Time Write Read Command Delay Internal read precharge command delay Exit self refresh non-read command Exit self refresh read command Exit precharge power down non-read command Exit active power down read command Exit active power down read command (Slow exit, Lower power) minimum pulse width (high pulse width) turn-on delay turn-on turn-on(Power-Down mode) turn-off delay turn-off turn-off (Power-Down mode) power down entry latency power down exit latency drive mode output delay Minimum time clocks remains after asynchronously drops Average periodic Refresh Interval Notes: details notes, please refer relevant Hynix component datasheet(HY5PS1G831(L)F). TCASE 85°C 85°C TCASE 95°C Symbol tRPRE tRPST tRFC tRRD tRRD tFAW tFAW tCCD tDAL tWTR tRTP tXSNR tXSRD tXARD tXARDS
DDR2-400 127.5 37.5 tWR+tRP tRFC
DDR2-533 127.5 37.5 tWR+tRP tRFC
Unit Note
AOND
tAONPD
AOFD
tAOF
tAOFPD
tANPD tAXPD tOIT tDelay tREFI tREFI
tAC(max) tAC(max) tAC(min) tAC(min) 2tCK+tAC 2tCK+tAC tAC(min)+2 tAC(min)+2 (max)+1 (max)+1 tAC(max)+ tAC(max)+ tAC(min) tAC(min) 2.5tCK+tAC 2.5tCK+tAC tAC(min)+2 tAC(min)+2 (max)+1 (max)+1 tIS+tCK+tIH tIS+tCK+tIH
Rev. Feb. 2005
1200pin Unbuffered DDR2 SDRAM SO-DIMMs PACKAGE OUTLINE
128Mx64 HYMP112S64[P]8
Front
67.60
20.00
Side
4.00 +/-0.10
30.00
20.00
(Front)
1.00 0.10
11.40 2.70 4.20
2.45
11.40 2.40
Back
4.20
47.40
note: note: dimension Units millimeters. dimension Units millimeters. outline dimensions tolerances match JEDEC standard. outline dimensions tolerances match JEDEC standard.
Rev. Feb. 2005
6.00
1200pin Unbuffered DDR2 SDRAM SO-DIMMs PACKAGE OUTLINE
256Mx64 HYMP325S64M[P]8
Front
67.60
20.00
Side
4.00 +/-0.10
30.00
(Front)
20.00
1.00 0.10
6.00
11.40 2.70 4.20
2.45
11.40 2.40
Back
4.20
47.40
note: note: dimension Units millimeters. dimension Units millimeters. outline dimensions tolerances match JEDEC standard.
outline dimensions tolerances match JEDEC standard.
Rev. Feb. 2005
1200pin Unbuffered DDR2 SDRAM SO-DIMMs REVISION HISTORY
Revision History Date Remark
First Version Release Data sheet coverage changed from individual module Feb. 2005 part component based module family.
Rev. Feb. 2005
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