MEMORY SYNCHRONOUS DYNAMIC DIMM 168-pin, Clock, 1-bank, base

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MEMORY SYNCHRONOUS DYNAMIC DIMM 168-pin, Clock, 1-bank, base

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DS05-11143-1E
MEMORY
SYNCHRONOUS DYNAMIC DIMM
168-pin, Clock, 1-bank, based SDRAMs with DESCRIPTION
Fujitsu MB8504S072CA fully decoded, CMOS Synchronous Dynamic Random Access Memory (SDRAM) Module consisting five MB81F641642C devices which organized four banks bits 2K-bit serial EEPROM 168-pin glass-epoxy substrate. MB8504S072CA features fully synchronous operation referenced positive edge clock whereby operations synchronized clock input which enables high performance simple user interface coexistence. MB8504S072CA optimized those applications requiring high speed, high performance large memory storage, high density memory organizations. This module ideally suited workstations, PCs, laser printers, other applications where simple interface needed.
Un-buffered
PRODUCT LINE FEATURES
Parameter CL-tRCD-tRP Clock Frequency Burst Mode Cycle Time Output Valid from Clock Banks Active Power Dissipation Self Refresh Mode MB8504S072CA-102/-102L 2-2-2 min. max. min. max. 3424 max. 18.0 max. (std. power) max. (low power) MB8504S072CA-103/-103L 3-2-2 min. max. min. max. 3424 max. 18.0 max. (std. power) max. (low power)
Un-buffered 168-pin DIMM Socket Type (Lead pitch: 1.27 Conformed JEDEC Standard CLK) Organization: 4,194,304 words bits Memory: MB81F641642C 4-bank) ±0.3 Supply Voltage input/output LVTTL compatible Conformed Intel PC/100 spec
4096 Refresh Cycle every 65.6 Auto Self Refresh Power Down Mode Byte Masking (Read/Write) Serial Presence Detect (SPD) with Serial EEPROM: Intel spec 1.2A Format Module size: 1.375" (height) 5.25" (length) 0.157" (thickness)
PACKAGE
168-pin plastic DIMM (socket type)
(MDS (MDS-168P-P41)
Package Ordering Information
168-pin DIMM, order std. power ver., Gold Pad) power ver., Gold Pad)
ASSIGNMENTS
Signal Name DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 N.C. N.C. DQMB0 Signal Name DQMB1 N.C. CLK0 N.C. DQMB2 DQMB3 N.C. N.C. N.C. DQ16 DQ17 Signal Name DQ18 DQ19 DQ20 N.C. N.C. N.C. DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CLK2 N.C. N.C. (WP) Signal Name DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 Signal Name Signal Name
DQMB5 N.C. CLK1 N.C. CKE0 N.C. DQMB6 DQMB7 N.C. N.C. N.C. DQ48 DQ49
DQ50 DQ51 DQ52 N.C. N.C. N.C. DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CLK3 N.C.
DQ44 DQ45 DQ46 DQ47 N.C. N.C. DQMB4
VIEW
133.37
34.93
PLANE
PLANE
(MDS-168P-P41)
DESCRIPTIONS
Symbol BA0, DQMB0 DQMB7 CLK0 CLK3 CKE0 CS0, Function Address Input Bank Select (Bank Address) Address Strobe Column Address Strobe Write Enable Data (DQ) Mask Clock Input Clock Enable Chip Select Symbol DQ63 N.C. Function Data Input/Data Output Data Power Supply (+3.3 Ground Connection Serial Address Input Serial Clock Serial Address/Data Input/Output Serial Write Protect
SERIAL-PD INFORMATION
Byte Function Described Value -102/ -103/ 102L 103L
Byte Defines Number Bytes Written into Serial Memory Module Manufacture Byte Total Number Bytes Memory Device SDRAM Fundamental Memory Type Number Addresses Number Column Addresses bank Number Module Banks Data Width Data Width (Continuation) LVTTL Interface Type 10/10 SDRAM Cycle Time (Highest Latency) SDRAM Access from Clock (Highest Latency) DIMM Configuration Type Self, Normal Refresh Rate/Type Primary SDRAM Width Error Checking SDRAM Width Cycle Minimum Clock Delay Back Back Random Column Addresses Page Burst Lengths Supported bank Number Banks Each SDRAM Device Latency Supported Latency Write Latency UN-buffer SDRAM Module Attributes SDRAM Device Attributes General 10/15 SDRAM Cycle Time (2nd. Highest Latency) SDRAM Access from Clock (2nd. Highest Latency) Support SDRAM Cycle Time (3rd. Highest Latency) Support SDRAM Access from Clock (3rd. Highest Latency) 20/20 Minimum Precharge Time (tRP) Activate Activate Minimum (tRRD) 20/20 Delay Min. (tRCD) 20/20 Minimum Pulse Width 50/50 Module Bank Density MByte Command Address Signal Input Setup Time Command Address Signal Input Hold Time Data Signal Input Setup Time Data Signal Input Hold Time Unused Storage Locations Data Revision Code Checksum Byte Manufacturer's JEDEC Code JEP-108E Optional Manufacturing Location Optional Manufacturer's Part Number Optional Revision Code Optional Manufacturing Data Optional Assembly Serial Number Optional Manufacturer Specific Data Optional Intel Specification Frequency Intel Specification Details Support Unused Storage Locations 128+ Note: write operation must executed into addresses Byte Byte 127. Some data stored into Byte Byte broken. Byte SDRAM Device Attributes Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Supports Supports Supports Lower Upper Write Precharge AutoTBD tolerance tolerance /Read Burst Precharge
Byte Checksum Byte This byte checksum Byte through This byte contains value 8-bits arithmetic Byte through
Bit0 Supports Early Precharge
BLOCK DIAGRAM
DQMB2 DQMB1 (39:32) (15:8) DQMB3 (47:40)
DQMB0 (7:0)
(7:0)
DQMB6 DQMB5 (55:48) (31:24) DQMB7 (63:56)
DQMB4 (23:16)
(11:0) SERIAL CLK0 N.C. (WP) CLK1 VSS: SDRAM CLK3 VCC: SDRAM CLK2 CKE0
RAS: SDRAM D0-4 CAS: SDRAM D0-4 SDRAM D0-4 (11:0): SDRAM D0-4 A13: SDRAM D0-4 A12: SDRAM D0-4 CKE: SDRAM D0-4
CLK: SDRAM 10pF
CLK: SDRAM 15pF
ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Supply Voltage* Input Voltage* Output Voltage* Storage Temperature Power Dissipation Output Current (D.C.) Voltages referenced WARNING: Semiconductor devices permanently damaged application stress (voltage, current, temperature, etc.) excess absolute maximum ratings. exceed these ratings. Symbol VOUT TSTG IOUT Value Min. -0.5 -0.5 -0.5 Max. +4.6 +4.6 +4.6 +125 Unit
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Input High Voltage, Inputs Input Voltage, Inputs Ambient Temperature Notes Symbol Value Min. -0.5 Typ. Max. +0.5 Unit
Voltages referenced (=0V) Overshoot limit: (max.) +1.5 with pulse-width Undershoot limit: (min.) -1.5 with pulse-width WARNING: recommended operating conditions required order ensure normal operation semiconductor device. device's electrical characteristics warranted when device operated within these ranges. Always semiconductor devices within their recommended operating conditionranges. Operation outside these ranges adversely affect reliability could result device failure. warranty made with respect uses, operating conditions, combinations represented data sheet. Users considering application outside listed conditions advised contact their FUJITSU representatives beforehand.
CAPACITANCE
(VCC +3.3 MHz, +25°C) Parameter A11, BA0, RAS, CAS, CS0, Input Capacitance CKE0 CLK0 CLK3 DQMB0 DQMB7 SA0, SA1, Input/Output Capacitance DQ63 Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CSCL CSDA Value Min. Max. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. Unit
CHARACTERISTICS
recommended operating conditions unless otherwise noted.) Notes
Value Parameter
Notes Symbol
Condition
Max. Min. std. ver. ver.
Unit
ICC1S
Operating Current (Average Power Supply Current)
Burst Length min, Bank Active, Outputs Open, Address changed times during tRC(min.), Burst Length (each Bank), (each Bank), min, Banks Active, Outputs Open, Address changed times during tRC(min.), VIL, min, Banks Idle, Power Down Mode, VIL, VIL, Banks Idle, Power Down Mode, VIH, min, Banks Idle, commands only, Input signals (except CMD) changed time during clock cycles, VIH, VIL, Banks Idle, Input Signals Stable,
ICC1D
ICC2P
ICC2PS
Precharge Standby Current (Power Supply Current)
ICC2N
ICC2NS
(Continued)
(Continued)
Value Parameter
Notes
Symbol
Condition
Max. Min. std. ver. ver.
Unit
ICC3P
VIL, min, Bank Active, VIL, VIL, Bank Active, VIH, min, Bank Active, commands only, Input signals (except CMD) changed time during clock cycles, VIH, VIL, Bank Active, min, Gapless data, Burst Length Outputs open, Multiple-banks Active, Auto Refresh, min, min, Self-refresh, min, other pins under test Output disabled (Hi-Z) -2.0 +2.0
ICC3PS
Active Standby Current (Power Supply Current)
ICC3N
ICC3NS
Burst Mode Current (Average Power Supply Current)
ICC4
Auto-refresh Current (Average Power Supply Current) Self-refresh Current (Average Power Supply Current) Input Leakage Current (All Inputs) Output Leakage Current LVTTL Output High Voltage LVTTL Output Voltage
ICC5
1200
ICC6
Notes: initial pause (DESL NOP) required after power-on followed minimum eight Auto-refresh cycles. characteristics Serial standby state (VIN VCC). depends output termination, load conditions, clock cycle rate signal clock rate. specified values obtained with output open termination resistors. Voltages referenced
CHARACTERISTICS
(SDRAM Component Specifications) Notes BASE CHARACTERISTICS recommended operating conditions unless otherwise noted.)
Parameter Notes Symbol tCK2 tCK3 tAC3 tHZ2 tHZ3 tREF tCKSP 65.6 65.6 tAC2 MB8504S072CA -102/-102L Min. Clock Period Clock High Time Clock Time Input Setup Time Input Hold Time Output Valid from Clock (tCLK min) Output Low-Z Output High-Z Output Hold Time Time between Refresh Transition Time Setup Time Power Down Exit Time Max. MB8504S072CA -103/-103L Min. Max. Unit
BASE VALUES CLOCK COUNT/LATENCY
Parameter Cycle Time Precharge Time Active Time Delay Time Write Recovery Time Data-in Precharge Lead Time Data-in Active/Refresh Command Period Mode Register Cycle Time Bank Active Delay Time tDAL3 tRSC tRRD Notes Symbol tRAS tRCD tDPL tDAL2 MB8504S072CA -102/-102L Min. Max. 110000 MB8504S072CA -103/-103L Unit Min. Max. 110000
CLOCK COUNT FORMULA (*9)
Clock Base Value Clock Period (Round whole number)
LATENCY (The latency values these parameters fixed regardless clock period.)
Clock Disable Output High-Z Input Data Delay Last Output Write Command Delay Write Command Input Data Delay Precharge Output High-Z Delay Burst Stop Command Output High-Z Delay Delay (min) Bank Delay (min) Parameter Symbol MB8504S072CA MB8504S072CA Unit -102/-102L -103/-103L ICKE IDQZ IDQD IOWD IDWD IROH2 IROH3 IBSH2 IBSH3 ICCD ICBD Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle
Notes: initial pause (DESL NOP) required after power-up followed minimum eight Auto-refresh cycles. VREF reference level measuring timing signals. Transition times measured between (min) (max). characteristics assume capacitance load. Assumes tRCD satisfied. also specifies access time burst mode except first access. Specified where output buffer longer driven. Actual clock count (IRC) will clock count tRAS (IRAS) (IRP). Operation within tRCD (min) ensures that access time determined tRCD (min) +tAC (max) tRCD greater than specified tRCD (min), access time determined tAC. base values measured from clock edge command input clock edge next command input. clock counts calculated simple formula: clock count equals base value divided clock period (round whole number). *Source: MB81F641642C Data Sheet details electrical.
OPERATING TEST CONDITION (Example Test Load Circuit)
SERIAL PRESENCE DETECT(SPD) FUNCTION
DESCRIPTIONS
(Serial Clock) input used clock data input/output SPD. (Serial Data) common used data input/output SPD. pull-up resistor required open-drain output. SA0, SA1, (Address) Address inputs used least significant three bits eight bits slave address. address inputs must fixed select particular module fixed address each module must different each other.
OPERATIONS
CLOCK DATA CONVENTION Data states change only during Low. state changes during High indicated start stop conditions. Refer Fig. below. START CONDITION commands preceded start condition, which transition state from High when High. will respond command until this condition been met. STOP CONDITION read write operation must terminated stop condition, which transition state from High when High. stop condition also used make into state standby power mode after read sequence.
Fig. START STOP CONDITIONS
START START High transition state when High STOP High transition state when High
STOP
ACKNOWLEDGE Acknowledge software convention used indicate successful data transfer. transmitting device, either master slave, will release after transmitting eight bits. During ninth clock cycle receiver will line order acknowledge that received eight bits data. will respond with acknowledge when received start condition followed slave address issued master. read operation, will transmit eight bits data, release line monitor line acknowledge. acknowledge detected stop condition issued master, will continue transmit data. acknowledge detected, will terminated further data transmissions. master must then issue stop condition return standby power mode. write operation, upon receipt eight bits data will respond with acknowledge, await next eight bits data, again responding with acknowledge until stop condition issued master. SLAVE ADDRESS ADDRESSING Following start condition, master must output eight bits slave address. most significant four bits slave address device type identifier. this fixed 1010[B]. Refer Fig. below. next three significant bits used select particular device. system could have eight devices -namely eight modules- bus. eight addresses eight devices defined state SA0, inputs. last slave address defines operation performed. When "1", read operation selected, when "0", write operation selected. Following start condition, monitors line comparing slave address being transmitted with slave address (device type state SA0, SA1, inputs). Upon correct compare outputs acknowledge line. Depending state bit, will execute read write operation. Fig. SLAVE ADDRESS
DEVICE TYPE IDENTIFIER DEVICE ADDRESS
READ OPERATIONS
CURRENT ADDRESS READ Internally contains address counter that maintains address last data accessed, incremented one. Therefore, last access (either read write operation) address(n), next read operation would access data from address(n+1). Upon receipt slave address with "1", issues acknowledge transmits eight bits data during next eight clock cycles. master terminates this transmission issuing stop condition, omitting ninth clock cycle acknowledge. Refer Fig. sequence address, acknowledge data transfer.
Fig. CURRENT ADDRESS READ
SLAVE ADDRESS
ACTIVITY MASTER LINE
ACTIVITY
DATA
RANDOM READ Random Read operations allow master access memory location random manner. Prior issuing slave address with "1", master must first perform "dummy" write operation SPD. master issues start condition, slave address followed word address. After word address acknowledge, master immediately reissues start condition slave address with "1". This will followed acknowledge from then eight bits data. master terminates this transmission issuing stop condition, omitting ninth clock cycle acknowledge. Refer Fig. sequence address, acknowledge data transfer.
Fig. RANDOM READ
ACTIVITY MASTER LINE ACTIVITY
SLAVE ADDRESS
WORD ADDRESS
SLAVE ADDRESS
DATA
SEQUENTIAL READ Sequential Read initiated either current address read random read. first data transmitted with other read mode, however, master responds with acknowledge, indicating requires additional data. continues output data each acknowledge received. master terminates this transmission issuing stop condition, omitting ninth clock cycle acknowledge. Refer Fig. sequence address, acknowledge data transfer. data output sequential, with data from address(n) followed data from address(n+1). address counter read operations increments address bits, allowing entire memory contents serially read during operation. address space (address 255), counter "rolls over" address continues output data each acknowledge received.
Fig. SEQUENTIAL READ
SLAVE ADDRESS ACTIVITY MASTER LINE ACTIVITY
DATA
DATA (n+1)
DATA (n+2)
DATA (n+x)
CHARACTERISTICS
Parameter Input Leakage Current Output Leakage Current Output Voltage Note: Referenced VSS. Note Symbol SILI SILO SVOL Condition VOUT Value Min. Max. Unit
CHARACTERISTICS
Parameter Clock Frequency Noise Suppression Time Constant SCL, Inputs Data Valid Time Must Free Before Transmission Start Start Condition Hold Time Clock Period Clock High Period Start Condition Setup Time Data Hold Time Data Setup Time Rise Time Fall Time Stop Condition Setup Time Data Hold Time Write Cycle Time Symbol fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tSU:STO Value Min. Max. Unit
Fig. TIMING WAVEFORM
tLOW (input) (output)
tHIGH
tBUF
PACKAGE DIMENSION
168-pin plastic DIMM (socket type) (MDS-168P-P41)
133.35±0.13(5.250±.005) 131.35±0.13(5.171±.005) 128.93±0.13(5.076±.005) 66.68±0.13(2.625±.005) 65.68±0.13(2.586±.005)
4-R1.27±0.10 (4-R.05±.004)
3.00(.118)MIN.
3.81(.150)MAX.
4.00±0.10 (.157±.004) 34.925±0.13 (1.375±.005) 4.00(.157)MIN.
3.00±0.13 (.118±.005) No.1 INDEX. 11.43±0.05 (.450±.002) 1.27 -0.08 .050 -.003
+0.10 +.004
36.83±0.05 (1.450±.002) 42.18±0.13 (1.661±.005)
3.17±0.13 1.27±0.03 (.125±.005) (.050±.001) 54.61±0.05(2.150±.002)
Details part
6.35±0.13 (.250±.005) 2.00±0.10(.079±.004) 1.00±0.05(.039±.002)
115.57±0.13(4.550±.005) 127.35±0.13(5.014±.005)
3.00 .118
+0.25 +.010
Details part
6.35±0.13 (.250±.005) 2.00±0.10(.079±.004) 1.00±0.05(.039±.002) 1.00±0.05 (.039±.002) 0.25(.010)MAX.
17.78±0.13 22.25±0.13 (.700±.005) (.876±.005)
3.00 .118
+0.25 +.010
Details part 2.54(.100)TYP. NOTCHES FULL
9.53±0.10 (.375±.004)
1998 FUJITSU LIMITED M168041SC-1-1
Dimension (inches)
FUJITSU LIMITED
further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
Rights Reserved. contents this document subject change without notice. Customers advised consult with FUJITSU sales representatives before ordering. information circuit diagrams this document presented examples semiconductor device applications, intended incorporated devices actual use. Also, FUJITSU unable assume responsibility infringement patent rights other rights third parties arising from this information circuit diagrams. FUJITSU semiconductor devices intended standard applications (computers, office automation other office equipment, industrial, communications, measurement equipment, personal household devices, etc.). CAUTION: Customers considering products special applications where failure abnormal operation directly affect human lives cause physical injury property damage, where extremely high levels reliability demanded (such aerospace systems, atomic energy controls, floor repeaters, vehicle operating controls, medical devices life support, etc.) requested consult with FUJITSU sales representatives before such use. company will responsible damages arising from such without prior approval. semiconductor devices have inherent chance failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. products described this document represent goods technologies subject certain restrictions export under Foreign Exchange Foreign Trade Japan, prior authorization Japanese government will required export those products from Japan.
http://www.fujitsu.co.jp/
North South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street Jose, 95134-1804, Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. Fri.: (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
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F9901 FUJITSU LIMITED Printed Japan

MEMORY SYNCHRONOUS DYNAMIC DIMM 168-pin, Clock, 1-bank, base

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