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MPC8245R2UMAD Rev. 2.2, 2/2004 MPC8245 Integrated Processor User's Manual Rev. Errata
This errata document describes corrections MPC8245 Integrated Processor User's Manual, Rev. convenience, errata items refer section page numbers user's manual. Items bold since last revision this document. locate published updates this document, refer
Part Document Revision History
Table provides revision history this errata addendum.
Table Document Revision History
Substantive Change Added errata item following section: Appendix pages E35-E61. Added explanation about previous user's manual errata being added Appendix
Revision Number
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Chapter Errata
Part Document Errata
following sections discuss errata MPC8245 Integrated Processor User's Manual, Rev.
Chapter Errata Appendix Errata
Currently errata exists chapters.
following list includes appendix errata from 2.1. Note that Appendix Revision History, previous revision's errata (Rev left out. errata provided below.
Section/Page
Changes
Appendix E-35
Added major revision changes from revision revision Appendix Revision Changes From Revision Revision following items major changes MPC8245 Integrated Processor User's Manual from Revision Revision
1.1.1, 1.1.1,
second bullet under Memory Interface heading should state: High-bandwidth data (32- 64-bit) SDRAM fourth bullet under Memory Interface heading should state: Supports banks 16-, 64-, 128-, 256-, 512-Mbit memory devices
1.1.1,
second last bullet under Memory Interface heading should state: Extended space supports 16-, 32-bit gathering data path, 64-bit (wide) data path
1.1.1,
second last bullet under 32-bit interface heading should replaced with following sentence: Address translation with inbound outbound units (ATU) second last bullet under Two-channel Integrated Controller (Writes ROM/PORTX Supported) heading should replaced with following: Local-to-PCI memory following statement should added list Debug Features: Error injection/capture data path
1.1.1,
1.1.1,
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Appendix Errata
2.1.1,
Sections that describe signals SDMA13 SDMA14 have been added this chapter:
Signal Name SDRAM address SDRAM address Memory Memory Interface Alternate Function(s) Table Pins Section 2.2.2.a 2.2.2.b
Signal SDMA13 SDMA14
2.1.2,
Table 2-2, Signals SDMA12/SRESET, SDMA12/TBEN, SDMA14/CHKSTOP_IN driven extended addressing mode enabled. last sentence state meanings SDRAM Address (SDMA[11:0]) SDRAM Address (SDMA12) should state: Section 6.2.2, "SDRAM Address Multiplexing," Section 6.3.1.1, "Base Address Multiplexing," Section 6.3.2.1, "Extended Address Multiplexing," complete description mapping these signals cases.
2.2.2.4 2.2.2.5, 2-18
2.2.2.5, 2-18
following sentence should added first paragraph this section: "SDMA12 used extended addressing mode. Section 6.2.2, "SDRAM Address Multiplexing" Section 2.4, "Configuration Signals Sampled Reset," more information."
2.2.2.6, 2-18
following signal descriptions SDMA13 SDMA14 should added this chapter after SDMA12 description: SDMA13 signal similar SDMA[11:0] that corresponds different column address bits, depending memory use. SDMA13 multiplexed with TBEN used extended addressing mode. Section 6.3.2, "Extended Interface," more information. State Meaning Asserted/Negated: Section 6.3.2.1, "Extended Address Multiplexing," complete description mapping this signal cases. Timing Comments Assertion/Negation: same SDMA[11:0].
2.2.2.a SDRAM Address (SDMA13)-Output
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2.2.2.b SDRAM Address (SDMA14)-Output SDMA14 signal similar SDMA[11:0] that corresponds different column address bits, depending memory use. SDMA14 multiplexed with CHKSTOP_IN used extended addressing mode. Section 6.3.2, "Extended Interface," more information. State Meaning Asserted/Negated: Section 6.3.2.1, "Extended Address Multiplexing," complete description mapping this signal cases.
Timing Comments Assertion/Negation: same SDMA[11:0]. 2.2.5, 2-25 following sentences should added first paragraph this section: "The signals SIN1, SOUT1, SIN2/CTS1, SOUT2/RTS1 multiplexed with PCI_CLK0, PCI_CLK1, PCI_CLK2, PCI_CLK3, respectively. Note that when using DUART signals, PCI_CLK[0:3] signals cannot used." 2.2.6.2, 2-27 last sentence first paragraph this section should replaced with following: "Note that SRESET signal multiplexed with SDMA12 signal. extended addressing mode, SDMA12 used SRESET available. Section 6.3.2, "Extended Interface," more information." 2.2.6.3, 2-27 following sentence should added first paragraph this section: "Note that output driver designated open-drain setting MIOCR[MCP_OD_MODE] parameter." 2.2.6.3, 2-28 PMCR2[SHARED_MCP] should replaced with MIOCR[MCP_OD_MODE] last paragraph this section follows: "High impedance: MIOCR[MCP_OD_MODE] set, signal placed high impedance when there error report." 2.2.6.6, 2-28 following sentences should added first paragraph this section: "Note that CHKSTOP_IN signal multiplexed with SDMA14 signal. extended addressing mode, SDMA14 used
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Appendix Errata
CHKSTOP_IN available. Section 6.3.2, "Extended Interface," more information." 2.2.6.7, 2-29 first paragraph should state: "Following state meaning timing comments TBEN. Note that TBEN signal multiplexed with SDMA13 signal. extended addressing mode, SDMA13 used TBEN available. this case, PICR1[DEC] used enable processor core's decrementer. Table 4-31 description PICR1[DEC]." 2.2.8.2, 2-34 following sentence should added this section: "Note that PCI_CLK[0:3] cannot used when using DUART signals SIN1, SOUT1, SIN2/CTS1, SOUT2/RTS1." 2.3.2, 2-37 fourth paragraph this section should state: order insure proper operation successful locking DLL, there certain requirements that must described MPC8245 Hardware Specification. some cases (depending board layout frequencies), lock range must lengthened setting MIOCR1[DLL_MAX_DELAY] described Section 4.5, "Output/Clock Driver Miscellaneous Control Registers." This accomplished increasing time between each points delay line. Although this increased time makes easier guarantee that reference clock within lock range, also means there slightly more jitter output clock DLL, should phase comparator shift clock between adjacent points. 2.4, 2-40
Signal Name MAA0 Default Address setting. This signal should always pulled high since MPC8245 only supports address MPC8245 configured address
Table 2-5, state meaning signal MAA0 should follows:
State Meaning
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2.4, 2-41
Signal Name PMAA2
Table 2-5, default value signal PMAA2 follows:
Default Driver capability EPIC controller output signals. value this signal sets initial value ODCR[DRV_PCI]. drive capability PCI/EPIC signals drive capability AD[31:0], C/BE[3:0], DEVSEL, FRAME, GNT[4:0], PAR, INTA, IRDY, PERR, SERR, STOP, TRDY, IRQ0/S_INT, IRQ1/S_CLK, IRQ4/L_INT signals drive capability IRQ2/S_RST IRQ3/S_FRAME State Meaning
2.4, 2-41
Table 2-5, second sentence SDMA1 state meaning should state following:
Default Extended addressing mode. When this signal during reset, extended addressing mode enabled. value this signal during reset determines function SRESET, TBEN, CHKSTOP_IN, TRIG_IN, TRIG_OUT signals. 6.3.2, "Extended Interface," more information multiplexing these signals. Extended addressing mode enabled. SDMA12, SDMA13, SDMA14, RCS2, RCS3 signals available. Extended addressing mode disabled. SRESET, TBEN, CHKSTOP_IN, TRIG_IN, TRIG_OUT available. State Meaning
Signal Name SDMA1
3.1,
Table 3-2, memory transaction address range 7000_0000-7FFF_FFFF local memory address range 7000_0000-7FFF_FFFF follows:
Local Memory Address Range 7000_0000-7FFF_FFFF Extended ROM/Flash (256 MBytes)11 Definition
Memory Transaction Address Range 7000_0000 7FFF_FFFF 256M Decimal
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Appendix Errata
3.1,
Figure 3-1, memory controller range between 32MB should state "Forwards memory space," follows:
MPC8245 Memory Controller forwarded bus. Memory controller performs local memory access Reserved
Processor
Local memory space 256MB
Local memory
Memory Space addressable processor
256MB Extended Forwards Memory Space Memory Space Extended
memory space range 32MB addressable processor local ROM, addressable memory. remote ROM, memory space
32MB 16MB
Space 32MB Space 32MB 64KB Clears A[31:24] forwards space, except 0xFE01_0000- 24MB 0xFE7F_FFFF, which reserved addresses 64KB range 64KB
addresses 12MB range 12MB
Space
CONFIG_ADDR CONFIG_DATA Flash
20MB 18MB 17MB 16MB Configuration Access Broadcast Access addressable processor
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Appendix Errata
3.1,
Replace Figure with following:
Master Space Addressable processor 64KB Reserved Addressable processor 12MB MPC8245 Memory Controller
MPC8245 does respond target accesses
addressable processor
Figure 3-3. Master Address
3.4.1, 3-26
Local Memory Offset
cross reference performance monitor section should added Table 3-13 follows:
Register Reference
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Appendix Errata
Local Memory Offset 0xF_E000 0xF_EFFF
Register Performance monitor
Reference Section 16.2.3, "Performance Monitor Counter (PMC0-PMC3)"
3.4.2, 3-27
Memory Offset 0xE00 0xEFF
cross reference performance monitor section should added Table 3-14 follows:
Register Performance monitor Section 16.2.3, "Performance Monitor Counter (PMC0-PMC3)" Reference
Chapter
correct Performance Monitor Command Registers CMDR registers (CMDR0-CMDR3) referenced Section 16.2. Performance Monitor Command Registers 0x48 through 0x5C should used. reference these registers have been removed from this chapter. Table 4-1, offsets 0xD8 0xDC should have reset values 0x0C00_000E 0x0800_000E, respectively.
Register Size (Bytes) Program Access (Bytes) Access Reset Value
4.1.3.1,
Address Offset 0xD8 0xDC
Read/Write Read/Write
0x0C00_000E 0x0800_000E
Extended configuration register Extended configuration register
4.2.8, 4-15
Bits 15-0
description this register Table 4-12 should read follows:
Reset Value Description Value determined startup through configuration pins MDH[16:31] programmed software after reset.
Initial value depends reset configuration signal. Section 2.4, "Configuration Signals Sampled Reset."
4.2.9, 4-15
Bits 15-0 Reset Value
Table 4-13 should titled "Table 4-13. Subsystem ID-0x2E description this register should read follows:
Description Value determined startup through configuration pins MDH[0:15] programmed software after reset.
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Initial value depends reset configuration signal. Section 2.4, "Configuration Signals Sampled Reset."
4.2.11, 4-16
Reset Value
Table 4-15 should contain following description PGCR:
Controls ability retry incoming read transactions local memory while processor core writing data (for example, while internal buffers have data written bus). Disables ability retry incoming memory read transactions local memory while processor core writing data bus. Enables ability retry incoming memory read transactions local memory while processor core writing data bus. Description
Bits
4.4.2, 4-23
figure 4-9, PCI_HOLD_DELAY[0-1] should include bits follows:
Reserved
PCI_HOLD_DELAY[0-1] DLL_EXTEND
PLL_SLEEP
4.4.2, 4-23
Bits Reset Value
Bits power management configuration register should updated follows:
Reserved Description
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Appendix Errata
Bits
Reset Value PCI_HOLD_DEL
Description output hold delay value relative PCI_SYNC_IN signal. MPC8245 Hardware Specification detailed number nanoseconds guaranteed each setting. There eight sequential settings this value; each corresponds increase hold time: Recommended (default) Recommended initial values bits determined inverse reset configuration signals, respectively. Section 2.4, "Configuration Signals Sampled Reset," more information. these pins have internal pull-up resistors, default value after reset 0b00.
Initial value depends reset configuration signal. Section 2.4, "Configuration Signals Sampled Reset."
4.5, 4-24 4-25
Table 4-21 should updated follows: output driver control register been renamed DRV_STD_MEM. Bits 5-4, DRV_MEM_CTRL[1-2], only drive SDRAM_CLK[0:3] SDRAM_SYNC_OUT signals silicon revision 1.1. Bits 1-0, DRV_MEM_CLK[1-2], should added table. Please note these changes table below:
Bits addr<73>
Name DRV_PCI
Reset Value
Description Driver capability EPIC controller output signals. drive capability PCI/EPIC signals drive capability AD[31:0], C/BE[3:0], DEVSEL, FRAME, GNT[4:0], PAR, INTA, IRDY, PERR, SERR, STOP, TRDY, IRQ0/S_INT, IRQ1/S_CLK, IRQ4/L_IN signals drive capability IRQ2/S_RST IRQ3/S_FRAME initial value this determined PMAA2 reset configuration pin. Driver capability standard memory signals (PMAA[0:2], SDA, SCL, CKO, QACK, DA[10:6], MCP, MDH[0:31], MDL[0:31], PAR[0:7], MAA[0:2]) drive capability standard signals drive capability standard signals
DRV_STD_MEM
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Bits
Name DRV_MEM_CTRL[1-2]
Reset Value
Description Driver capability memory signals (CS[0:7], DQM[0:7], FOE, RCS0, RCS1, SDBA[1:0], SDRAS, SDCAS, CKE, SDMA[11:0], CHKSTOP_IN, SRESET, TBEN,TRIG_OUT. Controls drive strength SDRAM_CLK[0:3] SDRAM_SYNC_OUT silicon revision DRV_MEM_CTRL[1-2]: reserved drive capability drive capability drive capability initial value DRV_MEM_CTRL[1-2] determined PMAA0 PMAA1 reset configuration pins, respectively. Controls drive strength PCI_CLK[0:4] PCI_CLK_SYNC_OUT. DRV_PCI_CLK[1-2]: reserved drive capability drive capability drive capability Controls drive strength SDRAM_CLK[0:3] SDRAM_SYNC_OUT silicon revision DRV_MEM_CLK_[1-2]: reserved drive capability drive capability drive capability
DRV_PCI_CLK[1-2]
DRV_MEM_CLK_[1-2]
Initial value depends reset configuration signal. Section 2.4, "Configuration Signals Sampled Reset."
4.5, 4-25
Table 4-22, description should state that disables/enables PCI_SYNC_OUT signal MPC8245 follows:
Name PCI_SYNC_OUT Reset Value Description This disables/enables PCI_SYNC_OUT signal MPC8245. value (0b1) disables output. value zero (0b0) enables output.
Bits addr<75>
4.5, 4-26
Table 4-23, MIOCR1 should reserved. Also note that description MIOCR1[DLL_MAX_DELAY] should added follows:
Name Reset Value Reserved Description
Bits
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Appendix Errata
Bits
Name DLL_MAX_DELAY
Reset Value
Description This used delay line length. Please Section 2.3.2, "DLL Operation Locking," more information. shorter normal) delay line length DLL_max_mode, longer delay line length
4.7.1, 4-27
extended starting ending address fields have three bits shown below. section originally showed these fields bits. correct formulas lower upper boundaries follows:
Lower boundary bank <extended starting address <starting address 0x0_0000.
Upper boundary bank <extended ending address <ending address 0xF_FFFF.
4.7.1, 4-28
correct figures extended memory starting address registers follows:
Reserved
Extended Starting Address Extended Starting Address
Extended Starting Address Extended Starting Address
0000_0
0000_0
0000_0
0000_0
Figure 4-12. Extended Memory Starting Address Register 1-0x88.
Reserved
Extended Starting Address Extended Starting Address
Extended Starting Address Extended Starting Address 0000_0
0000_0
0000_0
0000_0
Figure 4-13. Extended Memory Starting Address Register 2-0x8C
4.7.1, 4-29
correct settings extended memory starting address registers shown table 4-27 follows:
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Bits 31-27 26-24 23-19 18-16 15-11 10-8 31-27
Name Extended starting address Extended starting address Extended starting address Extended starting address Extended starting address Extended starting address Extended starting address Extended starting address
Reset Value Reserved
Description
Byte Address 0x88
Extended starting address bank Reserved Extended starting address bank Reserved Extended starting address bank Reserved Extended starting address bank Reserved Extended starting address bank Reserved Extended starting address bank Reserved Extended starting address bank Reserved Extended starting address bank 0x8C
26-24 23-19 18-16 15-11 10-8
4.7.1, 4-30
correct figures extended memory ending address registers follows:
Reserved
Extended Ending Address Extended Ending Address
Extended Starting Address Extended Ending Address
0000_0
0000_0
0000_0
0000_0
Figure 4-16. Extended Memory Ending Address Register 1-0x98
Reserved Extended Ending Address Extended Ending Address Extended Starting Address Extended Ending Address
0000_0
0000_0
0000_0
0000_0
Figure 4.17. Extended Memory Ending Address Register 2-0x9C
4.7.1, 4-30 4-31 correct settings extended memory ending address registers shown table 4-29 follows:
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Appendix Errata
Bits 31-27 26-24 23-19 18-16 15-11 10-8 31-27
Name Extended ending address Extended ending address Extended ending address Extended ending address Extended ending address Extended ending address Extended ending address Extended ending address
Reset Value Reserved
Description
Byte Address 0x98
Extended ending address bank Reserved Extended ending address bank Reserved Extended ending address bank Reserved Extended ending address bank Reserved Extended ending address bank Reserved Extended ending address bank Reserved Extended ending address bank Reserved Extended ending address bank
26-24 23-19 18-16 15-11 10-8
0x9C
4.8, 4-33
Speculative Reads CF_APARK LE_MODE ST_GATH_EN CF_DPARK MCP_EN FLASH_WR_EN PROC_TYPE RCS0 0b00 1111_1111
Figure 4-20 should include DEC, follows:
Reserved
Figure 4-20. Processor Interface Configuration Register (PIRC1)-0xA8
4.8, 4-34
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Table 4-32 should include description follows:
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Bits
Name
Reset Value
Description
This used enable time base decrementor processor core. extended addressing mode, TBEN signal functions SDMA13. This used software enable time base decrementor processor core. Disable processor core decrementer extended addressing mode Enable processor core decrementer extended addressing mode
4.9.2, 4-43
Table 4-40, reference MPC107 description SERR error should replaced with reference MPC8245, follows:
Name Reset Value Description This indicates assertion SERR external agent regardless whether MPC8245 initiator, target, non-participating agent. SERR detected SERR detected
Bits
SERR error
4.10, 4-45 4-48
Table 4-43 Table 4-44, description RCS2_BURST RCS3_BURST should replaced with description below. Also, description setting RCS2_DBW RCS3_DBW should follows:
Reset Value Description Burst mode chip-select timing enable Indicates standard (nonburst) access timing Indicates burst-mode access timing. When burst mode enabled, reads RCSn_ROMNAL burst beats. These bits control data width RCSn. 8-bit data path with gathering 16-bit data path with gathering 32-bit data path with gathering. Gathering occurs DBUS0 wide data path; 64-bit DBUS0 32-bit DBUS0
Bits
Name RCSn_BURST
29-28
RCSn_DBW
4.10, 4-46 4-49
Table 4-43 Table 4-44, setting 00000 RCS2_ASFALL RCS3_ASFALL have clock falling time. Also note that setting 11111 RCS2_ASFALL, RCS3_ASFALL,
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RSC2_ASRISE, RCS3_ASRISE clock falling time follows:
Bits 14-10 Name RCSn_ASFALL Reset Value RCSn fall time. These bits control falling edge timing signal relative falling edge RCSn Port interface. Section 6.3.5, "Port Interface," more information. 00000 clocks asserted coincident with chip select) 00001 clock 00010 clocks 00011 clocks 11111 clocks RCSn rise time. These bits control rising edge timing signal relative falling edge RCSn Port interface. Section 6.3.5, "Port Interface," more information. 00000 Disables signal generation 00001 clock 00010 clocks 00011 clocks 11111 clocks Description
RCSn_ASRISE
4.10, 4-51
Figure 4-32, RCSn_SADDR field bits long, follows:
Reserved
RCSn_SIZE 0000
RCSn_SADDR
0000_0000
Table 4-45 Table 4-46, RCS2_SADDR RCS3_SADDR fields bits long follows:
Bits 27-12 Name RCSn_SADDR Reset Value Description
0xC000 Starting address RCSn megabytes. Physical starting address RCSn_SADDR 0x000
Table 4-46 should titled "Table 4-46. Extended Configuration Register 4-0xDC"
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4.12, 4-53
Section 4.12 should read follows: configuration register (PCR) indicates values used mode. MPC8245 Hardware Specification more information Figure 4-34 shows bits PCR.
PLL_CFG
Figure 4-34. Configuration Register (PCR)-0xE2
Table 4-48 shows specific settings Configuration Register.
Table 4-48. Settings PCR-0xE2
Bits
Name PLL_CFG
Reset Value
Description Configuration. Indicates values used mode. Reserved
Initial value depends reset configuration signal. Section 2.4, "Configuration Signals Sampled Reset."
4.13, 4-54
Table 4-49, description MCCR1[DBUS_SIZ[0-1]] should added follows:
Name Reset Value Read-only. This field indicates state memory data path width. value this field determined reset configuration signals [DL[0], FOE]. Used with DBUS_SIZ2 (stored MCCR4[17]) shown below. DBUS_SIZ[0-2]: SDRAM: 32-bit data 64-bit data ROM/Flash chip select (RCSO): 32-bit data 8-bit data 64-bit data ROM/Flash chip select (RCS1): 32-bit data 8-bit data 64-bit data ROM/Flash chip select (RCS2) ROM/Flash chip select (RCS3) data width ERCR1[RCS2_DBW] ERCR2[RCS2_DBW], respectively. Description
Bits
22-21 DBUS_SIZ[0-1]
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4.13, 4-58
Table 4-50, description MCCR2[REFINT] bits long, follows:
Name REFINT Reset Value Refresh interval. These bits directly represent number clock cycles between refresh cycles. refreshed each bank during each refresh cycle. value REFINT depends specific RAMs used operating frequency MPC8245. Section 6.2.12, "SDRAM Refresh," more information. Note that period refresh interval must greater than read/write access time ensure that read/write operations complete successfully. Description
Bits 15-2
4.13, 4-59
MCCR2[DBUS_SIZE[2]], should included Figure 4-38 follows:
BUF_TYPE[1] BUF_TYPE[0] WMODE BSTOPRE[0-1] DBUS_SIZE[2] REGDIMM ACTOPRE SDMODE
Reserved
PRETOACT
BSTOPRE[6-9] ACTORW
4.13, 4-60
Table 4-52, description MCCR4[DBUS_SIZE[2]], should added follows:
Name Reset Value description bits 22-21 MCCR1. Description
Bits
DBUS_SIZE[2]
5.3.1.2.1, 5-16
following text table should added this section: Table shows HID0[SBCLK], HID0[ECLK], hard reset signals used configure when PMCR1[CKO_SEL] When PMCR1[CKO_SEL] CKO_MODE field PMCR1 determines signal driven CKO. Note that initial value PMCR1[CKO_SEL] determined value signal negation HRST_CPU. Section 2.2.8.8, "Debug
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Clock (CKO)-Output," Section 2.4, "Configuration Signals Sampled Reset," more information.
Table 5-2. HID0[BCLK] HID0[ECLK] Signal Configuration
HRST_CPU HRST_CTRL Asserted Negated Negated Negated Negated HID0[ECLK] HID0[SBCLK] Signal Driven Processor core clock High impedance sys-logic-clk divided Processor core clock sys-logic-clk
5.8, 5-33
second sentence second paragraph should state following: "The MPC8245 processor version number 0x8081, processor revision level starts 0x1014 incremented each revision chip."
Chapter 6.1,
SDRAM CLK[0:3], MCLK, CLK, MemCLK have been replaced SDRAM_CLKn timing figures this chapter. Table 6-2, SDMA12 should added 2-bank SDRAM address column next SDBA1 output signal following note should added JEDEC DIMM SDRAM 168-pin DIMM signal BA1: "When upgrading from MPC8240 system, SDRAM DIMM will already connected SDRAM12 13xnx2 configurations were used."
6.2.2, 6-11
following text after second paragraph this section: "Note that SDMA[14:12] available only when MPC8245 extended addressing mode, selected SDMA1 reset. Section 2.4, "Configuration Signals Sampled Reset," more information. When using extended addressing mode, TBEN, SRESET, CHKSTOP_IN, TRIG_IN, TRIG_OUT signals available. following function changes occur extended addressing mode: TBEN becomes SDMA13 SRESET becomes SDMA12 CHKSTOP_IN becomes SDMA14 TRIG_IN becomes RCS2 TRIG_OUT becomes RCS3
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Because TBEN functional, PICR1[DEC] used enable processor core's decrementer." 6.2.2, 6-11 Figure 6-4, rows labeled 13xnx2 should removed. Rows labeled "12x10x4," "12x9x4," "11x8x4 12x8x4" should updated follows:
Bank 12x10x4 SDRAS 13x9x2 SDCAS Physical Address
12x9x4 13x8x2
SDRAS
SDCAS
11x8x4, 12x8x4, 13x8x2
SDRAS
SDCAS
6.2.2, 6-13
Bank 12x10x4 13x10x2 SDRAS
Figure 6-5, rows labeled 13xnx2 should removed. Rows labeled "12x10x4" "12x9x4" should updated follows:
Physical Address
SDCAS
12x9x4 13x9x2
SDRAS
SDCAS
6.3.1, 6-51
fifth paragraph this section should replaced with following paragraph:
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"For 8-bit data path, MPC8245 uses either address bits depending state SDMA1 signal reset. extended addressing mode disabled (SDMA1 high reset), 8-bit interface uses address bits only address Mbytes associated chip select; extended addressing mode enabled (SDMA1 reset), 8-bit interface uses address bits address Mbytes associated chip select." 6.3.1, 6-52 Table 6-14 should replaced with following table. Note differences 8-bit interface cells.
DBUS_SIZE[0-2] SDRAM data width Bank (RCS0) Bank (RCS1)
MDL[0]
MCCR4 [DBUS_SIZE2]
bits
32-bit interface address bits 8-Mbyte space 32-bit interface address bits 8-Mbyte space 8-bit interface address bits1 8-Mbyte space1 8-bit interface address bits1 8-Mbyte space1 64-bit interface address bits 8-Mbyte space 64-bit interface address bits 8-Mbyte space 8-bit interface address bits1 8-Mbyte space1 8-bit interface address bits1 8-Mbyte space1
32-bit interface address bits 8-Mbyte space 8-bit interface address bits 8-Mbyte space1 32-bit interface address bits 8-Mbyte space 8-bit interface address bits1 8-Mbyte space1 64-bit interface address bits 8-Mbyte space 8-bit interface address bits1 8-Mbyte space1 64-bit interface address bits 8-Mbyte space 8-bit interface address bits1 8-Mbyte space1
bits
bits
bits
bits
bits
bits
bits
8-bit interface, setting SDMA1 signal reset determines whether address bits used provide Mbytes addressable space.
6.3.2, 6-54
first paragraph should replaced with following: power-on reset, 256-Mbyte extended space disabled. extended interface optional must first enabled pulling SDMA1 signal reset, enable extended addressing mode, setting MCCR4[EXTROM]. Once enabled,
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Appendix Errata
extended space accessed memory transactions physical addresses from 0x7000_0000 0x7FFF_FFFF. Note that extended addressing mode also effects base addressing 8-bit mode. Section 6.3.1, "Base Interface Operation," more information. 6.3.4, 6-60 following sentence, found towards middle second last paragraph this section, should removed: "Additionally, memory interface configured registered mode (MCCR4[REGISTERED] 1]), more clock cycle incurred these read access times." Chapter
references extended doorbell registers should removed from this chapter. SDR0-SDR15 will called SIR0-SIR15. DUART interrupt vector/priority registers offsets 0x5_1120 0x5_1140 should abbreviated IIVPRs follows.
Register Name DUART interrupt vector/priority register (IIVPR4) DUART interrupt vector/priority register (IIVPR5) PRIORITY, VECTOR PRIORITY, VECTOR Field Mnemonics
Chapter 11.2, 11-5
Address Offset from EUMBBAR 0x5_1120 0x5_1140
11.4, 11-10
second sentence second paragraph this section should include words "global timers" follows: "However, pass-through mode, EPIC unit passes interrupts from (including watchpoint facility, DUART, unit), L_INT output signal."
12.4.2, 12-14 12.4.7, 12-20
Table 12-4 should titled "Table 12-4. Settings Divisor Register UDMB, UDLB,-Offsets 0x501/0x601, 0x500/0x600" Table 12-13 been added. This table describes parity selected using PEN, bits ULCR.
Table 12-13. Parity Selection Using ULCR[PEN], ULCR[SP], ULCR[EPS]
Parity Selected parity parity parity
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Appendix Errata Table 12-13. Parity Selection Using ULCR[PEN], ULCR[SP], ULCR[EPS] (continued)
Parity Selected parity parity Even parity Mark parity Space parity
12.4.9, 12-21
Figure 12-12 should included:
TEMT
THRE
Figure 12-12. Line Status Register (ULSR)
12.4.13, 12-25
Table 12-18 includes tables description TXRDY RXRDY bits:
Table 12-18. Settings UDSR-0x510, 0x610
Name
Reset Value
Reserved
Description
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Appendix Errata Table 12-18. Settings UDSR-0x510, 0x610 (continued)
Name TXRDY Reset Value Description Transmitter ready reflects status transmitter FIFO UTHR. status dependent mode selected, which determined bits UFCR. This cleared following instances: Mode Meaning TXRDY cleared when there characters transmitter FIFO UTHR. TXRDY cleared when there characters transmitter FIFO UTHR TXRDY cleared when there characters transmitter FIFO UTHR. TXRDY cleared when there characters transmitter FIFO UTHR. TXRDY remains clear when transmitter FIFO full.
This following instances: Mode Meaning TXRDY after first character loaded into transmitter FIFO UTHR. TXRDY after first character loaded into transmitter FIFO UTHR. TXRDY after first character loaded into transmitter FIFO UTHR. TXRDY when transmitter FIFO full.
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Appendix Errata Table 12-18. Settings UDSR-0x510, 0x610 (continued)
Name RXRDY Reset Value Description Receiver ready reflects status receiver FIFO URBR. status dependent mode selected, which determined bits UFCR. This cleared following instances: Mode Meaning RXRDY cleared when there least character receiver FIFO URBR. RXRDY cleared when there least character receiver FIFO URBR. RXRDY cleared when there least character receiver FIFO URBR. RXRDY cleared when trigger level time-out been reached remains cleared until receiver FIFO empty.
This following instances: Mode Meaning RXRDY when there characters receiver FIFO URBR. RXRDY when there characters receiver FIFO URBR. RXRDY when there characters receiver FIFO URBR. RXRDY when trigger level been reached there been time out.
15.1, 15-1
second bullet under first paragraph this section should state: 2.0-volt core 3.6-volt Table 16-6, performance monitor events 55-58 63-64 supported should reserved. Throughout this chapter, DH[31:0], DL[31:0], DPAR[7:0] should replaced with MDH[31:0], MDL[31:0], PAR[7:0], respectively Table 17-1, change register names follows:
16.3.2, 16-10 Chapter
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Appendix Errata
Local Offset 0xF_F000 0xF_F004 0xF_F008 0xF_F00C 0xF_F010 0xF_F014
Offset 0xF00 0xF04 0xF08 0xF0C 0xF10 0xF14
Size (bytes)
Program Access Size (bytes)
Register
Register Access
Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000
Data High Error Injection Mask Data Error Injection Mask Parity Error Injection Mask Register Data High Error Capture Monitor Register Data Error Capture Monitor Register Parity High Error Capture Monitor Register
17.5.2, 17-17
first sentence second paragraph should state: "When memory data-path parity/ECC error data loaded into monitors, capture flag parity error capture monitor register, offsets 0xF_F014, 0xF14, also set."
D.1.3, D-12
Second implementation note under first bullet should state: "Implementation Note-The MPC8245 processor version number 0x8081; processor revision level starts 0x1014 incremented each revision chip. revision level updated silicon revisions."
D.1.3.2, D-15
second sentence second paragraph this section should state: "The MPC8245 processor version number 0x8081; processor revision level starts 0x1014 incremented each revision chip.
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