Download

PDF Abstract Text:

DS05-11138-1E

MEMORY

To Top / Lineup / Index
FUJITSU SEMICONDUCTOR DATA SHEET
DS05-11138-1E
MEMORY
Un-buffered
MB8516S064CZ-102 / -103 / -102L / -103L
s PRODUCT LINE & FEATURES
To Top / Lineup / Index
MB8516S064CZ-102 / -103 / -102L / -103L
s PACKAGE
168-pin plastic DIMM (socket type)
(MDS PP ) (MDS-168P-P38)
Package and Ordering Information
To Top / Lineup / Index
MB8516S064CZ-102 / -103 / -102L / -103L
s PIN ASSIGNMENTS
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Signal Name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 N.C. N.C. VSS N.C. N.C. VCC WE DQMB0 Pin No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Signal Name DQMB1 CS0 N.C. VSS A0 A2 A4 A6 A8 A10 BA1 VCC VCC CLK0 VSS N.C. CS2 DQMB2 DQMB3 N.C. VCC N.C. N.C. N.C. N.C. VSS DQ16 DQ17 Pin No. 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Signal Name DQ18 DQ19 VCC DQ20 N.C. N.C. CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS CLK2 N.C. N.C. (WP) SDA SCL VCC Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Signal Name VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 Pin No. Signal Name Pin No. Signal Name
113 DQMB5 114 CS1 115 RAS 116 VSS 117 A1 118 A3 119 A5 120 A7 121 A9 122 BA0 123 A11 124 VCC 125 CLK1 126 N.C. 127 VSS 128 CKE0 129 CS3 130 DQMB6 131 DQMB7 132 N.C. 133 VCC 134 N.C. 135 N.C. 136 N.C. 137 N.C. 138 VSS 139 DQ48 140 DQ49
141 DQ50 142 DQ51 143 VCC 144 DQ52 145 N.C. 146 N.C. 147 N.C. 148 VSS 149 DQ53 150 DQ54 151 DQ55 152 VSS 153 DQ56 154 DQ57 155 DQ58 156 DQ59 157 VCC 158 DQ60 159 DQ61 160 DQ62 161 DQ63 162 VSS 163 CLK3 164 N.C. 165 SA0 166 SA1 167 SA2 168 VCC
100 DQ44 101 DQ45 102 VCC 103 DQ46 104 DQ47 105 N.C. 106 N.C. 107 VSS 108 N.C. 109 N.C. 110 VCC 111 CAS 112 DQMB4
To Top / Lineup / Index
MB8516S064CZ-102 / -103 / -102L / -103L
TOP VIEW
133.37 mm
Chip 0 34.93 mm
Chip 1
Chip 2
Chip 3
Chip 5
Chip 6
Chip 7
Chip 8
PLANE 0 1 10 11 40 41 84
124 125 PLANE 1
Chip 9
Chip 10
Chip 11
Chip 12
Chip 14
Chip 15
Chip 16
Chip 17
(MDS-168P-P38)
s PIN DESCRIPTIONS
Symbol A0 to A11 RAS CAS WE DQMB0 to DQMB7 CLK0 to CLK3 CKE0, CKE1 CS0 to CS3 BA0, BA1 I / O I I I I I I I I I Function Address Input Row Address Strobe Column Address Strobe Write Enable Data (DQ) Mask Clock Input Clock Enable Chip Select Bank Select (Bank Address) Symbol DQ0 to DQ63 VCC VSS N.C. SA0 to SA2 SCL SDA WP I / O - - - I I I / O - Function Power Supply (+3.3 V) Ground (0 V) No Connection Serial PD Address Input Serial PD Clock Serial PD Address / Data Input / Output Serial PD Write Protect - I / O Data Input / Data Output
To Top / Lineup / Index
MB8516S064CZ-102 / -103 / -102L / -103L
s SERIAL-PD INFORMATION
Byte 0 Function Described Hex Value -102 / -103 / 102L 103L 80h 80h 08h 04h 0Ch 09h 02h 40h 00h 01h A0h 60h 00h 80h 08h 00h 01h 8Fh 04h 06h 01h 01h 00h 0Eh A0h 60h 00h 00h 14h 14h 14h 32h 10h 20h 10h 20h 10h 00h 12h 06h 00h 00h 00h 00h 00h 00h 00h 64h FFh - 08h 04h 0Ch 09h 02h 40h 00h 01h A0h 60h 00h 80h 08h 00h 01h 8Fh 04h 06h 01h 01h 00h 0Eh F0h 80h 00h 00h 14h 14h 14h 32h 10h 20h 10h 20h 10h 00h 12h 76h 00h 00h 00h 00h 00h 00h 00h 64h FDh -
0 0 0 0 1 1 1 2. Byte 63: Checksum for Byte 0 to 62 This byte is the checksum for Byte 0 through 62. This byte contains the value of the low 8-bits of the arithmetic sum of Byte 0 through 62. 5
Bit0 Supports Early RAS Precharge 0
To Top / Lineup / Index
MB8516S064CZ-102 / -103 / -102L / -103L
BLOCK DIAGRAM
VCC 10 K CKE1 CKE0 CKE: SDRAM D9-12, 14-17 CKE: SDRAM D0-3, 5-8 SERIAL PD SCL SDA SA2 CLK0 SA1 SA0 N.C. (WP) 47 K VSS CLK2 VCC C VSS VSS: SDRAM VCC: SDRAM 10 CLK3 CLK: SDRAM D14, 15 CLK: SDRAM D16, 17 +3.3 pF CLK1 10 CLK: SDRAM D9, 10 CLK: SDRAM D11, 12 +3.3 pF 10 CLK: SDRAM D5, 6 CLK: SDRAM D7, 8 +3.3 pF 10 CLK: SDRAM D0, 1 CLK: SDRAM D2, 3 +3.3 pF RAS CAS WE A (11:0) BA0 BA1 RAS: SDRAM D0-3, 5-12, 14-17 CAS: SDRAM D0-3, 5-12, 14-17 WE: SDRAM D0-3, 5-12, 14-17 A (11:0): SDRAM D0-3, 5-12, 14-17 A13: SDRAM D0-3, 5-12, 14-17 A12: SDRAM D0-3, 5-12, 14-17
To Top / Lineup / Index
MB8516S064CZ-102 / -103 / -102L / -103L
s ABSOLUTE MAXIMUM RATINGS (See WARNING)
s RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Input High Voltage, All Inputs Input Low Voltage, All Inputs Ambient Temperature Notes 1 1, 2 1, 3 Symbol VCC VSS VIH VIL TA Value Min. 3.0 0 2.0 -0.5 0 Typ. 3.3 0 - - - Max. 3.6 0 VCC +0.5 0.8 +70 Unit V V V V °C
To Top / Lineup / Index
MB8516S064CZ-102 / -103 / -102L / -103L
s CAPACITANCE
To Top / Lineup / Index
MB8516S064CZ-102 / -103 / -102L / -103L
s DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Notes 1, 2, 3
Value Parameter
Notes Symbol
Condition
Max. Min. std. ver. low ver.
ICC1S
Operating Current (Average Power Supply Current)
ICC1D
ICC2P
ICC2PS
Precharge Standby Current (Power Supply Current)
4 ICC2N
ICC2NS
(Continued)
To Top / Lineup / Index
MB8516S064CZ-102 / -103 / -102L / -103L
(Continued)
Value Parameter
Notes
Symbol
Condition
Max. Min. std. ver. 32 low ver. 16
ICC3P
ICC3PS
Active Standby Current (Power Supply Current)
4 ICC3N
ICC3NS
Burst Mode Current (Average Power Supply Current)
Auto-refresh Current (Average Power Supply Current) Self-refresh Current (Average Power Supply Current) Input Leakage Current (All Inputs) Output Leakage Current LVTTL Output High Voltage LVTTL Output Low Voltage
ILI ILO 5 5 VOH VOL
To Top / Lineup / Index
MB8516S064CZ-102 / -103 / -102L / -103L
s AC CHARACTERISTICS
(SDRAM Component Specifications) Notes 1, 2, 3 (1) BASE CHARACTERISTICS (At recommended operating conditions unless otherwise noted.)
To Top / Lineup / Index
MB8516S064CZ-102 / -103 / -102L / -103L
(2) BASE VALUES FOR CLOCK COUNT / LATENCY
(3) CLOCK COUNT FORMULA (9)
Clock Base Value Clock Period (Round off a whole number)
(4) LATENCY (The latency values on these parameters are fixed regardless of clock period.)
To Top / Lineup / Index
MB8516S064CZ-102 / -103 / -102L / -103L
s AC OPERATING TEST CONDITION (Example of AC Test Load Circuit)
To Top / Lineup / Index
MB8516S064CZ-102 / -103 / -102L / -103L
s SERIAL PRESENCE DETECT(SPD) FUNCTION
1. PIN DESCRIPTIONS
SCL (Serial Clock) SCL input is used to clock all data input / output of SPD. SDA (Serial Data) SDA is a common pin used for all data input / output of SPD. The SDA pull-up resistor is required due to the open-drain output. SA0, SA1, SA2 (Address) Address inputs are used to set the least significant three bits of the eight bits slave address. The address inputs must be fixed to select a particular module and the fixed address of each module must be different each other.
2. SPD OPERATIONS
Fig. 1 - START AND STOP CONDITIONS
To Top / Lineup / Index
MB8516S064CZ-102 / -103 / -102L / -103L
ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will put the SDA line to Low in order to acknowledge that it received the eight bits of data. The SPD will respond with an acknowledge when it received the start condition followed by slave address issued by master. In the read operation, the SPD will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is issued by master, the SPD will continue to transmit data. If an acknowledge is not detected, the SPD will terminated further data transmissions. The master must then issue a stop condition to return the SPD to the standby power mode. In the write operation, upon receipt of eight bits of data the SPD will respond with an acknowledge, and await the next eight bits of data, again responding with an acknowledge until the stop condition is issued by master. SLAVE ADDRESS ADDRESSING Following a start condition, the master must output the eight bits slave address. The most significant four bits of the slave address are device type identifier. For the SPD this is fixed as 1010B. Refer to the Fig. 2 below. The next three significant bits are used to select a particular device. A system could have up to eight SPD devices -namely up to eight modules- on the bus. The eight addresses for eight SPD devices are defined by the state of the SA0, SA1 and SA2 inputs. The last bit of the slave address defines the operation to be performed. When R / W bit is "1", a read operation is selected, when R / W bit is "0", a write operation is selected. Following the start condition, the SPD monitors the SDA line comparing the slave address being transmitted with its slave address (device type and state of SA0, SA1, and SA2 inputs). Upon a correct compare the SPD outputs an acknowledge on the SDA line. Depending on the state of the R / W bit, the SPD will execute a read or write operation. Fig. 2 - SLAVE ADDRESS
DEVICE TYPE IDENTIFIER DEVICE ADDRESS
To Top / Lineup / Index
MB8516S064CZ-102 / -103 / -102L / -103L
3. READ OPERATIONS
Fig. 3 - CURRENT ADDRESS READ
BUS ACTIVITY : MASTER SDA LINE
BUS ACTIVITY : SPD
Fig. 4 - RANDOM READ
S T BUS ACTIVITY : A R MASTER T SDA LINE BUS ACTIVITY : SPD A C K A C K A C K S T A R T
SLAVE ADDRESS
WORD ADDRESS
SLAVE ADDRESS
To Top / Lineup / Index
MB8516S064CZ-102 / -103 / -102L / -103L
SEQUENTIAL READ Sequential Read can be initiated as either a current address read or random read. The first data are transmitted as with the other read mode, however, the master now responds with an acknowledge, indicating it requires additional data. The SPD continues to output data for each acknowledge received. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig. 5 for the sequence of address, acknowledge and data transfer. The data output is sequential, with the data from address(n) followed by the data from address(n+1). The address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 255), the counter "rolls over" to address 0 and the SPD continues to output data for each acknowledge received.
Fig. 5 - SEQUENTIAL READ
SLAVE ADDRESS BUS ACTIVITY : MASTER SDA LINE BUS ACTIVITY : SPD A C K A C K A C K A C K S T O P
DATA (n)
DATA (n+1)
DATA (n+2)
DATA (n+x)
4. DC CHARACTERISTICS
To Top / Lineup / Index
MB8516S064CZ-102 / -103 / -102L / -103L
5. AC CHARACTERISTICS
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Parameter SCL Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out Valid Time the Bus Must Be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time Data in Hold Time Data in Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time Write Cycle Time Symbol fSCL TI tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH tWR Value Min. - - - 4.7 4.0 4.7 4.0 4.7 0 250 - - 4.7 100 - Max. 100 100 3.5 - - - - - - - 1 300 - - 15 Unit
Fig. 6 - TIMING WAVEFORM
tF tR tLOW SCL tSU : STA tHD : DAT tHD : STA SDA (input) tAA SDA (output) tDH tSU : DAT tSU : STO
tHIGH
To Top / Lineup / Index
MB8516S064CZ-102 / -103 / -102L / -103L
s PACKAGE DIMENSION
168-pin plastic DIMM (socket type) (MDS-168P-P38)
3.00(.118)MIN.
4.00(.157)MAX.
Details of "A" part
3.25(.128) 3.00(.118) Details of "B" part C L
1998 FUJITSU LIMITED M168038SC-1-1
3.25(.128) 3.00(.118) Details of "C" part 2.54(.100)TYP. NOTCHES FULL R
Dimension in mm (inches)
To Top / Lineup / Index
MB8516S064CZ-102 / -103 / -102L / -103L
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp /
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com /
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com /
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg /