MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER FAMILY 38000 SERIES 38
|
|
|
Top Searches for this datasheet
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER FAMILY 38000 SERIES
3820
Group
User's Manual
Keep safety first your circuit designs! Mitsubishi Electric Corporation puts maximum effort into making semiconductor products better more reliable, there always possibility that trouble occur with them. Trouble with semiconductors lead personal injury, fire property damage. Remember give consideration safety when making your circuit designs, with appropriate measures such placement substitutive, auxiliary circuits, (ii) non-flammable material (iii) prevention against malfunction mishap. Notes regarding these materials These materials intended reference assist customers selection Mitsubishi semiconductor product best suited customer's application; they convey license under intellectual property rights, other rights, belonging Mitsubishi Electric Corporation third party. Mitsubishi Electric Corporation assumes responsibility damage, infringement third-party's rights, originating product data, diagrams, charts circuit application examples contained these materials. information contained these materials, including product data, diagrams charts, represent information products time publication these materials, subject change Mitsubishi Electric Corporation without notice product improvements other reasons. therefore recommended that customers contact Mitsubishi Electric Corporation authorized Mitsubishi Semiconductor product distributor latest product information before purchasing product listed herein. Mitsubishi Electric Corporation semiconductors designed manufactured device system that used under circumstances which human life potentially stake. Please contact Mitsubishi Electric Corporation authorized Mitsubishi Semiconductor product distributor when considering product contained herein specific purposes, such apparatus systems transportation, vehicular, medical, aerospace, nuclear, undersea repeater use. prior written approval Mitsubishi Electric Corporation necessary reprint reproduce whole part these materials. these products technologies subject Japanese export control restrictions, they must exported under license from Japanese government cannot imported into country other than approved destination. diversion reexport contrary export control laws regulations Japan and/or country destination prohibited. Please contact Mitsubishi Electric Corporation authorized Mitsubishi Semiconductor product distributor further details these materials products contained therein.
REVISION DESCRIPTION LIST
Rev. First Edition
3820 GROUP USER'S MANUAL
Revision Description Rev. date 970901
(1/1)
Preface
This user's manual describes Mitsubishi's CMOS 8bit microcomputers 3820 Group. After reading this manual, user should have through knowledge functions features 3820 Group, should able fully utilize product. manual starts with specifications ends with application examples. details software, refer "SERIES <SOFTWARE> USER'S MANUAL."
BEFORE USING THIS USER'S MANUAL
This user's manual consists following three chapters. Refer chapter appropriate your conditions, such hardware design software development.
Organization
CHAPTER HARDWARE This chapter describes features microcomputer, operation each peripheral function electric characteristics. CHAPTER APPLICATION This chapter describes usage application examples peripheral functions, based mainly setting examples related registers. CHAPTER APPENDIX This chapter includes precautions systems development using microcomputer, list control registers, masking confirmation forms (mask version), programming confirmation forms (One Time PROM version) mark specification forms which submitted when ordering.
Structure register
figure each register structure describes functions, contents reset, attributes follows
attributes (Note Bits (Note Values immediately after reset release
mode register (CPUM) [Address:3B Stack page selection this "1." Port switch Main clock IN-XOUT) stop Main clock division ratio selection Internal system clock selection
port XCIN, XCOUT Oscillating Stopped f(XIN (high-speed mode) (high-speed mode) f(XIN (middle-speed mode) XIN-XOUT selected (middle-/high-speed mode) XCIN-XCOUT selected (low-speed mode)
Name Processor mode bits
b1b0
Functions
Single-chip mode available page page
reset
which nothing allocated
that used control corresponding function
Notes Values immediately after reset release reset release reset release reset release attributes control register bits classified into types read-only, write-only read write. figure, these attributes represented follows enabled enabled disabled disabled write enabled
Table contents
Table contents
CHAPTER HARDWARE
DESCRIPTION FEATURES APPLICATIONS CONFIGURATION (TOP VIEW) FUNCTIONAL BLOCK DIAGRAM (Package: 80P6N-A) DESCRIPTION PART NUMBERING GROUP EXPANSION GROUP EXPANSION (EXTENDED OPERATING TEMPERATURE VERSION) GROUP EXPANSION (LOW POWER SOURCE VOLTAGE VERSION) 1-10 FUNCTIONAL DESCRIPTION 1-11 Central Processing Unit (CPU) .1-11 Mode Register .1-11 MEMORY 1-12 Special Function Register (SFR) Area 1-12 .1-12 1-12 Interrupt Vector Area 1-12 Zero Page .1-12 Special Page .1-12 PORTS .1-14 Direction Registers (ports P41-P47, P5-P7) 1-14 Direction Registers (ports 1-14 Ports 1-14 Pull-up/Pull-down Control 1-14 INTERRUPTS 1-19 Interrupt Control .1-19 Interrupt Operation .1-19 Notes .1-19 Input Interrupt (Key-on Wake 1-21 TIMERS .1-22 Timer .1-23 Timer Write Control 1-23 Note CNTR0 Interrupt Active Edge Selection 1-23 Real Time Port Control .1-23 Timer .1-24 Note CNTR1 Interrupt Active Edge Selection 1-24 Timer Timer Timer 1-25 Timer Write Control 1-25 Timer Output Control .1-25 Note Timer Timer 1-25 SERIAL I/O1 1-26 Clock Synchronous Serial Mode 1-26 Serial I/O1 Control Register (SIO1CON) 001A16 1-28 UART Control Register (UARTCON) 001B16 1-28 Serial I/O1 Status Register (SIO1STS) 001916 1-28 Transmit Buffer/Receive Buffer Register (TB/RB) 001816 1-28 Baud Rate Generator (BRG) 001C16 1-28 SERIAL I/O2 1-30 Serial I/O2 Control Register (SIO2CON) 001D16 1-30
3820 GROUP USER'S MANUAL
Table contents
DRIVE CONTROL CIRCUIT 1-32 Bias Control Applied Voltage Power Input Pins 1-34 Common Duty Ratio Control 1-34 Display .1-35 Drive Timing .1-35 WATCHDOG TIMER 1-38 Initial Value Watchdog Timer. 1-38 Watchdog Timer Operation 1-38 CLOCK OUTPUT FUNCTION .1-39 RESET CIRCUIT 1-40 CLOCK GENERATING CIRCUIT 1-42 Frequency Control .1-42 Oscillation Control .1-42 NOTES PROGRAMMING 1-45 Processor Status Register 1-45 Interrupt 1-45 Decimal Calculations 1-45 Timers. 1-45 Multiplication Division Instructions 1-45 Ports .1-45 Serial I/O. 1-45 Instruction Execution Time 1-45 DATA REQUIRED MASK ORDERS 1-46 PROGRAMMIG METHOD 1-46 Absolute maximum ratings 1-47 Recommended operating conditions 1-47 Electrical characteristics 1-49 Timing requirements 1-51 Timing requirements 1-51 Switching characteristics 1-52 Switching characteristics 1-52 Absolute maximum ratings (Extended operating temperature version) 1-53 Recommended operating conditions (Extended operating temperature version) 1-53 Electrical characteristics (Extended operating temperature version) 1-55 Timing requirements (Extended operating temperature version) 1-57 Timing requirements (Extended operating temperature version) 1-57 Switching characteristics (Extended operating temperature version) 1-58 Switching characteristics (Extended operating temperature version) 1-58 Absolute maximum ratings (Low power source voltage version) 1-59 Recommended operating conditions (Low power source voltage version) 1-59 Electrical characteristics (Low power source voltage version) 1-61 Timing requirements (Low power source voltage version) 1-63 Timing requirements (Low power source voltage version) 1-63 Switching characteristics (Low power source voltage version) 1-64 Switching characteristics (Low power source voltage version) 1-64 Timing diagram 1-65 STANDARD CHARACTERISTICS 1-66 Power Source Current Characteristic Examples CC-VCC characteristics) 1-66 Power Source Frequency Characteristic Examples 1-68 Port Standard Characteristic Examples 1-69
3820 GROUP USER'S MANUAL
Table contents CHAPTER APPLICATION
pins 2.1.1 ports 2.1.2 Function pins .2-7 2.1.3 Application examples. 2.1.4 Notes .2-12 Interrupts .2-15 2.2.1 Explanation operations 2-15 2.2.2 Control 2-19 2.2.3 Related registers .2-22 2.2.4 interrupts .2-28 2.2.5 input interrupt .2-29 2.2.6 Notes .2-31 Timer timer .2-32 2.3.1 Explanation timer operations. 2-32 2.3.2 Explanation timer operations. 2-42 2.3.3 Related registers .2-50 2.3.4 Register setting example .2-66 2.3.5 Application examples. 2-75 2.3.6 Notes .2-82 Timer timer timer 2-85 2.4.1 Explanation operations 2-85 2.4.2 Related registers .2-90 2.4.3 Register setting example .2-99 2.4.4 Application example 2-100 2.4.5 Notes .2-102 Serial I/O1 2-103 2.5.1 Explanation operations 2-103 2.5.2 Pins 2-120 2.5.3 Related registers .2-121 2.5.4 Register setting example .2-129 2.5.5 Notes .2-139 Serial I/O2 2-141 2.6.1 Explanation operations 2-141 2.6.2 Pins 2-148 2.6.3 Related registers .2-149 2.6.4 Register setting example .2-152 2.6.5 Notes .2-154 drive control circuit .2-155 2.7.1 Explanation operations 2-155 2.7.2 Pins 2-156 2.7.3 Related registers .2-159 2.7.4 Register setting example .2-166 2.7.5 Application examples. 2-168 2.7.6 Notes .2-172 Watchdog timer .2-173 2.8.1 Explanation operations 2-173 2.8.2 Related register. 2-175 Standby function .2-176 2.9.1 Stop mode .2-176 2.9.2 Wait mode .2-181 2.9.3 State transitions internal clock 2-184
3820 GROUP USER'S MANUAL
Table contents
2.10 Reset .2-185 2.10.1 Explanation operations 2-185 2.10.2 Internal state microcomputer immediately after reset release 2-187 2.10.3 Reset circuit .2-188 2.10.4 Notes RESET 2-189 2.11 Oscillation circuit 2-190 2.11.1 Oscillation circuit.2-190 2.11.2 Internal clock .2-192 2.11.3 Oscillating operation .2-194 2.11.4 Oscillation stabilizing time 2-197
CHAPTER APPENDIX
Built-in PROM version 3.1.1 Product expansion 3.1.2 Performance overview 3.1.3 configuration .3-5 3.1.4 Functional block diagram 3.1.5 Notes .3-9 Countermeasures against noise 3-11 3.2.1 Shortest wiring length 3-11 3.2.2 Connection bypass capacitor across line line 3-12 3.2.3 Oscillator concerns 3-13 3.2.4 Installing oscillator away from signal lines where potential levels change frequently. 3-14 3.2.5 Oscillator protection using pattern 3-14 3.2.6 ports 3-14 3.2.7 Providing watchdog timer function software 3-15 Control registers .3-16 List instruction codes 3-29 Machine instructions 3-30 Mask ordering method 3-40 Mark specification form 3-52 Package outlines 3-54 allocation 3-56 3.10 configuration 3-57
3820 GROUP USER'S MANUAL
List figures
List figures
CHAPTER HARDWARE
Fig. configuration M38203M4-XXXFP Fig. configuration M38203M4-XXXGP/HP Fig. Function block diagram .1-4 Fig. Part numbering .1-7 Fig. Memory expansion plan .1-8 Fig. Memory expansion plan .1-9 Fig. Memory expansion plan 1-10 Fig. Structure mode register 1-11 Fig. Memory diagram 1-12 Fig. Memory special function register (SFR) 1-14 Fig. Structure PULL register PULL register 1-15 Fig. Port block diagram 1-16 Fig. Port block diagram 1-17 Fig. Port block diagram 1-18 Fig. Interrupt control 1-20 Fig. Structure interrupt-related registers 1-21 Fig. Connection example when using input interrupt port block diagram 1-21 Fig. Timer block diagram 1-22 Fig. Structure timer mode register 1-23 Fig. Structure timer mode register 1-24 Fig. Structure timer mode register 1-25 Fig. Block diagram clock synchronous serial I/O1 1-26 Fig. Operation clock synchronous serial I/O1 function 1-26 Fig. Block diagram UART serial I/O1 1-27 Fig. Operation UART serial I/O1 function 1-27 Fig. Structure serial I/O1 control registers 1-29 Fig. Structure serial I/O2 control register 1-29 Fig. Block diagram serial I/O2 function 1-30 Fig. Timing serial I/O2 function 1-31 Fig. Structure segment output enable register mode register 1-32 Fig. Block diagram controller/driver 1-33 Fig. Example circuit each bias 1-34 Fig. display 1-35 Fig. drive waveform (1/2 bias) 1-36 Fig. drive waveform (1/3 bias) 1-37 Fig. Watchdog timer block diagram 1-38 Fig. Structure watchdog timer control register 1-38 Fig. Structure output control register 1-39 Fig. Example reset circuit 1-40 Fig. Internal state microcomputer immediately after reset 1-40 Fig. Reset sequence 1-41 Fig. Ceramic resonator circuit 1-42 Fig. External clock input circuit 1-42 Fig. Clock generating circuit block diagram 1-43 Fig. State transitions internal clock 1-44 Fig. Programming testing Time PROM version 1-46 Fig. Circuit measuring output switching characteristics 1-64 Fig. Timing diagram 1-65 Fig. ICC-VCC characteristic example (f(XIN MHz)) 1-66 Fig. ICC-VCC characteristic example (f(XIN MHz)) 1-66 Fig. ICC-VCC characteristic example (f(XIN) kHz, oscillator used) 1-67 Fig. ICC-f(XIN) characteristic example (VCC 1-68
3820 GROUP USER'S MANUAL
List figures
Fig. ICC-f(XIN) characteristic example (VCC 1-68 Fig. IOH-VOH characteristic example CMOS output port P-channel drive (P0, 1-69 Fig. IOL-VOL characteristic example CMOS output port N-channel drive (P0, 1-69 Fig. IOH-VOH characteristic example CMOS output port P-channel drive (P2, 1-70 Fig. IOL-VOL characteristic example CMOS output port N-channel drive (P2, 1-70
CHAPTER APPLICATION
Fig. 2.1.1 port write read Fig. 2.1.2 Structure port direction register Fig. 2.1.3 Structure ports direction registers Fig. 2.1.4 Port direction register setting example Fig. 2.1.5 Structure PULL register .2-6 Fig. 2.1.6 Structure PULL register .2-6 Fig. 2.1.7 Connection example input Fig. 2.1.8 input control procedure Fig. 2.1.9 Timing diagram where switch pressed Fig. 2.1.10 Connection example input 2-10 Fig. 2.1.11 input control procedure 2-10 Fig. 2.1.12 Timing diagram where switch pressed 2-11 Fig. 2.2.1 Interrupt operation diagram 2-15 Fig. 2.2.2 Changes stack pointer program counter upon acceptance interrupt request 2-17 Fig. 2.2.3 Processing time execution interrupt processing routine 2-18 Fig. 2.2.4 Timing after acceptance interrupt request 2-18 Fig. 2.2.5 Interrupt control diagram 2-19 Fig. 2.2.6 Example multiple interrupts 2-21 Fig. 2.2.7 Memory allocation interrupt-related registers 2-22 Fig. 2.2.8 Structure interrupt edge selection register 2-22 Fig. 2.2.9 Structure interrupt request register 2-23 Fig. 2.2.10 Structure interrupt request register 2-24 Fig. 2.2.11 Structure interrupt control register 2-25 Fig. 2.2.12 Structure interrupt control register 2-26 Fig. 2.2.13 Structure processor status register 2-27 Fig. 2.2.14 Structure interrupt edge selection register 2-28 Fig. 2.2.15 Connection example when input interrupt used, port block diagram 2-29 Fig. 2.2.16 Setting values (corresponding Figure 2.2.15) input interrupt-related registers 2-30 Fig. 2.2.17 Register setting example 2-31 Fig. 2.3.1 Timer mode operation example 2-33 Fig. 2.3.2 Pulse output mode operation example 2-35 Fig. 2.3.3 Event counter mode operation example 2-37 Fig. 2.3.4 Pulse width measurement mode operation example 2-39 Fig. 2.3.5 Timer mode operation example with real time port function 2-41 Fig. 2.3.6 Timer mode operation example 2-43 Fig. 2.3.7 Period measurement mode operation example 2-45 Fig. 2.3.8 Event counter mode operation example 2-47 Fig. 2.3.9 Pulse width continuously measurement mode operation example 2-49 Fig. 2.3.10 Memory allocation timer timer Y-related registers 2-50 Fig. 2.3.11 Structure port direction register 2-51 Fig. 2.3.12 Structure port direction register 2-52 Fig. 2.3.13 Structure timer latch 2-53 Fig. 2.3.14 Structure timer counter 2-54 Fig. 2.3.15 Structure timer latch 2-55 Fig. 2.3.16 Structure timer counter 2-56 Fig. 2.3.17 Structure timer mode register 2-57 Fig. 2.3.18 Structure timer mode register 2-60 Fig. 2.3.19 Structure interrupt request register 2-62 Fig. 2.3.20 Structure interrupt request register 2-63 Fig. 2.3.21 Structure interrupt control register 2-64
3820 GROUP USER'S MANUAL
List figures
Fig. 2.3.22 Structure interrupt control register 2-65 Fig. 2.3.23 Example setting registers using timer mode 2-66 Fig. 2.3.24 Example setting registers using pulse output mode 2-67 Fig. 2.3.25 Example setting registers using event counter mode 2-68 Fig. 2.3.26 Example setting registers using pulse width measurement mode 2-69 Fig. 2.3.27 Example setting registers using 2-70 Fig. 2.3.28 Example setting registers using timer mode 2-71 Fig. 2.3.29 Example setting registers using period measurement mode 2-72 Fig. 2.3.30 Example setting registers using event counter mode 2-73 Fig. 2.3.31 Example setting registers using pulse width continuously measurement mode 2-74 Fig. 2.3.32 Example peripheral circuit 2-75 Fig. 2.3.33 Connection timer setting division ratio 2-75 Fig. 2.3.34 Setting related registers 2-76 Fig. 2.3.35 Control procedure .2-76 Fig. 2.3.36 Example peripheral circuit 2-77 Fig. 2.3.37 Setting related registers 2-77 Fig. 2.3.38 Ringer signal waveform 2-78 Fig. 2.3.39 Operation timing when ringing pulse input 2-78 Fig. 2.3.40 Control procedure .2-79 Fig. 2.3.41 Application connection example when used 2-80 Fig. 2.3.42 output example 2-80 Fig. 2.3.43 Timer interrupt processing procedure example when used 2-81 Fig. 2.4.1 Timer mode operation example 2-86 Fig. 2.4.2 Rewriting example counter latch corresponding timers 2-87 Fig. 2.4.3 Rewriting example timer counter timer latch (Writing timer latch only) 2-88 Fig. 2.4.4 Pulse output example 2-89 Fig. 2.4.5 Memory allocation timer-related registers 2-90 Fig. 2.4.6 Structure latches .2-91 Fig. 2.4.7 Structure timer counters 2-92 Fig. 2.4.8 Structure timer mode register 2-93 Fig. 2.4.9 Structure interrupt request register 2-95 Fig. 2.4.10 Structure interrupt request register 2-96 Fig. 2.4.11 Structure interrupt control register 2-97 Fig. 2.4.12 Structure interrupt control register 2-98 Fig. 2.4.13 Example setting registers timers 2-99 Fig. 2.4.14 Setting related registers 2-100 Fig. 2.4.15 Control procedure .2-101 Fig. 2.5.1 External connection example clock synchronous mode 2-103 Fig. 2.5.2 Shift clock .2-104 Fig. 2.5.3 Transmit operation clock synchronous mode 2-107 Fig. 2.5.4 Transmit timing example clock synchronous mode 2-108 Fig. 2.5.5 Receive operation clock synchronous mode 2-110 Fig. 2.5.6 Receive timing example clock synchronous mode 2-110 Fig. 2.5.7 Transmit/receive timing example clock synchronous mode 2-111 Fig. 2.5.8 External connection example UART mode 2-112 Fig. 2.5.9 Transfer data format UART mode .2-114 Fig. 2.5.10 transfer data formats UART mode .2-115 Fig. 2.5.11 Transmit timing example UART mode 2-117 Fig. 2.5.12 Receive timing example UART mode .2-119 Fig. 2.5.13 Memory allocation serial I/O1-related registers 2-121 Fig. 2.5.14 Structure transmit/receive buffer register 2-121 Fig. 2.5.15 Structure serial I/O1 status register 2-122 Fig. 2.5.16 Structure serial I/O1 control register 2-124 Fig. 2.5.17 Structure UART control register 2-127 Fig. 2.5.18 Transmitting method clock synchronous mode 2-129 Fig. 2.5.19 Transmitting method clock synchronous mode 2-130 Fig. 2.5.20 Receiving method clock synchronous mode 2-131 Fig. 2.5.21 Receiving method clock synchronous mode 2-132
3820 GROUP USER'S MANUAL
List figures
Fig. 2.5.22 Transmitting method UART mode .2-133 Fig. 2.5.23 Transmitting method UART mode .2-134 Fig. 2.5.24 Receiving method UART mode 2-135 Fig. 2.5.25 Receiving method UART mode 2-136 Fig. 2.6.1 External connection example serial I/O2 2-141 Fig. 2.6.2 Shift clock .2-142 Fig. 2.6.3 Transmit operation serial I/O2 .2-144 Fig. 2.6.4 Transmit timing example serial I/O2 2-144 Fig. 2.6.5 Receive operation serical I/O2 .2-146 Fig. 2.6.6 Receive timing example serial I/O2 2-146 Fig. 2.6.7 Transmit/receive timing example serial I/O2 (P53/SRDY2 used) 2-147 Fig. 2.6.8 Memory allocation serial I/O2-related registers 2-149 Fig. 2.6.9 Structure serial I/O2 control register 2-149 Fig. 2.6.10 Structure serial I/O2 register .2-151 Fig. 2.6.11 Transmitting method serial I/O2 2-152 Fig. 2.6.12 Receiving method serial I/O2 .2-153 Fig. 2.7.1 Memory allocation display-related registers 2-159 Fig. 2.7.2 Structure segment output enable register 2-160 Fig. 2.7.3 Structure mode register 2-162 Fig. 2.7.4 Structure port direction register .2-163 Fig. 2.7.5 Structure port direction register .2-164 Fig. 2.7.6 Structure PULL register .2-165 Fig. 2.7.7 Example setting registers display 2-166 Fig. 2.7.8 Example setting registers display 2-167 Fig. 2.7.9 8-segment panel display pattern example when duty ratio number 2-168 Fig. 2.7.10 panel example .2-169 Fig. 2.7.11 Segment allocation example 2-169 Fig. 2.7.12 display setting example 2-169 Fig. 2.7.13 Setting related registers 2-170 Fig. 2.7.14 Control procedure .2-171 Fig. 2.8.1 Internal reset signal output timing .2-173 Fig. 2.8.2 Structure watchdog timer control register 2-175 Fig. 2.9.1 Oscillation stabilizing time restoration reset input 2-177 Fig. 2.9.2 Execution sequence example restoration occurrence INT0 interrupt request 2-179 Fig. 2.9.3 Reset input time .2-182 Fig. 2.9.4 State transitions internal clock 2-184 Fig. 2.10.1 Internal reset state hold/release timing 2-185 Fig. 2.10.2 Internal processing sequence immediately after reset release 2-186 Fig. 2.10.3 Internal state microcomputer immediately after reset release 2-187 Fig. 2.10.4 Poweron reset conditions 2-188 Fig. 2.10.5 Poweron reset circuit examples .2-188 Fig. 2.11.1 Oscillation circuit example using ceramic resonators 2-190 Fig. 2.11.2 External clock input circuit example .2-191 Fig. 2.11.3 Clock generating circuit block diagram 2-192 Fig. 2.11.4 Structure output control register 2-193 Fig. 2.11.5 State transitions internal clock 2-196 Fig. 2.11.6 Oscillation stabilizing time poweron 2-197 Fig. 2.11.7 Oscillation stabilizing time reoscillation 2-198
3820 GROUP USER'S MANUAL
List figures CHAPTER APPENDIX
Fig. 3.1.1 configuration EPROM version (top view) Fig. 3.1.2 configuration Time PROM version (top view) Fig. 3.1.3 configuration Time PROM version (top view) Fig. 3.1.4 Functional block diagram built-in PROM version Fig. 3.1.5 Programming testing Time PROM version (shipped blank) 3-10 Fig. 3.2.1 Wiring RESET input 3-11 Fig. 3.2.2 Wiring clock pins 3-11 Fig. 3.2.3 Wiring Time PROM EPROM version 3-12 Fig. 3.2.4 Bypass capacitor across line line 3-12 Fig. 3.2.5 Analog signal line resistor capacitor 3-13 Fig. 3.2.6 Wiring large current signal line 3-13 Fig. 3.2.7 Wiring signal line where potential levels change frequently 3-14 Fig. 3.2.8 pattern underside oscillator 3-14 Fig. 3.2.9 Setup ports 3-14 Fig. 3.2.10 Watchdog timer software 3-15 Fig. 3.3.1 Structure port direction registers 3-16 Fig. 3.3.2 Structure port direction registers 3-16 Fig. 3.3.3 Structure PULL register 3-17 Fig. 3.3.4 Structure PULL register 3-17 Fig. 3.3.5 Structure serial I/O1 status register 3-18 Fig. 3.3.6 Structure serial I/O1 control register 3-19 Fig. 3.3.7 Structure UART control register 3-20 Fig. 3.3.8 Structure serial I/O2 control register 3-20 Fig. 3.3.9 Structure timer mode register 3-21 Fig. 3.3.10 Structure timer mode register 3-22 Fig. 3.3.11 Structure timer mode register 3-23 Fig. 3.3.12 Structure output control register 3-23 Fig. 3.3.13 Structure watchdog timer control register 3-24 Fig. 3.3.14 Structure segment output register 3-24 Fig. 3.3.15 Structure mode register 3-25 Fig. 3.3.16 Structure interrupt edge selection register 3-26 Fig. 3.3.17 Structure mode register 3-26 Fig. 3.3.18 Structure interrupt request register 3-27 Fig. 3.3.19 Structure interrupt request register 3-27 Fig. 3.3.20 Structure interrupt control register 3-28 Fig. 3.3.21 Structure interrupt control register 3-28
3820 GROUP USER'S MANUAL
List tables
List tables
CHAPTER HARDWARE
Table description Table description Table List supported products Table List supported products Table ports functions 1-15 Table Interrupt vector addresses priority 1-19 Table Maximum number display pixels each duty ratio 1-32 Table Bias control applied voltage VL1-VL3 1-34 Table Duty ratio control common pins used 1-34 Table Programming adapter 1-46 Table Absolute maximum ratings .1-47 Table Recommended operating conditions 1-47 Table Recommended operating conditions 1-48 Table Electrical characteristics 1-49 Table Electrical characteristics 1-50 Table Timing requirements 1-51 Table Timing requirements 1-51 Table Switching characteristics .1-52 Table Switching characteristics .1-52 Table Absolute maximum ratings (Extended operating temperature version) 1-53 Table Recommended operating conditions (Extended operating temperature version) 1-53 Table Recommended operating conditions (Extended operating temperature version) 1-54 Table Electrical characteristics (Extended operating temperature version) 1-55 Table Electrical characteristics (Extended operating temperature version) 1-56 Table Timing requirements (Extended operating temperature version) 1-57 Table Timing requirements (Extended operating temperature version) 1-57 Table Switching characteristics (Extended operating temperature version) 1-58 Table Switching characteristics (Extended operating temperature version) 1-58 Table Absolute maximum ratings (Low power source voltage version) 1-59 Table Recommended operating conditions (Low power source voltage version) 1-59 Table Recommended operating conditions (Low power source voltage version) 1-60 Table Electrical characteristics (Low power source voltage version) 1-61 Table Electrical characteristics (Low power source voltage version) 1-62 Table Timing requirements (Low power source voltage version) 1-63 Table Timing requirements (Low power source voltage version) 1-63 Table Switching characteristics (Low power source voltage version) 1-64 Table Switching characteristics (Low power source voltage version) 1-64
CHAPTER APPLICATION
Table 2.1.1 Memory allocation port registers Table 2.1.2 Memory allocation port direction registers Table 2.1.3 ports which either pull-up pull-down controlled software Table 2.1.4 Termination unused pins 2-14 Table 2.2.1 Interrupt sources interrupt request generating conditions 2-16 Table 2.2.2 List interrupt bits individual interrupt sources 2-20 Table 2.3.1 Real time ports bits storing data 2-40 Table 2.3.2 Relation between timer operating mode bits operating modes 2-58 Table 2.3.3 Relation between timer operating mode bits operating modes 2-61 Table 2.3.4 Table example timer setting value 2-81 Table 2.3.5 Table example setting value 2-81
3820 GROUP USER'S MANUAL
List tables
Table 2.4.1 Relation between timer count source selection count sources 2-94 Table 2.4.2 Relation between timer count source selection count sources 2-94 Table 2.4.3 Relation between timer count source selection count sources 2-94 Table 2.5.1 Baud rate selection table (reference values) 2-113 Table 2.5.2 Each function UART transmit data 2-114 Table 2.5.3 Control contents transmit enable 2-125 Table 2.5.4 Control contents receive enable 2-126 Table 2.5.5 Relation between UART control register transfer data formats 2-128 Table 2.6.1 Relation between internal synchronization clock selection synchronizing clock 2-150 Table 2.7.1 functions setting segment output enable register 2-156 Table 2.7.2 functions setting corresponding registers when they used segment output pins 2-157 Table 2.7.3 Setting segment output pins display 2-157 Table 2.7.4 Setting input port ports 2-158 Table 2.7.5 Setting pull-down pins 2-158 Table 2.8.1 Program runaway detection time (maximum) 2-173 Table 2.9.1 State stop mode 2-176 Table 2.9.2 State wait mode 2-181 Table 2.10.1 Timers reset 2-186
CHAPTER APPENDIX
Table 3.1.1 Product expansion built-in PROM version Table 3.1.2 Performance overview built-in PROM version
3820 GROUP USER'S MANUAL
CHAPTER HARDWARE
DESCRIPTION FEATURES APPLICATIONS CONFIGURATION FUNCTIONAL BLOCK DESCRIPTION PART NUMBERING GROUP EXPANSION FUNCTIONAL DESCRIPTION NOTES PROGRAMMING DATA REQUIRED MASK ORDERS PROGRAMMING METHOD
MITSUBISHI MICROCOMPUTERS MITSUBISHI MICROCOMPUTERS
3820 3820 Group Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
3820 group 8-bit microcomputer based family core technology. 3820 group drive control circuit serial additional functions. various microcomputers 3820 group include variations internal memory size packaging. details, refer section part numbering. details availability microcomputers 3820 group, refer section group expansion.
drive control circuit
Bias 1/2, Duty 1/2, 1/3, Common output Segment output Clock generating circuit Clock (XIN-XOUT) Internal feedback resistor Sub-clock (XCIN-XCOUT) Without internal feedback resistor (connect external ceramic resonator quartz-crystal oscillator) Watchdog timer 15-bit Power source voltage high-speed mode 8MHz oscillation frequency high-speed selected) middle-speed mode 8MHz oscillation frequency middle-speed selected) low-speed mode (Extended operating temperature version: Power dissipation high-speed mode oscillation frequency) low-speed mode oscillation frequency, power source voltage) Operating temperature range 85°C (Extended operating temperature version: 85°C)
FEATURES
Basic machine-language instructions minimum instruction execution time
8MHz oscillation frequency)
Memory size
bytes 1024 bytes Programmable input/output ports Software pull-up/pull-down resistors (Ports P0-P7 except Port P40) Interrupts sources, vectors (includes input interrupt) Timers 8-bit 16-bit Serial I/O1 8-bit (UART Clock-synchronized) Serial I/O2 8-bit (Clock-synchronized)
APPLICATIONS
Household appliances, consumer electronics, etc.
CONFIGURATION (TOP VIEW)
P30/SEG16 P31/SEG17 P32/SEG18 P33/SEG19 P34/SEG20 P35/SEG21 P36/SEG22 P37/SEG23 P00/SEG24 P01/SEG25 P02/SEG26 P03/SEG27 P04/SEG28 P05/SEG29 P06/SEG30 P07/SEG31 P10/SEG32 P11/SEG33 P12/SEG34 P13/SEG35 P14/SEG36 P15/SEG37 P16/SEG38 P17/SEG39
SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
M38203M4-XXXFP M38203M4-XXXFP
XOUT P70/XCOUT P71/XCIN RESET P41/
Fig. configuration M38203M4-XXXFP
SEG0 COM3 COM2 COM1 COM0 P61/RTP1 P60/INT3/RTP0 P57/INT2 P56/TOUT P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/INT1 P42/INT0
Package type 80P6N-A 80-pin plastic-molded
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CONFIGURATION (TOP VIEW)
P32/SEG18 P33/SEG19 P34/SEG20 P35/SEG21 P36/SEG22 P37/SEG23 P00/SEG24 P01/SEG25 P02/SEG26 P03/SEG27 P04/SEG28 P05/SEG29 P06/SEG30 P07/SEG31 P10/SEG32 P11/SEG33 P12/SEG34 P13/SEG35 P14/SEG36 P15/SEG37
P31/SEG17 P30/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3
M38203M4-XXXGP M38203M4-XXXHP
P16/SEG38 P17/SEG39 XOUT P70/XCOUT P71/XCIN RESET P41/ P42/INT0 P43/INT1
Package type 80P6S-A/80P6D-A 80-pin plastic-molded
Fig. configuration M38203M4-XXXGP/
COM2 COM1 COM0 P61/RTP1 P60/INT3/RTP0 P57/INT2 P56/TOUT P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD
3820 GROUP USER'S MANUAL
RTP0,RTP1
XCIN P5(8) P4(8) P3(8)
INT0,INT1
Real time port function
INT2
Key-on wake
Reset input RESET (5V)
FUNCTIONAL BLOCK DIAGRAM (Package 80P6N-A)
Clock input (0V)
Clock output XOUT
Fig. Functional block diagram
Data
Clock generating circuit Timer X(16) Timer Y(16) Timer 1(8) Timer 3(8) Timer 2(8) display bytes)
drive control circuit COM0 COM1 COM2 COM3
XCIN Subclock input
XCOUT Subclock output
FUNCTIONAL BLOCK DIAGRAM (Package 80P6N-A)
3820 GROUP USER'S MANUAL
SI/O2(8) TOUT CNTR0,CNTR1 SI/O1(8) P2(8) P1(8)
Watchdog timer
RESET
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15
XCOUT
P7(2)
P6(2)
P0(8) P0(8)
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
port
port
port
port
Input port
port
port
port
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
Table description RESET XOUT Reset input Clock input Clock output Reset input active Input output pins main clock generating circuit. Feedback resistor built between XOUT pin. Connect ceramic resonator quartz-crystal oscillator between XOUT pins oscillation frequency. external clock used, connect clock source leave XOUT open. This clock used oscillating source system clock. Input voltage Input voltage common output pins COM2 COM3 used duty ratio. COM3 used duty ratio. segment output pins 8-bit port CMOS compatible input level CMOS 3-state output structure direction register allows each port individually programmed either input output. Pull-down control enabled. 8-bit port CMOS compatible input level CMOS 3-state output structure direction register allows each port individually programmed either input output. Pull-down control enabled. 8-bit port CMOS compatible input level CMOS 3-state output structure direction register allows each individually programmed either input output. Pull-up control enabled. 8-bit Input port CMOS compatible input level Pull-down control enabled. 1-bit input CMOS compatible input level 7-bit port CMOS compatible input level CMOS 3-state output structure direction register allows each individually programmed either input output. Pull-up control enabled. clock output Interrupt input pins Serial I/O1 function pins input (key-on wake interrupt input pins segment pins Name Power source Function Apply voltage VCC, VSS. (Extended operating temperature version Function except port function
COM0 COM3
power source Common output
SEG0 SEG15 P00/SEG24 P07/SEG31
Segment output port
P10/SEG32 P17/SEG39
port
port
P30/SEG16 P37/SEG23 P41/ P42/INT0, P43/INT1 P44/RXD, P45/TXD, P46/SCLK1, P47/SRDY1
Input port
segment pins
Input port port
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table description P50/SIN2, P51/SOUT2, P52/SCLK2, P53/SRDY2 P54/CNTR0, P55/CNTR1 P56/TOUT P57/INT2 P60/INT3/RTP0 P61/RTP1 port 2-bit port CMOS compatible input level CMOS 3-state output structure direction register allows each individually programmed either input output. Pull-up control enabled. 2-bit port CMOS compatible input level CMOS 3-state output structure direction register allows each individually programmed either input output. Pull-up control enabled. Name port Function Function except port function 8-bit port CMOS compatible input level CMOS 3-state output structure direction register allows each individually programmed either input output. Pull-up control enabled. Serial I/O2 function pins
Timer function pins Timer output Interrupt input Interrupt input pins(P60) Real time port function
P70/XCOUT, P71/XCIN
port
Sub-clock generating circuit input pins (Connect resonator. External clock cannot used.)
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product M3820 Package type 80P6N-A package 80P6S-A package 80P6D-A package 80D0 package number Omitted some types. Normally, using hyphen When electrical characteristic, division quality identification code using alphanumeric character standard Extended operating temperature version ROM/PROM size 4096 bytes 8192 bytes 12288 bytes 16384 bytes 20480 bytes 24576 bytes 28672 bytes 32768 bytes first bytes last bytes reserved areas they cannot used. Memory type Mask version EPROM Time PROM version size bytes bytes bytes bytes bytes bytes bytes 1024 bytes
Fig. Part numbering
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans expand 3820 group follows: Support mask ROM, Time PROM, EPROM versions ROM/PROM size bytes size 1024 bytes
Packages 80P6N-A mm-pitch plastic molded 80P6S-A 0.65 mm-pitch plastic molded 80P6D-A mm-pitch plastic molded 80D0 mm-pitch ceramic (EPROM version)
Memory Expansion Plan
size (bytes) product M38207M8/E8
Mass product M38203M4/E4
size (bytes)
1024
Products under development: development schedule specification revised without notice. Fig. Memory expansion plan Currently supported products listed below. Table List supported products Product M38203M4-XXXFP M38203E4-XXXFP M38203E4FP M38203M4-XXXGP M38203E4-XXXGP M38203E4GP M38203M4-XXXHP M38203E4-XXXHP M38203E4HP M38203E4FS M38207M8-XXXFP M38207E8-XXXFP M38207E8FP M38207M8-XXXGP M38207E8-XXXGP M38207E8GP M38207M8-XXXHP M38207E8-XXXHP M38207E8HP M38207E8FS size (bytes) size User size (bytes) Package Remarks Mask version Time PROM version Time PROM version (blank) Mask version Time PROM version Time PROM version (blank) Mask version Time PROM version Time PROM version (blank) EPROM version Mask version Time PROM version Time PROM version (blank) Mask version Time PROM version Time PROM version (blank) Mask version Time PROM version Time PROM version (blank) EPROM version
April 1995
80P6N-A
16384 (16254)
80P6S-A
80P6D-A 80D0 80P6N-A
32768 (32638)
1024
80P6S-A
80P6D-A 80D0
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION (EXTENDED OPERATING TEMPERATURE VERSION)
Mitsubishi plans expand 3820 group (extended operating temperature version) follows: Support mask ROM, Time PROM, EPROM versions
size bytes size 1024 bytes Packages 80P6N-A mm-pitch plastic molded
Memory Expansion Plan
size (bytes) product M38207M8D
product M38203M4D
size (bytes)
1024
Products under development: development schedule specification revised without notice. Fig. Memory expansion plan
Currently supported products listed below. Table List supported products Product M38203M4DXXXFP M38207M8DXXXFP size (bytes) size User 16384(16254) 32768(32638) size (bytes) 1024 Package 80P6N-A 80P6N-A Mask version Mask version Remarks April 1995
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Packages 80P6N-A mm-pitch plastic molded 80P6S-A 0.65 mm-pitch plastic molded 80P6D-A mm-pitch plastic molded 80D0 mm-pitch ceramic (EPROM version)
GROUP EXPANSION (LOW POWER SOURCE VOLTAGE VERSION)
Mitsubishi plans expand 3820 group (low power source voltage version) follows: Support mask ROM, Time PROM, EPROM versions ROM/PROM size bytes size 1024 bytes
Memory Expansion Plan
size (bytes)
product M38203M4L
product M38203M2L
size (bytes)
1024
Products under development: development schedule specification revised without notice. Fig. Memory expansion plan
Currently supported products listed below. Table List supported products Product M38203M2L-XXXFP M38203M2L-XXXGP M38203M2L-XXXHP M38203M4L-XXXFP M38203M4L-XXXGP M38203M4L-XXXHP size (bytes) size User 8192 (8062) 16384 (16254) size (bytes) Package 80P6N-A 80P6S-A 80P6D-A 80P6N-A 80P6S-A 80P6D-A Mask version Mask version Mask version Mask version Mask version Mask version Remarks April 1995
1-10
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)
3820 group uses standard family instruction set. Refer table family addressing modes machine instructions SERIES <Software> User's Manual details instruction set. Machine-resident family instructions follows: instruction cannot used. STP, WIT, MUL, instruction used.
Mode Register
mode register allocated address 003B16. mode register contains stack page selection internal system clock selection bit.
mode register
(CPUM (CM) address 003B16)
Processor mode bits Single-chip mode available Stack page selection page page used (returns when read) write this bit) Port switch port CIN, XCOUT Main clock IN-XOUT) stop Oscillating Stopped Main clock division ratio selection IN)/2 (high-speed mode) IN)/8 (middle-speed mode) Internal system clock selection IN-XOUT selected (middle-/high-speed mode) CIN-XCOUT selected (low-speed mode)
Fig. Structure mode register
3820 GROUP USER'S MANUAL
1-11
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY Special Function Register (SFR) Area
Special Function Register area zero page contains control registers such ports timers.
Zero Page
bytes from addresses 000016 00FF called zero page area. internal special function registers (SFR) allocated this area. zero page addressing mode used specify memory register addresses zero page area. Access this area with only bytes possible zero page addressing mode.
used data storage stack area subroutine calls interrupts.
Special Page
first bytes last bytes reserved device testing rest user area storing programs. bytes from addresses FF0016 FFFF16 called special page area. special page addressing mode used specify memory addresses special page area. Access this area with only bytes possible special page addressing mode.
Interrupt Vector Area
interrupt vector area contains reset interrupt vectors.
area
size (bytes) Address XXXX16
000016
area Zero page
1024
00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16
004016 display area 005416 010016
XXXX16 Reserved area 044016
area
size (bytes) Address YYYY16 Address ZZZZ16
used YYYY16
4096 8192 12288 16384 20480 24576 28672 32768
F00016 E00016 D00016 C00016 B00016 A00016 900016 800016
F08016 E08016 D08016 C08016 B08016 A08016 908016 808016
Reserved area
(128 bytes)
ZZZZ16
FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Reserved area Special page
Fig. Memory diagram
1-12
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16
Port (P0) Port direction register (P0D) Port (P1) Port direction register (P1D) Port (P2) Port direction register (P2D) Port (P3)
002016 002116 002216 002316 002416 002516 002616 002716
Timer (low-order) (TXL) Timer (high-order) (TXH) Timer (low-order) (TYL) Timer (high-order) (TYH) Timer (T1) Timer (T2) Timer (T3) Timer mode register (TXM) Timer mode register (TYM) Timer mode register (T123M) output control register (CKOUT)
Port (P4) Port direction register (P4D) Port (P5) Port direction register (P5D) Port (P6) Port direction register (P6D) Port (P7) Port direction register (P7D)
002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516
PULL register (PULLA) PULL register (PULLB) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Serial I/O2 control register (SIO2CON)
003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 Watchdog timer control register (WDTCON) Segment output enable register (SEG) mode register (LM) Interrupt edge selection register (INTEDGE) mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Interrupt control register 2(ICON2)
Serial I/O2 register (SIO2)
003F16
Fig. Memory special function register (SFR)
3820 GROUP USER'S MANUAL
1-13
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PORTS Direction Registers (ports 1-P47, P5-P7)
3820 group programmable pins arranged seven ports (ports P0-P2 P4-P7). ports P41-P4 P5-P7 have direction registers which determine input/output direction each individual pin. Each direction register corresponds pin, each input port output port. When written corresponding pin, that becomes input pin. When written that bit, that becomes output pin. data read from output, value port output latch read, value itself. Pins input floating. input written only port output latch written remains floating.
PULL register (PULLA address 0016 P00-P07 pull-down P10-P17 pull-down P20-P27 pull-up P30-P37 pull-down P70, pull-up used (return when read)
PULL register (PULLB address 0017 P41-P43 pull-up P44-P47 pull-up P50-P53 pull-up P54-P57 pull-up P60, pull-up used (return when read) pull-up pull-down) Pull-up (pull-down) Note ports output mode, pull-up pull-down impossible.
Direction Registers (ports
Ports have direction registers which determine input /output direction each individual port. Each port direction register corresponds port, each port input output. When written direction register, that port becomes input port. When written that port, that port becomes output port. Bits ports direction registers used.
Fig. Structure PULL register PULL register
Ports
These ports only input.
Pull-up/Pull-down Control
setting PULL register (address 001616) PULL register (address 001716), ports except port control either pull-down pull-up (pins that shared with segment output pins pull-down; other pins pull-up) with program. However, contents PULL register PULL register affect ports programmed output ports.
1-14
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table ports functions P00/SEG24- P07/SEG31 P10/SEG32- P17/SEG39 Name Port Input/Output Input/output, individual ports Input/output, individual ports Input/output, individual bits Format CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS compatible input level clock output PULL register output control register PULL register Interrupt edge selection register PULL register Serial I/O1 control register Serial I/O1 status register UART control register PULL register Serial I/O2 control register PULL register Timer mode register PULL register Timer mode register PULL register Timer mode register PULL register Interrupt edge selection register PULL register Timer mode register Interrupt edge selection register PULL register Timer mode register PULL register mode register mode register Non-Port Function segment output Related SFRs PULL register Segment output enable register PULL register Segment output enable register PULL register Interrupt control register PULL register Segment output enable register Diagram
Port
segment output input(Key-on wake interrupt input segment output
Port
P30/SEG16- P37/SEG23
Port
Input
Input
P41/
P42/INT0, P43/INT1 P44/RXD P45/TXD P46/SCLK1 P47/SRDY1 P50/SIN2 P51/SOUT2 P52/SCLK2 P53/SRDY2 P54/CNTR0
Port
Input/output, individual bits
CMOS compatible input level CMOS 3-state output
External interrupt input
(10) (11) (12) (13) (14) (10) (15)
Serial I/O1 function
Serial I/O2 function
Port P55/CNTR1 P56/TOUT
Input/output, individual bits
CMOS compatible input level CMOS 3-state output
Timer Timer Timer output
P57/INT2
External interrupt input
P60/INT3/RTP0 Port P61/RTP1 P70/XCOUT Port P71/XCIN COM0-COM3 SEG0-SEG15 Common Segment Input/output, individual bits
CMOS compatible input level CMOS 3-state output
External interrupt input Real time port function output Real time port function output Sub-clock generating circuit
(16)
Input/output, individual bits output output
CMOS compatible input level CMOS 3-state output common output segment output
(17) (18) (19) (20)
Note Make sure that input level each either during execution instruction. When input level intermediate potential, current will flow from through input-stage gate.
3820 GROUP USER'S MANUAL
1-15
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1)Ports P0,P1
VL2/VL3
(2)Ports P2,P42,P43,P57
Pull-up control VL1/VSS
Segment output enable
(Note) Direction register Direction register
Data Data Port latch
Port latch
input (Key-on wake interrupt input INT0-INT2 interrupt input Pull-down control Segment output enable Note. port direction register port direction register.
(3)Ports P30-P37
VL2/VL3
(4)Port
Data VL1/VSS Data Pull-down control Segment output enable
(5)Port
Pull-up control
(6)Port
Pull-up control Serial I/O1 enable Reception enable
Direction register Direction register
Data
Port latch Data Port latch
output control Serial I/O1 input
(7)Port
(8)Port
Serial I/O1 synchronization clock selection Serial I/O1 enable Serial I/O1 mode selection Serial I/O1 enable
Direction register
Pull-up control P45/TXD P-channel output disable Serial I/O1 enable Transmission enable
Direction register
Pull-up control
Data
Port latch
Data
Port latch
Serial I/O1 output
Serial I/O1 clock output Serial I/O1 clock input
Fig. Port block diagram
1-16
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port
Pull-up control
(10) Ports P50,P55
Pull-up control
Serial I/O1 mode selection Serial I/O1 enable SRDY1 output enable
Direction register
Direction register
Data
Port latch
Data
Port latch
Serial I/O1 ready output
Serial I/O2 input CNTR1 interrupt input
(11) Port
(12) Port
Internal synchronization clock select bits Serial I/O2 port selection
Direction register Direction register
Pull-up control Serial I/O2 transmit completion signal Serial I/O2 port selection
Pull-up control
Data
Port latch
Data
Port latch
Serial I/O2 output
Serial I/O2 clock output Serial I/O2 clock input
(13) Port
Pull-up control SRDY2 output enable
Direction register
(14) Port
Pull-up control
Direction register
Data
Port latch
Data
Port latch
Serial I/O2 ready output
Timer operating mode (Pulse output mode selection) Timer output CNTR0 interrupt input
(15) Port
Pull-up control
(16) Ports P60,
Pull-up control
Direction register
Direction register
Data
Port latch
Data
Port latch
TOUT output control Timer output
Real time port control Data real time port INT3 interrupt input Except
Fig. Port block diagram
3820 GROUP USER'S MANUAL
1-17
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(17) Port
Port selection/Pull-up control Port switch
Direction register
(18) Port
Port selection/Pull-up control Port switch
Direction register
Data
Port latch
Data
Port latch
Oscillation circuit Port Port switch Sub-clock generating circuit input
(19) COM0 -COM3
(20) SEG0 SEG15
VL2/VL3
VL1/VSS
gate input signal each transistor controlled duty ratio bias value.
voltage applied sources P-channel N-channel transistors controlled voltage bias value.
Fig. Port block diagram
1-18
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur sixteen sources: seven external, eight internal, software.
Interrupt Operation
When interrupt received, contents program counter processor status register automatically stored into stack. interrupt disable flag inhibit other interrupts from interfering.The corresponding interrupt request cleared interrupt jump destination address read from vector table into program counter.
Interrupt Control
Each interrupt controlled interrupt request bit, interrupt enable bit, interrupt disable flag except software interrupt instruction. interrupt occurs corresponding interrupt request enable bits interrupt disable flag "0". Interrupt enable bits cleared software. Interrupt request bits cleared software, cannot software. instruction cannot disabled with flag bit. (interrupt disable) flag disables interrupts except instruction interrupt.
Notes
When active edge external interrupt (INT0-INT3, CNTR0, CNTR changed, corresponding interrupt request also set. Therefore, please take following sequence; Disable external interrupt which selected. Change active edge selection. Clear interrupt request which selected "0". Enable external interrupt which selected.
Table Interrupt vector addresses priority Interrupt Source Reset (Note INT0 INT1 Serial I/O1 receive Serial I/O1 transmit Timer Timer Timer Timer CNTR0 CNTR1 Timer INT2 INT3 input (Key-on wake Serial I/O2 instruction Priority Vector Addresses (Note High FFFC16 FFFD16 FFFB16 FFF916 FFF716 FFFA16 FFF816 FFF616 Interrupt Request Generating Conditions reset detection either rising falling edge INT0 input detection either rising falling edge INT1 input completion serial I/O1 data reception completion serial I/O1 transmit shift when transmit buffer register empty timer underflow timer underflow timer underflow timer underflow detection either rising falling edge CNTR0 input detection either rising falling edge CNTR1 input timer underflow detection either rising falling edge INT2 input detection either rising falling edge INT3 input falling conjunction input level port input mode) completion serial I/O2 data transmission reception instruction execution Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 selected
FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFDD16
FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 FFDC16
Valid when serial I/O1 selected
External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid when level applied) Valid when serial I/O2 selected Non-maskable software interrupt
Note Vector addresses contain interrupt jump destination addresses. Reset function same interrupt with highest priority.
3820 GROUP USER'S MANUAL
1-19
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request Interrupt enable
Interrupt disable flag
instruction Reset
Interrupt request
Fig. Interrupt control
Interrupt edge selection register (INTEDGE address 003A16) INT0 interrupt edge selection INT1 interrupt edge selection INT2 interrupt edge selection INT3 interrupt edge selection used (return when read) Falling edge active Rising edge active Interrupt request register (IREQ2 address 003D16) CNTR0 interrupt request CNTR1 interrupt request Timer interrupt request INT2 interrupt request INT3 interrupt request input interrupt request Serial I/O2 interrupt request used (returns when read) interrupt request issued Interrupt request issued
Interrupt request register (IREQ1 address 003C16) INT0 interrupt request INT1 interrupt request Serial I/O1 receive interrupt request Serial I/O1 transmit interrupt request Timer interrupt request Timer interrupt request Timer interrupt request Timer interrupt request
Interrupt control register (ICON1 address 003E16) INT0 interrupt enable INT1 interrupt enable Serial I/O1 receive interrupt enable Serial I/O1 transmit interrupt enable Timer interrupt enable Timer interrupt enable Timer interrupt enable Timer interrupt enable
Interrupt control register (ICON2 address 003F16) CNTR0 interrupt enable CNTR1 interrupt enable Timer interrupt enable INT2 interrupt enable INT3 interrupt enable input interrupt enable Serial I/O2 interrupt enable used (returns when read) write this bit) Interrupts disabled Interrupts enabled
Fig. Structure interrupt-related registers
1-20
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Input Interrupt (Key-on Wake
input interrupt request generated applying level port that have been input mode. other words, generated when input level goes from "0".
example using input interrupt shown Figure where interrupt request generated pressing keys consisted active-low matrix which inputs ports P20-P23.
Port level output PULL register Port direction register Port latch
input interrupt request
output
Port direction register Port latch
output
Port direction register Port latch
output
Port direction register Port latch
output
Port direction register Port latch
Port Input reading circuit
input
Port direction register Port latch
input
Port direction register Port latch
input
Port direction register Port latch
input
P-channel transistor pull-up CMOS output buffer
Fig. Connection example when using input interrupt port block diagram
3820 GROUP USER'S MANUAL
1-21
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
3820 group five timers: timer timer timer timer timer Timer timer 16-bit timers, timer timer timer 8-bit timers. timers down count timers. When timer reaches "0016", underflow occurs next count pulse corresponding timer latch reloaded into timer count continued. When timer underflows, interrupt request corresponding that timer "1".
Read write operation 16-bit timer must performed both high low-order bytes. When reading 16-bit timer, read high-order byte first. When writing 16-bit timer, write low-order byte first. 16-bit timer cannot perform correct operation when reading during write operation, when writing during read operation.
Real time port control direction register
Data Latch data real time port
latch Real time port control direction register latch
Latch
data real time port Real time port control Timer stop control Timer (low) latch Timer (low)
Timer mode register write signal
f(XIN)/16 (f(XCIN)/16 low-speed mode*) CNTR0 active edge switch Timer operating mode "00","01","11"
Timer write control Timer (high) latch Timer (high) Timer interrupt request CNTR0 interrupt request
P54/CNTR0
"10" Pulse width measurement CNTR0 active mode edge switch
Pulse output mode Rising edge detection Timer operating mode "00","01","10"
Pulse width continuously measurement mode
direction register latch Pulse output mode
CNTR1 interrupt request
"11"
Period measurement mode
P55/CNTR1
CNTR1 active edge switch
Falling edge detection f(XIN)/16 (f(XCIN)/16 low-speed mode*) Timer stop control "00","01","11" Timer (low) latch Timer (low)
Timer (high) latch Timer (high) Timer interrupt request
"10"Timer operating mode
f(XIN)/16 (f(XCIN)/16 low-speed mode*) Timer count source selection XCIN Timer count source selection Timer latch Timer
f(XIN)/16 (f(XCIN)/16 low-speed mode*)
Timer write control
Timer interrupt request Timer interrupt request
Timer latch Timer
TOUT output TOUT output control active edge switch P56/TOUT direction register latch Timer latch Timer Timer count source selection Timer interrupt request
TOUT output control f(XIN)/16(f(XCIN)/16 low-speed mode*) Internal clock XCIN/2.
Fig. Timer block diagram
1-22
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer
Timer 16-bit timer that selected four modes controlled timer write real time port setting timer mode register. Timer mode timer counts f(XIN)/16 f(XCIN)/16 low-speed mode). Pulse output mode Each time timer underflows, signal output from CNTR0 inverted. Except this, operation pulse output mode same timer mode. When using timer this mode, corresponding port direction register output mode. Event counter mode timer counts signals input through CNTR0 pin. Except this, operation event counter mode same timer mode. When using timer this mode, corresponding port direction register input mode. Pulse width measurement mode count source f(XIN)/16 f(XCIN)/16 low-speed mode. CNTR0 active edge switch "0", timer counts while input signal CNTR0 "H". "1", timer counts while input signal CNTR0 "L". When using timer this mode, corresponding port direction register input mode.
Note CNTR0 Interrupt Active Edge Selection
CNTR0 interrupt active edge depends CNTR0 active edge switch bit.
Real Time Port Control
While real time port function valid, data real time port output from each time timer underflows. (However, after rewriting data real time port, real time port control changed from "1", data output without timer data real time port changed while real time port function valid, changed data output next underflow timer Before using this function, corresponding port direction registers output mode.
Timer mode register (TXM address 0027 Timer write control Write value latch counter Write value latch only Real time port control Real time port function invalid Real time port function valid data real time port level output level output data real time port level output level output Timer operating mode bits Timer mode Pulse output mode Event counter mode Pulse width measurement mode CNTR0 active edge switch CNTR0 interrupt Falling edge active Rising edge active Pulse output mode Start initial level output Start initial level output Event counter mode Rising edge active Falling edge active Pulse width measurement mode Measure level width Measure level width Timer stop control Count start Count stop
Timer Write Control
timer write control "0", when value written address timer value loaded timer latch same time. timer write control "1", when value written address timer value loaded only latch. value latch loaded timer after timer underflows. value written latch only, unexpected value high-order counter when writing high-order latch underflow timer performed same timing.
Fig. Structure timer mode register
3820 GROUP USER'S MANUAL
1-23
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer
Timer 16-bit timer that selected four modes. Timer mode timer counts f(XIN)/16 f(XCIN)/16 low-speed mode). Period measurement mode CNTR interrupt request generated rising/falling edge CNTR1 input signal. Simultaneously, value timer latch reloaded timer timer continues counting down/Except above-mentioned, operation period measurement mode same timer mode. timer value just before reloading rising/falling CNTR1 input signal retained until timer read once after reload. rising/falling timing CNTR input signal found CNTR1 interrupt. When using timer this mode, corresponding port direction register input mode. Event counter mode timer counts signals input through CNTR1 pin. Except this, operation event counter mode same timer mode. When using timer this mode, corresponding port direction register input mode. Pulse width continuously measurement mode CNTR interrupt request generated both rising falling edges CNTR input signal. Except this, operation pulse width continuously measurement mode same period measurement mode. When using timer this mode, corresponding port direction register input mode.
Timer mode register (TYM address 0028 used (return when read) Timer operating mode bits Timer mode Period measurement mode Event counter mode Pulse width continuously measurement mode CNTR1 active edge switch CNTR1 interrupt Falling edge active Rising edge active Period measurement mode Measure falling edge falling edge Measure rising edge rising edge Event counter mode Rising edge active Falling edge active Timer stop control Count start Count stop
Fig. Structure timer mode register
Note CNTR1 Interrupt Active Edge Selection
CNTR1 interrupt active edge depends CNTR1 active edge switch bit. However, pulse width continuously measurement mode, CNTR interrupt request generated both rising falling edges CNTR1 input signal regardless setting CNTR1 active edge switch bit.
1-24
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer Timer Timer
Timer timer timer 8-bit timers. count source each timer selected timer mode register. timer latch value affected change count source. However, because changing count source cause inadvertent count down timer. Therefore, rewrite value timer whenever count source changed.
Timer mode register (T123M :address 0029 TOUT output active edge switch Start output Start output TOUT output control TOUT output disabled TOUT output enabled Timer write control Write value latch counter Write value latch only Timer count source selection Timer underflow f(XIN)/16 (Middle-/high-speed mode) f(XCIN)/16 (Low-speed mode)(Note) Timer count source selection Timer underflow f(XIN)/16 (Middle-/high-speed mode) f(XCIN)/16 (Low-speed mode)(Note) Timer count source selection f(XIN)/16 (Middle-/high-speed mode) f(XCIN)/16 (Low-speed mode)(Note) f(XCIN) used (return when read) Note Internal clock (XCIN)/2 low-speed mode.
Timer Write Control
timer write control "0", when value written address timer value loaded timer latch same time. timer write control "1", when value written address timer value loaded only latch. value latch loaded timer after timer underflows.
Timer Output Control
When timer OUT) output enabled, inversion signal from TOUT output each time timer underflows. this case, port shared with port TOUT output mode.
Note Timer Timer
When count source timer changed, timer counting value changed large because thin pulse generated count input timer timer output selected count source timer timer when timer written, counting value timer timer changed large because thin pulse generated timer output. Therefore, value timer order timer timer timer after count source selection timer
Fig. Structure timer mode register
3820 GROUP USER'S MANUAL
1-25
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O1
Serial I/O1 used either clock synchronous asynchronous (UART) serial I/O1. dedicated timer (baud rate generator) also provided baud rate generation.
Clock Synchronous Serial Mode
Clock synchronous serial I/O1 mode selected setting mode selection serial I/O1 control register "1". clock synchronous serial I/O1, transmitter receiver must same clock. internal clock used, transfer started write signal TB/RB (address 001816).
Data Serial I/O1 control register Address 001A
Address 0018
Receive buffer register (RB)
Receive buffer full flag (RBF) Serial receive interrupt request (RI) Clock control circuit
P44/RXD
Receive shift register Shift clock
P46/SCLK1 Serial I/O1 synchronization clock selection Frequency division ratio 1/(n+1) Baud rate generator Address 001C
f(XIN
count source selection
P47/SRDY1
Falling-edge detector Shift clock
Clock control circuit Transmit shift register shift completion flag (TSC) Transmit interrupt source selection Serial transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 0019
P45/TXD
Transmit shift register
Transmit buffer register (TB)
Address 0018 Data
Fig. Block diagram clock synchronous serial I/O1
Transfer shift clock (1/2 1/2048 internal clock, external clock) Serial output Serial input
Receive enable signal SRDY1
Write signal receive/transmit buffer register (address 001816)
Overrun error (OE) detection
Notes serial I/O1 transmit interrupt (TI) selected occur either when transmit buffer register emptied (TBE=1) after transmit shift operation ended (TSC=1), setting transmit interrupt source selection (TIC) serial I/O1 control register. data written transmit buffer register when TSC=0, transmit clock generated continuously serial data output continuously from pin. serial I/O1 receive interrupt (RI) when receive buffer full flag (RBF) becomes
Fig. Operation clock synchronous serial I/O1 function
1-26
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Asynchronous Serial I/O1 (UART) Mode
Clock asynchronous serial I/O1 mode (UART) selected clearing serial I/O1 mode selection serial I/O1 control register "0". Eight serial data transfer formats selected, transfer formats used transmitter receiver must identical. transmit receive shift registers each have buffer regis-
ter, buffers have same address memory. Since shift register cannot written read from directly, transmit data written transmit buffer register, receive data read from receive buffer register. transmit buffer register also hold next data transmitted, receive buffer register hold character while next character being received.
Data Address 0018 Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF)
Serial receive interrupt request (RI)
Receive buffer register(RB) Character length selection
P44/RXD
STdetector
bits bits
Receive shift register 1/16 detector Clock control circuit UART control register Address 001B16
Serial I/O1 synchronization clock selection P46/SCLK1 count source selection Frequency division ratio 1/(n+1) Baud rate generator Address 001C ST/SP/PA generator 1/16 P45/TXD Character length selection
Transmit buffer register
f(XIN)
Transmit shift register shift completion flag (TSC) Transmit interrupt source selection Serial I/O1 status register Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916
Transmit shift register
Address 001816 Data
Fig. Block diagram UART serial I/O1
Transmit receive clock
Transmit buffer register write signal TBE=0 TSC=0 TBE=1 TBE=0 TBE=1 TSC=1V
Serial output
start data bits parity stop
Generated 2-stop-bit mode
Receive buffer register read signal
RBF=0 RBF=1 RBF=1
Serial input
Notes Error flag detection occurs same time that flag becomes stop bit, during reception). transmit interrupt (TI) selected occur when either flag becomes "1", depending setting transmit interrupt source selection (TIC) serial I/O1 control register. serial I/O1 receive interrupt (RI) when flag becomes "1". After data written transmit buffer register when TSC=1, cycles data shift cycle necessary until changing TSC=0.
Fig. Operation UART serial I/O1 function
3820 GROUP USER'S MANUAL
1-27
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O1 Control Register (SIO1CON) 001A16
serial I/O1 control register contains eight control bits serial I/O1 function.
UART Control Register (UARTCON) 001B16
UART control register consists four control bits (bits which valid when asynchronous serial selected data format data transfer. this register (bit always valid sets output structure P45/TXD pin.
Serial I/O1 Status Register (SIO1STS) 001916
read-only serial I/O1 status register consists seven flags (bits which indicate operating status serial function various errors. Three flags (bits valid only UART mode. receive buffer full flag (bit cleared when receive buffer read. there error, detected same time that data transferred from receive shift register receive buffer register, receive buffer full flag set. write serial status register clears error flags (bit respectively). Writing serial enable SIOE (bit Serial Control Register) also clears status flags, including error flags. bits serial I/O1 status register initialized reset, transmit enable (bit serial control register been "1", transmit shift register shift completion flag (bit transmit buffer empty flag (bit become "1".
Transmit Buffer/Receive Buffer Register (TB/ 001816
transmit buffer register receive buffer register located same address. transmit buffer register writeonly receive buffer register read-only. character length bits, data stored receive buffer register "0".
Baud Rate Generator (BRG) 001C16
baud rate generator determines baud rate serial transfer. baud rate generator divides frequency count source 1/(n where value written baud rate generator.
1-28
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O1 status register (SIO1STS address 0019 Transmit buffer empty flag (TBE) Buffer full Buffer empty Receive buffer full flag (RBF) Buffer empty Buffer full Transmit shift register shift completion flag (TSC) Transmit shift progress Transmit shift completed Overrun error flag (OE) error Overrun error Parity error flag (PE) error Parity error Framing error flag (FE) error Framing error Summing error flag (SE) used (returns when read)
Serial I/O1 control register (SIO1CON address 001A count source selection (CSS) IN)/4 Serial I/O1 synchronization clock selection (SCS) clock synchronous mode output/4 External clock input UART mode output/16 External clock input/16 SRDY1 output enable (SRDY) SRDY1 operates port SRDY1 operates signal output SRDY1 (SRDY1 signal indicates receive enable state) Transmit interrupt source selection (TIC) When transmit buffer emptied When transmit shift operation completed Transmit enable (TE) Transmit disabled Transmit enabled Receive enable (RE) Receive disabled Receive enabled Serial I/O1 mode selection (SIOM) Clock asynchronous serial I/O1 (UART) mode Clock synchronous serial I/O1 mode Serial I/O1 enable (SIOE) Serial I/O1 disabled (pins 4-P4 operate pins) Serial I/O1 enabled (pins 4-P4 operate serial I/O1 pins)
UART control register (UARTCON address 001B Character length selection (CHAS) bits bits Parity enable (PARE) Parity checking disabled Parity checking enabled Parity selection (PARS) Even parity parity Stop length selection (STPS) stop stop bits P45/TXD P-channel output disable (POFF) CMOS output output mode) N-channel open-drain output output mode) used (return"1" when read)
Fig. Structure serial I/O1 control registers
3820 GROUP USER'S MANUAL
1-29
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O2
serial I/O2 function used only clock synchronous serial I/O. clock synchronous serial I/O2 transmitter receiver must same clock. internal clock used, transfer started write signal serial I/O2 register.
Serial I/O2 control register (SIO2CON address 001D16) Internal synchronization clock select bits
Serial I/O2 Control Register (SIO2CON) 001D16
serial I/O2 control register contains bits which control various serial functions.
f(XIN)/8 f(XIN)/16 f(XIN)/32 f(XIN)/64 f(XIN)/128 f(XIN)/256 Serial I/O2 port selection port SOUT2,SCLK2 signal output SRDY2 output enable port SRDY2 signal output Transfer direction selection first first Synchronization clock selection External clock Internal clock used (returns when read)
Fig. Structure serial I/O2 control register
1/16
Divider
Internal synchronization clock select bits
1/32 1/64 1/128 1/256
Data
latch Synchronization clock selection SRDY2 Synchronization circuit
SCLK2
P53/SRDY2
SRDY2 output enable
External clock
latch
P52/SCLK2
Serial I/O2 port selection latch
Serial counter
Serial I/O2 interrupt request
P51/SOUT2
Serial I/O2 port selection
P50/SIN2
Serial shift register
Fig. Block diagram serial I/O2 function
1-30
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Transfer clock (Note Serial I/O2 register write signal
(Note
Serial I/O2 output OUT2 Serial I/O2 input
Receive enable signal SRDY2
Serial I/O2 interrupt request Notes When internal clock selected transfer clock, divide ratio selected setting bits serial I/O2 control register. When internal clock selected transfer clock, OUT2 goes high impedance after transfer completion.
Fig. Timing serial I/O2 function
3820 GROUP USER'S MANUAL
1-31
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
segment output enable register display RAM, drive control circuit starts reading display data automatically, performs bias control duty ratio control, displays data panel. Table Maximum number display pixels each duty ratio Duty ratio Maximum number display pixel dots segment digits dots segment digits dots segment digits
DRIVE CONTROL CIRCUIT
3820 group built-in Liquid Crystal Display (LCD) drive control circuit consisting following. display Segment output enable register mode register Selector Timing controller Common driver Segment driver Bias control circuit maximum segment output pins common output pins used. pixels controlled display. When enable after data mode register,
Segment output enable register (SEG address 0038 Segment output enable Input ports P30-P37 Segment output SEG16-SEG23 Segment output enable ports P00, Segment output 24,SEG25 Segment output enable ports P02-P07 Segment output SEG26-SEG31 Segment output enable ports P10,P11 Segment output SEG32,SEG33 Segment output enable port Segment output SEG34 Segment output enable ports P13-P17 Segment output SEG35-SEG39 used (return when read) write this bit)
mode register address 0039 Duty ratio selection bits available (use 0,COM1) (use 0-COM2) (use 0-COM3) Bias control bias bias enable used (returns when read) write this bit) circuit divider division ratio selection bits LCDCK count source division LCDCK count source division LCDCK count source division LCDCK count source LCDCK count source selection (Note) f(XCIN)/32 f(XIN)/8192 Note LCDCK clock timing controller.
Fig. Structure segment output enable register mode register
1-32
3820 GROUP USER'S MANUAL
Data
enable
Address 005316
Address 004016
Address 004116
display circuit divider division ratio selection bits Bias control divider
Duty ratio selection bits LCDCK count source selection f(XIN)/ 1/32 f(XCIN)
Fig. Block diagram controller/driver
Selector Selector
Selector
Selector
Selector
Selector
3820 GROUP USER'S MANUAL
Timing controller Segment Segment driver driver Bias control P30/SEG16 P16/SEG38 P17/SEG39
LCDCK
Segment Segment Segment Segment driver driver driver driver
Common Common Common Common driver driver driver driver
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SEG0
SEG1
SEG2
SEG3
COM0 COM1 COM2 COM3
1-33
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Bias Control Applied Voltage Power Input Pins
power input pins (VL1-VL3), apply voltage shown Table according bias value. Select bias value bias control (bit mode register).
Table Bias control applied voltage VL1-VL3 Bias value bias Voltage value VL3=VLCD VL2=2/3 VLCD VL1=1/3 VLCD VL3=VLCD VL2=VL1=1/2 VLCD
bias
Common Duty Ratio Control
common pins (COM 0-COM3) used determined duty ratio. Select duty ratio duty ratio selection bits (bits mode register).
Note VLCD maximum value supplied voltage panel. Table Duty ratio control common pins used Duty ratio Duty ratio selection Common pins used COM0, COM1 (Note COM0-COM2 (Note COM0-COM3
Notes COM2 COM3 open COM3 open
Contrast control
Contrast control
bias
bias
Fig. Example circuit each bias
1-34
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Display
Address 004016 005316 designated display. When written these addresses, corresponding segments display panel turned
Drive Timing
LCDCK timing frequency (LCD drive timing) generated internally frame frequency determined with following equation; f(LCDCK)= (frequency count source LCDCK) (divider division ratio LCD) f(LCDCK) duty ratio
Frame frequency=
Address
004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316
SEG1 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13 SEG15 SEG17 SEG19 SEG21 SEG23 SEG25 SEG27 SEG29 SEG31 SEG33 SEG35 SEG37 SEG39
SEG0 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12 SEG14 SEG16 SEG18 SEG20 SEG22 SEG24 SEG26 SEG28 SEG30 SEG32 SEG34 SEG36 SEG38
Fig. display
3820 GROUP USER'S MANUAL
1-35
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal logic LCDCK timing
duty
Voltage level VL2=VL1
COM0 COM1 COM2 COM3 SEG0
COM3 COM2 COM1
COM0 COM3
COM2 COM1
COM0
duty COM0 COM1 COM2 VL2=VL1
SEG0
COM0 duty COM0 COM1 SEG0
COM2 COM1
COM0
COM2 COM1
COM0
COM2
VL2=VL1
COM1 COM0 COM1 COM0 COM1 COM0 COM1 COM0
Fig. drive waveform (1/2 bias)
1-36
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal logic LCDCK timing
duty
Voltage level
COM0
COM1 COM2 COM3 SEG0
COM3 COM2 COM1
COM0 COM3
COM2 COM1
COM0
duty COM0 COM1 COM2
SEG0
COM0 duty COM0 COM1 SEG0
COM2 COM1
COM0
COM2 COM1
COM0
COM2
COM1 COM0 COM1 COM0 COM1 COM0 COM1 COM0
Fig. drive waveform (1/3 bias)
3820 GROUP USER'S MANUAL
1-37
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
watchdog timer gives mean returning reset status when program cannot normal loop (for example, because software run-away). watchdog timer consists 8-bit watchdog timer 6bit watchdog timer
Initial Value Watchdog Timer
reset when writing data into watchdog timer control register, watchdog timer "3F16" watchdog timer "FF16". write instruction, possible instruction that cause write signal such STA, CLB. Write data except significance above value independently.
Watchdog Timer Operation
watchdog timer stops reset starts countdown writing watchdog timer control register. When watchdog timer underflows, internal reset occurs, reset status released after waiting reset release time.
Then program executes from reset vector address. Usually, program designed that data written into watchdog timer control register before watchdog timer underflows. data written once into watchdog timer control register, watchdog timer does function. execution instruction, both clock watchdog timer stops. same time that stop mode released, watchdog timer restarts count (Note). other hand, execution instruction, watchdog timer does stop. time from execution writing watchdog timer control register until underflow watchdog timer register follows: (When watchdog timer control register "0") Middle High-speed mode (f(XIN)=8 MHz) 32.768 Low-speed mode (f(XCIN)=32 kHz) 8.19 Note: During stop release wait time [XIN XCIN) about 8200 clock cycles], watchdog timer counts. Accordingly, does underflow watchdog timer
XCIN
Internal system clock selection (Note)
When writing watchdog timer control register "FF16" Watchdog timer
Data
When writing watchdog timer control register "3F16" Watchdog timer
1/16
Watchdog timer count source selection
Undefined instruction Reset RESET Reset circuit Internal reset
Reset release wait time (about 8200 clock cycles) Note: This mode register. selects mode (middle/high-speed low-speed)
Fig. Watchdog timer block diagram
Watchdog timer control register (WDTCON address 0037 Watchdog timer bits (read only) used (returns when read) Watchdog timer count source selection Underflow from watchdog timer f(XIN)/16 CIN)/16
Fig. Structure watchdog timer control register
1-38
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK OUTPUT FUNCTION
internal system clock output from port setting output control register. port direction register when outputting clock.
output control register (CKOUT address 002A output control Port function clock output used (return when read)
Fig. Structure output control register
3820 GROUP USER'S MANUAL
1-39
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
reset microcomputer, RESET should held level more. Then RESET returned level (the power source voltage should between oscillation should stable), reset released. order give clock time stabilize, internal operation does begin until after 8200 clock cycles (timer timer connected together cycles f(XIN)/16) complete. After reset completed, program starts from address contained address FFFD (high-order byte) address FFFC16 (low-order byte). Make sure that reset input voltage less than (Extended operating temperature version: reset input voltage less than 0.6V 3.0V).
Address Port direction register Port direction register Port direction register Port direction register Port direction register Port direction register Port direction register PULL register PULL register (10) Serial I/O1 status register (11) Serial I/O1 control register (12) UART control register (13) Serial I/O2 control register (14) Timer (low-order)
Power Power source voltage Reset input voltage (Note)
Register contents 0016 0016 0016 0016 0016 0016 0016
(000116) (000316) (000516) (000916) (000B16) (000D16) (000F16)
(001616) (001716) 0016
(001916) (001A16) 0016
(001B16) (001D16) (002016) (002116) (002216) (002316) (002416) (002516) (002616) (002716) (002816) (002916) (002A16) 0016 FF16 FF16 FF16 FF16 FF16 0116 FF16 0016 0016 0016 0016
(15) Timer (high-order) (16) Timer (low-order) (17) Timer (high-order)
RESET
0.2VCC
(18) Timer (19) Timer
Note. Reset release voltage 2.5V (Extended operating temperature version 3.0V)
(20) Timer (21) Timer mode register
RESET
Power source voltage detection circuit
(22) Timer mode register (23) Timer mode register (24) output control register (25) Watchdog timer control register (26) Segment output enable register (27) mode register (28) Interrupt edge selection register (29) mode register (30) Interrupt request register
(003716) (003816) (003916) (003A16) 0016 0016 0016
(003B16) (003C16) (003D16) (003E16) (003F16) 0016 0016 0016 0016
Fig. Example reset circuit
(31) Interrupt request register (32) Interrupt control register (33) Interrupt control register (34) Processor status register (35) Program counter
(PS) (PCH) Contents address FFFD (PCL) Contents address FFFC
Note. Undefined contents other registers undefined poweron reset, they must initialized software.
Fig. Internal state microcomputer immediately after reset
1-40
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET
Internal reset
Reset address from vector table
Address Data
FFFC
FFFD
ADH,
SYNC about 8200 clock cycles Notes relation f(XIN) Notes question mark indicates undefined status that depens previous status.
Fig. Reset sequence
3820 GROUP USER'S MANUAL
1-41
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
3820 group built-in oscillation circuits. oscillation circuit formed connecting resonator between XOUT (XCIN XCOUT). circuit constants accordance with resonator manufacturer's recommended values. external resistor needed between XOUT since feed-back resistor exists on-chip. However, external feed-back resistor needed between XCIN XCOUT. supply clock signal externally, input make open. sub-clock XCIN-XCOUT oscillation circuit cannot directly input clocks that externally generated. Accordingly, sure cause external resonator oscillate. Immediately after poweron, only oscillation circuit starts oscillating, COUT pins function ports. pull-up resistor XCOUT pins must made invalid sub-clock.
Oscillation Control
Stop mode instruction executed, internal clock stops level, XCIN oscillators stop. Timer "FF16" timer "0116". Either divided input timer count source, output timer connected timer bits timer mode register except cleared "0". timer timer interrupt enable bits disabled ("0") before executing instruction. Oscillator restarts reset when external interrupt received, internal clock supplied until timer underflows. This allows time clock circuit oscillation stabilize. Wait mode instruction executed, internal clock stops level. states XCIN same state before executing instruction. internal clock restarts reset when interrupt received. Since oscillator does stop, normal operation started immediately after clock restarted.
Frequency Control
Middle-speed mode internal clock frequency divided After reset, this mode selected. High-speed mode internal clock half frequency XIN. Low-speed mode
internal clock half frequency XCIN. low-power consumption operation realized stopping
main clock this mode. stop main clock, mode register "1". When main clock restarted, enough time oscillation stabilize programming. Note: switch mode between middle/high-speed lowspeed, stabilize both XCIN oscillations. sufficient time required sub-clock stabilize, especially immediately after poweron returning from stop mode. When switching mode between middle/highspeed low-speed, frequency condition that f(XIN)>3f(XCIN).
XCIN CCIN
XCOUT CCOUT
XOUT
COUT
Fig. Ceramic resonator circuit
XCIN CCIN
XCOUT CCOUT
XOUT Open
External oscillation circuit
Fig. External clock input circuit
1-42
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCIN
XCOUT
Port switch
XOUT
Internal system clock selection (Note Low-speed mode
Timer count source selection
Timer count source selection
Middle/High-speed mode
Timer
Timer
Main clock division ratio selection Middle-speed mode
High-speed mode Low-speed mode Main clock stop
Timing (Internal system clock)
instruction instruction
instruction
Reset Interrupt disable flag Interrupt request
Note When using low-speed mode, port switch
Fig. Clock generating circuit block diagram
3820 GROUP USER'S MANUAL
1-43
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
Middle-speed mode (f() MHz) CM7=0(8MHz selected) CM6=1(Middle-speed) CM5=0(8MHz oscillating) CM4=0(32kHz stopped)
High-speed mode (f() =4MHz) CM7=0(8MHz selected) CM6=0(High-speed) CM5=0(8MHz oscillating) CM4=0(32kHz stopped)
Middle-speed mode (f() MHz) CM7=0(8MHz selected) CM6=1(Middle-speed) CM5=0(8MHz oscillating) CM4=1(32kHz oscillating)
High-speed mode (f() =4MHz) CM7=0(8MHz selected) CM6=0(High-speed) CM5=0(8MHz oscillating) CM4=1(32kHz oscillating)
Low-speed mode kHz) CM7=1(32kHz selected) CM6=1(Middle-speed) CM5=0(8MHz oscillating) CM4=1(32kHz oscillating)
Low-speed mode (f() kHz)
CM7=1(32kHz selected) CM6=0(High-speed) CM5=0(8MHz oscillating) CM4=1(32kHz oscillating)
Low-speed mode kHz) CM7=1(32kHz selected) CM6=1(Middle-speed) CM5=1(8MHz stopped) CM4=1(32kHz oscillating)
Low-speed mode (f() kHz)
CM7=1(32kHz selected) CM6=0(High-speed) CM5=1(8MHz stopped) CM4=1(32kHz oscillating)
Note 1:Switch mode allows shown between mode blocks. switch between mode directly without allow.) 2:The modes switched stop mode wait mode returned source mode when stop mode wait mode released. 3:Timer operate wait mode. 4:In middle-/high-speed mode, when stop mode released, delay approximately occurs automatically timer timer 5:In low-speed mode, when stop mode released, delay approximately 0.25 occurs automatically timer timer 6:Wait until oscillation stabilizes after oscillating main clock before switching from low-speed mode middle-/highspeed mode. 7:The example assumes that being applied XCIN pin. indicates internal clock.
Fig. State transitions internal clock
1-44
3820 GROUP USER'S MANUAL
mode register (CPUM address 003B
Port switch port CIN, XCOUT Main clock IN-XOUT) stop Oscillating Stopped CM6: Main clock division ratio selection IN)/2 (high-speed mode) IN)/8 (middle-speed mode) CM7: Internal system clock selection IN-XOUT selected (middle-/high-speed mode) CIN-XCOUT selected (low-speed mode)
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES PROGRAMMING Processor Status Register
contents processor status register (PS) after reset undefined, except interrupt disable flag which "1". After reset, initialize flags which affect program execution. particular, essential initialize index mode decimal mode flags because their effect calculations.
Serial
clock synchronous serial I/O, receive side using external clock output SRDY signal, transmit enable bit, receive enable bit, SRDY output enable "1". Serial I/O1 continues output final from after transmission completed. SOUT2 from serial I/O2 goes high impedance after transmission completed.
Interrupt
contents interrupt request bits change immediately after they have been written. After writing interrupt request register, execute least instruction before performing instruction.
Instruction Execution Time
instruction execution time obtained multiplying frequency internal clock number cycles needed execute instruction. number cycles required execute instruction shown list machine instructions. frequency internal clock half frequency.
Decimal Calculations
calculate decimal notation, decimal mode flag "1", then execute instruction. Only instructions yield proper decimal results. After executing instruction, execute least instruction before executing SEC, CLC, instruction. decimal mode, values negative (N), overflow (V), zero flags invalid. carry flag used indicate whether carry borrow occurred. Initialize carry flag before each calculation. Clear carry flag before flag before SBC.
Timers
value (between 255) written timer latch, frequency division ratio 1/(n
Multiplication Division Instructions
index mode decimal mode flags affect instruction. execution these instructions does change contents processor status register.
Ports
contents port direction registers cannot read. following cannot used: data transfer instruction (LDA, etc.) operation instruction when index mode flag addressing mode which uses value direction register index bit-test instruction (BBC BBS, etc.) direction register read-modify-write instruction (ROR, CLB, SEB, etc.) direction register instructions such STA, etc., port direction registers.
3820 GROUP USER'S MANUAL
1-45
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED MASK ORDERS
following necessary when ordering mask production: Mask Order Confirmation Form Mark Specification Form Data written ROM, EPROM form (three identical copies)
PROGRAMMING METHOD
built-in PROM blank Time PROM version builtin EPROM version read programmed with generalpurpose PROM programmer using special programming adapter. address PROM programmer user area. Table Programming adapter Package 80P6N-A 80P6S-A 80P6D-A 80D0 Name Programming Adapter PCA4738F-80A PCA4738G-80 PCA4738H-80 PCA4738L-80A
PROM blank Time PROM version tested screened assembly process following processes. ensure proper operation after programming, procedure shown Figure recommended verify programming.
Programming with PROM programmer
Screening (Caution) (150°C hours)
Verification with PROM programmer
Functional check target device Caution screening temperature higher than storage temperature. Never expose exceeding hours.
Fig. Programming testing Time PROM version
1-46
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Absolute maximum ratings
Table Absolute maximum ratings Symbol Topr Tstg Parameter Power source voltage Input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60, P61, P70, Input voltage Input voltage Input voltage Input voltage RESET, Output voltage P00-P07, P10-P17 Output voltage P30-P37 Output voltage P20-P27, P41-P47, P50-P57, P60, P61, P70, Output voltage SEG0-SEG15 Output voltage XOUT Power dissipation Operating temperature Storage temperature Conditions Ratings -0.3 -0.3 +0.3 voltages based VSS. Output transistors off. -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 Unit
output port segment output segment output
Recommended operating conditions
Table Recommended operating conditions (VCC unless otherwise noted) Symbol Parameter High-speed mode f(XIN)=8 Middle-speed mode f(XIN)=8 Low-speed mode P00-P07, P53, P56, P20-P27, RESET P00-P07, P51, P53, P20-P27, RESET P10-P17, P30-P37, P41, P45, P47, P51, P61, P70, (CM4=0) P42-P44, P46, P50, P52, P54, P55, P57, Min. Limits Typ. Max. Unit
Power source voltage Power source voltage input voltage input voltage input voltage input voltage input voltage input voltage input voltage input voltage
P10-P17, P30-P37, P40, P41, P45, P47, P56, P61, P70, (CM4=0) P42-P44, P46, P50, P52, P54, P55, P57,
3820GROUP USER'S MANUAL
1-47
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table Recommended operating conditions (VCC unless otherwise noted) Symbol IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) total peak output current total peak output current total peak output current total peak output current total average output current total average output current total average output current total average output current peak output current peak output current peak output current average output current average output current average output current average output current Clock input frequency timers (duty cycle Main clock input oscillation frequency (Note Parameter P00-P07, P10-P17, P20-P27 (Note P41-P47,P50-P57, P60, P61, P70, (Note P00-P07, P10-P17, P20-P27 (Note P41-P47,P50-P57, P60, P61, P70, (Note P00-P07, P10-P17, P20-P27 (Note P41-P47,P50-P57, P60, P61, P70, (Note P00-P07, P10-P17, P20-P27 (Note P41-P47,P50-P57, P60, P61, P70, (Note P00-P07, P10-P17, P20-P27, P41-P47, P50-P57, P60, P61, P70, (Note P00-P07, P10-P17 (Note P20-P27, P41-P47, P50-P57, P60, P61, P70, (Note P00-P07, P10-P17 (Note P20-P27, P41-P47, P50-P57, P60, P61, P70, (Note P00-P07, P10-P17 (Note P20-P27, P41-P47, P50-P57, P60, P61, P70, (Note High-speed mode (4.0 High-speed mode (VCC Middle-speed mode Min. Limits Typ. Max. -1.0 -2.5 Unit
f(CNTR0) f(CNTR1)
(2XVCC)-4 (4XVCC)-8 32.768
f(XIN) f(XCIN)
Sub-clock input oscillation frequency (Note
Note total output current currents flowing through applicable ports. total average current average value measured over total peak current peak value currents. peak output current peak current flowing each port. average output current average value measured over When oscillation frequency duty cycle When using microcomputer low-speed mode, make sure that sub-clock input oscillation frequency f(XCIN) less than f(XIN)/3.
1-48
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Electrical characteristics
Table Electrical characteristics (VCC =4.0 unless otherwise noted) Symbol Parameter Test conditions -0.1 -1.25 -1.25 1.25 1.25 Min. VCC-2.0 VCC-1.0 VCC-2.0 VCC-0.5 VCC-1.0 -5.0 Pull-ups "off" VCC= Pull-ups "on" VCC= Pull-ups "on" When clock stopped -5.0 -140 -5.0 -4.0 Limits Typ. Max. Unit
output voltage P00-P07, P10-P17, P30-P37
output voltage P20-P27, P41-P47,P50-P57, P60, P61, P70, (Note
output voltage P00-P07, P10-P17, P30-P37
output voltage P20-P27, P41-P47, P50-P57, P60, P61, P70, (Note Hysteresis Hysteresis Hysteresis CNTR0, CNTR1, INT0-INT3, P20-P27 RXD, SCLK1, SIN2, SCLK2 RESET
input current
P00-P07, P10-P17, P30-P37
RESET: VCC=2.5 Pull-downs "off" VCC= Pull-downs "on" VCC= Pull-downs "on"
input current input current input current input current
P20-P27, P40-P47, P50-P57, P60, P61, P70, RESET P00-P07, P10-P17, P30-P37, P40,
input current
P20-P27, P41-P47, P50-P57, P60, P61,
VRAM
input current RESET input current hold voltage
Note When port switch (bit address 003B16) mode register, drive ability port different from value above mentioned.
3820GROUP USER'S MANUAL
1-49
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table Electrical characteristics (VCC =2.5 unless otherwise noted) Symbol Parameter Test conditions High-speed mode, f(XIN) f(XCIN) 32.768 Output transistors "off" High-speed mode, f(XIN) state) f(XCIN) 32.768 Output transistors "off" Low-speed mode, 55°C f(XIN) stopped f(XCIN) 32.768 Output transistors "off" Low-speed mode, 25°C f(XIN) stopped f(XCIN) 32.768 state) Output transistors "off" Low-speed mode, 55°C f(XIN) stopped f(XCIN) 32.768 Output transistors "off" Low-speed mode, 25°C f(XIN) stopped f(XCIN) 32.768 state) Output transistors "off" oscillation stopped state) Output transistors "off" Min. Limits Typ. Max. Unit
Power source current
14.0
1-50
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing requirements
Table Timing requirements (VCC unless otherwise noted) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1) twH(SCLK1) twL(SCLK1) tsu(RXD-SCLK1) th(SCLK1-RXD) tc(SCLK2) twH(SCLK2) twL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Parameter Reset input pulse width Main clock input cycle time (XIN input) Main clock input pulse width Main clock input pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input pulse width CNTR0, CNTR1 input pulse width INT0 INT3 input pulse width INT0 INT3 input pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input pulse width (Note) Serial I/O1 clock input pulse width (Note) Serial I/O1 input time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input pulse width Serial I/O2 clock input pulse width Serial I/O2 input time Serial I/O2 input hold time Min. 1000 Limits Typ. Max. Unit
Note: When f(XIN) address 001A16 (clock synchronous). Divide this value four when f(XIN) address 001A16 (UART).
Timing requirements
Table Timing requirements (VCC unless otherwise noted) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1) twH(SCLK1) twL(SCLK1) tsu(RXD-SCLK1) th(SCLK1-RXD) tc(SCLK2) twH(SCLK2) twL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Parameter Reset input pulse width Main clock input cycle time (XIN input) Main clock input pulse width Main clock input pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input pulse width CNTR0, CNTR1 input pulse width INT0 INT3 input pulse width INT0 INT3 input pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input pulse width (Note) Serial I/O1 clock input pulse width (Note) Serial I/O1 input time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input pulse width Serial I/O2 clock input pulse width Serial I/O2 input time Serial I/O2 input hold time Min. 500/ (VCC-2) 250/ (VCC-2)-20 250/ (VCC-2)-20 2000 2000 Limits Typ. Max. Unit
Note: When f(XIN) address 001A16 (clock synchronous). Divide this value four when f(XIN) address 001A16 (UART).
3820GROUP USER'S MANUAL
1-51
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Switching characteristics
Table Switching characteristics (VCC unless otherwise noted) Symbol twH(SCLK1) twL(SCLK1) td(SCLK1-TXD) tv(SCLK1-TXD) tr(SCLK1) tf(SCLK1) twH(SCLK2) twL(SCLK2) td(SCLK2-SOUT2) tv(SCLK2-SOUT2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output pulse width Serial I/O1 clock output pulse width Serial I/O1 output delay time (Note Serial I/O1 output valid time (Note Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output pulse width Serial I/O2 clock output pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note CMOS output falling time (Note Limits Min. tc(SCLK1)/2-30 tc(SCLK1)/2-30 tc(SCLK2)/2-160 tc(SCLK2)/2-160 0.2!tC(SCLK2) Typ. Max. Unit
Note1: When P45/TXD P-channel output disable UART control register (bit address 001B16) "0". XOUT XCOUT pins excluded.
Switching characteristics
Table Switching characteristics (VCC unless otherwise noted) Symbol twH(SCLK1) twL(SCLK1) td(SCLK1-TXD) tv(SCLK1-TXD) tr(SCLK1) tf(SCLK1) twH(SCLK2) twL(SCLK2) td(SCLK2-SOUT2) tv(SCLK2-SOUT2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output pulse width Serial I/O1 clock output pulse width Serial I/O1 output delay time (Note Serial I/O1 output valid time (Note Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output pulse width Serial I/O2 clock output pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note CMOS output falling time (Note Min. tc(SCLK1)/2-50 tc(SCLK1)/2-50 tc(SCLK2)/2-240 tc(SCLK2)/2-240 0.2!tC(SCLK2) Limits Typ. Max. Unit
Note1: When P45/TXD P-channel output disable UART control register (bit address 001B16) "0". XOUT XCOUT pins excluded.
1-52
3820 GROUP USER'S MANUAL
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Absolute maximum ratings (Extended operating temperature version)
Table Absolute maximum ratings (Extended operating temperature version) Symbol Topr Tstg Parameter Power source voltage Input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60, P61, P70, Input voltage Input voltage Input voltage Input voltage RESET, Output voltage P00-P07, P10-P17 Output voltage P30-P37 Output voltage P20-P27, P41-P47, P50-P57, P60, P61, P70, Output voltage SEG0-SEG15 Output voltage XOUT Power dissipation Operating temperature Storage temperature Conditions Ratings -0.3 -0.3 +0.3 voltages based VSS. Output transistors off. -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 Unit
output port segment output segment output
Recommended operating conditions (Extended operating temperature version)
Table Recommended operating conditions (Extended operating temperature version) (VCC unless otherwise noted) Symbol Parameter High-speed mode f(XIN)=8 Power source voltage Middle-speed mode f(XIN)=8 Low-speed mode Power source voltage input voltage input voltage input voltage input voltage input voltage input voltage input voltage input voltage Min. Limits Typ. Max. Unit
P00-P07, P10-P17, P30-P37, P41, P45, P47, P51, P53, P56, P61, P70, (CM4=0) P20-P27, P42-P44, P46, P50, P52, P54, P55, P57, RESET P00-P07, P10-P17, P30-P37, P40, P41, P45, P47, P51, P53, P56, P61, P70, (CM4=0) P20-P27, P42-P44, P46, P50, P52, P54, P55, P57, RESET
3820GROUP USER'S MANUAL
1-53
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table Recommended operating conditions (Extended operating temperature version) (VCC unless otherwise noted) Symbol IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) total peak output current total peak output current total peak output current total peak output current total average output current total average output current total average output current total average output current peak output current peak output current peak output current average output current average output current average output current average output current Clock input frequency timers (duty cycle Main clock input oscillation frequency (Note Para
Other recent searches
Si7892BDP - Si7892BDP Si7892BDP Datasheet
SDR953 - SDR953 SDR953 Datasheet
SDR955 - SDR955 SDR955 Datasheet
MMSZ5238B - MMSZ5238B MMSZ5238B Datasheet
MC-108 - MC-108 MC-108 Datasheet
INA116 - INA116 INA116 Datasheet
GQ2153 - GQ2153 GQ2153 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
