SN54 74LS109A consists high speed completely independent transition cl
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SN54/74LS109A DUAL POSITIVE EDGE-TRIGGERED FLIP-FLOP
SN54 74LS109A consists high speed completely independent transition clocked flip-flops. clocking operation independent rise fall times clock waveform. design allows operation flip-flop simply connecting pins together. LOGIC DIAGRAM
DUAL POSITIVE EDGE-TRIGGERED FLIP-FLOP
POWER SCHOTTKY
(SD) 5(11) CLEAR (CD) 1(15) CLOCK 4(12)
6(10)
SUFFIX CERAMIC CASE 620-09
2(14) 3(13)
7(9)
SUFFIX PLASTIC CASE 648-08
MODE SELECT TRUTH TABLE
INPUTS OPERATING MODE Reset (Clear) *Undetermined Load (Set) Hold Toggle Load (Reset) OUTPUTS
SUFFIX SOIC CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC
LOGIC SYMBOL
Both outputs will HIGH while both LOW, output states unpredictable HIGH simultaneously. HIGH Voltage Level Voltage Level Don't Care Lower case letters indicate state referenced input output) set-up time prior HIGH clock transition.
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SN54/74LS109A
GUARANTEED OPERATING RANGES
Symbol Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Parameter 4.75 5.25 Unit
CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol Parameter Input HIGH Voltage Input Voltage Input Clamp Diode Voltage Output HIGH Voltage Output Voltage Input HIGH Current Clock Set, Clear Clock Set, Clear Input Current Clock Set, Clear Output Short Circuit Current (Note Power Supply Current 0.35 0.65 0.25 Unit Test Conditions Guaranteed Input HIGH Voltage Inputs Guaranteed Input Voltage Inputs MIN, MIN, MAX, MAX, MIN, Truth Table MIN, Truth Table
MAX,
MAX,
MAX,
Note more than output should shorted time, more than second.
CHARACTERISTICS 25°C,
Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Clock Clear Output Clock, Clear, Unit Test Conditions
SETUP REQUIREMENTS 25°C,
Limits Symbol Parameter Clock High Clear, Pulse Width Data Setup Time HIGH Data Setup Time Hold time Unit Test Conditions
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