Overview 2-104 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Ar
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XC3000 Logic Cell Array Families
Overview 2-104 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families 2-105 Architecture 2-106 Programmable Interconnect 2-111 Crystal Oscillator 2-117 Programming 2-118 Special Configuration Functions 2-122 Master Serial Mode 2-124 Master Serial Mode Programming Switching Characteristics 2-125 Master Parallel Mode 2-126 Master Parallel Mode Programming Switching Characteristics 2-127 Peripheral Mode 2-128 Peripheral Mode Programming Switching Characteristics 2-129 Slave Serial Mode 2-130 Slave Serial Mode Programming Switching Characteristics 2-131 Program Readback Switching Characteristics 2-131 General Switching Characteristics 2-132 Performance 2-133 Power 2-134 Descriptions 2-136 Functions During Configuration. 2-138 XC3000 Families Assignments 2-139 XC3000 Families Pinouts 2-140 Component Availability 2-151 Ordering Information 2-152 XC3000 Logic Cell Array Family 2-153 Absolute Maximum Ratings 2-154 Operating Conditions 2-154 Characteristics 2-155 Switching Characteristic Guidelines 2-156 Buffer 2-156 2-158 Ordering Information 2-160 Component Availability 2-160 XC3000A Logic Cell Array Familiy 2-161 Absolute Maximum Ratings 2-162 Operating Conditions 2-162 Characteristics 2-163 Switching Characteristic Guidelines 2-164 Buffer 2-164 2-166 Ordering Information 2-168 Component Availability 2-168 XC3000L Voltage Logic Cell Array Family 2-169 Absolute Maximum Ratings 2-170 Operating Conditions 2-170 Characteristics 2-171 Switching Characteristic Guidelines 2-172 Buffer 2-172 2-174 Ordering Information 2-176 Component Availability 2-176 XC3100, XC3100A Logic Cell Array Families 2-177 Absolute Maximum Ratings 2-178 Operating Conditions 2-178 Characteristics 2-179 Switching Characteristic Guidelines 2-180 Buffer 2-180 2-182 Ordering Information 2-184 Component Availability 2-184
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Overview
Introduced 1987/88, XC3000 industry's most successful family FPGAs, with over million devices shipped. 1992/93, Xilinx introduced three additional families, offering more speed, functionality, supply-voltage option. There five distinct family groupings within XC3000 class devices. XC3000 Family XC3000A Family (use designs) XC3000L Family (use designs) XC3100 Family XC3100A Family (use designs) other user-friendly enhancements. ease-of-use XC3000A family makes obvious choice designs that require speed XC3100 operation XC3000L. XC3000L Family XC3000L identical architecture features XC3000A family, operates nominal supply voltage XC3000L right solution battery-operated low-power applications. XC3100 Family XC3100 performance-optimized relative basic XC3000 family. While both families bitstream footprint compatible, XC3100 family extends toggle rates in-system performance MHz. XC3100 family also offers additional array size, XC3195. XC3100 best suited designs that require highest clock speed shortest delays. XC3100A Family XC3100A combines enhanced feature XC3000A with performance XC3100. offers highest functionality, speed capacity XC3000 families. figure below illustrates relationships between families. Compared original XC3000 family, XC3000A offers additional functionality coming soon, increased speed. XC3000L family offers same additional functionality, reduced speed lower supply voltage XC3100 family offers additional functionality, substantially higher speed, higher density with member, XC3195.
five families share common architecture, development software, design programming methodology, also common package pin-outs. extensive Product Description covers these common aspects. (Page 2-99). much shorter individual Product Specifications then provide detailed parametric information four individual product families. Here simple overview. XC3000 Family basic XC3000 family forms cornerstone rest XC3000 class devices. basic XC3000 family offers five different device densities with guaranteed toggle rates from MHz. XC3000A Family XC3000A enhanced version basic XC3000 family, featuring additional interconnect resources
Functio
nality
XC310
XC300 XC300
XC310 C3000
Speed
XC31
Capa city
Gate
X3447
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IMPORTANT NOTICE
designs should XC3000A XC3100A. Information XC3000 XC3100 presented here reference existing designs.
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Product Description
Features
Complete XACT Development System
Schematic capture, automatic place route Logic timing simulation Interactive design editor design optimization Timing calculator Interfaces popular design environments like Viewlogic, Cadence, Mentor Graphics, others
Complete line five related Field Programmable
Gate Array product families XC3000, XC3000A, XC3000L, XC3100, XC3100A
Ideal wide range custom VLSI design tasks
Replaces TTL, MSI, other logic Integrates complete sub-systems into single package Avoids NRE, time delay, risk conventional masked gate arrays High-performance CMOS static memory technology Guaranteed toggle rates MHz, logic delays from System clock speeds over quiescent active power consumption Flexible FPGA architecture Compatible arrays ranging from 1,000 7,500 gate complexity Extensive register, combinatorial, capabilities High fan-out signal distribution, low-skew clock nets Internal 3-state capabilities CMOS input thresholds On-chip crystal oscillator amplifier Easy design iteration In-system logic changes Extensive Packaging Options Over different packages Plastic ceramic surface-mount pin-gridarray packages Thin Very Thin Quad Flat Pack (TQFP VQFP) options Standard, off-the-shelf product availability 100% factory pre-tested devices Excellent reliability record
Device XC3020, 3020A, 3020L, 3120, 3120A XC3030, 3030A, 3030L, 3130, 3130A XC3042, 3042A, 3042L, 3142, 3142A XC3064, 3064A, 3064L, 3164, 3164A XC3090, 3090A, 3090L, 3190, 3190A XC3195, 3195A CLBs Array
Description
CMOS XC3000 Class Logic Cell Array (LCA) families provide group high-performance, high-density, digital integrated circuits. Their regular, extendable, flexible, user-programmable array architecture composed configuration program store plus three types configurable elements: perimeter Blocks (IOBs), core array Configurable Logic Bocks (CLBs) resources interconnection. general structure device shown Figure next page. XACT development system provides schematic capture auto place-and-route design entry. Logic timing simulation, in-circuit emulation available design verification alternatives. design editor used interactive design optimization, compile data pattern that represents configuration program. user logic functions interconnections determined configuration program data stored internal static memory cells. program loaded several modes accommodate various system requirements. program data resides externally EEPROM, EPROM application circuit board, floppy disk hard disk. On-chip initialization logic provides optional automatic loading program data power-up. companion XC17XX Serial Configuration PROMs provide very simple serial configuration program storage one-time programmable package.
Unlimited reprogrammability
Ready volume production
User I/Os
Flip-Flops 1,320
Horizontal Longlines
Configuration Data Bits 14,779 22,176 30,784 46,064 64,160 94,984
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
XC3000 Logic Cell Array families provide variety logic capacities, package styles, temperature ranges speed grades.
Architecture
perimeter configurable IOBs provides programmable interface between internal logic array device package pins. array CLBs performs user-specified logic functions. interconnect resources programmed form networks, carrying logic signals among blocks, analogous printed circuit board traces connecting MSI/SSI packages. block logic functions implemented programmed look-up tables. Functional options implemented program-controlled multiplexers. Interconnecting networks between blocks implemented with metal segments joined program-controlled pass transistors. These functions established configuration program which loaded into internal, distributed array configuration memory cells. configuration program loaded into device power-up reloaded command. Logic Cell Array includes logic control signals implement automatic passive
configuration. Program data either serial byte parallel. XACT development system generates configuration program bitstream used configure device. memory loading process independent user logic functions. Configuration Memory static memory cell used configuration memory Logic Cell Array been designed specifically high reliability noise immunity. Integrity device configuration memory based this design assured even under adverse conditions. Compared with other programming alternatives, static memory provides best combination high density, high performance, high reliability comprehensive testability. shown Figure basic memory cell consists CMOS inverters plus pass transistor used writing reading cell data. cell only written during configuration only read during readback. During normal operation, cell provides continuous control pass transistor does affect cell stability. This quite different from operation conventional memory devices, which cells frequently read rewritten.
Blocks
3-State Buffers With Access Horizontal Long Lines
Configurable Logic Blocks
Interconnect Area
Configuration Memory
X3241 Figure Logic Cell Array Structure. consists perimeter programmable blocks, core configurable logic blocks their interconnect resources. These controlled distributed array configuration program memory cells.
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Frame Pointer
Read Write Data
Configuration Control
X5382
method loading configuration data selectable. methods serial data, while three byte-wide data. internal configuration logic utilizes framing information, embedded program data XACT development system, direct memory-cell loading. serial-data framing length-count preamble provide programming compatibility mixes various device devices synchronous, serial, daisy-chain fashion. Block Each user-configurable shown Figure provides interface between external package device internal user logic. Each includes both registered direct input paths. Each provides programmable 3-state output buffer, which driven registered direct output signal. Configuration options allow each inversion, controlled slew rate high impedance pull-up. Each input circuit also provides input clamping diodes provide electrostatic protection, circuits inhibit latch-up produced input currents.
Figure Static Configuration Memory Cell. loaded with configuration program controls program selection Logic Cell Array.
memory cell outputs ground levels provide continuous, direct control. additional capacitive load together with absence address decoding sense amplifiers provide high stability cell. structure configuration memory cells, they affected extreme power-supply excursions very high levels alpha particle radiation. reliability testing, soft errors have been observed even presence very high doses alpha radiation.
PROGRAM-CONTROLLED MEMORY CELLS
INVERT
3-STATE INVERT
OUTPUT SELECT
SLEW RATE
PASSIVE PULL
STATE (OUTPUT ENABLE)
FLIP FLOP
OUTPUT BUFFER
DIRECT REGISTERED FLIP FLOP LATCH (GLOBAL RESET) CMOS INPUT THRESHOLD
PROGRAM CONTROLLED MULTIPLEXER PROGRAMMABLE INTERCONNECTION POINT
X3029
Figure Input/Output Block. Each includes input output storage elements options selected configuration memory cells. choice clocks available each edge. polarity each clock line (not each flip-flop latch) programmable. clock line that triggers flip-flop rising edge active Latch Enable (Latch transparent) signal vice versa. Passive pull-up only enabled inputs, outputs. user inputs programmed CMOS thresholds.
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
input-buffer portion each provides threshold detection translate external signals applied package internal logic levels. global input-buffer threshold IOBs programmed compatible with either CMOS levels. buffered input signal drives data input storage element, which configured either flip-flop latch. clocking polarity (rising/falling edge-triggered flip-flop, High/Low transparent latch) programmable each clock lines each four edges. Note that clock line driving rising edge-triggered flip-flop makes latch driven same line same edge Lowlevel transparent vice versa (falling edge, High transparent). Xilinx primitives supported schematic-entry packages, however, positive edgetriggered flip-flops High transparent latches. When clock line must drive flip-flops well latches, necessary compensate difference clocking polarities with additional inverter either flip-flop clock input latch-enable input. storage elements reset during configuration active-Low chip RESET input. Both direct input (from registered input (from signals available interconnect. reliable operation, inputs should have transition times less than should left floating. Floating CMOS input-pin circuits might threshold produce oscillations. This produce additional power dissipation system noise. typical hysteresis about reduces sensitivity input noise. Each user includes programmable high-impedance pull-up resistor, which selected program provide constant High otherwise undriven package pins. Although Logic Cell Array provides circuitry provide input protection electrostatic discharge, normal CMOS handling precautions should observed. Flip-flop loop delays logic-block flip-flops about This short delay provides good performance under asynchronous clock data conditions. Short loop delays minimize probability metastable condition that result from assertion clock during data transitions. Because short-loop-delay characteristic Logic Cell Array, flip-flops used synchronize external signals applied device. Once synchronized IOB, signals used internally without further consideration their clock relative timing, except applies internal logic routing-path delays. output buffers provide CMOS-compatible 4-mA source-or-sink drive high fan-out CMOS TTL- compatible signal levels XC3100 family). network driving becomes registered direct data source output buffer. 3-state control signal
(IOB) control output activity. open-drain output obtained using same signal driving output 3-state signal nets that buffer output enabled only Low. Configuration program bits each control features such optional output register, logic signal inversion, 3-state slew-rate control output. program-controlled memory cells Figure control following options.
Logic inversion output controlled
configuration program IOB.
Logic 3-state control each output buffer
determined states configuration program bits which turn buffer off, select output buffer 3-state control interconnection (IOB When this output control signal High, logic one, buffer disabled package high impedance. When this output control signal Low, logic zero, buffer enabled package active. Inversion buffer 3-state control-logic sense (output enable) controlled additional configuration program bit.
Direct registered output selectable each IOB.
register uses positive-edge, clocked flip-flop. clock source supplied (IOB either metal lines available along each edge. Each these lines driven invertible buffer.
Increased output transition speed selected
improve critical timing. Slower transitions reduce capacitive-load peak currents non-critical outputs minimize system noise.
internal high-impedance pull-up resistor (active
default) prevents unconnected inputs from floating. Summary Options
Inputs
Direct Flip-flop/latch CMOS/TTL threshold (chip inputs) Pull-up resistor/open circuit Direct/registered Inverted/not 3-state/on/off Full speed/slew limited 3-state/output enable (inverse)
Outputs
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Configurable Logic Block array CLBs provides functional elements from which user's logic constructed. logic blocks arranged matrix within perimeter IOBs. XC3020 such blocks arranged rows columns. XACT development system used compile configuration data which loaded into internal configuration memory define operation interconnection each block. User definition CLBs their interconnecting networks done automatic translation from schematic-capture logic diagram optionally installing library user macros.
Each combinatorial logic section, flip-flops, internal control section. Figure There are: five logic inputs common clock input (K); asynchronous direct RESET input (RD); enable clock (EC). driven from interconnect resources adjacent blocks. Each also outputs which drive interconnect networks. Data input either flip-flop within supplied from function outputs combinatorial logic, block input, Both flip-flops each share
DATA LOGIC VARIABLES COMBINATORIAL FUNCTION OUTPUTS
ENABLE CLOCK (ENABLE)
CLOCK
DIRECT RESET
(INHIBIT) (GLOBAL RESET)
X3032
Figure Configurable Logic Block. Each includes combinatorial logic section, flip-flops program memory controlled multiplexer selection function. has. five logic variable inputs direct data enable clock clock (invertible) asynchronous direct RESET outputs
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Function Variables
Count Enable Parallel Enable Clock
Terminal Count
Dual Function Variables
Function Variables
Mode
Function Variables
Function Variables
Mode
Mode
X5442
Function Variables
Function Variables
Mode
X5383
Figure C8BCP Macro.
Function Variables
C8BCP macro (modulo-8 binary counter with parallel enable clock enable) uses combinatorial logic block each option.
Figure Combinatorial Logic Option generates functions four variables each. variable, must common both functions. second third variable choice fourth variable choice Combinatorial Logic Option generates function five variables: choices Combinatorial Logic Option allows variable select between functions four variables: Both have common inputs choice remaining variables. Option then implement some functions seven variables.
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asynchronous which, when enabled High, dominant over clocked inputs. flip-flops reset active-Low chip input, RESET, during configuration process. flip-flops share enable clock (EC) which, when Low, recirculates flip-flops' present states inhibits response data-in combinatorial function inputs CLB. user enable these control inputs select their sources. user also select clock input (K), well active sense within each CLB. This programmable inversion eliminates need route both phases clock signal throughout device. Flexible routing allows common individual clocking. combinatorial-logic portion uses look-up table implement Boolean functions. Variables selected from five logic inputs internal block flip-flops used table address inputs. combinatorial propagation delay through network independent logic function generated spike free single input variable changes. This technique generate independent logic functions four variables each shown Figure single function five variables shown Figure some functions seven variables shown Figure Figure shows modulo-8 binary counter with parallel enable. uses each type. partial functions seven variables implemented using input variable dynamically select between functions four different variables. functions four variables each, independent results used data inputs either flip-flop either logic block output. single function five variables merged functions seven variables, outputs identical. Symmetry functions flip-flops allows interchange outputs optimize routing efficiencies networks interconnecting CLBs IOBs.
switch connections block inputs unidirectional, block outputs, they usable only block input connection routing. Figure illustrates routing access logic block input variables, control inputs block outputs. Three types metal resources provided accommodate various network interconnect requirements.
General Purpose Interconnect Direct Connection Longlines (multiplexed busses wide gates) General Purpose Interconnect General purpose interconnect, shown Figure consists grid five horizontal five vertical metal segments located between rows columns logic IOBs. Each segment height width logic block. Switching matrices join ends these segments allow programmed interconnections between metal grid segments adjoining rows columns. switches unprogrammed device nonconducting. connections through switch matrix established automatic routing using Editnet select desired pairs matrix pins connected disconnected. legitimate switching matrix combinations each indicated Figure highlighted Show-Matrix command XACT system.
Programmable Interconnect
Programmable-interconnection resources Logic Cell Array provide routing paths connect inputs outputs IOBs CLBs into logic networks. Interconnections between blocks composed two-layer grid metal segments. Specially designed pass transistors, each controlled configuration bit, form programmable interconnect points (PIPs) switching matrices used implement necessary connections between selected metal segments block pins. Figure example routed net. XACT development system provides automatic routing these interconnections. Interactive routing (Editnet) also available design optimization. inputs CLBs IOBs multiplexers which programmed select input network from adjacent interconnect segments. Since
Figure XACT view routing resources used form typical interconnection network from
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
X2662
Figure XACT Development System Locations interconnect access, control inputs, logic inputs outputs. pattern represents available programmable interconnection points (PIPs). Some interconnect PIPs directional. This indicated XACT design editor status line: nondirectional interconnection. D:H->V that drives from horizontal vertical line. D:V->H that drives from vertical horizontal line. D:C->T that drives from cross tail. D:CW corner that drives clockwise direction. indicates non-conducting
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Special buffers within general interconnect areas provide periodic signal isolation restoration improved performance lengthy nets. interconnect buffers available propagate signals either direction given general interconnect segment. These bidirectional (bidi) buffers found adjacent switching matrices, above right highlighted Show BIDI command XACT system. other PIPs adjacent matrices accessed from Longlines. development system automatically defines buffer direction based location interconnection network source. delay calculator XACT development system automatically calculates displays block, interconnect buffer delays paths selected. Generation simulation netlist with worst-case delay model provided XACT option. Direct Interconnect Direct interconnect, shown Figure provides most efficient implementation networks between adjacent CLBs Blocks. Signals routed from block block using direct interconnect exhibit minimum interconnect propagation general interconnect resources. each CLB, output connected directly input immediately right input left. output direct interconnect drive input block immediately above input block below. Direct intercon-
Figure General-Purpose Interconnect. Composed grid metal segments that interconnected through switch matrices form networks X2664 inputs outputs.
1105 X2663
Figure Switch Matrix Interconnection Options Each Pin. Switch matrices edges different. Show Matrix menu option XACT system
Figure Outputs. outputs each have single contact, direct access inputs adjacent CLBs
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
X2660
Figure XC3020 Die-Edge IOBs. XC3020 die-edge IOBs provided with direct access adjacent CLBs.
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nect should used maximize speed highperformance portions logic. Where logic blocks adjacent IOBs, direct connect provided alternately inputs outputs four edges die. right edge provides additional direct connects from outputs adjacent IOBs. Direct interconnections IOBs with CLBs shown Figure Longlines Longlines bypass switch matrices intended primarily signals that must travel long distance, must have minimum skew among multiple destinations. Longlines, shown Figure vertically horizontally height width interconnect area. Each interconnection column three vertical Longlines, each interconnection horizontal Longlines. additional Longlines located adjacent outer sets switching matrices. devices larger than XC3020, vertical Longlines each column connectable half-length lines. XC3020, only outer Longlines connectable half-length lines. Longlines driven logic block output column-by-column basis. This capability provides common skew control clock line within each column logic blocks. Interconnections these Longlines shown Figure Isolation buffers provided each input Longline enabled automatically development system when connection made.
buffer upper left corner chip drives global which available inputs logic blocks. Using global buffer clock signal provides skewfree, high fan-out, synchronized clock IOBs CLBs. Configuration bits input each logic block select this global line another routing resource clock source flip-flops. This also programmed drive edge clock lines use. enhanced speed, CMOS threshold, direct access this buffer available second from left edge. buffer lower right corner array drives horizontal Longline that drive programmed connections vertical Longline each interconnection column. This alternate buffer also skew high fan-out. network formed this alternate buffer's Longlines selected drive inputs CLBs. CMOS threshold, high speed access this buffer available from third from bottom right edge. Internal Busses pair 3-state buffers, located adjacent each CLB, permits logic drive horizontal Longlines. Logic operation 3-state buffer controls allows them implement wide multiplexing functions. 3-state buffer input selected drive horizontal long-line applying logic level 3-state control line. Figure 15a. user required avoid contention which result from multiple drivers with opposing logic levels.
X1243
Figure Horizontal Vertical Longlines. These Longlines provide high fan-out, low-skew signal distribution each column. global buffer upper left corner drives common line throughout device.
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Control 3-state input same signal that drives buffer input, creates open-drain wired-AND function. logic High both buffer inputs creates high impedance, which represents contention. logic enables buffer drive Longline Low. Figure 15b. Pull-up resistors available each
Longline provide High output when connected buffers non-conducting. This forms fast, wide gating functions. When data drives inputs, separate signals drive 3-state control lines, these buffers form multiplexers (3-state busses). this case, care must used prevent contention through multiple active buffers
X1244
Figure Programmable Interconnection Longlines. This provided edges routing area. Three-state buffers allow horizontal Longlines form on-chip wired multiplexed buses. left non-clock vertical Longlines column (except XC3020) outer perimeter Longlines programmed connectible half-length lines.
(LOW)
X3036
Figure 15a. 3-State Buffers Implement Wired-AND Function. When buffer 3-state lines High, (high impedance), pull-up resistor(s) provide High output. buffer inputs driven control signals Low.
WEAK KEEPER CIRCUIT
X1741
Figure 15b. 3-State Buffers Implement Multiplexer. selection accomplished buffer 3-state signal.
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conflicting levels common line. Each horizontal Longline also driven weak keeper circuit that prevents undefined floating levels maintaining previous logic level when line driven active buffer pull-up resistor. Figure shows 3-state buffers, Longlines pull-up resistors.
Crystal Oscillator
Figure also shows location internal high speed inverting amplifier which used implement onchip crystal oscillator. associated with auxiliary buffer lower right corner die. When oscillator configured MakeBits connected signal source, special user IOBs also configured connect oscillator amplifier with external crystal oscillator components shown Figure divide
option available assure symmetry. oscillator circuit becomes active early configuration process allow oscillator stabilize. Actual internal connection delayed until completion configuration. Figure feedback resistor between output input, biases amplifier threshold. inversion amplifier, together with networks AT-cut series resonant crystal, produce 360-degree phase shift Pierce oscillator. series resistor included amplifier output impedance when needed phase-shift control, crystal resistance matching, limit amplifier input swing control clipping large amplitudes. Excess feedback voltage corrected ratio C2/C1. amplifier designed used from about one-half specified toggle frequency. frequencies below require individual characterization with respect series
X1245
Figure XACT Development System. extra large view possible interconnections lower right corner XC3020.
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Internal External
Alternate Clock Buffer
XTAL1
XTAL2 (IN) Suggested Component Values (may required frequency, phase)t (shift and/or compensation level crystal AT-cut parallel resonant PLCC PLCC PLCC
XTAL (OUT) XTAL (IN)
CQFP PQFP
PQFP
CQFP
PQFP
X5302
Figure Crystal Oscillator Inverter. When activated MakeBits program selecting output network buffer, crystal oscillator inverter uses unconfigured package pins external components implement oscillator. optional divide-by-two mode available assure symmetry.
resistance. Crystal oscillators above generally require crystal which operates third overtone mode, where fundamental frequency must suppressed inductor across turning this parallel resonant circuit double fundamental crystal frequency, i.e., desired third harmonic frequency network. When oscillator inverter used, these IOBs their package pins available general user I/O.
Programming
Table CCLK output output output output input Mode Master Master reserved Master Data
Serial Byte Wide Addr. 0000 Byte Wide Addr. FFFF down reserved Peripheral Byte Wide reserved Slave Serial
Initialization Phase internal power-on-reset circuit triggered when power applied. When reaches voltage which portions device begin operate (nominally programmable output buffers 3-stated high-impedance pull-up resistor provided user pins. time-out delay initiated allow power supply voltage stabilize. During this time powerdown mode inhibited. Initialization state time-out (about determined 14-bit counter driven self-generated internal timer. This nominal 1MHz timer subject variations with process, temperature power supply. shown Table five configuration mode choices available determined input levels three mode pins; Master configuration modes, device becomes source Configuration Clock (CCLK). beginning configuration devices using Peripheral Slave modes must delayed long enough their initialization completed. device with mode lines selecting Master configuration mode extends initialization state using four times delay assure that daisy-chained slave devices, which driving, will
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ready even master very fast, slave(s) very slow. Figure shows state sequences. Initialization, device enters Clear state where clears configuration memory. active Low, open-drain initialization signal INIT indicates when Initialization Clear states complete. device tests absence external active RESET before makes final sample mode lines enters Configuration state. external wired-AND more INIT pins used control configuration assertion active-Low RESET master mode device signal processor that devices initialized. configuration begun, re-assertion RESET minimum three internal timer cycles will recognized device will initiate abort, returning Clear state clear partially loaded configuration memory words. device will then resample RESET mode lines before re-entering Configuration state. re-program initiated.when configured XC3000 family device senses High-to-Low transition subsequent level Done/PROG package pin, this externally held permanently Low, High-to-Low transition subsequent time RESET package pin. device returns Clear state where configuration memory cleared mode lines resampled, aborted configuration. complete configuration program cleared loaded during each configuration program cycle.
Length count control allows system multiple Logic Cell Arrays, assorted sizes, begin operation synchronized fashion. configuration program generated MakePROM program XACT development system begins with preamble 111111110010 followed 24-bit length count representing total number configuration clocks needed complete loading configuration program(s). data framing shown Figure devices connected series read shift preamble length count positive negative configuration clock edges. device which received preamble length count then presents High Data until intercepted appropriate number data frames. When configuration program memory device full length count does compare, device shifts additional data through, preamble length count. When device configuration memory full length count compares, device will execute synchronous start-up sequence become operational. Figure CCLK cycles after completion loading configuration data, user pins enabled configured. selected MakeBits, internal userlogic RESET released either clock cycle before after pins become active. similar timing selection programmable DONE/PROG output signal. DONE/PROG also programmed open drain include pull-up resistor accommodate wired ANDing. High During Configuration (HDC) During Configuration (LDC) user pins which driven active while device Initialization,
User Pins 3-Stated with High Impedance Pull-Up, HDC=High, LDC=Low
INIT Output PWRDWN Inactive
Power Down HDC, Pull-Up
Initialization Power-On Time Delay Active RESET
PWRDWN Active
Clear Configuration Memory
RESET Active
Test Mode Pins
Configuration Program Mode
Start-Up
Operational Mode
DONE/PROGRAM RESET
Active RESET Operates User Logic Clear Cycles XC3020-130 Cycles XC3030-165 Cycles XC3042-195 Cycles XC3064-220 Cycles XC3090-250
Power-On Delay Cycles Non-Master Mode-11 Cycles Master Mode-43
X3399
Figure State Diagram Configuration Process Power-up Reprogram.
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Clear Configure states. They DONE/PROG provide signals control external logic signals such RESET, enable PROM enable during configuration. parallel Master configuration modes, these signals provide PROM enable control allow data pins shared with user logic signals. User inputs programmed either CMOS compatible thresholds. power-up, inputs have thresholds change CMOS thresholds
completion configuration user selected CMOS thresholds. threshold PWRDWN direct clock inputs fixed CMOS level. crystal oscillator used, will begin operation before configuration complete allow time stabilization before connected internal circuitry. Configuration Data Configuration data define function interconnection within Logic Cell Array loaded from external
11111111 0010 24-Bit Length Count 1111
-Dummy Bits* -Preamble Code -Configuration Program Length -Dummy Bits Bits Minimum)
Header
<Data Frame <Data Frame <Data Frame <Data Frame <Data Frame
XC3120 Configuration Data Frames (Each Frame Consists Start 71-Bit Data Field Three Stop Bits Program Data Repeated Each Logic Cell Array Daisy Chain
1111
Postamble Code Bits Minimum) *The Device Require Four Dummy Bits Min; XACT Software Generates Eight Dummy Bits
X5300
Device Gates CLBs IOBs Flip-flops
XC3020 XC3020A XC3020L XC3120 XC3120A 1,000 1,500
XC3030 XC3030A XC3030L XC3130 XC3130A 1,500 2,000 22,176
XC3042 XC3042A XC3042L XC3142 XC3142A 2,000 3,000 30,784
XC3064 XC3064A XC3064L XC3164 XC3164A 3,500 4,500 46,064
XC3090 XC3090A XC3090L XC3190 XC3190A 5,000 6,000 64,160
XC3195 XC3195A 6,500 7,500 1,320 94,944
Horizontal Longlines TBUFs/Horizontal Bits Frame (including1 start stop bits) Frames Program Data 14,779 Bits Frames bits (excludes header) PROM size (bits) Program Data 40-bit Header 14,819
22,216
30,824
46,104
64,200
94,984
Figure Internal Configuration Data Structure Device. This shows preamble, length count data frames generated XACT Development System. Length Count produced MakeBits program [(40-bit preamble program data daisy chain device) rounded multiple where function DONE RESET timing selected. additional added roundup increment less than additional clocks needed complete start-up after length count reached.
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Postamble Data Frame STOP
Last Frame
Stop
Preamble
Length Count
Data
Start Start configuration data consists composite 40-bit preamble/length count, followed more concatenated programs, separated 4-bit postambles. additional final postamble added each slave device result rounded byte boundary. length count less than number resulting bits. Timing assertion DONE termination INTERNAL RESET each programmed occur cycle before after outputs become active. Heavy lines indicate default condition
Length Count*
Weak Pull-Up
Active
PROGRAM
DONE
Internal Reset
X5303
Figure Configuration Start-up More Devices.
storage power-up after re-program signal. Several methods automatic controlled loading required data available. Logic levels applied mode selection pins start configuration time determine method used. Table data either bit-serial byte-parallel, depending configuration mode. different devices have different sizes numbers data frames. maintain compatibility between various device types, Xilinx product families compatible configuration formats. XC3020, configuration requires 14779 bits each device, arranged data frames. additional bits used header. Figure specific data format each device produced MakeBits command development system more these files then combined appended length count preamble transformed into PROM format file MakePROM command XACT development system. compatibility exception precludes XC2000-series device master XC3000series devices their DONE RESET programmed occur after their outputs become active. Option MakeBits program defines output levels unused blocks design connects these unused routing resources. This prevents indeterminate levels that might produce parasitic supply currents. unused blocks sufficient complete tie,
Flagnet command EDITLCA used indicate nets which must used drive remaining unused routing, that might affect timing user nets. Norestore will retain results timing analysis with Querynet before Restore returns design untied condition. omitted quick breadboard iterations where additional milliamps acceptable. configuration bitstream begins with eight High preamble bits, 4-bit preamble code 24-bit length count. When configuration initiated, counter device zero begins count total number configuration clock cycles applied device. each configuration data frame supplied device, internally assembled into data word, which then loaded parallel into word internal configuration memory array. configuration loading process complete when current length count equals loaded length count required configuration program data frames have been written. Internal user flip-flops held Reset during configuration. user-programmable pins defined unconfigured Logic Cell array. High During Configuration (HDC) During Configuration (LDC) well DONE/PROG used external control signals during configuration. Master mode configurations convenient active-Low EPROM Chip
2-121
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Enable. After last configuration data loaded length count compares, user pins become active. Options MakeBits program allow timing choices clock earlier later timing internal logic RESET assertion DONE signal. open-drain DONE/PROG output ANDtied with multiple devices used active-High READY, active-Low PROM enable RESET other portions system. state diagram Figure illustrates configuration process. Master Mode Master mode, device automatically loads configuration data from external memory device. There three Master modes that internal timing source supply configuration clock (CCLK) time incoming data. Master Serial mode uses serial configuration data supplied Data-in (DIN) from synchronous serial source such Xilinx Serial Configuration PROM shown Figure Master Parallel High modes automatically parallel data supplied D0-D7 pins response 16-bit address generated device. Figure shows example parallel Master mode connections required. starting address 0000 increments Master mode FFFF decrements Master High mode. These modes provide address compatibility with microprocessors which begin execution from opposite ends memory. Peripheral Mode Peripheral mode provides simplified interface through which device loaded byte-wide, processor peripheral. Figure shows peripheral mode connections. Processor write cycles decoded from common assertion active Write Strobe (WS), active active high Chip Selects (CS0, CS1, CS2). device generates configuration clock from internal timing generator serializes parallel input data internal framing succeeding slaves Data (DOUT). output High READY/BUSY indicates completion loading each byte when input register ready byte. with Master modes, Peripheral mode also used lead device daisy-chain slave devices. Slave Serial Mode Slave Serial mode provides simple interface loading Logic Cell Array configuration shown Figure Serial data supplied conjunction with synchronizing input clock. Most Slave mode applications daisychain configurations which data input driven from previous Logic Cell Array's data out, while clock supplied lead device Master Peripheral mode. Data also supplied processor other special circuits.
Daisy Chain XACT development system used create composite configuration selected devices including: preamble, length count total bitstream, multiple concatenated data programs postamble plus additional fill device serial chain. After loading passing-on preamble length count possible daisy-chain, lead device will load configuration data frames while providing High DOUT possible down-stream devices shown Figure Loading continues while lead device received configuration program current length count reached full value. additional data passed through lead device appears Data (DOUT) serial form. lead device also generates Configuration Clock (CCLK) synchronize serial output data data down-stream devices. Data read slave devices positive edge CCLK shifted DOUT negative edge CCLK. parallel Master mode device uses internal timing generator produce internal CCLK times EPROM address rate, while Peripheral mode device produces burst CCLKs each chip select writestrobe cycle. internal timing generator continues operate general timing synchronization inputs modes.
Special Configuration Functions
configuration data includes control over several special functions addition normal user logic functions interconnect. Input thresholds Readback disable DONE pull-up resistor DONE timing RESET timing Oscillator frequency divided
Each these functions controlled configuration data bits which selected part normal XACT development system bitstream generation process. Input Thresholds Prior completion configuration device input thresholds compatible. Upon completion configuration, input thresholds become either CMOS compatible programmed. threshold option requires some additional supply current threshold shifting. exception threshold PWRDWN input direct clocks which always have CMOS input. Prior completion configuration user pins each have high impedance pull-up.
2-122
configuration program used enable pullup resistors Operational mode either input load avoid floating input otherwise unused pin. Readback contents Logic Cell Array read back been programmed with bitstream which Readback option been enabled. Readback used verification configuration method determining state internal logic nodes during debugging. There three options generating configuration bitstream. "Never" inhibits Readback capability. "One-time," inhibits Readback after Readback been executed verify configuration. "On-command" allows unrestricted Readback. Readback accomplished without user pins; only CCLK used. initiation Readback produced High transition M0/RTRIG (Read Trigger) pin. CCLK input must then driven external logic read back configuration data. first three Low-to-High CCLK transitions clock dummy data. subsequent Lowto-High CCLK transitions shift data frame information M1/RDATA (Read Data) pin. Note that logic polarity always inverted, zero configuration becomes Readback, vice versa. Note also that each Readback frame Start (read back one) but, unlike configuration, each Readback frame only Stop (read back zero). third leading dummy mentioned above considered Start first frame. data frames must read back complete process return Mode Select CCLK pins their normal functions. Readback data includes current state each flip-flop, each input flip-flop latch, each device pad. These data imbedded into unused configuration positions during Readback. This state information used XACT development system In-Circuit Verifier provide visibility into internal operation logic while system operating. readback uniform timesample storage elements, necessary inhibit system clock. Reprogram initiate re-programming cycle, dual-function DONE/PROG must given High-to-Low transition.
reduce sensitivity noise, input signal filtered cycles device internal timing generator. When reprogram begins, user-programmable output buffers disabled high-impedance pull-ups provided package pins. device returns Clear state clears configuration memory before indicates `initialized'. Since this Clear operation uses chipindividual internal timing, master might complete Clear operation then start configuration before slave completed Clear operation. avoid this problem, slave INIT pins must AND-wired used force RESET master (see Figure 22). Reprogram control often implemented using external opencollector driver which pulls DONE/PROG Low. Once stable request recognized, DONE/PROG held until configuration been completed. Even re-program request externally held beyond configuration period, device will begin operation upon completion configuration. DONE Pull-up DONE/PROG open-drain that indicates device operational state. optional internal pull-up resistor enabled user XACT development system when MAKEBITS executed. DONE/PROG pins multiple devices daisychain connected together indicate DONE direct them reprogram. DONE Timing timing DONE status signal controlled selection MakeBits program occur either CCLK cycle before, after, outputs going active. Figure This facilitates control external functions such PROM enable holding system wait state. RESET Timing with DONE timing, timing release internal reset controlled selection MakeBits program occur either CCLK cycle before, after, outputs going active. Figure This reset keeps user programmable flip-flops latches zero state during configuration. Crystal Oscillator Division selection MakeBits program allows user incorporate dedicated divide-by-two flip-flop between crystal oscillator alternate clock line. This guarantees symmetrical clock signal. Although frequency stability crystal oscillator very good, symmetry waveform affected bias feedback drive.
following seven pages describe different configuration modes detail
2-123
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Master Serial Mode
READBACK ACTIVATED, RESISTOR REQUIRED SERIES WITH DURING CONFIGURATION PULL-DOWN RESISTOR OVERCOMES INTERNAL PULL-UP, ALLOWS USER I/O.
PWRDWN OPTIONAL DAISY-CHAINED LCAs WITH DIFFERENT CONFIGURATIONS CCLK OPTIONAL DAISY-CHAINED LCAs WITH DIFFERENT CONFIGURATIONS
DOUT GENERALPURPOSE USER PINS INIT
RESET
Figure Master Serial Mode
Master Serial mode, CCLK output lead device drives Xilinx Serial PROM that feeds input. Each rising edge CCLK output increments Serial PROM internal address counter. This puts next data SPROM data output, connected pin. lead device accepts this data subsequent rising CCLK edge. lead device then presents preamble data (and data that overflows lead device) DOUT pin. There internal delay CCLK periods, which
OTHER PINS
CCLK OPTIONAL SLAVE LCAs WITH IDENTICAL CONFIGURATIONS OPTIONAL SLAVE LCAs WITH IDENTICAL CONFIGURATIONS
XC3000 DEVICE
RESET CCLK
INIT
DATA CASCADED SERIAL MEMORY
DATA OE/RESET XC17xx
OE/RESET
(LOW RESETS XC17xx ADDRESS POINTER)
X6092
means that DOUT changes falling CCLK edge, next device daisy-chain accepts data subsequent rising CCLK edge. SPROM input driven from either DONE Using avoids potential contention pin, this configured user-I/O, then restricted permanently High user output. Using DONE also avoids contention DIN, provided early DONE option invoked.
2-124
Master Serial Mode Programming Switching Characteristics
CCLK (Output) TCKDS Serial Data TDSCK
Serial DOUT (Output)
X3223
Speed Grade Description CCLK Data setup Data hold Symbol TDSCK CKDS
Units
Notes: power-up, must rise from less than this possible, configuration delayed holding RESET until reached (2.5 XC3000L). very long rise time >100 non-monotonically rising require >6-µs High level RESET, followed >6-µs level RESET after reached (2.5 XC3000L). Configuration controlled holding RESET with until after INIT daisy-chain slave-mode devices High. Master-serial-mode timing based slave-mode testing.
2-125
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Master Parallel Mode
Readback
Activated, Resistor Required Series With
M1PWRDWN CCLK DOUT Slave
M1PWRDWN CCLK DOUT Slave
M1PWRDWN CCLK DOUT RCLK
GeneralPurpose User Pins
GeneralPurpose User Pins
GeneralPurpose User Pins
N.C. RESET EPROM
Other Pins Master
Other Pins INIT
Other Pins INIT Reset
Reprogram System Reset
Note: XC2000 Devices Have INIT Hold Master Device. Reset Master Device Should Asserted External Timing Circuit Allow CCLK Variations Clear State Time.
RESET
INIT
Open Collector Each
X3159
Figure Master Parallel Mode
Master Parallel mode, lead device directly addresses industry-standard byte-wide EPROM accepts eight data bits right before incrementing decrementing) address outputs. eight data bits serialized lead device, which then presents preamble data (and data that overflows lead device) DOUT pin. There
internal delay CCLK periods, after rising CCLK edge that accepts byte data, also changes EPROM address, until falling CCLK edge that makes (D0) this byte appear DOUT. This means that DOUT changes falling CCLK edge, next device daisy chain accepts data subsequent rising CCLK edge.
2-126
Master Parallel Mode Programming Switching Characteristics
A0-A15 (output) Address Byte Address Byte TRAC D0-D7 Byte TDRC RCLK (output) CCLKs CCLK TRCD
CCLK (output)
DOUT (output)
Byte
X5380
Description RCLK address valid data setup data hold RCLK High RCLK
Symbol TRAC TDRC TRCD TRCH TRCL
Units
Notes: power-up, must rise from less than this possible, configuration delayed holding RESET until reached (2.5 XC3000L). very long rise time >100 non-monotonically rising require >6-µs High level RESET, followed >6-µs level RESET after reached (2.5 XC3000L). Configuration controlled holding RESET with until after INIT daisy-chain slave-mode devices High.
This timing diagram shows that EPROM requirements extremely relaxed: EPROM access time longer than 4000 EPROM data output hold time requirements.
2-127
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Peripheral Mode
CONTROL SIGNALS ADDRESS DATA D0-7 READBACK ACTIVATED, RESISTOR REQUIRED SERIES WITH
CCLK
D0-7
DOUT ADDRESS DECODE LOGIC OTHER PINS RDY/BUSY INIT REPROGRAM RESET
OPTIONAL DAISY-CHAINED LCAs WITH DIFFERENT CONFIGURATIONS
GENERALPURPOSE USER PINS
Figure Peripheral Mode.
X3031
Peripheral mode uses trailing edge logic condition CS0, CS1, CS2, inputs accept byte-wide data from microprocessor bus. lead device, this data loaded into double-buffered UARTlike parallel-to-serial converter serially shifted into internal logic. lead device presents preamble data (and data that overflows lead device) DOUT pin. Ready/Busy output from lead device acts handshake signal microprocessor. RDY/BUSY goes when byte been received, goes High
again when byte-wide input buffer transferred information into shift register, buffer ready receive data. length BUSY signal depends activity UART. shift register been empty when byte received, BUSY signal lasts only CCLK periods. shift register still full when byte received, BUSY signal long nine CCLK periods. Note that after last byte been entered, only seven bits shifted out. CCLK remains High with DOUT equal (the next-to-last bit) last byte entered.
2-128
Peripheral Mode Programming Switching Characteristics
WRITE
CS0,
D0-D7
Valid
CCLK
TWTRB
RDY/BUSY
TBUSY
DOUT
Previous Byte
Byte
X3249
Description Write Effective Write time required (Assertion CS0, CS1, CS2, Setup time required Hold time required RDY/BUSY delay after Earliest next after BUSY BUSY time generated
Notes:
Symbol
Units
TWTRB TRBWT TBUSY
CCLK
Periods
power-up, must rise from less than this possible, configuration delayed holding RESET until reached (2.5 XC3000L). very long rise time >100 non-monotonically rising require >6-µs High level RESET, followed >6-µs level RESET after reached (2.5 XC3000L). Configuration must delayed until INIT LCAs High. Time from CCLK cycle byte data depends completion previous byte processing phase internal timing generator CCLK. CCLK DOUT timing tested slave mode. TBUSY indicates that double-buffered parallel-to-serial converter ready receive data. shortest TBUSY occurs when byte loaded into empty parallel-to-serial converter. longest TBUSY occurs when word loaded into input register before second-level buffer started shifting data.
This timing diagram shows very relaxed requirements: Data need held beyond rising edge BUSY will active within after BUSY will stay active several microseconds. asserted immediately after BUSY.
2-129
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Slave Serial Mode
Readback Activated, Resistor Required Series with Optional Daisy-Chained LCAs with Different Configurations
Micro Computer STRB Port RESET INIT RESET CCLK
PWRDWN
DOUT GeneralPurpose User Pins
Other Pins
X3157
Figure Slave Serial Mode.
Slave Serial mode, external signal drives CCLK input(s) device(s). serial configuration bitstream must available input lead device short set-up time before each rising CCLK edge. lead device then presents preamble
data (and data that overflows lead device) DOUT pin. There internal delay CCLK periods, which means that DOUT changes falling CCLK edge, next device daisy-chain accepts data subsequent rising CCLK edge.
2-130
Slave Serial Mode Programming Switching Characteristics
TDCC CCLK TCCH DOUT (Output) TCCO
X5379
TCCD
TCCL
Description CCLK DOUT setup hold High time time (Note Frequency
Symbol TCCO TDCC TCCD TCCH TCCL
Units
0.05 0.05
Notes: limit CCLK time caused dynamic circuitry inside device. Configuration must delayed until INIT devices High. power-up, must rise from less than this possible, configuration delayed holding RESET until reached (2.5 XC3000L). very long rise time >100 non-monotonically rising require >6-µs High level RESET, followed >6-µs level RESET after reached (2.5 XC3000L).
Program Readback Switching Characteristics
DONE/PROG (OUTPUT) TRTH RTRIG (M0) TRTCC TCCL TCCL
CCLK(1) TCCRD Input/ RDATA Output H1-Z VALID READBACK OUTPUT VALID READBACK OUTPUT
X6116
RTRIG CCLK
Description RTRIG High RTRIG setup RDATA delay High time time
Symbol TRTH TRTCC TCCRD TCCHR TCCLR
Units
Notes:
During Readback, CCLK frequency exceed MHz. RETRIG positive transition) shall done until after clock following active pins. Readback should initiated until configuration complete. TCCLR XC3000L.
2-131
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
General Switching Characteristics
TMRW RESET M0/M1/M2 TPGW DONE/PROG TPGI INIT (Output) User State Clear State Configuration State
PWRDWN Note (Valid) VCCPD
X5387
Description RESET setup time required hold time required RESET Width (Low) req. Abort
Symbol TMRW TPGW TPGI VCCPD
Units
DONE/PROG
Width (Low) required Re-config. INIT response after pulled Power Down
PWRDWN
Notes: power-up, must rise from less than this possible, configuration delayed holding RESET until reached (2.5 XC3000L). very long rise time >100 non-monotonically rising require >1-µs High level RESET, followed >6-µs level RESET after reached (2.5 XC3000L). RESET timing relative valid mode lines (M0, relevant when RESET used delay configuration. specified hold time caused shift-register filter slowing down response RESET during configuration. PWRDWN transitions must occur while >4.0 V(2.5 XC3000L).
2-132
Performance
Device Performance XC3000 families FPGAs achieve very high performance. This result sub-micron manufacturing process, developed continuously being enhanced production state-of-the-art CMOS SRAMs. Careful optimization transistor geometries, circuit design, lay-out, based years experience with XC3000 family. look-up table based, coarse-grained architecture that collapse multiple-layer combinatorial logic into single function generator. implement four layers conventional logic little Actual system performance determined timing critical paths, including delay through combinatorial sequential logic elements within CLBs IOBs, plus delay interconnect routing. ac-timing specifications state worst-case timing parameters various logic resources available XC3000families architecture. Figure shows variety elements involved determining system performance. Logic block performance expressed propagation time from interconnect point input block output block interconnect area. Since combinatorial logic implemented with memory lookup table within CLB, combinatorial delay through CLB, called TILO, always same, regardless function being implemented. combinatorial logic function driving data input storage element, critical timing data set-up relative clock edge provided flip-flop element. delay from clock source output logic block critical timing signals produced storage elements. Loading logicClock Output TCKO Logic Combinatorial TILO
block output limited only resulting propagation delay larger interconnect network. Speed performance logic block function supply voltage temperature. Figure Interconnect performance depends routing resources used implement signal path. Direct interconnects neighboring provide extremely fast path. Local interconnects through switch matrices (magic boxes) suffer delay, equal resistance pass transistor multiplied capacitance driven metal line. Longlines carry signal across length breadth chip with only access delay. Generous on-chip signal buffering makes performance relatively insensitive signal fan-out; increasing fan-out from changes delay only 10%. Clocks distributed with low-skew clock distribution networks. tools XACT Development System used place route design XC3000 FPGA (the Automatic Place Route [APR] program XACT Design Editor)automatically calculate actual maximum worstcase delays along each signal path. This timing information back-annotated design's netlist timing simulation examined with X-DELAY, static timing analyzer. Actual system performance applications dependent. maximum clock rate that used system determined critical path delays within that system. These delays combinations incremental logic routing delays, vary from design design. synchronous system, maximum clock rate depends number combinatorial logic layers between resynchronizing flip-flops. Figure shows achievable clock rate function number layers.
Setup TICK Logic
CLOCK
TCKO
TOKPO
X3178
Figure Primary Block Speed Factors. Actual timing function various block factors combined with routing factors. Overall performance evaluated with XACT timing calculator optional simulation.
2-133
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
SPECIFIED WORST-CASE VALUES
1.00
(4.7
0.80 NORMALIZED DELAY
0.60
TYPICAL COMMERCIAL 25°C)
TYPICAL MILITARY 0.40
ERCIAL COMM (5.25 ERCIA COMM
MILIT (4.5
MILITAR
(5.5
0.20
X6094
TEMPERATURE (°C)
Figure Relative Delay Function Temperature, Supply Voltage Processing Variations
System Clock (MHz)
Power
Power Distribution Power device distributed through grid achieve high noise immunity isolation between logic I/O. Inside device, dedicated ground ring surrounding logic array provides power drivers. independent matrix groundlines supplies interior logic device. This power distribution grid provides stable supply ground internal logic, providing external package power pins connected appropriately decoupled. Typically 0.1-µF capacitor connected near ground pins will provide adequate decoupling. Output buffers capable driving specified 8-mA loads under worst-case conditions capable driving much times that current best case. Noise reduced minimizing external load capacitance reducing simultaneous output transitions same direction. also beneficial locate heavily loaded output buffers near ground pads. Block output buffers have slew-limited mode which should used where output rise fall times speed critical. Slew-limited outputs maintain their drive capability, generate less external reflections internal noise.
XC3100-3
XC3000-125 Levels: CLBs Gate Levels: (4-16)
CLBs (3-12)
CLBs (2-8)
(1-4)
Toggle Rate
X3250
Figure Clock Rate Function Logic Complexity (Number Combinational Levels between Flip-Flops)
2-134
Dynamic Power Consumption XC3042 driving three local interconnects global clock buffer clock line device output with load 0.25 2.25 1.25 XC3042A 0.17 1.40 1.25 XC3042L 0.07 0.50 0.55 XC3142A 0.25 1.70 1.25
Power Consumption Logic Cell Array exhibits power consumption characteristic CMOS ICs. design, configuration option chip input threshold requires power threshold reference. power required static memory cells that hold configuration data very maintained power-down mode. Typically, most power dissipation produced external capacitive loads output buffers. This load frequency dependent power µW/pF/MHz output. Another component power external loading output pins. Internal power dissipation function number size nodes, frequency which they change. device, fraction nodes changing given clock typically (10-20%). example, long binary counter, total activity counter flip-flops equivalent that only outputs toggling clock frequency. Typical global clock-buffer power between mW/MHz XC3020 mW/MHz XC3090. internal capacitive load more function interconnect than fan-out. With typical load three general interconnect segments, each output requires about 0.25 output frequency. Because control storage Logic Cell Array CMOS static memory, cells require very standby current data retention. some systems, this data retention current characteristic used method preserving configurations event primary
power loss. Logic Cell Array built Powerdown logic which, when activated, will disable normal operation device retain only configuration data. internal operation suspended output buffers placed their high-impedance state with pull-ups. Different from XC3000 family which powered down current consumption microamps, XC3100 draws even power-down. This makes power-down operation less meaningful. contrast, ICCPD XC3000L only force Logic Cell Array into Powerdown state, user must pull PWRDWN continue supply retention voltage pins. When normal power restored, elevated normal operating voltage PWRDWN returned High. Logic Cell Array resumes operation with same internal sequence that occurs conclusion configuration. Internal-I/O logic-block storage elements will reset, outputs will become enabled DONE/PROG will released. When shut down disconnected, some power might unintentionally supplied from incoming signal driving pin. conventional electrostatic input protection implemented with diodes supply ground. positive voltage applied input output) will cause positive protection diode conduct drive connection. This condition produce invalid power conditions should avoided. large series resistor might used limit current bipolar buffer used isolate input signal.
2-135
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Descriptions
Permanently Dedicated Pins. eight (depending package type) connections positive supply voltage. must connected. eight (depending package type) connections ground. must connected. PWRDWN this CMOS-compatible input stops internal activity, retains configuration. flip-flops latches reset, outputs 3-stated, inputs interpreted High, independent their actual level. When PWDWN returns High, device becomes operational with DONE cycles internal 1-MHz clock.Before during configuration, PWRDWN must High. used, PWRDWN must tied VCC. RESET This active input which three functions. Prior start configuration, input will delay start configuration process. internal circuit senses application power begins minimal time-out cycle. When time-out RESET complete, levels lines sampled configuration begins. RESET asserted during configuration, device re-initialized restarts configuration termination RESET. RESET asserted after configuration complete, provides global asynchronous RESET storage elements device. CCLK During configuration, Configuration Clock output device Master mode Peripheral mode, input Slave mode. During Readback, CCLK clock input shifting configuration data device CCLK drives dynamic circuitry inside device. time may, therefore, exceed microseconds. When used input, CCLK must "parked High". internal pull-up resistor maintains High when being driven.
DONE/PROG (D/P) DONE open-drain output, configurable with without internal pull-up resistor completion configuration, device circuitry becomes active synchronous order; DONE programmed active High cycle either before after outputs active. Once configuration done, High-to-Low transition this will cause initialization device start reconfiguration. M0/RTRIG Mode this input sampled power-on determine power-on delay (214 cycles High, cycles Low). Before start configuration, this input again sampled together with determine configuration mode used Low-to-High input transition, after configuration complete, acts Read Trigger initiates Readback configuration storage-element data clocked CCLK. selecting appropriate Readback option when generating bitstream, this operation limited single Readback, inhibited altogether. M1/RDATA Mode this input sampled before start configuration establish configuration mode used. Readback never used, tied directly ground VCC. Readback ever used, must resistor ground VCC, accommodate RDATA output. active-Low Read Data, after configuration complete, this output Readback data.
2-136
User Pins that have special functions. During configuration, this input weak pull-up resistor. Together with sampled before start configuration establish configuration mode used. After configuration, this user-programmable pin. During configuration, this output held High level indicate that configuration complete. After configuration, this user-programmable pin. During Configuration, this output held level indicate that configuration complete. After configuration, this user-programmable pin. particularly useful Master mode enable EPROM, must then programmed High after configuration. INIT This active open-drain output with weak pullup held during power stabilization internal clearing configuration memory. used indicate status configuring microprocessor wired several slave mode devices, hold-off signal master mode device. After configuration this becomes user-programmable pin. BCLKIN This direct CMOS level input alternate clock buffer (Auxiliary Buffer) lower right corner. XTL1 This user used operate output amplifier driving external crystal bias circuitry. XTL2 This user used input amplifier connected external crystal bias circuitry. Block left unconfigured. oscillator configuration activated routing from oscillator buffer symbol output MakeBits program. CS0, CS1, CS2, These four inputs represent signals, three active active High, that used control configuration-data entry Peripheral mode. Simultaneous assertion four inputs generates Write internal data buffer. removal assertion clocks D0D7 data. Master-Parallel mode, outputs. After configuration, these pins userprogrammable pins.
RDY/BUSY During Peripheral Parallel mode configuration this indicates when chip ready another byte data written After configuration complete, this becomes user-programmed pin. RCLK During Master Parallel mode configuration, each change A0-15 outputs preceded rising edge RCLK, redundant output signal. After configuration complete, this becomes user-programmed pin. D0-D7 This eight pins represents parallel configuration byte parallel Master Peripheral modes. After configuration complete, they user-programmed pins. A0-A15 During Master Parallel mode, these pins present address output configuration EPROM. After configuration, they user-programmable pins. During Slave Master Serial configuration, this used serial-data input. Master Peripheral configuration, this Data input. After configuration complete, this becomes user-programmed pin. DOUT During configuration this used output serialconfiguration data daisy-chained slave. After configuration complete, this becomes userprogrammed pin. TCLKIN This direct CMOS-level input global clock buffer. This also configured user programmable pin. However, since TCLKIN preferred input global clock net, global clock should used primary clock source, this usually clock input chip.
Unrestricted User Pins. programmed user Input Output following configuration. unrestricted pins, plus special pins mentioned following page, have weak pull-up resistor that becomes active soon device powers stays active until configuration.
Before during configuration, outputs that used configuration process 3-stated with pull-up resistor.
2-137
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Functions During Configuration
Configuration Mode <M2:M1:M0> SLAVE <1:1:1> PWRDWN (HIGH) (HIGH) (HIGH) (HIGH) (LOW) INIT* RESET DONE MASTER-SER <0:0:0> PWRDWN (LOW) (LOW) (LOW) (HIGH) (LOW) INIT* RESET DONE PERIPHERAL <1:0:1> PWRDWN (LOW) (HIGH) (HIGH) (HIGH) (LOW) INIT* RESET DONE DATA DATA DATA DATA DATA DATA DATA RDY/BUSY DATA DOUT CCLK(O) MASTER-HIGH <1:1:0> PWRDWN (HIGH) (LOW) (HIGH) (HIGH) (LOW) INIT* RESET DONE DATA DATA DATA DATA DATA DATA DATA RCLK DATA DOUT CCLK(O) MASTER-LOW <1:0:0> PWRDWN (LOW) (LOW) (HIGH) (HIGH) (LOW) INIT* RESET DONE DATA DATA DATA DATA DATA DATA DATA RCLK DATA DOUT CCLK(O) **** PLCC PLCC PLCC PQFP TQFP PQFP PQFP
User Operation PWRDWN RDATA RTRIG XTL2 RESET PROGRAM XTL1 CCLK Others XC3020 etc. XC3030 etc. XC3042 etc. XC3064 etc. XC3090 etc. XC3195
X5266
DOUT CCLK
DOUT CCLK(O)
****
Represents 50-k 100-k pull-up before during configuration INIT open drain output during configuration Represents input assignmnent XC3064/XC3090 XC3195 differ from those shown. page 2-138. Peripheral mode master parallel mode supported PC44 package. page 2-135. assignments XC3195 PQ208 differ from those shown. page 2-146. assignments Footprint PLCC sockets packages electrically identical. Generic pins shown. information this page provided convenient summary. detailed descriptions, preceding pages. detailed description configuration modes, pages 2-190 through 2-200. pinout details, pages 2-136 through 2-146.
Before during configuration, outputs that used configuration process 3-stated with pull-up resistor.
2-138
XC3000 Families Assignments
Xilinx offers different array sizes XC3000 families variety surface-mount through-hole package types, with counts from 223. Each chip offered several package types accommodate available board space manufacturing technology. Most package types also offered with different chips accommodate design changes without need board changes.
Note that there perfect match between number bonding pads chip number pins package. some cases, chip more pads than there pins package, indicated information ("unused" pads) below line following table. IOBs unconnected pads still used storage elements specified propagation delays set-up times acceptable. other cases, chip fewer pads than there pins package; therefore, some package pins connected (n.c.), shown above line following table.
Number Unbounded Unconnected Pins
Number Package Pins Device Pads 3020 3030 3042 3064 3090 3195 n.c.
n.c.
n.c. n.c. n.c.
n.c. n.c.
n.c. n.c.
n.c. n.c.
X6095
n.c. Unconnected package Unbonded device
Number Available Pins
Number Package Pins XC3020/XC3120 XC3030/XC3130 XC3042/XC3142 XC3064/XC3164 XC3090/XC3190 XC3195
X3478
2-139
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3000 Family 44-Pin PLCC Pinouts XC3000, XC3000A, XC3000L, XC3100 XC3100A families have identical pinouts
XC3030 PWRDWN TCLKIN-I/O M1-RDATA M0-RTRIG M2-I/O HDC-I/O LDC-I/O INIT-I/O XC3030 XTL2(IN)-I/O RESET DONE-PGM XTL1(OUT)-BCLK-I/O DIN-I/O DOUT-I/O CCLK
Peripheral mode Master Parallel mode supported PC44 package XC3030 Family 64-Pin Plastic VQFP Pinouts XC3000, XC3000A, XC3000L XC3100 families have identical pinouts
XC3030 A0-WS-I/O A1-CS2-I/O A2-I/O A3-I/O A4-I/O A14-I/O A5-I/O A13-I/O A6-I/O A12-I/O A7-I/O A11-I/O A8-I/O A10-I/O A9-I/O PWRDN TCLKIN-I/O M1-RDATA M0-RTRIG XC3030 M2-I/O HDC-I/O LDC-I/O INIT-I/O XTAL2(IN)-I/O RESET DONE-PG D7-I/O XTAL1(OUT)-BCLKIN-I/O D6-I/O D5-I/O CS0-I/O D4-I/O D3-I/O CS1-I/O D2-I/O D1-I/O RDY/BUSY-RCLK-I/O D0-DIN-I/O DOUT-I/O CCLK
2-140
XC3000 Families 68-Pin PLCC, 84-Pin PLCC Pinouts
XC3000, XC3000A, XC3000L, XC3100 XC3100A families have identical pinouts
PLCC XC3030 XC3020 XC3020 XC3030, XC3042 PWRDN TCLKIN-I/O I/O* M1-RDATA M0-RTRIG M2-I/O HDC-I/O LDC-I/O I/O* I/O* INIT-I/O I/O* I/O* XTL2(IN)-I/O PLCC PLCC XC3030 XC3020 XC3020 XC3030, XC3042 RESET DONE-PG D7-I/O XTL1(OUT)-BCLKIN-I/O D6-I/O D5-I/O CS0-I/O D4-I/O D3-I/O CS1-I/O D2-I/O I/O* D1-I/O RDY/BUSY-RCLK-I/O D0-DIN-I/O DOUT-I/O CCLK A0-WS-I/O A1-CS2-I/O A2-I/O A3-I/O I/O* I/O* A15-I/O A4-I/O A14-I/O A5-I/O A13-I/O A6-I/O A12-I/O A7-I/O I/O* I/O* A11-I/O A8-I/O A10-I/O A9-I/O
PLCC
Unprogrammed IOBs have default pull-up. This prevents undefined level unbonded unused IOBs. Programmed outputs default slew-rate limited. This table describes pinouts three different chips three different packages. pin-description column lists pads XC3042 (and pads XC3030) that connected package pins. pads, indicated asterisk, exist XC3020, which pads; therefore corresponding pins 84-pin packages have connections XC3020. pads XC3020 pads XC3030, indicated dash PLCC column, have connection PLCC, connected 84-pin packages.
2-141
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
XC3064/XC3090/XC3195 84-Pin PLCC Pinouts
XC3000, XC3000A, XC3000L, XC3100 XC3100A families have identical pinouts
PLCC Number PLCC Number
XC3064, XC3090, XC3195 PWRDN TCLKIN-I/O GNDI M1-RDATA M0-RTRIG M2-I/O HDC-I/O LDC-I/O INIT/I/OI VCCI XTL2(IN)-I/O
XC3064, XC3090, XC3195 RESET DONE-PG D7-I/O XTL1(OUT)-BCLKIN-I/O D6-I/O D5-I/O CS0-I/O D4-I/O GNDI D3-I/OI CS1-I/OI D2-I/OI D1-I/O RDY/BUSY-RCLK-I/O D0-DIN-I/O DOUT-I/O CCLK A0-WS-I/O A1-CS2-I/O A2-I/O A3-I/O A15-I/O A4-I/O A14-I/O A5-I/O VCCI A13-I/OI A6-I/OI A12-I/OI A7-I/OI A11-I/O A8-I/O A10-I/O A9-I/O
Unprogrammed IOBs have default pull-up. This prevents undefined level unbonded unused IOBs. Programmed ouptuts default slew-rate limited.
PC84 package, XC3064, XC3090 XC3195 have additional pins thus different definition than XC3020/XC3030/XC3042.
2-142
XC3000 Families 100-Pin Pinouts
XC3000, XC3000A, XC3000L, XC3100 XC3100A families have identical pinouts
CQFP PQFP TQFP VQFP
XC3020 XC3030 XC3042
A13-I/O A6-I/O A12-I/O A7-I/O I/O* I/O* A11-I/O A8-I/O A10-I/O A9-I/O VCC* GND* PWRDN TCLKIN-I/O I/O** I/O* I/O*
CQFP PQFP TQFP VQFP
XC3020 XC3030 XC3042
I/O* I/O* M1-RD GND* MO-RT VCC* M2-I/O HDC-I/O LDC-I/O I/O* I/O* INIT-I/O I/O* I/O* XTL2-I/O GND* RESET VCC* DONE-PG D7-I/O BCLKIN-XTL1-I/O D6-I/O
CQFP PQFP TQFP VQFP
XC3020 XC3030 XC3042
I/O* I/O* D5-I/O CS0-I/O D4-I/O D3-I/O CS1-I/O D2-I/O I/O* I/O* D1-I/O RDY/BUSY-RCLK-I/O DO-DIN-I/O DOUT-I/O CCLK VCC* GND* AO-WS-I/O A1-CS2-I/O I/O** A2-I/O A3-I/O I/O* I/O* A15-I/O A4-I/O A14-I/O A5-I/O
Unprogrammed IOBs have default pull-up. This prevents undefined level unbonded unused IOBs. Programmed outputs default slew-rate limited. This table describes pinouts three different chips three different packges. pin-description column lists pads XC3042 that connected package pins. pads, indicated double asterisks, exist XC3030, which pads; therefore corresponding pins have connections. Twenty-six pads, indicated single double asterisks, exist XC3020, which pads; therefore, corresponding pins have connections. (See table page 2-139.)
2-143
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
XC3000 Families 132-Pin Ceramic Plastic Pinouts
XC3000, XC3000A, XC3000L, XC3100 XC3100A families have identical pinouts
Number XC3042 XC3064 Number XC3042 XC3064 M1-RD Number XC3042 XC3064 RESET Number XC3042 XC3064 DOUT-I/O CCLK
PWRDN I/O-TCLKIN I/O* I/O*
M0-RT
DONE-PG D7-I/O XTL1-I/O-BCLKIN D6-I/O I/O* D5-I/O CS0-I/O I/O* I/O* D4-I/O
M2-I/O HDC-I/O LDC-I/O I/O* INIT-I/O
A0-WS-I/O A1-CS2-I/O A2-I/O A3-I/O A15-I/O A4-I/O I/O* A14-I/O A5-I/O
I/O* I/O* I/O*
I/O* XTL2(IN)-I/O
D3-I/O CS1-I/O I/O* I/O* D2-I/O D1-I/O RDY/BUSY-RCLK-I/O D0-DIN-I/O
A13-I/O A6-I/O I/O* A12-I/O A7-I/O A11-I/O A8-I/O A10-I/O A9-I/O
Unprogrammed IOBs have default pull-up. This prevents undefined level unbonded unused IOBs. Programmed outputs default slew-rate limited. Indicates unconnected package pins (14) XC3042.
2-144
XC3000 Families 144-Pin Plastic TQFP Pinouts
XC3000, XC3000A, XC3000L, XC3100 XC3100A families have identical pinouts
Number XC3042 XC3064 PWRDN I/O-TCLKIN I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* M1-RD MO-RT M2-I/O HDC-I/O LDC-I/O I/O* Number XC3042 XC3064 I/O* INIT-I/O I/O* I/O* XTL2(IN)-I/O RESET DONE-PG D7-I/O XTL1(OUT)-BCLKIN-I/O D6-I/O I/O* I/O* D5-I/O CS0-I/O I/O* I/O* D4-I/O D3-I/O CS1-I/O I/O* I/O* D2-I/O Number XC3042 XC3064 I/O* I/O* D1-I/O RDY/BUSY-RCLK-I/O D0-DIN-I/O DOUT-I/O CCLK A0-WSI/O A1-CS2-I/O A2-I/O A3-I/O A15-I/O A4-I/O I/O* I/O* A14-I/O A5-I/O A13-I/O A6-I/O I/O* I/O* A12-I/O A7-I/O A11-I/O A8-I/O A10-I/O A9-I/O
Unprogrammed IOBs have default pull-up. This prevents undefined level unbonded unused IOBs. Programmed outputs default slew-rate limited. Indicates unconnected package pins (24) XC3042.
2-145
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
XC3000 Families160-Pin PQFP Pinouts
XC3000, XC3000A, XC3000L, XC3100 XC3100A families have identical pinouts
PQFP Number XC3064, XC3090, XC3195 I/O* I/O* M1-RDATA PQFP Number XC3064, XC3090, XC3195 M0-RTRIG M2-I/O HDC-I/O LDC-I/O I/O* INIT-I/O XTL2-I/O RESET DONE/PG
PQFP Number
XC3064, XC3090, XC3195 D7-I/O XTL1-I/O-BCLKIN D6-I/O D5-I/O CS0-I/O D4-I/O D3-I/O CS1-I/O D2-I/O D1-I/O RDY/BUSY-RCLK-I/O D0-DIN-I/O DOUT-I/O
PQFP Number
XC3064, XC3090, XC3195 CCLK A0-WS-I/O A1-CS2-I/O A2-I/O A3-I/O A15-I/O A4-I/O A14-I/O A5-I/O A13-I/O A6-I/O A12-I/O A7-I/O A11-I/O A8-I/O A10-I/O A9-I/O PWRDWN TCLKIN-I/O
Unprogrammed IOBs have default pull-up. This prevents undefined level unbonded unused IOBs. Programmed IOBs default slew-rate limited. *Indicates unconnected package pins (18) XC3064.
2-146
XC3000 Families 175-Pin Ceramic Plastic Pinouts
XC3000, XC3000A, XC3000L, XC3100 XC3100A families have identical pinouts
Number XC3090, XC3195 PWRDN TCLKIN-I/O Number XC3090, XC3195 M1-RDATA Number XC3090, XC3195 DONE-PG D7-I/O XTL1(OUT)-BCLKIN-I/O D6-I/O D5-I/O CS0-I/O D4-I/O Number XC3090, XC3195 D0-DIN-I/O DOUT-I/O CCLK
M0-RTRIG
M2-I/O HDC-I/O LDC-I/O INIT-I/O
A0-WS-I/O A1-CS2-I/O A2-I/O A3-I/O A15-I/O A4-I/O A14-I/O A5-I/O
XTL2(IN)-I/O
D3-I/O CS1-I/O D2-I/O D1-I/O RDY/BUSY-RCLK-I/O
A13-I/O A6-I/O A12-I/O A7-I/O A11-I/O A8-I/O A10-I/O A9-I/O
RESET
Unprogrammed IOBs have default pull-up. This prevents undefined level unbonded unused IOBs. Programmed outputs default slew-rate limited. Pins A15, A16, connected. does exist.
2-147
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
XC3090 176-Pin TQFP Pinouts
XC3000, XC3000A, XC3000L, XC3100 XC3100A families have identical pinouts
Number Number Number Number
XC3090 PWRDWN TCLKIN-I/O
XC3090 M1-RDATA M0-RTRIG M2-I/O HDC-I/O LDC-I/O INIT-I/O XTAL2(IN)-I/O RESET
XC3090 DONE-PG D7-I/O
XTAL1(OUT)-BCLKIN-I/O
XC3090 A0-WS-I/O A1-CS2-I/O A2-I/O A3-I/O A15-I/O A4-I/O A14-I/O A5-I/O A13-I/O A6-I/O A12-I/O A7-I/O A11-I/O A8-I/O A10-I/O A9-I/O
D6-I/O D5-I/O CS0-I/O D4-I/O D3-I/O CS1-I/O D2-I/O D1-I/O
RDY/BUSY-RCLK-I/O
D0-DIN-I/O DOUT-I/O CCLK
Unprogrammed IOBs have default pull-up. This prevents undefined level unbonded unused IOBs. Programmed outputs default slew-rate limited.
2-148
XC3090 208-Pin PQFP Pinouts
XC3000, XC3000A, XC3000L, XC3100 XC3100A families have identical pinouts
Number Number Number Number
XC3090 PWRDWN TCLKIN-I/O M1-RDATA M0-RTRIG
XC3090 M2-I/O HDC-I/O LDC-I/O INIT-I/O XTL2-I/O RESET
XC3090 D7-I/O XTL1-BCLKIN-I/O D6-I/O D5-I/O CS0-I/O D4-I/O D3-I/O CS1-I/O D2-I/O D1-I/O RDY/BUSY-RCLK-I/O DIN-D0-I/O DOUT-I/O CCLK
XC3090 WS-A0-I/O CS2-A1-I/O A2-I/O A3-I/O A15-I/O A4-I/O A14-I/O A5-I/O A13-I/O A6-I/O A12-I/O A7-I/O A11-I/O A8-I/O A10-I/O A9-I/O
Unprogrammed IOBs have default pull-up. This prevents undefined level unbonded unused IOBs. Programmed outputs default slew-rate limited. PQ208, XC3090 XC3195 have different pinouts.
2-149
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
XC3195 PQ208 PG223 Pinouts
Description A9-I/O A10-I/O A8-I/O A11-I/O A7-I/O A12-I/O A6-I/O A13-I/O A5-I/O A14-I/O A4-I/O A15-I/O A3-I/O A2-I/O A1-CS2-I/O A0-WS-I/O CCLK DOUT-I/O
PG223
PQ208
Description INIT LDC-I/O HDC-I/O M2-I/O M0-RTIG M1/RDATA
PG223
PQ208
Description TCLKIN-I/O PWRDN
PG223
PQ208
Unprogrammed IOBs have default pull-up. This prevents undefined level unbonded unused IOBs. Programmed outputs default slew-rate limited. PQ208 package, pins 142, 143, connected. PQ208, XC3090 XC3195 have different pinouts.
2-150
XC3000 Component Availability
PINS TYPE
PLAST. PLCC
PLAST. VQFP
PLAST. PLCC
PLAST. PLCC CERAM PLAST. PQFP
PLAST. TQFP
TOPPLAST. BRAZED PLAST. CERAM. PLAST. VQFP CQFP TQFP
TOPPLAST. BRAZED PLAST. CERAM. PLAST. PQFP CQFP TQFP
PLAST. CERAM. PQFP
CODE
PC44 -100 -125 -100 -125 -100 -125 -100 -125 -100 -125
VQ64
PC68
PC84
PG84 PQ100 TQ100 VQ100 CB100 PP132 PG132 TQ144 PQ160 CB164 PP175 PG175 TQ176 PQ208 PG223
CIMB CIMB CIMB CIMB CIMB CIMB CIMB CIMB CIMB CIMB CIMB CIMB CIMB CIMB
XC3020
XC3030
XC3042
XC3064
XC3090
XC3020A XC3030A XC3042A XC3064A XC3090A XC3020L XC3030L XC3042L XC3064L XC3090L
XC3120A
XC3130A
XC3142A
XC3164A
XC3190A
XC3195A
Commercial +85° Industrial -40° +100° Parentheses indicate future product plans
Temp -55° +125°
MIL-STD-883C Class
2-151
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
detailed description device architecture, pages 2-105 through 2-123. detailed description configuration modes their timing, pages 2-124 through 2-132. detailed lists package pin-outs, pages 2-140 through 2-150. package physical dimensions thermal data, Section
Ordering Information
Example: Device Type Block Delay
XC3130A- PC44C
Temperature Range Number Pins Package Type
XC3000, XC3000A, XC3000L, XC3100, XC3100A
features original XC3000 family described preceding pages. XC3100A functionally identical with XC3000, offers substantially faster performance. There also additional high-end family member, XC3195A. XC3000L uses supply voltage lower power-down current. XC3000A, XC3000L XC3100A families offer identical enhanced functionality. They thus supersets XC3000 familiy. Additional routing resources provide improved performance higher density. There direct connection from each output data input nearest TBUF. This speeds path preserves general routing resources that used other purposes. clock enable TBUF output enable driven different vertical Longlines. XC3000/3100 devices, clock enable signal adjacent TBUF output enable signal both driven only from same vertical Longline. That makes these functions mutually exclusive, thus creates placement constraints. Using separate Longlines these functions leads improved density performance, especially bus-oriented applications. Bitstream error checking protects against erroneous configuration. Each Xilinx FPGA bitstream consists 40-bit preamble, followed device-specific number data frames. number bits frame also device-specific; however, each frame ends with three stop bits (111) followed start next frame (0). devices XC3000 families start reading frame when they find first after previous frame. XC3000/XC3100 devices check correct stop bits, XC3000A/XC3100A XC3000L devices check that last three bits frame actually 111. Under normal circumstances, these FPGAs behave same way; however, bitstream corrupted,
XC3000/XC3100 device will always start frame soon finds first after previous frame, even data completely wrong out-of-sync. Given sufficient zeros data stream, device will also Done, with incorrect configuration possibility internal contention. XC3000A/XC3100A/XC3000L device starts frame only three preceding bits ones. this check fails, pulls INIT stops internal configuration, although Master CCLK keeps running. user must then start configuration applying level RESET. This simple check does protect against random errors, offers almost percent protection against erroneous configuration files, defective configuration data sources, synchronization errors between configuration source FPGA, PC-board level defects, such broken lines solder-bridges. separate modification slows down RESET input before configuration using two-stage shift register driven from internal clock. tolerates submicrosecond High spikes RESET before configuration. XC3000 master connected like XC4000 master, with RESET input used instead INIT. XC3000, INIT output only). Soft start-up. After configuration, outputs device daisy-chain become active simultaneously, result same CCLK edge. original XC3000/ 3100 devices, each output becomes active either fast slew-rate limited mode, depending configured. This lead large ground-bounce signals. XC3000A/XC3000L/XC31000A devices, outputs become active first slew-rate limited mode, reducing ground bounce. After this soft start-up, each individual output slew rate again controlled respective configuration bit. XC3000, XC3000L, ZC3100A fully supported XACT Version 5.0, later, development system. XACT provides many advanced features available with XC3000 software such timing-driven place route (XACT-PerformanceTM)and X-BLOXmodule generator.
2-152
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