Dual Wideband, High Output Current Operational Amplifier with Current
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OPA2674
Dual Wideband, High Output Current Operational Amplifier with Current Limit
WIDEBAND +12V OPERATION: 220MHz UNITY-GAIN STABLE: 250MHz HIGH OUTPUT CURRENT: 500mA OUTPUT VOLTAGE SWING: 10VPP HIGH SLEW RATE: 2000V/µs SUPPLY CURRENT: 18mA FLEXIBLE POWER CONTROL: SO-14 Only OUTPUT CURRENT LIMIT (±800mA)
DESCRIPTION
OPA2674 provides high output current distortion required emerging xDSL Power Line Modem driver applications. Operating single +12V supply, OPA2674 consumes 9mA/ch quiescent current deliver very high 500mA output current. This output current supports even most demanding ADSL requirements with 380mA minimum output current (+25°C minimum value) with harmonic distortion. Differential driver applications deliver -85dBc distortion peak upstream power levels full rate ADSL. high 200MHz bandwidth also supports most demanding VDSL line driver requirements. Power control features included SO-14 package version allow system power minimized. logic control lines allow four quiescent power settings. These include full power, power cutback short loops, idle state signal transmission line match maintenance, shutdown power with high impedance output. Specified supplies support +12V operation), OPA2674 will also support single dual supply. Video applications will benefit from very high output current drive parallel video loads (15) with 0.1%/0.1° dG/dP nonlinearity.
APPLICATIONS
POWER LINE MODEM xDSL LINE DRIVERS CABLE MODEM DRIVERS MATCHED CHANNEL AMPLIFIERS BROADBAND VIDEO LINE DRIVERS LINE DRIVERS HIGH LOAD DRIVER
OPA2674 RELATED PRODUCTS
SINGLES OPA691 DUALS OPA2691 THS6042 OPA2677 TRIPLES OPA3691 NOTES Single +12V Capable ±15V Capable Single +12V Capable
+12V
17.4 1:1.7
Output
+6.0V 2VPP
17.7VPP 15VPP Twisted Pair 82.5 17.4
Single- Supply Upstream Driver
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. trademarks property their respective owners.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2003, Texas Instruments Incorporated
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OPA2674
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ORDERING INFORMATION
PRODUCT OPA2674 PACKAGE-LEAD SO-8 PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE -40°C +85°C PACKAGE MARKING OPA2674ID ORDERING NUMBER OPA2674ID OPA2674IDR OPA2674I-14D OPA2674I-14DR TRANSPORT MEDIA, QUANTITY Rails, Tape Reel, 2500 Rails, Tape Reel, 2500
OPA2674
SO-14
-40°C +85°C
OPA2674I-14D
most current specification package information, refer site www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Power Supply ±6.5VDC Internal Power Dissipation Thermal Analysis Differential Input Voltage ±1.2V Input Common-Mode Voltage Range Storage Temperature Range: -14D -40°C +125°C Lead Temperature (soldering, 10s) +300°C Junction Temperature (TJ) +150°C Rating Human Body Model (HBM)(2) 2000V Charge Device Model (CDM) 1000V Machine Model (MM) 100V Stresses above these ratings cause permanent damage. Exposure absolute maximum conditions extended periods degrade device reliability. These stress ratings only, functional operation device these other conditions beyond those specified supported. Pins SO-8 package, pins SO-14 package 500V HBM.
This integrated circuit damaged ESD. Texas Instruments recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
CONFIGURATIONS
View SO-8 View OPA2674I- OPA2674ID Power Control Connection SO-14
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OPA2674
ELECTRICAL CHARACTERISTICS:
Boldface limits tested +25°C.
+25°C, (full power: SO-14 only), 402, 100, unless otherwise noted. Figure performance only.
OPA2674ID, OPA2674I-14D PARAMETER Performance (see Figure Small-Signal Bandwidth 0.5VPP) TEST CONDITIONS 0.5VPP 5VPP step step 5MHz, 2VPP 1MHz 1MHz 1MHz NTSC, NTSC, 37.5 NTSC, NTSC, 37.5 5MHz, Input Referred +25°C 2000 0.03 0.05 0.01 0.04 ±4.5 ±5.1 ±5.0 ±4.8 ±500 ±800 0.01 ±500 ±450 ±100 +25°C(1) MIN/MAX OVER TEMPERATURE +70°C(2) -40°C +85°C(2) UNITS V/µs nV/Hz pA/Hz pA/Hz µV/°C nA/°C nA/°C MIN/ TEST LEVEL
1500
1450
1400
Peaking Gain Bandwidth 0.1dB Gain Flatness Large-Signal Bandwidth Slew Rate Rise Time Fall Time Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Noninverting Input Current Noise Inverting Input Current Noise NTSC Differential Gain NTCS Differential Phase Channel-to-Channel Crosstalk Performance(4) Open-Loop Transimpedance Gain Input Offset Voltage Offset Voltage Drift Noninverting Input Bias Current Noninverting Input Bias Current Drift Inverting Input Bias Current Inverting Input Bias Current Drift Input(4) Common-Mode Input Range (CMIR)(5) Common-Mode Rejection Ratio (CMRR) Noninverting Input Impedance Minimum Inverting Input Resistance Maximum Inverting Input Resistance Output Output Voltage Swing
±4.5 ±100 ±4.1 ±4.9 ±4.8 ±380
±100 ±4.0
±5.3 ±150 ±4.0
Input Referred Open-Loop Open-Loop Load 100kHz
±4.8 ±4.7 ±350
±4.7 ±4.5 ±320
Current Output Short-Circuit Current Closed-Loop Output Impedance Output (SO-14 Only) Current Output Full Power Current Output Power Cutback Current Output Idle Power
±380 ±350
±350 ±320
±320 ±300
Junction temperature ambient +25°C specifications. Junction temperature ambient temperature limit; junction temperature ambient +23°C high temperature limit over temperature specifications. Test levels: 100% tested +25°C. Over temperature limits characterization simulation. Limits characterization simulation. Typical value only information. Current considered positive node. input common-mode voltage. Tested below minimum CMRR specification CMIR limits.
OPA2674
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ELECTRICAL CHARACTERISTICS: (continued)
Boldface limits tested +25°C.
+25°C, (full power: SO-14 only), 402, 100, unless otherwise noted. Figure performance only.
OPA2674ID, OPA2674I-14D PARAMETER Power Supply Specified Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power-Supply Rejection Ratio (PSRR) Power Supply (SO-14 Only) Maximum Logic Minimum Logic Logic Input Current Supply Current Full Power Supply Current Power Cutback Supply Current Idle Power Supply Current Shutdown Output Impedance Idle Power Output Impedance Shutdown Supply Current Step Time Output Switching Glitch Shutdown Isolation Thermal Characteristics Specification: I-14D Thermal Resistance, SO-8 I-14D SO-14 Junction-to-Ambient °C/W °C/W Each Line (logic levels) (logic levels) (logic levels) (logic levels) 1MHz Change Inputs 1MHz, 18.0 13.3 18.6 14.2 18.8 14.4 19.2 14.8 100kHz, Input Referred ±6.3 18.6 17.4 ±6.3 18.8 16.5 ±6.3 19.2 16.0 TEST CONDITIONS +25°C +25°C(1) MIN/MAX OVER TEMPERATURE +70°C(2) -40°C +85°C(2) UNITS MIN/ TEST LEVEL
Junction temperature ambient +25°C specifications. Junction temperature ambient temperature limit; junction temperature ambient +23°C high temperature limit over temperature specifications. Test levels: 100% tested +25°C. Over temperature limits characterization simulation. Limits characterization simulation. Typical value only information. Current considered positive node. input common-mode voltage. Tested below minimum CMRR specification CMIR limits.
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OPA2674
ELECTRICAL CHARACTERISTICS:
Boldface limits tested +25°C.
+25°C, (Full Power: SO-14 only), 453, 100, unless otherwise noted. Figure performance only.
OPA2674ID, OPA2674I-14D PARAMETER Performance (see Figure Small-Signal Bandwidth 0.5VPP) 0.5VPP 5VPP Step Step 5MHz, 2VPP 1MHz 1MHz 1MHz 5MHz, Input Referred V/µs nV/Hz pA/Hz pA/Hz TEST CONDITIONS +25°C +25°C(1) MIN/MAX OVER TEMPERATURE +70°C(2) -40°C +85°C(2) UNITS MIN/ TEST LEVEL
Peaking Gain Bandwidth 0.1dB Gain Flatness Large-Signal Bandwidth Slew Rate Rise Time Fall Time Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Noninverting Input Current Noise Inverting Input Current Noise Channel-to-Channel Crosstalk Performance(4) Open-Loop Transimpedance Gain Input Offset Voltage Offset Voltage Drift Noninverting Input Bias Current Noninverting Input Bias Current Drift Inverting Input Bias Current Inverting Input Bias Current Drift Input Most Positive Input Voltage(5) Most Negative Input Voltage(5) Common-Mode Rejection Ratio (CMRR) Noninverting Input Impedance Minimum Inverting Input Resistance Maximum Inverting Input Resistance Output Most Positive Output Voltage Most Negative Output Voltage Current Output Closed-Loop Output Impedance Output (SO-14 Only) Current Output Full Power Current Output Power Cutback Current Output Idle Power
±0.8
±3.5 ±100
±4.0 ±100
±4.3 ±150
µV/°C nA/°C nA/°C
2.5V, Input Referred Open-Loop Open-Loop Load Load 100kHz
±260 0.02 ±260 ±200
±200
±180
±160
±200 ±160
±180 ±140
±160 ±120
Junction temperature ambient +25°C specifications. Junction temperature ambient temperature limit; junction temperature ambient +23°C high temperature limit over temperature specifications. Test levels: 100% tested +25°C. Over temperature limits characterization simulation. Limits characterization simulation. Typical value only information. Current considered positive node. input common-mode voltage. Tested below minimum CMRR min/max input ranges.
OPA2674
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ELECTRICAL CHARACTERISTICS: +5V(continued)
Boldface limits tested +25°C.
+25°C, (Full Power: SO-14 only), 453, 100, unless otherwise noted. Figure performance only.
OPA2674ID, OPA2674I-14D PARAMETER Power Supply (Single-Supply Mode) Specified Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power-Supply Rejection Ratio (PSRR) Power Control (SO-14 Only) Maximum Logic Minimum Logic Logic Input Current Supply Current Full Power Supply Current Power Cutback Supply Current Idle Power Supply Current Shutdown Output Impedance Idle Power Output Impedance Shutdown Supply Current Step Time Output Switching Glitch Shutdown Isolation Thermal Characteristics Specification: I-14D Thermal Resistance, SO-8 I-14D SO-14 Junction-to-Ambient °C/W °C/W Change Inputs 1MHz, Each Line (logic levels) (logic levels) (logic levels) (logic levels) 1MHz 13.8 10.2 14.8 10.8 15.2 11.1 15.6 11.4 100kHz, Input Referred 13.6 13.6 12.6 14.8 12.6 15.2 11.7 12.6 15.6 11.4 TEST CONDITIONS +25°C +25°C(1) MIN/MAX OVER TEMPERATURE +70°C(2) -40°C +85°C(2) UNITS MIN/ TEST LEVEL
Junction temperature ambient +25°C specifications. Junction temperature ambient temperature limit; junction temperature ambient +23°C high temperature limit over temperature specifications. Test levels: 100% tested +25°C. Over temperature limits characterization simulation. Limits characterization simulation. Typical value only information. Current considered positive node. input common-mode voltage. Tested below minimum CMRR min/max input ranges.
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OPA2674
TYPICAL CHARACTERISTICS:
+25°C, 402, 100, unless otherwise noted.
NONINVERTING SMALL- SIGNAL FREQUENCY RESPONSE OVER GAIN 0.5VPP Normalized Gain (dB) Figure Normalized Gain (dB)
INVERTING SMALL- SIGNAL FREQUENCY RESPONSE OVER GAIN 0.5VPP
Figure Frequency (MHz)
Frequency (MHz)
NONINVERTING SMALL- SIGNAL FREQUENCY RESPONSE OVER POWER SETTINGS Gain (dB) Full Power Figure Idle Power Power Cutback Gain (dB) 0.5VPP
INVERTING SMALL- SIGNAL FREQUENCY RESPONSE OVER POWER SETTINGS 0.5VPP
Full Power Figure Idle Power
Power Cutback
Frequency (MHz)
Frequency (MHz)
NONINVERTING LARGE- SIGNAL FREQUENCY RESPONSE Gain (dB) 10VPP Figure 8VPP 2VPP 1VPP Gain (dB) Frequency (MHz) Figure
INVERTING LARGE- SIGNAL FREQUENCY RESPONSE 1VPP
5VPP 10VPP 8VPP
Frequency (MHz)
OPA2674
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TYPICAL CHARACTERISTICS: (continued)
+25°C, 402, 100, unless otherwise noted.
NONINVERTING PULSE RESPONSE 4VPP Large Signal 200mVPP Small Signal Right Scale
NONINVERTING PULSE RESPONSE 4VPP Large Signal 200mVPP Small Signal Right Scale
Output Voltage (100mV/div)
Figure Time (5ns/div)
Figure Time (5ns/div)
Harmonic Distortion (dBc) -100 -105
HARMONIC DISTORTION FREQUENCY 2VPP
HARMONIC DISTORTION OUTPUT VOLTAGE 5MHz 2nd- Harmonic
Harmonic Distortion (dBc)
2nd- Harmonic
3rd- Harmonic Single Channel, Figure -100
3rd- Harmonic Single Channel, Figure Frequency (MHz)
Output Voltage (VPP)
HARMONIC DISTORTION NONINVERTING GAIN 2VPP 5MHz
HARMONIC DISTORTION INVERTING GAIN 2VPP 5MHz
Harmonic Distortion (dBc)
2nd- Harmonic
Harmonic Distortion (dBc)
2nd- Harmonic
3rd- Harmonic
3rd- Harmonic Single Channel, Figure Gain Magnitude (V/V)
Single Channel, Figure Gain Magnitude (-V/V)
Output Voltage (100mV/div)
Left Scale Output Voltage (1V/div)
Left Scale Output Voltage (1V/div)
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OPA2674
TYPICAL CHARACTERISTICS: (continued)
+25°C, 402, 100, unless otherwise noted.
HARMONIC DISTORTION LOAD RESISTANCE Harmonic Distortion (dBc) -100 Single Channel, Figure Load Resistance 3rd- Harmonic 2nd- Harmonic 2VPP 5MHz 3rd- Order Spurious Level (dBc)
TONE, 3rd- ORDER SPURIOUS LEVEL Below Carriers 20MHz 10MHz
5MHz
1MHz
Power Matched 50Load, Figure -100 Single- Tone Load Power (dBm)
MAXIMUM OUTPUT SWING LOAD RESISTANCE Output Voltage Load Resistance -600
OUTPUT VOLTAGE CURRENT LIMITATIONS
terna ower ingle nnel
ternal ower Single
-400
-200
(mA)
INPUT VOLTAGE CURRENT NOISE DENSITY Inverting Current oise Voltage Noise (nV/Hz) Current Noise (pA/Hz) 24pA/ Crosstalk, Input Referred (dB)
-100 -105 -110
CHANNEL- CHANNEL CROSSTALK Input Referred
Noninverting Current Noise 16pA/
Voltage Noise 100k
2.0nV/
Frequency (Hz)
100M
Frequency (Hz)
OPA2674
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TYPICAL CHARACTERISTICS: (continued)
+25°C, 402, 100, unless otherwise noted.
RECOMMENDED CAPACITIVE LOAD Normalized Gain Capacitive Load (dB) Capacitive Load (pF)
FREQUENCY RESPONSE CAPACITIVE LOAD 10pF
100pF
22pF
OPA2674
47pF
1k(1)
NOTE: optional.
100M
Frequency (Hz)
CMRR PSRR FREQUENCY Power- Supply Rejection Ratio (dB) Common- Mode Rejection Ratio (dB) CMRR Transimpedance Gain (dB) +PSRR 100k 100M Frequency (Hz) -PSRR
OPEN- LOOP TRANSIMPEDANCE GAIN PHASE Gain Phase Transimpedance Phase -135 -180 -225 -270 100k 100M Frequency (Hz)
CLOSED- LOOP OUTPUT IMPEDANCE FREQUENCY 0.10 0.09 Output Resistance dG/dP (%/_) 0.08 0.07 Idle Power 0.06 0.05 0.04 0.03 0.01 Full Power Power Cutback 0.001 100k Frequency (Hz) 100M 0.02 0.01
COMPOSITE VIDEO dG/dP Positive Video Negative Video
Negative Video
Positive Video
Number 150Loads
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OPA2674
TYPICAL CHARACTERISTICS: (continued)
+25°C, 402, 100, unless otherwise noted.
NONINVERTING OVERDRIVE RECOVERY Input Output Voltage Figure Time (25ns/div) TYPICAL DRIFT OVER TEMPERATURE Inverting Bias Current Noninverting Bias Current Output Current (mA) Output Output Voltage Input Voltage
INVERTING OVERDRIVE RECOVERY Input Output Figure Time (25ns/div) SUPPLY OUTPUT CURRENT TEMPERATURE Supply Current, Power Cutback Sinking Output Current Sourcing Output Current Supply Current, Idle Power Temperature Supply Current, Both Channels (mA) Supply Current, Full Power Input Voltage
Input Offset Voltage (mV) Input Bias Current (µA)
Input Offset Voltage
Ambient Temperature (_C) COMMON- MODE INPUT VOLTAGE RANGE OUTPUT SWING SUPPLY VOLTAGE Voltage Range (±V) Negative Output Swing
Positive Output Swing
Negative Common- Mode Input Voltage Positive Common- Mode Input Voltage Supply Voltage (±V)
OPA2674
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TYPICAL CHARACTERISTICS:
+25°C, Differential Gain 300, unless otherwise noted. Figure performance only.
DIFFERENTIAL SMALL- SIGNAL FREQUENCY RESPONSE Normalized Gain (dB) Figure Frequency (MHz) 1VPP Gain (dB)
DIFFERENTIAL LARGE- SIGNAL FREQUENCY RESPONSE 1VPP 16VPP Figure 4VPP 8VPP
Frequency (MHz)
DIFFERENTIAL DISTORTION LOAD RESISTANCE Harmonic Distortion (dB) -100 -105 -110 3rd- Harmonic 2nd- Harmonic 500kHz 4VPP
DIFFERENTIAL DISTORTION FREQUENCY
Harmonic Distortion (dB)
2nd- Harmonic -100 -110 Figure Frequency (MHz) 3rd- Harmonic
Figure Load Resistance
DIFFERENTIAL DISTORTION OUTPUT VOLTAGE 3rd- Harmonic -100 Figure -110 Differential Output Voltage (VPP) 500kHz Power (dBm) 2nd- Harmonic -100
ADSL MULTITONE POWER RATIO (Upstream)
Harmonic Distortion (dBc)
Figure
Frequency (kHz)
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OPA2674
TYPICAL CHARACTERISTICS:
+25°C, 453, 100, unless otherwise noted.
NONINVERTING SMALL- SIGNAL FREQUENCY RESPONSE Normalized Gain (dB) Figure Normalized Gain (dB) Figure
INVERTING SMALL- SIGNAL FREQUENCY RESPONSE
Frequency (MHz)
Frequency (MHz)
NONINVERTING LARGE- SIGNAL FREQUENCY RESPONSE Gain (dB) Gain (dB) 3VPP Figure 1VPP 2VPP VS/2
INVERTING LARGE- SIGNAL FREQUENCY RESPONSE VS/2
3VPP 2VPP
Figure
1VPP
Frequency (MHz)
Frequency (MHz)
NONINVERTING PULSE RESPONSE
INVERTING PULSE RESPONSE
Left Scale Input Voltage (100mV/div) Output Voltage (0.5V/div) Output Voltage (0.5V/div) 2VPP Large Signal Right Scale 200mVPP Small Signal
Left Scale Input Voltage (100mV/div) 2VPP Large Signal Right Scale 200mVPP Small Signal
100to VS/2 Time (5ns/div)
Figure
100to VS/2 Time (5ns/div)
Figure
OPA2674
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TYPICAL CHARACTERISTICS: (continued)
+25°C, 453, 100, unless otherwise noted.
Harmonic Distortion (dBc)
HARMONIC DISTORTION FREQUENCY 2VPP VS/2 2nd- Harmonic
HARMONIC DISTORTION OUTPUT VOLTAGE 5MHz VS/2
Harmonic Distortion (dBc)
2nd- Harmonic 3rd- Harmonic Single Channel, Figure Output Voltage (VPP)
3rd- Harmonic Single Channel, Figure Frequency (MHz)
HARMONIC DISTORTION NONINVERTING GAIN 2VPP 5MHz VS/2
HARMONIC DISTORTION INVERTING GAIN 2VPP 5MHz VS/2 2nd- Harmonic
Harmonic Distortion (dBc)
2nd- Harmonic
Harmonic Distortion (dBc)
3rd- Harmonic
3rd- Harmonic
Single Channel, Figure Gain Magnitude (V/V)
Single Channel, Figure Gain (-V/V)
Harmonic Distortion (dBc)
HARMONIC DISTORTION LOAD RESISTANCE 2VPP 5MHz 100to VS/2
TONE, 3rd- ORDER SPURIOUS LEVEL 3rd- Order Spurious Level (dBc) Single Channel. Figure Power matched load. 10MHz 5MHz 20MHz
2nd- Harmonic
3rd- Harmonic
1MHz
Single Channel, Figure Load Resistance
Single- Tone Load Power (dBm)
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OPA2674
TYPICAL CHARACTERISTICS:
+25°C, Differential Gain 316, unless otherwise noted.
DIFFERENTIAL PERFORMANCE TEST CIRCUIT
DIFFERENTIAL SMALL- SIGNAL FREQUENCY RESPONSE Normalized Gain (dB)
GD=1+
Frequency (MHz)
DIFFERENTIAL LARGE- SIGNAL FREQUENCY RESPONSE Harmonic Distortion (dBc) Gain (dB) Frequency (MHz) 1VPP 2VPP 4VPP 5VPP
-100
HARMONIC DISTORTION LOAD RESISTANCE 500kHz 4VPP
2nd- Harmonic
3rd- Harmonic
Load Resistance
DIFFERENTIAL DISTORTION FREQUENCY 3rd- Harmonic -100 Frequency (MHz) Harmonic Distortion (dB)
HARMONIC DISTORTION OUTPUT VOLTAGE 500kHz
Harmonic Distortion (dBc)
2nd- Harmonic
2nd- Harmonic
3rd- Harmonic -100 Output Voltage (VPP)
OPA2674
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APPLICATION INFORMATION
WIDEBAND CURRENT-FEEDBACK OPERATION
OPA2674 gives exceptional performance wideband current-feedback with highly linear, high-power output stage. Requiring only 9mA/ch quiescent current, OPA2674 swings within either supply rail delivers excess 380mA room temperature. This output headroom requirement, along with supply voltage independent biasing, gives remarkable single (+5V) supply operation. OPA2674 delivers greater than 150MHz bandwidth driving 2VPP output into single supply. Previous boosted output stage amplifiers typically suffer from very poor crossover distortion output current goes through zero. OPA2674 achieves comparable power gain with much better linearity. primary advantage current-feedback over voltage-feedback that performance (bandwidth distortion) relatively independent signal gain. Figure shows DC-coupled, gain dual power-supply circuit configuration used basis Electrical Typical Characteristics. test purposes, input impedance with resistor ground output impedance with series output resistor. Voltage swings reported electrical characteristics taken directly input output pins whereas load powers (dBm) defined matched load. circuit Figure total effective load
Figure shows DC-coupled, bipolar supply circuit inverting gain configuration used basis Electrical Typical Characteristics. design considerations inverting configuration developed Inverting Amplifier Operation discussion.
Power- supply decoupling shown. 50Load
OPA2674
Source
Figure DC-Coupled, Bipolar Supply, Specification Test Circuit
Figure shows coupled, gain single-supply circuit configuration used basis Electrical Typical Characteristics. Though rail-to-rail design, OPA2674 requires minimal input output voltage headroom compared other wideband current-feedback amps. will deliver 3VPP output swing single supply with greater than 100MHz bandwidth. requirement broadband singlesupply operation maintain input output signal swings within usable voltage ranges both input output. circuit Figure establishes input midpoint bias using simple resistive divider from supply (two resistors). input signal then AC-coupled into this midpoint voltage bias. input voltage swing within 1.3V either supply pin, giving 2.4VPP input signal range centered between supply pins. input impedance matching resistor (57.6) used testing adjusted give input match when parallel combination biasing divider network included. gain resistor (RG) AC-coupled, giving circuit gain +1which puts input bias voltage (2.5V) output well. feedback resistor value adjusted from bipolar supply condition re-optimize flat frequency response +5V, gain operation. Again, single supply, output voltage swing within either supply while delivering more than 200mA output current. demanding load midpoint bias used this characterization circuit. output stage used OPA2674 deliver large bipolar output currents into this midpoint load with minimal crossover distortion, shown supply, harmonic distortion plots Typical Characteristics charts.
0.1µF
6.8µF
Source Load
OPA2674
6.8µF 0.1µF
Figure DC-Coupled, Bipolar Supply, Specification Test Circuit
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OPA2674
reduction even-order harmonic distortion products. Another important advantage ADSL that each amplifier needs only half total output swing required drive load.
0.1µF 6.8µF +12V VS/2 0.1µF
A2674
0.1µF
57.6
OPA2674
128mA 17.4
82.5
1:1.7
0.1µF
2VPP Assumed
0.1µF
17.7VPP 17.4
ZLine
128mA
A2674
Figure AC-Coupled, Single-Supply, Specification Test Circuit Figure Single-Supply ADSL Upstream Driver
last configuration used basis Electrical Typical Characteristics shown Figure Design considerations this inverting, bipolar supply configuration covered either single-supply configuration shown Figure Inverting Amplifier Operation discussion.
analog front-end (AFE) signal AC-coupled driver noninverting input each amplifier biased mid-supply voltage this case, +6V). Furthermore, providing proper biasing amplifier, this scheme also provides high-pass filtering with corner frequency here 5kHz. upstream signal bandwidth starts 26kHz, this high-pass filter does generate problems advantage filtering unwanted lower frequencies. input signal amplified with gain following equation:
0.1µF
6.8µF
OPA2674
VS/2
0.1µF 88.7
With 82.5, gain this differential amplifier 8.85. This gain boosts signal, assumed maximum 2VPP, maximum 17.7VPP. Refer Setting Resistor Values Optimize Bandwidth section discussion which feedback resistor value choose. back-termination resistors (17.4 each) added each input transformer make impedance modem match impedance phone line, also provide means detecting received signal receiver. value these resistors (RM) function line impedance transformer turns ratio (n), given following equation:
Figure AC-Coupled, Single-Supply, Specification Test Circuit
SINGLE-SUPPLY ADSL UPSTREAM DRIVER
Figure shows single-supply ADSL upstream driver. dual OPA2674 configured differential gain stage provide signal drive primary transformer (here, step-up transformer with turns ratio 1:1.7). main advantage this configuration
LINE
OPA2674
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OPA2674 HDSL2 UPSTREAM DRIVER
Figure shows HDSL2 implementation singlesupply driver.
Consolidating Equations through allows required peak-to-peak voltage load function crest factor, load impedance, power load expressed. Thus:
+12V
OPA2674
(1mW)
This VLPP usually computed nominal line impedance taken fixed design target.
185mA 11.5 1:2.4
0.1µF
2VPP Assumed
0.1µF
82.5
17.7VPP 11.5
ZLine
next step driver compute individual amplifier output voltage currents function line transformer turns ratio. turns ratio changes, minimum allowed supply voltage also changes. peak current amplifier given
185mA
OPA2674
With VLPP defined Equation defined Equation peak current computed Figure noting that total load that peak current half peak-to-peak calculated using VLPP.
Figure HDSL2 Upstream Driver
designs differ values matching impedance, load impedance, ratio turns transformers. these differences reflected higher peak current thus, higher maximum power dissipation output driver.
2VLPP VLPP
VLPP
LINE DRIVER HEADROOM MODEL
first step driver design compute peak-to-peak output voltage from target specifications. This done using following equations:
Figure Driver Peak Output Model
With required output voltage current versus turns ratio set, output stage headroom model will allow required supply voltage versus turns ratio developed. headroom model (see Figure described with following equations: First, available output voltage each amplifier:
VRMS (1mW)
With power VRMS voltage load, load impedance, this gives:
(1mW)
CrestFactor
(10)
second, required single-supply voltage:
with peak voltage load Crest Factor;
VOPP
VRMS
with VLPP: peak-to-peak voltage load.
minimum supply voltage power load requirement given Equation
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OPA2674
SBOS270 AUGUST 2003 +VCC
output stages used drive load Figure seen H-Bridge Figure average current drawn from supply into this H-Bridge load will peak current load given Equation divided crest factor (CF) xDSL modulation. This total power from supply then reduced power leave power dissipated internal drivers four output stage transistors. That power simply target line power used Equation plus power lost matching elements (RM). examples here, perfect match targeted giving same power matching elements load. output stage power then Equation
(11)
total amplifier power then:
Figure Line Driver Headroom Model
Table gives both +12V operation OPA2674.
(12)
Table Line Driver Headroom Model Values
+12V 0.9V 0.9V 0.8V 0.9V
ADSL upstream driver design Figure peak current 128mA signal that requires crest factor 5.33 with target line power 13dBm into (20mW). With typical quiescent current 18mA nominal supply voltage +12V, total internal power dissipation solution Figure will
(13)
PTOT 18mA(12V) 128mA (12V) 2(20mW) 464mW 5.33
TOTAL DRIVER POWER xDSL APPLICATIONS
total internal power dissipation OPA2674 xDSL line driver application will quiescent power output stage power. OPA2674 holds relatively constant quiescent current versus supply voltage-giving power contribution that simply quiescent current times supply voltage used (the supply voltage will greater than solution given Equation 10). total output stage power computed with reference Figure
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Several boards available assist initial evaluation circuit performance using OPA2674 package styles. These available, free, unpopulated boards delivered with descriptive documentation. Table shows summary information these boards.
Table Demo Board Availability
PRODUCT PACKAGE SO-8 SO-14 DEMO BOARD NUMBER DEM-OPA268XU DEM-OPA268XN ORDERING NUMBER SBOU003 SBOU002
+VCC IAVG
OPA2674ID OPA2674I-14D
site (www.ti.com) request either these boards.
MACROMODELS APPLICATIONS SUPPORT
Computer simulation circuit performance using SPICE often useful when analyzing performance analog circuits systems. This particularly true video amplifier circuits where parasitic capacitance
Figure Output Stage Power Model
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inductance have major effect circuit performance. SPICE model OPA2674 available through site (www.ti.com). This model does good predicting small-signal transient performance under wide variety operating conditions, does well predicting harmonic distortion dG/dP characteristics. This model does attempt distinguish between package types small-signal performance, does attempt simulate channel-tochannel coupling.
IERR feedback error current signal Z(s) frequency dependent open-loop transimpedance gain from IERR NoiseGain
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES OPTIMIZE BANDWIDTH
current-feedback such OPA2674 hold almost constant bandwidth over signal gain settings with proper adjustment external resistor values, which shown Typical Characteristics; small-signal bandwidth decreases only slightly with increasing gain. These characteristic curves also show that feedback resistor changed each gain setting. resistor values inverting side circuit current-feedback treated frequency response compensation elements, whereas ratios signal gain. Figure shows small-signal frequency response analysis circuit OPA2674.
buffer gain typically very close 1.00 normally neglected from signal gain considerations. This gain, however, sets CMRR single differential amplifier configuration. buffer gain 1.0, CMRR log(1 )dB. buffer output impedance, critical portion bandwidth control equation. OPA2674 inverting output impedance typically current-feedback senses error current inverting node opposed differential input error voltage voltage-feedback amp) passes this output through internal frequency dependent transimpedance gain. Typical Characteristics show this open-loop transimpedance response, which analogous open-loop voltage gain curve voltage-feedback amp. Developing transfer function circuit Figure gives Equation
Z(s)
Z(s)
(14)
Z(S) IERR
IERR
This written loop-gain analysis format, where errors arising from non-infinite open-loop gain shown denominator. Z(s) were infinite over frequencies, denominator Equation reduces ideal desired signal gain shown numerator achieved. fraction denominator Equation determines frequency response. Equation shows this loop-gain equation:
Z(s) LoopGain
(15)
Figure Current-Feedback Transfer Function Analysis Circuit
elements this current-feedback model are:
buffer gain from noninverting input inverting input buffer output impedance
log(RF drawn open-loop transimpedance plot, difference between would loop gain given frequency. Eventually, Z(s) rolls equal denominator Equation which point loop gain reduced (and curves have intersected). This point equality where amplifier closed-loop frequency response given Equation starts roll off, exactly analogous frequency which noise gain equals open-loop voltage gain voltage-feedback amp. difference here that total impedance denominator Equation controlled somewhat separately from desired signal gain NG). OPA2674 internally compensated give maximally flat frequency response
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OPA2674
supplies. Evaluating denominator Equation (which feedback transimpedance) gives optimal target 490. signal gain changes, contribution term feedback transimpedance changes, total held constant adjusting Equation gives approximate equation optimum over signal gain:
INVERTING AMPLIFIER OPERATION
OPA2674 general-purpose, wideband current-feedback amp, most familiar application circuits available designer. Those dual applications that require considerable flexibility feedback element (for example, integrators, transimpedance, some filters) should consider unity-gain stable, voltage-feedback amplifier such OPA2822, because feedback resistor compensation element current-feedback amp. Wideband inverting operation (and especially summing) particularly suited OPA2674. Figure shows typical inverting configuration where impedances signal gain from Figure retained inverting circuit configuration.
Power- supply decoupling shown. Load
(16)
desired signal gain increases, this equation eventually suggests negative somewhat subjective limit this adjustment also holding minimum value Lower values load both buffer stage input output stage gets lowactually decreasing bandwidth. Figure shows recommended versus both single operation. values versus gain shown here approximately equal values used generate Typical Characteristics. They differ that optimized values used Typical Characteristics also correcting board parasitic considered simplified analysis leading Equation values shown Figure give good starting point designs where bandwidth optimization desired.
Source
97.6
Feedback Resistor
Figure Inverting Gain with Impedance Matching
Noise Gain
Figure Feedback Resistor Noise Gain
total impedance going into inverting input used adjust closed-loop signal bandwidth. Inserting series resistor between inverting input summing junction increases feedback impedance (the denominator Equation 15), decreasing bandwidth. internal buffer output impedance OPA2674 slightly influenced source impedance coming from noninverting input terminal. High-source resistors also have effect increasing decreasing bandwidth. those single-supply applications that develop midpoint bias noninverting input through high valued resistors, decoupling capacitor essential power-supply ripple rejection, noninverting input noise current shunting, minimize high-frequency value Figure
inverting configuration, design considerations must noted. First, gain resistor (RG) becomes part signal source input impedance. input impedance matching desired (which beneficial whenever signal coupled through cable, twisted pair, long board trace, other transmission line conductor), normally necessary additional matching resistor ground. itself, normally required input impedance since value, along with desired gain, will determine which nonoptimal from frequency response standpoint. total input impedance source becomes parallel combination second major consideration that signal source impedance becomes part noise gain equation slight effect bandwidth through Equation values shown Figure have accounted this slightly decreasing (from optimum values) reoptimize bandwidth noise gain Figure 3.98). example Figure value combines parallel with external source impedance, yielding effective driving impedance 33.5. This impedance added series
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with calculating noise gainwhich gives 3.98. This value, inverting input impedance inserted into Equation that appears Figure Note that noninverting input this bipolar supply inverting application connected directly ground. often suggested that additional resistor connected ground noninverting input achieve bias current error cancellation output. input bias currents current-feedback generally matched either magnitude polarity. Connecting resistor ground noninverting input OPA2674 circuit Figure actually provides additional gain that input bias noise currents, does decrease output error because input bias currents matched.
specifications since output stage junction temperatures will higher than minimum specified operating ambient.
DRIVING CAPACITIVE LOADS
most demanding very common load conditions capacitive loading. Often, capacitive load input analog-to-digital (A/D) converterincluding additional external capacitance that recommended improve converter linearity. high-speed, high open-loop gain amplifier like OPA2674 very susceptible decreased stability closed-loop response peaking when capacitive load placed directly output pin. When amplifier open-loop output resistance considered, this capacitive load introduces additional pole signal path that decrease phase margin. Several external solutions this problem have been suggested. When primary considerations frequency response flatness, pulse response fidelity, and/or distortion, simplest most effective solution isolate capacitive load from feedback loop inserting series isolation resistor between amplifier output capacitive load. This does eliminate pole from loop response, rather shifts adds zero higher frequency. additional zero acts cancel phase from capacitive load pole, thus increasing phase margin improving stability. Typical Characteristics show Recommended Capacitive Load resulting frequency response load. Parasitic capacitive loads greater than begin degrade performance OPA2674. Long board traces, unmatched cables, connections multiple devices easily cause this value exceeded. Always consider this effect carefully, recommended series resistor close possible OPA2674 output (see Board Layout Guidelines section).
OUTPUT CURRENT VOLTAGE
OPA2674 provides output voltage current capabilities that unsurpassed low-cost dual monolithic amp. Under no-load conditions 25°C, output voltage typically swings closer than either supply rail; tested (+25°C) swing limit within 1.1V either rail. Into load (the minimum tested load), delivers more than ±380mA. specifications described previously, though familiar industry, consider voltage current limits separately. many applications, voltage times current product) that more relevant circuit operation. Refer Output Voltage Current Limitations plot Typical Characteristics (see page axes this graph show zero-voltage output current limit zero-current output voltage limit, respectively. four quadrants give more detailed view OPA2674 output drive capabilities, noting that graph bounded safe operating area maximum internal power dissipation this case, channel only). Superimposing resistor load lines onto plot shows that OPA2674 drive into ±4.5V into without exceeding output capabilities dissipation limit. load line (the standard test circuit load) shows full ±5.0V output swing capability, stated Electrical Characteristics tables. minimum specified output voltage current over temperature worst-case simulations cold temperature extreme. Only cold startup will output current voltage decrease numbers shown Electrical Characteristics tables. output transistors deliver power, junction temperatures increase, decreasing VBE's (increasing available output voltage swing), increasing current gains (increasing available output current). steady-state operation, available output voltage current will always greater than that shown over-temperature
DISTORTION PERFORMANCE
OPA2674 provides good distortion performance into load supplies. also provides exceptional performance into lighter loads and/or operating single supply. Generally, until fundamental signal reaches very high frequency power levels, 2nd-harmonic dominates distortion with negligible 3rd-harmonic component. Focusing then 2nd-harmonic, increasing load impedance improves distortion directly. Remember that total load includes feedback networkin noninverting configuration (see Figure this inverting configuration, Also, providing additional supply decoupling capacitor (0.01µF) between supply pins (for bipolar operation) improves 2nd-order distortion slightly (3dB 6dB).
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most amps, increasing output voltage swing directly increases harmonic distortion. Typical Characteristics show 2nd-harmonic increasing little less than expected rate, whereas 3rd-harmonic increases little less than expected rate. Where test power doubles, difference between 2nd-harmonic decreases less than expected 6dB, whereas difference between 3rd-harmonic decreases less than expected 12dB. This factor also shows 2-tone, 3rd-order intermodulation spurious (IM3) response curves. 3rd-order spurious levels extremely low-output power levels. output stage continues hold them even fundamental power reaches very high levels. Typical Characteristics show, spurious intermodulation powers increase predicted traditional intercept model. fundamental power level increases, dynamic range does decrease significantly. tones centered 20MHz, with 10dBm/tone into matched load (i.e., 2VPP each tone load, which requires 8VPP overall 2-tone envelope output pin), Typical Characteristics show 67dBc difference between test-tone power 3rd-order intermodulation spurious levels. This exceptional performance improves further when operating lower frequencies.
total output spot noise voltage computed square root squared output noise voltage contributors. Equation shows general form output noise voltage using terms given Figure
4kTRS
4kTRFNG
(17)
OPA2674
4kTRS
4kTRF 1.6E -20J 290_K
Figure Noise Analysis Model
Dividing this expression noise gain RF/RG)) gives equivalent input referred spot noise voltage noninverting input, shown Equation
4kTR 4kTR
NOISE PERFORMANCE
Wideband current-feedback amps generally have higher output noise than comparable voltage-feedback amps. OPA2674 offers excellent balance between voltage current noise terms achieve output noise. inverting current noise (24pA/Hz) lower than earlier solutions whereas input voltage noise (2.0nV/Hz) lower than most unity-gain stable, wideband voltage-feedback amps. This input voltage noise achieved price higher noninverting input current noise (16pA/Hz). long source impedance from noninverting node less than 100, this current noise does contribute significantly total output noise. input voltage noise input current noise terms combine give output noise under wide variety operating conditions. Figure shows noise analysis model with noise terms included. this model, noise terms taken noise voltage current density terms either nV/Hz pA/Hz.
(18)
Evaluating these equations OPA2674 circuit component values Figure gives total output spot noise voltage 14.3nV/Hz total equivalent input spot noise voltage 3.6nV/Hz. This total input referred spot noise voltage higher than 2.0nV/Hz specification voltage noise alone. This reflects noise added output inverting current noise times feedback resistor. feedback resistor reduced high-gain configurations suggested previously), total input referred voltage noise given Equation approaches just 2.0nV/Hz amp. example, going gain using gives total input referred noise 2.3nV/Hz.
DIFFERENTIAL NOISE PERFORMANCE
OPA2674 used differential driver xDSL applications, important analyze noise such configuration. Figure noise model differential configuration.
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Driver
order minimize noise contributed recommended keep noninverting source impedance possible.
ACCURACY OFFSET CONTROL
current-feedback such OPA2674 provides exceptional bandwidth high gains, giving fast pulse settling only moderate accuracy. Electrical Characteristics show input offset voltage comparable high-speed, voltage-feedback amplifiers; however, input bias currents somewhat higher unmatched. While bias current cancellation techniques very effective with most voltage-feedback amps, they generally reduce output offset wideband current-feedback amps. Because input bias currents unrelated both magnitude polarity, matching input source impedance reduce error contribution output ineffective. Evaluating configuration Figure using worst-case +25°C input offset voltage input bias currents, gives worst-case output offset range equal
4kTRS 4kTRG 4kTRF 4kTRF
4kTRS
VIO(MAX)) (IBN RS/2 (IBI
where noninverting signal gain
4.5mV) (30µA (402 35µA) ±18mV 14mV ±35.0mV (max 25°C)
Figure Differential Noise Analysis Model
reminder, differential gain expressed
POWER CONTROL OPERATION (SO-14 ONLY)
OPA2674I-14D provides power control feature that used reduce system power. four modes operation this power control feature full-power, power cutback, idle state, power shutdown. These four operating modes through logic lines Table shows different modes operation.
(19)
output noise voltage expressed shown below:
(20)
4kTR 4kTR
Table Power Control Mode Operation
MODE OPERATION Full-Power
Dividing this expression differential noise gain gives equivalent input referred spot noise voltage noninverting input, shown Equation
Power Cutback Idle State Shutdown
(21)
4kTR
4kTR
Evaluating this equation OPA2674 circuit component values Figure gives total output spot noise voltage 31.0nV/Hz total equivalent input spot noise voltage 3.5nV/Hz.
full-power mode used normal operating condition. power cutback mode brings quiescent power 13.5mA. idle state mode keeps output impedance reduces output power bandwidth. shutdown mode high output impedance well lowest quiescent power (1.0mA). pins left unconnected, OPA2674I-14D operates normally (full-power).
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change power mode, control pins (either must asserted low. This logic control referenced positive supply, shown simplified circuit Figure
70°C ((12V 18.8mA) 128mA/(5.33) 40mW) 125°C/W 129°C This maximum junction temperature well below maximum 150°C exceed system design targets. Lower junction temperature would possible using SO-14 package power cutback feature. Repeating this calculation that solution gives: 70°C ((12V 14.2mA) 128mA/(5.33) 40mW) 100°C/W 112°C
120k
1.2V
extremely high internal power applications, where improved thermal performance required, consider PSO-8 package OPA2677-a similar part with output stage current limit thermal impedance less than 50°C/W.
Control
BOARD LAYOUT GUIDELINES
Achieving optimum performance with high-frequency amplifier like OPA2674 requires careful attention board layout parasitic external component types. Recommendations that optimize performance include: Minimize parasitic capacitance ground signal pins. Parasitic capacitance output inverting input pins cause instability; noninverting input, react with source impedance cause unintentional band limiting. reduce unwanted capacitance, window around signal pins should opened ground power planes around those pins. Otherwise, ground power planes should unbroken elsewhere board. Minimize distance 0.25) from power-supply pins high-frequency 0.1µF decoupling capacitors. device pins, ground power plane layout should close proximity signal pins. Avoid narrow power ground traces minimize inductance between pins decoupling capacitors. power-supply connections pins SO-8 package) should always decoupled with these capacitors. optional supply decoupling capacitor across power supplies (for bipolar operation) improves 2nd-harmonic distortion performance. Larger (2.2µF 6.8µF) decoupling capacitors, effective lower frequency, should also used main supply pins. These placed somewhat farther from device shared among several devices same area board. Careful selection placement external components preserve high-frequency performance OPA2674. Resistors should very reactance type. Surface-mount resistors work best allow tighter overall layout. Metal film carbon composition axially leaded resistors also provide good high-frequency performance. Again, keep leads board trace length short possible. Never wire-wound type resistors high-frequency application. Although output inverting input most
Figure Supply Power Control Circuit
shutdown feature OPA2674 positive-supply referenced, current-controlled interface. Open-collector drain) interfaces most effective, long controlling logic sustain resulting voltage open mode) that appears pins. A0/A1 voltage diode below positive supply voltage applied OPA2674 logic interface open. voltage output logic interfaces, on/off voltage levels described Electrical Characteristics apply only either used specifications single-supply specifications. open-drain interface recommended operate pins using higher positive supply and/or logic families with inadequate high-level voltage swings.
THERMAL ANALYSIS
high output power capability OPA2674, heat-sinking forced airflow required under extreme operating conditions. Maximum desired junction temperature sets maximum allowed internal power dissipation, described below. case should maximum junction temperature allowed exceed 150°C. Operating junction temperature (TJ) given qJA. total internal power dissipation (PD) quiescent power (PDQ) additional power dissipation output stage (PDL) deliver load power. Quiescent power specified no-load supply current times total supply voltage across part. depends required output signal load. Using example power calculation ADSL line driver concluded Equation worst-case analysis +70°C ambient, maximum internal junction temperature SO-8 package will TAMBIENT PMAX 125°C/W
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sensitive parasitic capacitance, always position feedback series output resistor, any, close possible output pin. Other network components, such noninverting input termination resistors, should also placed close package. Where double-side component mounting allowed, place feedback resistor directly under package other side board between output inverting input pins. frequency response primarily determined feedback resistor value described previously. Increasing value reduces bandwidth, whereas decreasing gives more peaked frequency response. feedback resistor used Typical Characteristics gain supplies good starting point design. Note that feedback resistor, rather than direct short, recommended unity-gain follower application. current-feedback requires feedback resistor even unity-gain follower configuration control stability. Connections other wideband devices board made with short direct traces through onboard transmission lines. short connections, consider trace input next device lumped capacitive load. Relatively wide traces (50mils 100mils) should used, preferably with ground power planes opened around them. Estimate total capacitive load from plot Recommended Capacitive Load (see page 10). parasitic capacitive loads 5pF) need because OPA2674 nominally compensated operate with parasitic load. long trace required, signal loss intrinsic doubly-terminated transmission line acceptable, implement matched impedance transmission line using microstrip stripline techniques (consult design handbook microstrip stripline layout techniques). environment normally necessary onboard. fact, higher impedance environment improves distortion; distortion versus load plots. With characteristic board trace impedance defined based board material trace dimensions, matching series resistor into trace from output OPA2674 used, well terminating shunt resistor input destination device. Remember also that terminating impedance parallel combination shunt resistor input impedance destination device. This total effective impedance should match trace impedance. high output voltage current capability OPA2674 allows multiple destination
devices handled separate transmission lines, each with their series shunt terminations. attenuation doubly-terminated transmission line unacceptable, long trace series-terminated source only. Treat trace capacitive load this case, series resistor value shown plot Capacitive Load. However, this does preserve signal integrity well doubly-terminated line. input impedance destination device low, there some signal attenuation voltage divider formed series output into terminating impedance. Socketing high-speed part like OPA2674 recommended. additional lead length pin-to-pin capacitance introduced socket create extremely troublesome parasitic network, which make almost impossible achieve smooth, stable frequency response. Best results obtained soldering OPA2674 onto board.
INPUT PROTECTION
OPA2674 built using high-speed complementary bipolar process. internal junction breakdown voltages relatively these very small geometry devices reflected absolute maximum ratings table. device pins have limited protection using internal diodes power supplies, shown Figure These diodes provide moderate protection input overdrive voltages above supplies well. protection diodes typically support 30mA continuous current. Where higher currents possible (for example, systems with ±15V supply parts driving into OPA2674), current-limiting series resistors should added into inputs. Keep these resistor values possible, because high values degrade both noise performance frequency response.
+VCC
External
Internal Circuitry
-VCC
Figure Steering Diodes
PACKAGE OPTION ADDENDUM
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9-Dec-2004
PACKAGING INFORMATION
Orderable Device OPA2674I-14D OPA2674I-14DR OPA2674ID OPA2674IDR
Status ACTIVE ACTIVE ACTIVE ACTIVE
Package Type SOIC SOIC SOIC SOIC
Package Drawing
Pins Package Plan 2500 2500 None None None None
Lead/Ball Finish SNPB SNPB SNPB SNPB
Peak Temp Level-3-220C-168 Level-3-220C-168 Level-3-235C-168 Level-3-235C-168
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan currently available please check latest availability information additional product content details. None: available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean "Pb-Free" addition, uses package materials that contain halogens, including bromine (Br) antimony (Sb) above 0.1% total product weight.
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDECindustry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
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