N-CHANNEL 0.018 -40A DPAK STripFETII POWER MOSFET TYPE STD45NF75

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N-CHANNEL 0.018 -40A DPAK STripFETII POWER MOSFET TYPE STD45NF75

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STD45NF75
N-CHANNEL 0.018 -40A DPAK STripFETII POWER MOSFET
TYPE STD45NF75
VDSS
RDS(on) <0.024
A(**)
TYPICAL RDS(on) 0.018 100% AVALANCHE TESTED GATE CHARGE MINIMIZED SURFACE-MOUNTING DPAK (TO-252) POWER PACKAGE TAPE REEL (SUFFIX "T4")
DPAK TO-252 (Suffix "T4")
DESCRIPTION This Power MOSFET latest development STMicroelectronis unique "Single Feature SizeTM" strip-based process. resulting transistor shows extremely high packing density onresistance, rugged avalanche characteristics less critical alignment steps therefore remarkable manufacturing reproducibility. APPLICATIONS HIGH CURRENT, SWITCHING APPLICATIONS
INTERNAL SCHEMATIC DIAGRAM
Ordering Information
SALES TYPE STD45NF75T4 MARKING D45NF75 PACKAGE DPAK PACKAGING TAPE REEL
ABSOLUTE MAXIMUM RATINGS Symbol Parameter Drain-source Voltage (VGS VDGR Drain-gate Voltage (RGS Gate- source Voltage ID(**) Drain Current (continuous) 25°C Drain Current (continuous) 100°C Drain Current (pulsed) Ptot Total Dissipation 25°C Derating Factor Peak Diode Recovery voltage slope dv/dt Single Pulse Avalanche Energy Tstg Storage Temperature Operating Junction Temperature Pulse width limited safe operating area.
(**) Current Limited Package
Value 0.67
Unit W/°C V/ns
40A, di/dt 800A/µs, V(BR)DSS, TJMAX Starting
April 2004
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STD45NF75
THERMAL DATA
Rthj-case Rthj-pcb Thermal Resistance Junction-case Thermal Resistance Junction-pcb Maximum Lead Temperature Soldering Purpose (for sec. from case) curve page °C/W °C/W
ELECTRICAL CHARACTERISTICS (Tcase unless otherwise specified)
Symbol V(BR)DSS IDSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS Gate-body Leakage Current (VDS Test Conditions Min. ±100 Typ. Max. Unit
Rating Rating 125°C
IGSS
Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source Resistance Test Conditions Min. 0.018 Typ. Max. 0.024 Unit
DYNAMIC
Symbol Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions Min. Typ. 1760 Max. Unit
25V, MHz,
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STD45NF75
ELECTRICAL CHARACTERISTICS (continued) SWITCHING
Symbol td(on) Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions (Resistive Load, Figure
VDD=60 ID=40A VGS=
Min.
Typ.
Max.
Unit
(see test circuit, Figure
SWITCHING
Symbol td(off) Parameter Turn-off Delay Time Fall Time Test Conditions 4.7, (Resistive Load, Figure Min. Typ. Max. Unit
SOURCE DRAIN DIODE
Symbol ISDM IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Test Conditions Min. Typ. Max. Unit
di/dt 100A/µs 150°C (see test circuit, Figure
(*)Pulsed: Pulse duration duty cycle width limited safe operating area.
Safe Operating Area
Thermal Impedance
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Output Characteristics Transfer Characteristics
Transconductance
Static Drain-source Resistance
Gate Charge Gate-source Voltage
Capacitance Variations
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STD45NF75
Normalized Gate Threshold Voltage Temperature Normalized Resistance Temperature
Source-drain Diode Forward Characteristics
Normalized Breakdown Voltage Temperature.
Power Derating
Current
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STD45NF75
Thermal Resistance Rthj-a Copper Area Power Dissipation Copper Area
Allowable Time Avalanche
previous curve gives safe operating area unclamped inductive loads, single pulse repetitive, under following conditions: PD(AVE) (1.3 BVDSS IAV) EAS(AR) PD(AVE) Where: Allowable Current Avalanche PD(AVE) Average Power Dissipation Avalanche (Single Pulse) Time Avalanche derate above fixed IAV, following equation must applied: (Tjmax TCASE)/ (1.3 BVDSS Zth) Where: value coming from Normalized Thermal Response fixed pulse width equal
6/12
STD45NF75
SPICE THERMAL MODEL
Parameter CTHERM1 CTHERM2 CTHERM3 CTHERM4 CTHERM5 CTHERM6
Node
Value 10-4 10-3 10-2 10-2 9.65 10-2 10-1
RTHERM1 RTHERM2 RTHERM3 RTHERM4 RTHERM5 RTHERM6
0.045 0.105 0.150 0.225 0.375 0.600
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STD45NF75
Fig. Unclamped Inductive Load Test Circuit Fig. Unclamped Inductive Waveform
Fig. Switching Times Test Circuits Resistive Load
Fig. 3.1: Switching Time Waveform
Fig. Gate Charge Test Circuit
Fig. 4.1: Gate Charge Test Waveform
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STD45NF75
Fig. Diode Switching Test Circuit Fig. 5.1: Diode Recovery Times Waveform
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STD45NF75
TO-252 (DPAK) MECHANICAL DATA
MIN. 0.03 0.64 0.45 0.48 9.35 0.023 TYP. MAX. 0.23 10.1 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.252 0.173 0.368 0.031 0.039 inch TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 0.260 0.181 0.397
DIM.
DETAIL
DETAIL
0068772-B
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Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics other names property their respective owners.
2004 STMicroelectronics Rights Reserved
STMicroelectronics GROUP COMPANIES Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco -Singapore Spain Sweden Switzerland United Kingdom United States. www.st.com
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N-CHANNEL 0.018 -40A DPAK STripFETII POWER MOSFET TYPE STD45NF75

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