AK2306/2306LV Dual CODEC ISDN/VoIP TERMINAL ADAPTER GENERAL

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AK2306/2306LV Dual CODEC ISDN/VoIP TERMINAL ADAPTER GENERAL

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[AK2306/LV]
AK2306/2306LV
Dual CODEC ISDN/VoIP TERMINAL ADAPTER
GENERAL DESCRIPTION
AK2306 dual CODEC-Filter most suitable ISDN Terminal Adapter. includes Selectable A-law/u-law function, Internal Gain Adjustment from +6dB -18dB step control, Selectable 16Hz/20Hz Ring Tone Generator SLIC. these functions controlled internal register accessed through serial interface. interface AK2306 accepts Long Frame, Short Frame clock formats format. kHz(128k-4096kHz) clock input available interface. AK2306 AK2306LV pin-compatible, different products which power supply voltage 5.0V 3.3V,respectively.
Dual
FEATURE
CODEC Filtering systems ISDN Terminal Adapter Selectable Ring Tone Generator SLIC 16Hz 20Hz tone available. Independent functions each channel controlled internal register Power Down Mode Mute Gain Adjustment: -18dB (1dB step) Selectable Data Interface Timing: Long Frame Short Frame/GCI Variable Data Rate: [Hz] (128k 4.096MHz) External Gain Adjustment A-law/u-law Register Selectable Serial Interface access internal register Power Reset Single Power Supply Voltage +5.0V (AK2306) +3.3V 0.3V (AK2306LV) Power Consumption
PACKAGE
24pinVSOP (0.5mm pitch)
MS0093-E-04
2001/11
[AK2306/LV]
CONTENTS
ITEMS BLOCK DIAGRAM. ASSIGNMENT. CONDITION. FUNCTION. FUNCTIONAL DESCRIPTION. LONGFRAME/SHORTFRAME/GCI MUTE. GAIN ADJUSTMENT. RING TONE GENERATOR RESET PAGE
CIRCUIT DESCRIPTION. INTERFACE.
POWER DOWN. SERIAL INTERFACE. REGISTER. ABSOLUTE MAXIMUM RATINGS. RECOMMENDED OPERATING CONDITIONS. ELECTRICAL CHARACTERISTICS. APPLICATION CIRCUIT EXAMPLE. PACKAGE INFORMATION.
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[AK2306/LV]
BLOCK DIAGRAM
GST0 VFTP0 VFTN0 VFR0 GSR0 GST1 VFTP1 VFTN1 VFR1 GSR1 TNOUT VREF
GA0T AMPT0 GA0R
AAF0
CODEC
SMF0
AMPR0
BCLK
GA1T AMPT1 GA1R AMPR1
AAF1
CODEC
SMF1
RING TONE GENERATOR BGREF
RXVlm0
TXVlm1 TXVlm0 RXVlm1
PWDN
A/u_SEL
Mut0
Mut1
Power Reset
Internal Register
Serial
SCLK DATA
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[AK2306/LV]
ASSIGNMENT
VFTP1 VFTN1 GST1 GSR1 VFR1 BCLK TNOUT
VREF VFTP0 VFTN0 GST0 GSR0 VFR0 DATA SCLK
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[AK2306/LV]
CONDITION
Pin# Name type load (MAX.) load (MIN.)
Outout status (Power down mode) Output status (Reset)
Remarks
VFTP1 Analog VFTN1 Analog GST1 50pF Analog Hi-Z Hi-Z 10k(*1) GSR1 50pF Analog Hi-Z Hi-Z (*1) VFR1 Analog 50pF Analog Hi-Z Hi-Z TTL/CMOS(*3) BCLK TTL/CMOS(*3) 15pF CMOS Hi-Z Hi-Z TTL/CMOS(*3) TNOUT 15pF CMOS SCLK TTL/CMOS(*3) DATA 15pF TTL/CMOS(*3) Input Input TTL/CMOS(*3) Analog 0.22uF (*2) 50pF Analog Hi-Z Hi-Z VFR0 Analog GSR0 50pF Analog Hi-Z Hi-Z (*1) GST0 50pF Analog Hi-Z Hi-Z (*1) VFTN0 Analog VFTP0 Analog VREF Analog (*2) load(MIN.) includes feedback resistance input/output op-amp. *2)External capacitance should connected VSS. *3)TTL level applied only input level AK2306LV. Output level both AK2306 AK230LV,and input level AK2306 CMOS level.
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[AK2306/LV]
FUNCTION
Pin# Name VFTP1 Function Positive analog input transmit OPamp(AMPT1) channel Transmit gain defined ratio R2/R1. external input resister connected this pin. external feedback resister connected between this GST1. Negative analog input transmit OPamp(AMPT1) channel Output transmit OPamp(AMPT1) channel external feedback resister connected between this VFTP1. Output receive OPamp(AMPR1) channel Negative analog input receive OPamp(AMTR1) channel Receive gain defined ratio R4/R3. external input resister connected this pin. external feedback resister connected between this VR1. Analog Output equivalent received data channel Output gain adjusted GA1R. Negative analog input transmit OPamp(AMPT0) channel Transmit gain defined ratio R2/R1. external input resister connected this pin. external feedback resister connected between this GST0. Positive analog input transmit OPamp(AMPT0) channel Output transmit OPamp(AMPT0) channel external feedback resister connected between this VFTP0. Analog Output equivalent received data channel Output gain adjusted GA0R Negative analog input receive OPamp(AMTR0) channel Receive gain defined ratio R4/R3. external input resister connected this pin. external feedback resister connected between this VR0. Output receive OPamp(AMPR0) channel Serial output data. channel data output following channel data. data rate synchronized with BCLK. This output remains high impedance state except period transmitting data. Serial input data. channel data received following channel data. data rate synchronized with BCLK. Frame sync input. This clock input internal which gerenates internal system clocks. must 8kHz clock which synchronized with BCLK. clock data interface. This clock defines input/output timing frequency BCLK should kHz(128k 4096kHz).
VFTN1 GST1 GSR1 VFR1
VFTN0
VFTP0 GST0 VFR0
GSR0
BCLK
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Pin# Name TNOUT DATA SCLK VREF Function Ring Tone output pin. 16Hz 20Hz tone selected internal register. Data input serial interface. Clock input serial interface. Read write enable serial interface.
[AK2306/LV]
loop filter. External capacitance(Min 0.22uF) should connected between this VSS. Analog ground output. External capacitance(1.0 should connected between this VSS. Positive supply voltage. +5V(AK2306) +3.3V(AL2306LV) supply. Ground.
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[AK2306/LV]
CIRCUIT DESCRIPTION
Block AMPT0,1 Function Op-amp input gain adjustment. This op-amp differential inputs. Adjusting gain with external resistors. resistor larger than recommended feedback resistor. <NOTE> AMPT0(1) becomes automatically power down, when CODEC ch0(1) power down. Op-amp output gain adjustment. This op-amp used inverting amplifier. Adjusting gain with external resistors. resistor larger than recommended feedback resistor. Integrated anti-aliasing filter which prevents signals around sampling rate from folding back into voice band. order low-pass filter. Converts analog signal 8bit data according companding schemes recommendation G.711; A-law u-law. band limiting filter also integrated. selection companding schemes ALAWN register follows: "H": u-Law "L": A-Law Expands 8bit data according A-law u-law. selection companding schemes ALAWN register follows: "H": u-Law "L": A-Law Extracts inband signal from output. also corrects sinx/x effect output. Provides stable analog ground voltage using on-chip band-gap reference circuit which temperature compensated. output voltage 2.4V operation(AK2306) 1.5V +3.3V operation(AK2306LV). Generates kinds tone; 16Hz 20Hz. Tone selection Tone ON/OFF controlled registers. Gain selects analog signals. posibble select gain from +6dB -18dB (1dB/step). Gain defined internal register. Interface internal register using SCLK, DATA, pins. generates system clock AK2306. Reference clock (8KHz). More than 0.22uF external capacitance should connected between VSS. data rate available 64xN(N 64)kHz which synchronizes with BCLK. kinds data format (Long Frame, Short Frame) available. Each data format automatically detected. data stream, which includes data, output through input through pin. data stream always follows data stream.
AMPR0,1
BGREF
RING TONE GENERATOR GA0T/R GA1T/R GATN SERIAL
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[AK2306/LV]
FUNCTIONAL DESCRIPTION Data Interface
AK2306 supports following data formats Long Frame Sync(LF) Short Frame Sync(SF) data both channels multiplexed interfaced through common pins(DR,DX).The first 8bit defined channel seconds 8bit defined channel data stream. order data first each channel. Selection interface mode ordinary interface(LF,SF) selectable through register following table. automatically selected AK2306 means detecting length 8KHz frame signal.
Register Interface mode select (Address:101 Bit:0) PCMIF Interface
Comments
LF/SF selected automatically
Default power-on reset =LF/SF mode(PCMIF=0).
LONG FRAME( SHORT FRAME Automatic LF/SF selection AK2306 monitors duration level automatically selects interface format.
period FS="H" more than clocks clock
Timing interface
Interface format
bits data accommodated frame( 125us defined 8kHz frame sync signal. Although there time slots maximum 8kHz frame(when BCK=4.096MHz), data AK2306 occupy first second time slot channel channel 1,respectively indicated figures next page. Frame Sync signal (FS) 8kHz reference signal. This signal indicated timing frame position 8kHz interface. internal clock generated based this signal. Clock (BCLK) BCLK defines data rate. BCLK varied from 128kHz 4.096MHz 64kHz step. Position Ch0,Ch1 data DX/DR data flow
channel data channel assigned Analog defined SEL2B register.
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CH0,1selection (Address:100 Bit:5) SEL2B Remarks Default Reset
[AK2306/LV]
<2ch Multiplexed> LongFrame
BCLK
Don't care
Don't care
SEL2B=0 SEL2B=1
B1-CHANNEL (CH0) B1-CHANNEL (CH1)
B2-CHANNEL (CH1) B2-CHANNEL (CH0)
ShortFrame
BCLK
Don't care SEL2B=0 SEL2B=1
Don't care
B1-CHANNEL (CH0) B1-CHANNEL (CH1)
B2-CHANNEL (CH1) B2-CHANNEL (CH0)
<Non Multiplex> supported
Important Notice
Please don't stop feeding BCLK except Full power down mode. Internal does free running when either BCLK provided. this case, frequency Ring Tone output guaranteed.
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General Circuit Interface
format used ISDN application. data format clocking showed timing interface
[AK2306/LV]
bits data accommodated frame( 125us defined 8kHz frame sync signal. Although there time slots maximum 8kHz frame(when BCK=4.096MHz), data occupy first second time slot channel channel 1,respectively.
Frame Sync signal (FS) 8kHz reference signal. This signal indicated timing frame position 8kHz GCI. internal clock generated based this signal. High level duration clock period BCLK. Clock (BCLK) BCLK defines data rate. rate data half BCLK. BCLK varied from 512kHz 4.096MHz 128kHz step. Position Ch0,Ch1 data DX/DR data flow
channel data channel assigned Analog defined SEL2B register same interface. CH0,1selection( Address:100 Bit:5) SEL2B
Remarks Default Reset
<2ch Multiplex>
BCLK
Don't care
Don't care
SEL2B=0 SEL2B=1
B1-CHANNEL (CH0) B1-CHANNEL (CH1)
B2-CHANNEL (CH1) B2-CHANNEL (CH0)
<Non Multiplex> supported
Important Notice
Please don't stop feeding BCLK except Full power down mode. Internal does free running when either BCLK provided. this case, frequency Ring Tone output guaranteed.
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[AK2306/LV]
MUTE
output each channel muted independently through register shown table. Mute register( Address:100 Bit:5,4
MTCH0,1
Operation Normal Mute
data output High-Impedance(*
CODEC analog output AGND*
(*1) MTCH0 MTCH1 mute control CH1,respectively. channel muted MTCH0/1 defined SEL2B shown Interface section. <EXAMPLE> Mode mute (MTCH=1, MTCH1=0, SEL2B=0)
BCLK
Don't care B1-CHANNEL(CH0) <SEL2B="0">
Don't care
B2-CHANNEL(CH1) <SEL2B="0">
VRX0 VRX1
mode
CODEC analog output always AGND level. CODEC analog output signal converted from data input through pin.
mute (MTCH0=1, MTCH1=0, SEL2B=0)
BCLK
Don't care B1-CHANNEL(CH0) <SEL2B="0">
Don't care
B2-CHANNEL(CH1) <SEL2B="0">
VRX0 VRX1
CODEC analog output always AGND level. CODEC analog output signal converted from data input through pin.
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[AK2306/LV]
GAIN ADJUSTMENT
Analog input/output gain adjusted range from +6dB -18dB 1.0dB step through register. Register( Address:011 -000 Bit:4
GanT4 GanR4
GanT3 GanR3
GAnT2 GAnR2
GAnT1 GAnR1
GAnT0 GAnR0
Gain [dB]
Remarks
Default
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[AK2306/LV]
RING TONE GENERATOR
Ring tone generator generates kinds ring tone, 16Hz 20Hz. frequency tone selected register. Tone frequency selection Tone Selection register (Address: 101, Bit:
TNFQ
Tone output enable
Tone Frequency 16Hz 20Hz
Remarks Default
Tone output enabled/disabled through register.
RING TONEGEN Enable (Address: 100, Bit: PDTN RING TONE GENERATOR Power Down* Tone output enabled Remarks Default
When Power down selected, TNOUT output fixed level.
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[AK2306/LV]
RESET
Power Reset AK2306 automatically generates internal reset pulse which resets circuit that necessary start initialization after power reset. registers default value. After internal reset pulse generated, CODEC Ch0/Ch1 starts initialization procedure being signal, takes 180ms( typ.), 350ms(max) complete initialization after detection power Power slope enable Power-on Reset
When power-up slope longer than 50ms(=5tau:tau time constant), Power Reset works normally. When time longer than 50ms, Power Reset activated internal registers initialized. this case registers must written through interface.
NOTE) stable operation after power recommend write register value through interface after power Recommended start procedure
following start procedure recommended when AK2306/LV going power
Power
Wait 200ms case rising time =50ms(=5tau)
FS="L" BCLK="L" When 1stFS BCLK "L", CODEC ch0,ch1 dose interface with external devices.
Write data internal register through serial
Write data internal register before CODEC starts working.
Supply BCLK
CODEC Initialization starts. Wait 130ms CODEC Initialization complete. CODEC starts working
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[AK2306/LV]
POWER
DOWN
Power consumption reduced power down mode. power down mode, current analog circuits clock digital circuits, stopped, relating circuits hold status. There power down modes. Power down circuits Power down block power down mode, output pins corresponding blocks turn Hi-Z except TNOUT pin.(See page POWER DOWN MODE SETTING power down modes Mode Circuits Registers Operation "0"/"1" Note Registers reset. Serial available. need supply BCLK.
circuit
Normal Power down
CODEC CODEC RING TONEGEN
PDCH0
Block
PDCH1
Normal Power down
PDTN
Keep supplying even when CODEC CH0,1 power down mode (see page10,11). When CODEC CHn(n=0,1) power down mode, functions below active: AMPTn(n=0,1) Input/Output TNOUT Output Please refer next page table deltail.
CANCELLATION POWER DOWN CODEC When power down mode CODEC CH0/CH1 cleared, CODEC circuitry starts initialized. takes 130mS(typ.). When full circuit power down mode CODEC cleared, AK2306/LV starts same wake sequence power takes 250ms(Typ) Wake time Tone generator 125us(Typ).
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POWER DOWN BLOCK REGISTER AMPT0 GA0T Channel AAF0 CODEC SMF0 GA0R AMPR0 AMPT1 GA1T Channel AAF1 CODEC SMF1 GA1R AMPR1 RING TONEGEN BGREF SERIAL BLOCK CODEC PDCH0 CODEC PDCH1 CODEC CH0&1 PDCH0 PDCH1 RING TONEGEN PDTN
[AK2306/LV]
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[AK2306/LV]
SERIAL INTERFACE
internal registers read/written with SCLK, DATA, pins. 1word consists 16bits. first 4bits instruction code which specifies read/write. following 3bits specify address. rest 8bits setting registers. Address (3bit)
Instruction code (4bit)
Data internal registers (8bit)
*)Dummy adjusting timing when reading register.
INSTRUCTION CODEC
Read/Write Read Write action
Other codes
SCLK WRITE/READ
Input data loaded into internal shift register rising edge SCLK. rising edge SCLK counted after falling edge CSN. When more than SCLK pulses: [WRITE] Data loaded into internal register rising edge SCLK pulse. [READ] DATA switched input falling edge SCLK pulse.
WRITE READ CANCELLATION
WRITE cancelled when goes before rising edge SCLK pulse. READ cancelled when goes before falling edge SCLK pulse.
SERIAL WRITE READ (SERIAL ACCESS)
must before next access successive access. When next access going done remains "L", successive access done.
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WRITE Continuous SCLK
Must goes once
[AK2306/LV]
SCLK DATA
Goes anytime after SCLK 16th pulse
Address "000"
Instruction Code
Write data address"000"
WRITE rising edge SCLK 16th pulse
Instruction Code
Write data
Burst SCLK SCLK stop level level anytime during write cycle. After resuming SCLK, write cycle retrieved normally.
Must once Goes anytime after SCLK 16th pulse
SCLK DATA
Address "000"
Instruction Code
Write data address "000"
WRITE rising edge SCLK 16th pulse
CANCELLATION
goes before rising edge 16th SCLK pulse
SCLK DATA
Address "000"
Instruction Code
Write data address"000"
Write Excuted
DATA pin: Input mode (Hi-Z)
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SERIAL ACCESS Serial access with staying during serise write cycle.
SCLK DATA
[AK2306/LV]
Write data
Instruction Code
Address "000"
Write data Address"000" EXCUTE!
Instruction Code
EXCUTED!
READ CONTINOUS SCLK
Must once going anytime after SCLK 16th pulse
SCLK DATA
Read Instruction
Address
Read Data
Read Instruction
Read Data
Data output starts falling edge SCLK pulse
Read period until earlier edge either rising SCLK 16th pulse falling
Burst SCLK
Must once going anytime after SCLK 16th pulse
SCLK DATA
Read Data
Read Instruction
Address
Read output starts falling edge SCLK pulse
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SERIAL ACCESS Serial access with staying during serise read cycle.
[AK2306/LV]
SCLK DATA
Address "000"
Read Instruction
Read data READ EXCUTED!
Read Instruction READ EXCUTED!
DISCORD INSTRUCTION CODE
SCLK DATA
Address
IInstructions except specified 0bbb 10bb 110b (b=0
WRITE/READ EXCUTED!
DATA pin: Input mode (Hi-Z)
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[AK2306/LV]
REGISTER
MTCH1
GA0R4 GA1R4 GA0T4 GA1T4 MTCH0
GA0R3 GA1R3 GA0T3 GA1T3 TNFQ
GA0R2 GA1R2 GA0T2 GA1T2 PDTN ALAWN
GA0R1 GA1R1 GA0T1 GA1T1 PDCH1 SEL2B
GA0R0 GA1R0 GA0T0 GA1T0 PDCH0 PCMIF
Reserved Reserved
*)Dummy Note) registers except address(000 011), Bit5(D5) read/write. Note) Please write "all 0's" address(000 100), Bit7,6(D7,D6) address(101), Bit7,6,5,4(D7 normal operation. Note) Address(000 011),Bit5(D5) write data will output when accessed read. INITIALIZATION REGISTERS registers initialized POWER RESET only. Power reset excuted difference power time constant. Thus highly recommended that register (address(000 101) written time power after abnormal circumstances happens such micro interrupt power line operation lightning. REGISTER FUNCTION
Address
Name GA0R0 GA0R1 GA0R2 GA0R3 GA0R4 GA1R0 GA1R1 GA1R2 GA1R3 GA1R4
Default
Function Receive gain adjustment -18dB 1.0dB step 00000: +6dB 11xxx: -18dB
Refer
Test mode Please write "0". Receive gain adjustment -18dB 1.0dB step 00000: +6dB 11xxx: -18dB
Test mode Please write "0".
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Address Name GA0T0 GA0T1 GA0T2 GA0T3 GA0T4 GA1T0 GA1T1 GA1T2 GA1T3 GA1T4 PDCH0 PDCH1 PDTN MTDX0 MTDX1 PCMIF SEL2B ALAWN TNFQ Default Function Transmit gain adjustment -18dB 1.0dB step 00000: +6dB 11xxx: -18dB Refer
[AK2306/LV]
Test mode Please write "0". Transmit gain adjustment -18dB 1.0dB step 00000: +6dB 11xxx: -18dB
Test mode Please write "0". CODEC CH0,1 Power down control Power Power RING TONEGEN Power down control Power Power Full Power down Power Power Mute control: VR0.VR1,DX Normal output Mute Test mode Please write "0". Interface select LF/SF data channel select A/u-law select A-law u-law Tone frequency select 16Hz 20Hz Test mode Please write "0".
Reserved
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Address Name Default Function Reserved Refer
[AK2306/LV]
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[AK2306/LV]
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Power Supply Voltages Analog/Digital Power Supply -0.3 Voltage -0.1 Digital Input Voltage -0.3 VDD+0.3 Analog Input Voltage -0.3 VDD+0.3 Input current (except power supply pins) Storage Temperature Tstg Warning: Exceeding absolute maximum ratings cause permanent damage. Normal operation guaranteed these extremes. Units
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol 4.75 5.25 Units
Power Supplies Analog/Digital power supply( AK2306 Power Supplies Analog/Digital power supply( AK2306 Ambient Operating Temperature Frame Sync Frequency FS0,FS1 Note) voltages reference ground VSS=0V
ELECTRICAL CHARACTERISTICS
Unless otherwise noted, guaranteed VDD=+5V 5%(AK2306), VDD=+3V+/-0.3V(AK2306LV), FS=8kHz.
Characteristics
Parameter Power Consumption BCLK=2048kHz Output High Voltage (CMOS level) Output Voltage (CMOS level) Input High Voltage1 (CMOS level) Input High Voltage2 (TTL level) Input Voltage1 (CMOS level) Input Voltage2 (TTL level) Input Leakage Current Input Capacitance Output Leakage Current Power Consump.@PD Symbol Conditions PDD1 PDCH0,1 PDDT0,1=0,0 output unloaded PDD2 PDCH0,1 PDDT0,1=1,0 output unloaded IOH=-1.6mA VIH1 VIH2 VIL1 VIL2 Tri-state mode PDDd IOL=1.6mA 0.7VDD 0.3VDD 0.8VDD Units
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ASAHI KASEI CODEC
Absolute Gain AK2306: VDD=5.0V +/-5%, AK2306LV VDD=3.3V +/-0.3V Parameter Conditions Analog Input Level Input: AK2306 0dBm0@1020Hz AK2306LV Absolute Transmit Gain -0.6 Analog Output Level Input: AK2306 0dBm0@1020Hz AK2306LV Absolute Receive Gain -0.6 Maximum Overload Level +3.14dBm0 AK2306 AK2306LV Gain Tracking Parameter Transmit Gain Tracking Error
[AK2306/LV]
0.849 0.531 0.849 0.531 1.219 0.762
Units Vrms Vrms Vrms
Receive Gain Tracking Error
Conditions Reference Level: -55dBm0 ~-50dBm0 -10dBm0 -50dBm0 ~-40dBm0 1020Hz Tone -40dBm0 3dBm0 Reference Level: -55dBm0 ~-50dBm0 -10dBm0 -50dBm0 ~-40dBm0 1020Hz Tone -40dBm0 3dBm0
-1.2 -0.4 -0.2 -1.2 -0.4 -0.2
Units
Frequency Response Parameter Transmit Frequency Response
Receive Frequency Response
Conditions Relative 0.05kHz 0dBm0@1020Hz 0.06kHz 0.2kHz ~3.0kHz 3.4kHz 4.0kHz Relative ~3.0kHz 0dBm0@1020Hz 3.4kHz 4.0kHz
-1.8 -0.15 -0.8 -0.15 -0.8
0.15 0.15
Units
Distortion Parameter Transmit Signal Distortion
Receive Signal Distortion
Conditions -40dBm0 ~-45dBm0 -30dBm0 ~-40dBm0 0dBm0 ~-30dBm0 1020Hz Tone -40dBm0 ~-45dBm0 -30dBm0 ~-40dBm0 0dBm0 ~-30dBm0 1020Hz Tone
Single Frequency Distortion Transmit Single Frequency Distortion Receive Intermodulation Distortion -6dBm@860Hz,1380Hz Note) C-message Weighted u-Law, Psophometric Weighted A-Law
Units
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Envelope delay Distortion Parameter Transmit Delay, Absolute Transmit Delay, Relative Conditions =1600Hz =500Hz ~600Hz =600Hz ~1000Hz =1000Hz ~2600Hz =2600Hz ~2800Hz =2800Hz ~3000Hz =1600Hz =500Hz ~1000Hz =1000Hz ~1600Hz =1600Hz ~2600Hz =2600Hz ~2800Hz =2800Hz ~3000Hz
[AK2306/LV]
Units
Relative f=1600Hz Receive Delay, Absolute Receive Delay, Relative
Relative f=1600Hz
Noise Conditions u-law, C-message A-law, Psophometric u-law, C-message A-law, Psophometric VFXIN Vrms, ~100kHz PSRR, Transmit AVDD=DVDD=5V±100mVop ~50kHz PSRR, Receive AVDD=DVDD=5V±100mVop ~50kHz Spurious Out-of-Band Signal 0dBm0, ~7.6kHz Output ~3.4kHz ~8.4kHz CODE ~100kHz Note Analog Input Analog Ground Note Digital Input(DR) Code Note tested production Test. Parameters guaranteed design. Interchannel Crosstalk Parameter Transmit Receive Receive Transmit Transmit Transmit Receive Receive Parameter Load Resistance Load Capacitance VDD=5V Output voltage Swing VDD=3.3V Parameter Idle Channel Noise Idle Channel Noise Noise, Single Frequency Units dBrnC0 dBm0p dBrnC0 dBm0p dBm0
Conditions 0dBm0@VFXIN, Idle code 0dBm0 code level, VFXIN Vrms 0dBm0@VFXIN, Idle code 0dBm0 code level, VFXIN Vrms Conditions
2.25
Units Units kohm Vp-p
Analog Interface Transmit Amplifier
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Analog Interface Receive Output Parameter Output voltage(AGND level) Load Resistance Load Capacitance Output voltage Swing
[AK2306/LV]
(AK2306 5.0V±5%, AK2306LV 3.3V±0.3V) Conditions AK2306 code input AK2306LV AK2306 AK2306LV 2.25
Units kohm Vp-p
Analog Interface Receive Output Amplifier
Parameter Input Resistance Load Resistance Load Capacitance Output Voltage Swing
Conditions
AK2306 AK2306LV
2.25
Units Vp-p
VOLUME GA0T,GA0R,GA1T,GA1R)
Parameter Step margin Conditions Relative -1.0 Unit +1.0*)
*)Monotonus increase/decrease guranteed RING TONE GENERATOR
Parameter Signal frequency 16Hz/20Hz Tone Duty Conditions Jitter 8KHz frame signal Jitter 8KHz frame signal 16/20 Unit
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ASAHI KASEI INTERFACE Long Frame, Short Frame,
[AK2306/LV]
Unless otherwise noted, specification applies 5V±5%/3V±0.3V,VSS FS0= 8kHz. timing parameters measured 0.8VDD =0.4V. Parameter Frequency BCLK Frequency BCLK Pulse Width High BCLK Pulse Width Rising Time: (BCLK,FS0,FS1,DX0,DX1,DR0,DR1) Falling Time: (BCLK,FS0,FS1,DX0,DX1,DR0,DR1) Hold Time: BCLK High Setup Time: High BCLK Setup Time: BCLK Hold Time: BCLK Delay Time: BCLK High valid Long Frame Hold Time: period BCLK Delay Time: BCLK High, whichever later,to valid Note1) Delay Time: BCLK High-Z Note1) Pulse Width Short Frame Hold Time: BCLK Setup Time: BCLK Delay Time: BCLK High-Z Note1) BCLK Frequency Delay Time: Second BCLK High-Z Setup Time: Second BCLK High Hold Time: Second BCLK High 1/tPBG tDZCG tSDBG tHBDG 4096 Fig3 tHBFS tSFBS tDZCS Fig2
Symbol 1/tPF 1/tPB tWBH tWBL tHBF tSFB tSDB tHBD Note1) tDBD
4096
Units
Fig1 Fig2 Fig3
tHBFL tDZFL tDZCL tWFSL
Fig1
Note1) Measured with 150pF Load capacitance driving LSTTLs
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BCLK tHBFL
[AK2306/LV]
tDZF
tWFSL
Fig1 Interface Timing
Long Frame
BCLK
tWBH
tHBF
tHBF tSFB tDBD tDBD tDZC
Fig2
Interface Timing
Short Frame
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10111213141516 BCLK tSDB tHBD tDZC
[AK2306/LV]
BCLK tHBF tWFS tDZF
Fig3
Interface Timing
MS0093-E-04
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ASAHI KASEI SERIAL INTERFACE
Parameter SCLK Frequency SCLK Pulse Width High SCLK Pulse Width Pulse Width Hold Time: SCLK High Setup Time: SCLK High Rising Time: CSN,SCLK Falling Time: CSN,SCLK Symbol 1/tPSCLK tWSH tWSL tWCL tHCS tSCS
[AK2306/LV]
Units Fig4
Setup Time: DATA SCLK High Hold Time: SCLK High DATA Hold Time: SCLK High tSDC tHDC tHCS2 Fig4
Delay Time: SCLK DATA drive Delay Time: SCLK DATA valid Delay Time: SCLK DATA High-Z Delay Time: High DATA High-Z Pulse Width High tDDD tDVD tDZSD tDZCD tWCH Fig5 Fig6
MS0093-E-04
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tWCL
[AK2306/LV]
tHCS tWSH tWSL tPSCLK tHCS
SCLK
tHDC
DATA
Fig4 Serial Interface Timing
tWCL
<WRITE>
tHCS tWSH tWSL tPSCLK tHCS2
SCLK
tHDC tDDD tDVD
DATA
Fig5 Serial Interface Timing
tWCH
<READ>
SCLK
tDZSD tDZCD
DATA
Fig6 Serial Interface Timing <READ>
MS0093-E-04
2001/11
[AK2306/LV]
APPLICATION CIRCUIT EXAMPLE
Analog input circuit(AMPT0,1) AK2306/LV op-amp analog input each channel. Each op-amp used gain adjustment. Op-amp used inverting amplifier differential input buffer with AMPRn VREF buffer Feedback resistor must larger. Single buffer AK2306 GSXn (n=0,1) VFXn
C1=0.47uF R1=R2=33kohm
AMPTn BGREF
more than 1.0uF
Differential buffer
GSXn VFXn (n=0,1)
AMPTn C1=0.47uF R1=R2=33kohm
AMPRn Important Notice
BGREF
Please AMPRn AGND buffer avoid cross talk between channel1 channel2 when input composed differential input.
MS0093-E-04
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[AK2306/LV]
Analog output circuit(AMPR0,1) AK2306/LV op-amp analog output stage each channel consist inverting amplifier gain adjustment 0dBm0 level. Feedback resistor must 10kohm larger. AK2306 GSRn BGREF (n=0,1) R1=R2=33kohm GAnR VFRn
Important Notice
When AMPRn used AGND buffer, they used gain adjustment.
Analog ground stabilization capacitor external capacitor more than 1.0uF should connected between VREF stabilize analog ground (VREF).
AK2306/LV VREF
Loop filter capcitor external capacitor more than 0.22uF should connected between VSS.
AK2306/LV
Power Supply attenuate power supply noise, connect capacitors between VSS, shown below. AK2306/LV C1=C3=0.1uF C2=C4=10uF
MS0093-E-04
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[AK2306/LV]
PACKAGE INFORMATION
24pin VSOP Marking Date Code: digit XXXXX Marketing Code: AK2306/AK2306LV Logo
AK2306 XXXXX
AK2306LV XXXXX
MS0093-E-04
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PACKAGE SIZE
[AK2306/LV]
24pin VSOP (Unit:
*7.9±0.2
7.6±0.2 0.15+0.10 -0.05 0.10±0.05 Detail 0.5±0.2 0-10°
2001/11
0.65
0.12
0.22+0.10 -0.05
1.15±0.10 Seating Plane 0.08
NOTE: Dimension does include mold flash.
MS0093-E-04
[AK2306/LV]
IMPORTANT NOTICE These products their specifications subject change without notice. Before considering application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representative Director AKM. used here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product distributes, disposes otherwise places product with third party notify that party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification.
MS0093-E-04
2001/11

AK2306/2306LV Dual CODEC ISDN/VoIP TERMINAL ADAPTER GENERAL

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