Table Contents1. GENERAL DESCRIPTION FEATURES CONFIGURATION.3 DESCRIPT
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Preliminary W9321 ADPCM CODEC
Table Contents1. GENERAL DESCRIPTION FEATURES CONFIGURATION.3 DESCRIPTIONS 4.1. Power Control Interface.3 4.2. Analog Interface 4.3. ADPCM/PCM Serial Interface 4.4. Serial Setup Port(SSP) Interface SYSTEM DIAGRAM.6 Pair Gain System 5.2. Cordless Phone System BLOCK DIAGRAM.8 FUNCTIONAL DESCRIPTIONS 7.1. Power Supply Management System 7.2. 7.3. 7.4. 7.5. 7.6. Codec-Filter Engine Serial Setup Port (SSP).12 Sequence Control Level
CONTROL STATUS REGISTERS.14 8.1. Introduction.15 8.2. Byte Register Description ELECTRICAL CHARACTERISTICS 9.1. Absolute Maximum Ratings.24 9.2. Characteristics 9.3. Analog Transmission Characteristics.25 9.4. Analog Electrical Characteristics 9.5. Digital Switching Characteristics.27 APPLICATION INFORMATION.30 10.1. Handset Application Wireless Communication.30 10.2. Transformer Application Public Switching Telephone Network (PSTN).30 PROGRAM TONE GENERATOR 11.1. Introduction 11.2. Tone Frequency Coefficient Calculation.32 11.3. Tone Attenuation Coefficient Calculation 11.4. Frequency Coefficients DTMF Signal PACKAGE DIMENSIONS
Publication Release Date: 1999 Revision
Preliminary W9321
GENERAL DESCRIPTION
Winbond ADPCM Codec single channel chip incorporating codec filter with 32K, 24K, ADPCM encoder/decoder complying with CCITT G.721 G.726 standards. addition, this chip also meets conformance specification CCITT G.714 recommendation. This chip allows full-duplex operation over wide voltage range from 5.25 volts; it's power consumption makes ideal battery powered applications. chip includes serial setup port (SSP) interface with byte setup status registers. microcontroller access many built-in features through interface. addition, this chip also consists some amplifiers integrated with codec-filter allow easy control analog interface. This chip used applications. application wireless telephone systems such CT2, DECT. Another application public switch telephone network (PSTN) applications such pair gain. section application information more details.
FEATURES
Single 5.25 volt power supply Master clock rate: 10.24 oscillator typically Winbond cordless system Typical power consumption volt; power down Full-duplex single channel speech codec Linear codec-filter converter Complete Mu-Law A-Law companding ADPCM transcoder Kbps rates Serial PCM/ADPCM transfer data rate from 2048 Kbps Universal programmable dual tone generator such DTMF application Noise burst detection algorithm ADPCM receive path Analog input: differential amplifier with external gain adjustment microphone interface Programmable transmit gain, receive attenuation, sidetone gain Analog output:
Differential power driver with load external gain adjustment Differential auxiliary driver with load ringer interface
Volt regulator digital circuit Volt charge pump analog circuit voltage applications Setup status registers with bits monitoring microcontroller applications Packaged 28-pin DIP/SOP
Preliminary W9321
CONFIGURATION
TITI+ AXOAXO+ POPO+ PDI/RESET
BCLKR MCLK BCLKT
Figure
DESCRIPTIONS
4.1. Power Control Interface
NAME VEXT VDSP FUNCTION This external power supply between 5.25 volt. This should decoupled with capacitor. This output on-chip volt regulator which supplies digital circuit chip. This should decoupled with ceramic capacitor. This cannot used powering external loads. This output on-chip volt charge pump which supplies analog circuit. When VEXT ±5%, input should connected VEXT externally. Charge pump capacitor should used BR0[b2] must written into logic "1". this case VEXT share same decoupling capacitor VSS. When VEXT 5.25 volt, volt charge pump output should connected VEXT. should decoupled with capacitor. This cannot used powering external loads. This connects analog digital ground typically connected volt.
Publication Release Date: 1999 Revision
Preliminary W9321
4.1. Power Control Interface, continued
NAME
FUNCTION This analog ground output which supplies volt reference voltage analog signal processing. This should decoupled with capacitor. This becomes high impedance when chip enters analog power down mode. charge pump capacitor pins. When VEXT ±5%, these capacitors should used BR0[b2] must written into logic "1". When VEXT 5.25 volt, capacitor should placed between C1-. power down/reset input pin. When logic chip enters power down mode. When switches from logic logic this chip active resets ADPCM transcoder circuits.
C1+,
PDI/RESET
4.2. Analog Interface
NAME FUNCTION This analog output transmit input amplifier. used gain external resistors. When chip analog power down mode, this high impedance. This inverting input transmit input amplifier. Connecting this (pin-3) will force into high impedance state. non-inverting input transmit input amplifier. Connecting this (pin-2) will force high impedance. Note this connected inverting configuration input signal referenced pin. This non-inverting analog output receive smoothing filter. This typically drive load 1.13 volt peak referenced pin. This referenced either VEXT/2 determined (b7). When chip analog power down mode, this high impedance. This auxiliary inverting analog output. This drive load differentially. output swing between volt VEXT. This referenced either VEXT/2 (b7). When chip analog power down mode, this high impedance. This auxiliary non-inverting analog output. This drive load differentially. output swing between volt VEXT. This referenced either VEXT/2 (b7). When chip analog power down mode, this high impedance.
AXO-
AXO+
Preliminary W9321
4.2. Analog Interface, continued
NAME
FUNCTION This inverting input (pin-11) power amplifier. referenced either VEXT/2 (b7). This used gain using external resistors. Connecting this will power down chip outputs will high impedance. This inverting power amplifier output. operation same AXO- (pin-6). application, this drive speaker receiver. This non-inverting power amplifier output. operation same AXO+ (pin-7). application, this drive speaker receiver.
4.3. ADPCM/PCM Serial Interface
NAME MCLK FUNCTION This system master clock input pin. typically accepts 10.24 Winbond cordless applications. This oscillator input. This pulse train transmission frame syncs. This synchronizes output (pin-20). clock transmission. shifts data rising edge. frequency vary from 128K 2048 KHz. This tri-state output data transmission controlled BCLKT pin. This pulse train receive frame syncs. This synchronizes input (pin-25). This receive clock. shifts data into chip falling edge. frequency varies from 128K 2048 KHz. This receive input data controlled BCLKR pins.
BCLKT
BCLKR
4.4. Serial Setup Port(SSP) Interface
NAME FUNCTION This enable signal setup. This held select the16 control status registers. There timing controls. double transfer mode; other control single transfer mode. timing diagram, Figure 7-9, Section 7.4.
Publication Release Date: 1999 Revision
Preliminary W9321
Serial Setup Port(SSP) Interface, continued
NAME
FUNCTION This clock setup. Note that data shifted falling edge this pin, shifted into rising edge. frequency from 2048 KHz. This tri-state output data transmission controlled (pin-15). This receive input data controlled (pin-15).
SYSTEM DIAGRAM
Pair Gain System
Applications this device include public switching telephone system. such application pair gain system shown Figure 5-1. figure illustrates chip used pair gain system connect telephone system between users central office terminal These chips used devices installed both central office terminal (COT) remote office terminal (ROT). chip operating Kbps ADPCM mode, must four chips 4-channel communication because interface chip support channel, i.e., 128K bps. transmission path, telephone system first sends analog signal ADPCM chip compress into Kbps digital signal. interface then build 2B+D channel, Kbps, with four ADPCM chip channels, send Kbps digital signal COT. After receiving digital signal, interface separates Kbps data into four ADPCM channels Kbps) sends this data chip execute ADPCM decoder reconstruction into analog signal. analog signal then sent central office (CO) complete transmission operation. receive path reverse operation transmission path mentioned above. pair gain system, analog signal (voice signal, modem signal) digitized compressed ADPCM signal e.g. Kbps ADPCM. subscriber loop, connection between user central office, digitized interface transceiver. This provides B-channels Kbps) data channel signaling. short, data transmitted received subscriber loop interface transceiver. B-channel carry Kbps data, i.e. Kbps ADPCM channels. Therefore pair gain system supply four telephones.
Preliminary W9321
Remote Office Terminal (ROT)
Analog ADPCM Codec
Central Office Terminal (COT)
ADPCM Codec Analog
Centeral Office (CO)
Channel
Analog
ADPCM Codec interface 2B+D Interface Layer
ADPCM Codec Interfac Layer interface 2B+D
Analog
Channel
Analog
ADPCM Codec
ADPCM Codec
Analog
Channel
Micro-Controller
Micro-Controller
Analog
ADPCM Codec
ADPCM Codec
Analog
Channel
User Telephone System
Figure System Diagram Pair Gain Application
5.2. Cordless Phone System
Figure shows cordless phone system block diagram. transmission side, voice sent W9321 ADPCM Codec from external microphone. First, analog speech signal digitized into 14-bit linear signal compressed into Kbps ADPCM data. compressed signal then sent W9330F which provides baseband functions required Part compliant cordless phone. W9330 will generate spread spectrum binary sequence output modulator. microprocessor manages other functions cordless phone such keypad display control. receive side, WHT9362 Module converts received signal baseband. W9330 then performs de-correlation demoulation sends speech signal into W9321 ADPCM. W9321 then reconstructs digital speech signal into analog signal using ADPCM decoder before sending this analog signal speaker.
Antenna Microphon ADPCM Voice Codec W9321
Spread Spectrum Transceiver W9330F
Module WHT9362
Speaker
Microprocessor W921E880F
Figure System Diagram Cordless Phone Application
Publication Release Date: 1999 Revision
Preliminary W9321
BLOCK DIAGRAM
POPI AXO+ AXOTITI+
Codec-filter
Vref
Engine
Digital Gain ADPCM Decoder
BCLKR
Analog Smoothing Filter
Analog
Digital Demodulator
Digital Anti-Alias Intp. Filter
Atten. Control
NoiseBurst Detection
Sidetone Gain
Universal Tone Generator
Serial Data Port (SDP)
Gain Control
Analog Modulator
Digital Anti-aliasing Dec. Filter
BCLKT
Digital
Mu/A Expander Linear
ADPCM Encoder
2.5V Reference Voltage
Power Supply Management System
Mu/A Compressor
VEXT C1VDD VDSP
Charge-Pump volt Regulator Analog Processing
volt Regulator Digital Signal Processor
Serial Setup Port Bits Setup Status Registers
Sequence Control
MCLK
PDI/RESET
Figure Winbond ADPCM Codec Block Diagram
FUNCTIONAL DESCRIPTIONS
Figure illustrates functional blocks Winbond ADPCM codec. chip divided into four subsystems which described following subsections.
7.1. Power Supply Management System
this block groups comprise power supply management system. group 5-volt power supply system analog signal processing. second group 3-volt power supply system digital signal processing. 7.1.1. Power Supply Analog Signals Processing analog circuits except output power amplifiers supplied with 5-volt power. This voltage applied directly volt charge pump circuit. Note that power drivers powered VEXT which main positive power supply pin. When VEXT (e.g. base station applications) input should connected externally VEXT pin. charge pump capacitor should used BR0[b2] must logic disable charge pump circuit. this case VEXT share same decoupling capacitor VSS. When VEXT 5.25 volts (e.g. battery applications) volt charge pump circuit output should connected VEXT. should decoupled with capacitor. This cannot used powering external loads.
Preliminary W9321
7.1.2. Power Supply Digital Signals Processing digital circuits supplied VDSP from 3-volt regulator circuit. This reduces chip power consumption. Whatever value power supply VEXT, range from volts, digital circuits will always powered volt voltage supply. Note that VDSP should decoupled with capacitor that this cannot used powering external loads. 7.1.3. Reference Voltage Control System analog reference voltages such power amplifier AXO, volt VEXT/2 determined BR2(b7).
7.2. Codec-Filter
This device built linear 14-bit codec-filter using technology. There paths block, transmit path receive path. 7.2.1. Transmit Path Codec-Filter analog signal input, from microphone interface, passed three terminal operational amplifiers (TI+, TI-, driving typical load externally amplify input analog signal. analog signal then have further transmission gain from steps transmit gain control block. gain programmed through port BR1(b2:b0). modulator block oversamples analog signal 1.024 with resolution. next antialiasing decimation filter reduces sampling frequency from 1.024 bit) bit). Digital biquad filters perform decimation from CCITT low-pass filtering 3400 digital block performs high-pass filtering final step, conversed data sent transmit path engine further signal processing (e.g. ADPCM encoder). 7.2.2. Receive Path Codec-Filter 14-bit linear digital signal from Attenuation control block engine first passed digital anti-aliasing interpolation filter block. interpolation block performs reverse operation decimation filter (described above transmit path) sampling rate will increased from bits) 1.024 bits). digital demodulator will then reduce 14-bit samples (1.024 MHz) (1.024 MHz). digital output signal will passed 3400 switched capacitor low-pass filter with sin(x)/x correction analog smoothing filter reduce spectral components switched capacitor filter. Finally, analog output signal sent power amplifier, which capable driving load connected pin, high current analog output driver simultaneously with differential load. Note device provides another power amplifier, connected push-pull configuration. have different circuit configurations different applications. handset ringer applications, driver accommodate large gain ranges adjusting external resistors applications such driving telephone line handset receiver.
7.3. Engine
This block kernel ADPCM transcoder tone generator. There paths this block, transmit path receive path.
Publication Release Date: 1999 Revision
Preliminary W9321
7.3.1. Transmit Path Engine linear sample input from transmit path Codec-filter block sent three processing directions: sidetone gain process, Mu/A compressor/Linear, ADPCM encoder/ tone encoder. sidetone gain block, input sample fedback receive path summed with output digital receive gain. value kept -8.5 range port BR1(b6:b4).The output then saved linearly into BR9(b7:b0) BR10(b7:b2). ADPCM encoder/tone encoder provides Kbps, Kbps, Kbps ADPCM, Kbps respectively, determined length transmit frame sync (pin 18). length frame sync calculated number falling edges BCLKT when transmit frame sync high. Because frame sync clock KHz, encode interrupt performed once every default value transmit ADPCM will delayed frames after being requested, i.e. current frame request ADPCM operation, will computed next frame ADPCM result transmitted next frames. applications such signaling channel frame structure delay status configured total frames port BR7(b5). ADPCM output result will sent serial data port (SDP) output data rate from 2048 will controlled serial data port BCLKT pin. universal tone generator mode, input ADPCM encoder comes from output universal tone generator, from transmit path codec-filter. ADPCM encoder outputs tone ADPCM signal through 7.3.2. Receive Path Engine device receives data from serial data port (SDP) under control BCLKR pins. clock receive frame sync KHz. ADPCM decoder receives decode interrupt every serial data rate BCLKR 2048 range. input parameter data sent ADPCM decoder which also provides Kbps, Kbps, Kbps ADPCM Kbps PCM, determined length receive frame sync pin. length frame sync calculated number falling edges BCLKR when receive frame sync high. ADPCM decoder consists sync adjustment operation correction sync. tandem application, except when receive digital gain used handset application. digital receive gain programmed from through port BR3(b6:b0). order prevent noise from influencing result ADPCM decoder, noise burst detection algorithm enabled setting BR7(b6) register detect interfering sounds mute receive path. reconstructed linear will compressed Mu/A compressor block sent BR11 (b7:b0) port after sync. adjustment G.726 CCITT test mode. After control digital receive gain, synthesized data will added feedback signal transmit path sidetone gain block. value then passed attenuation control block protect output driver, from distortion when amplitude synthesis data large (e.g. battery applications). gain attenuation block programmed through (b2:b0) register port. receive attenuation range from programmed steps. device enables universal tone generator, function ADPCM decoder will disabled. Different tone types (i.e. tone tone programmed through BR7, BR4, registers port. tone generator used generate DTMF tones, different ringing tones, call progress tones handset applications. telephone line applications, this tone generator used signaling line.
Preliminary W9321
7.3.3. Frame Sync. Types frame sync operation uses industrial control types transfer ADPCM data words. These types long frame sync short frame sync. 7.3.3.1. Long Frame Sync long frame sync types various data rates shown Figure 7-4. rate ADPCM encoder decoder determined length frame sync (FST FSR). length frame sync calculated number falling edges BCLKT BCLKR when frame sync high. example, number falling edges BCLKT BCLKR equal when frame sync high, this corresponds Kbps rate encoder decoder ADPCM operation. number device becomes Kbps operation. device shifts data BCLKT rising edge shifts data BCLKR falling edge. length frame sync changed frame frame basis. 7.3.3.2. Short Frame Sync short frame sync types Kbps ADPCM timing shown Figure 7-5. rate this type frame performs only Kbps ADPCM encoding decoding. length frame sync equal device shifts data BCLKT rising edge shifts data BCLKR falling edge. Switching between long frame sync short frame sync without going through power down operation recommended.
(FSR) BCLKT (BCLKR)
Don't Care
Don't Care
Figure Long Frame Sync Kbps ADPCM Timing
(FSR) BCLKT (BCLKR)
Don't Care
Don't Care
Figure Long Frame Sync Kbps ADPCM Timing
Publication Release Date: 1999 Revision
Preliminary W9321
(FSR) BCLKT (BCLKR)
Don't Care
Don't Care
Figure Long Frame Sync Kbps ADPCM Timing
(FSR) BCLKT (BCLKR)
Don't Care
Don't Care
Figure Long Frame Sync Kbps ADPCM Timing
(FSR) BCLKT
Don't Care
(BCLKR)
Don't Care
Figure Short Frame Sync Kbps ADPCM Timing
7.4. Serial Setup Port (SSP)
W9321 sixteen 8-bit wide setup status registers, BR0-BR15, controlling monitoring functions serial setup port (SSP). used external microcontroller such Winbond W921E880F. full-duplex four wire interface (marked CLK, communicating with external micro-
Preliminary W9321
controller. timing controls, double 8-bit transfer mode single 16-bit transfer mode, available when held select setup registers. data rate ranges from 2048 KHz. data shifted port falling edge CLK, shifted into port rising edge CLK. This latch operation reverse serial data port engine. byte registers selected bits first byte from shown Figure 7-9. first byte indicates whether status read (logic write (logic second byte data word (D7:D0). description setup status registers, BR0-BR15 described greater detail next section (Control Status Registers).
High Impedence
Don't Care
Don't Care
Don't Care
Figure Double Write Operation Register
Don't Care
Don't Care
Figure Double Read Operation Register
High Impedence
Don't Care
Don't Care
Figure Single Write Operation Register
Publication Release Date: 1999 Revision
Preliminary W9321
Don't Care
Don't Care
Figure Single Read Operation Register
7.5. Sequence Control
This block generates some internal clocks, providing clocks such 1.024 codec-filter operation. master clock MCLK, which supports clock engine, asynchronous other blocks. frequency typically 10.24 cordless applications using Winbond chips. codec-filter BCLKR direct 1.024 input. rising edge this input clock must approximately aligned with rising edge FST. This mode requires that ADPCM transmit receive controlled BCLKT pin. This configured port through BR0(b7) register. There ways forcing device into power consumption condition power down mode. hardware power down mode where PDI/RESET held logic other software power down mode where register BR0(b1:b0) through SSP. When BR0(b1) setting initiates analog power down, clocks analog signal processing will halted. initiate digital power down, BR0(b0) register programmed logic halt clocks digital signal processing. When chip powered down, VAG, AXO, outputs high impedance. When power reactivated from power down mode, ADPCM algorithm reset CCITT initiate state.
7.6. Level
Digital device programmed either Mu-law A-law. Full scale zero words these log-PCM forms shown Table 7-1. analog signal processing, maximum transmit level 3.17 dBm0 Mu-Law 3.14 dBm0 A-Law. These values meet CCITT G.711specifications. MU-LAW Level max. scale +Zero Zero max. scale Sign Segment Bits Step Bits 0000 1111 1111 0000 Sign A-LAW Segment Bits Step Bits 1010 0101 0101 1010
Table Full Scale Zero Word Mu/A-Law
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CONTROL STATUS REGISTERS
8.1. Introduction
There available byte setup status registers port. functional description read/write status each illustrated sections that follow. read write status described Table indicated symbol SYMBOL ro/wo TYPE Read/Write Read Only MEANING Data read from port written into port micro-processor
Data only read from port. Writing this port effect. Read Only/Write Only Data read written external micro-processor internal chip simultaneously. value written into read back external micro-controller
Table Read/Write Status Description Byte Register
8.2. Byte Register Description
There byte registers controlling monitoring status chip. These registers labeled BR15. descriptions follows. Note that "setting" corresponding logic "clearing" corresponding logic "0".". 8.2.1. Byte Register (BR0) This control register. bits cleared when PDI/RESET logic zero. Function Mode Select[0] Charge Pump Disable Analog Power Down Digital Power Down
Function 1024 Mu/A Analog Mode Select Loopback Select[1] Clock
External 1024 Clock (b7): This controls mux. When this cleared, selects 1024 clock from internal clock generator. When this set, BCLKR used provide external 1024 clock internal BCLKR connected BCLKT; BR0[b1] must reset codec. Mu/A (b6): When this logic zero, device selects Mu-Law companding Log-PCM. Setting this selects A-Law companding Log-PCM. Analog Loopback (b5): Setting this causes analog loopback from receive path transmit path. Internally output receive path routed transmit gain control transmit path; op-amp bypassed.
Publication Release Date: 1999 Revision
Preliminary W9321
Mode Select[1:0] (b4:b3): function modes shown Table 8-2. ADPCM Codec mode performs combination codec ADPCM transcoder full duplex. codec mode subset ADPCM codec mode, where only codec executed. CCITT test mode uses CCITT ADPCM test vectors conformance testing. Enabling this mode will remove codec-filter operation. test vectors through port BR9[b7:b0] BR10[b7:b0]. BR10 descriptions more details. battery test mode allows testing voltage present VEXT pin. this mode, output register BR8[b4] must disabled. Note that steady linear code VEXT will delayed about samples. output result linear bits stored registers BR10. FUNCTION MODE SELECT[1:0] (B4:B3) TYPE ADPCM Codec Codec CCITT Test Battery Test
Table Function Mode Selection
Charge Pump Disable (b2): Setting this disables volt charge pump. this mode, charge pump capacitor should used should connected externally VEXT pin. Analog Power Down (b1): Setting this causes analog power down. this mode, clocks analog processing (e.g. codec) will halted reduce power consumption. analog circuit will operate normally until this cleared. Digital Power Down (b0): Setting this causes digital power down. this mode, clocks digital processing (e.g. engine) will halted reduce power consumption. digital circuit ADPCM initialization will operate until this cleared. 8.2.2. Byte Register (BR1) This register controls sidetone gain value transmit gain. This register also mute transmit signal. bits cleared when PDI/RESET logic zero. Reserved Sidetone Gain[2] Reserved (b7): This reserved. Sidetone Gain[1] Sidetone Gain[0] Transmit Mute Transmit Gain[2] Transmit Gain[1] Transmit Gain[0]
Preliminary W9321
Sidetone[2:0] (b6:b4): These three bits control sidetone attenuation. sidetone attenuation range from -8.5 shown Table 8-3. Transmit Mute (b3): Setting this will mute transmit path codec-filter block. send zero sent engine further processing. Transmit Gain (b2:b0): These three bits control transmit gain control shown Table 8-4. gain range range steps. SIDETONE[2] (B6) SIDETONE[1] (B5) SIDETONE[0] (B4)
Table Sidetone Attenuation
SIDETONE ATTEN. (DB) -21.5 -18.0 -15.0 -13.5 -11.5 -10.5 -8.0
TRANSMIT GAIN[2] (B2)
TRANSMIT GAIN[1] TRANSMIT GAIN[0] (B1) (B0)
Table Transmit Gain Control
TRANSMIT GAIN CONTROL(DB) +1.5 +6.8
Publication Release Date: 1999 Revision
Preliminary W9321
8.2.3. Byte Register (BR2) This register controls operations receive path code-filter block. bits cleared when PDI/RESET logic zero. Reference Point Select Enable Disable Reserved Mute Receive Atten.[2] Receive Atten.[1] Receive Atten.[0]
Reference Point Select (b7): This determines reference voltage power amplifiers such AXO, output reference voltage. Setting this sets reference voltage volts. When this cleared, reference voltage default value VEXT/2. Enable (b6): This determines status power amplifier AXO. Setting will enable operation amplifier. When this cleared, amplifier will disabled default. power down mode, output pins high impedance. Disable (b5): This determines status power amplifier Setting will disable operation amplifier. When this cleared, amplifier enabled default. power down mode, output pins high impedance. Reserved (b4): This reserved. Mute (b3): Setting this will force input amplifier ground. remains offset order avoid audible pops" when turning block off. Receive Attenuation[2:0] (b2:b0): These three bits control receive attenuation shown Table 8-5. attenuation range from steps. RECEIVE ATTEN.[2] (B2) RECEIVE ATTEN.[1] RECEIVE ATTEN.[0] RECEIVE ATTENUATION (B0) (DB)
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Continued
RECEIVE ATTEN.[2] (B2) RECEIVE ATTEN.[1]
RECEIVE ATTEN.[0] (B0)
RECEIVE ATTENUATION (DB)
Table Receive Attenuation Control
8.2.4. Byte Register (BR3)
Digital Gain Enable Dig. Gain[6] Dig. Gain[5] Dig. Gain[4] Dig. Gain[3] Dig. Gain[2] Dig. Gain[1] Dig. Gain[0]
This register contains information digital receive gain. bits cleared when PDI/RESET logic zero. Digital Gain Enable (b7): Setting this will enable digital receive gain routine engine. receive gain programmed setting gain factors defined this register BR3[B6:B0]. When this cleared, digital receive gain routine disabled. Digital Gain[6:0](b6:b0): These seven bits show value digital receive gain factor. gain value calculated follows: +1/16 +1/32 first bits (b6:b5) integers last five bits fractions. decimal point placed after gain range 8.2.5. Byte Register (BR4)
TonePar[7] TonePar[6] TonePar[5] TonePar[4] TonePar[3] TonePar[2] TonePar[1] TonePar[0]
This register holds parameters tone generator. bits cleared when PDI/RESET logic zero. Tone Generator Parameters[7:0](b7:b0): These seven bits contain eight frequencies tone generator attenuation coefficients. tone generator enabled when BR7[b3] register four tone parameters placed BR5[b3:b0]. Switching between frequency attenuation factor determined BR5[b7:b6] register.
Publication Release Date: 1999 Revision
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8.2.6. Byte Register (BR5) This register holds parameters noise burst detection tone generator. noise burst detection tone generator modes enabled through BR7(b3) register. bits cleared when PDI/RESET logic zero.
Thd[7]/ ToneAddr[1] Thd[6]/ ToneAddr[0] Thd[5]/ Don't Care Thd[4]/ Don't Care Thd[3]/ TonePar[11] Thd[2]/ TonePar[10] Thd[1]/ TonePar[9] NBThd[0]/ TonePar[8]
Noise Burst Detect Threshold[7:0] (b7:b0): When device noise burst detection mode (i.e. BR7[b3] BR7[b6] these eight bits contain threshold noise burst detection. detected algorithm frequency value decide whether noise present not. suggest threshold value greater than written decimal format, i.e. above). Tone Generator Address[1:0](b7:b6): When tone generator enabled, (i.e. BR7[b3] these bits programmed select frequency attenuation factor shown Table 8-6. Tone Generator Parameters[11:8](b3:b0): These four bits contain four frequencies tone generator attenuation coefficients. tone generator enabled when (b3) register last eight LSBs placed BR4[b7:b0] register. Switching between frequency attenuation factor determined
TONE ADDRESS[1] (B7) TONE ADDRESS[0] (B6)
Table Tone generator Address Parameters
TONE PARAMETER SELECTION Frequency Tone Attenuation Tone Frequency Tone Attenuation Tone
8.2.7 Byte Register (BR6)
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
This register reserved. user should read write this register. 8.2.8. Byte Register (BR7) This register used enable noise burst detection tone generator. Additional options include frame delay writing ready status registers. bits cleared when PDI/RESET logic zero.
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Ready
Detect Enable ro/wo
Delay
Don't Care
Tone Gen. Enable
Reserved
Tone1 Enable
Tone Enable
Ready Writing (b7): This read-only indicates whether parameters have been written into register. This after writing BR5. This cleared when internal Engine reads from registers. Noise Burst Detect Enable (b6): This read-only/write-only bit. Setting this enables noise burst detection routine. noise detected, this cleared polled external micro-controller. This mutes receive path. Delay (b5): This controls frame delay status. Setting this inserts 6-frame delay between frame control changes. Clearing this inserts 2-frame delay between frame control changes. Don't Care (b4): effect whenever read written external micro-controller. Tone Generator Enable (b3): Setting this performs tone generator routine instead ADPCM decoder. addition, noise burst detection will disabled. result tone generator will passed ADPCM encoder compress tone transmit encoded result pin. Reserved (b2):
This reserved.
Tone Enable (b1): Setting this enables tone routine tone generator. When this cleared, tone1 routine disabled. Tone Enable (b0): Setting this enables tone routine tone generator. When this cleared, tone routine disabled. DTMF enabled, user must tone tone enable. 8.2.9. Byte Register (BR8) This register contains miscellaneous control bits. bits cleared when PDI/RESET logic zero.
Publication Release Date: 1999 Revision
Preliminary W9321
Encoder Reset Decoder Reset Linear Codec Mode Disable Reserved Reserved Reserved Reserved
Software Encoder Reset (b7): Setting this forces device execute ADPCM encoder initialization every time encoder receives interrupt. Software Decoder Reset (b6): Setting this forces device execute ADPCM decoder initialization every time decoder receives interrupt. Linear Codec Mode (b5): Setting this forces device perform linear codec. linear converted output from codec-filter will truncated this mode. Disable (b4): Setting this will disable high pass filter (HPF) transmit path applications such battery test mode BR0[b4:b3] "11"". Reserved (b3:b0): These bits reserved should used user. CAUTION: Reserved bits (b3:b0) must zero times normal operation. 8.2.10. Byte Register (BR9)
PCM[7]/ Linear PCM[13] ro/wo PCM[6]/ Linear PCM[12] ro/wo PCM[5]/ Linear PCM[11] ro/wo PCM[4]/ Linear PCM[10] ro/wo PCM[3]/ Linear PCM[9] ro/wo PCM[2]/ Linear PCM[8] ro/wo PCM[1]/ Linear PCM[7] ro/wo PCM[0]/ Linear PCM[6] ro/wo
This register contains value transmit path. value comes from transmit path codec-filter, then internally written into most siginificant bits linear (b13:b6). device applications such CCITT test mode i.e. BR0[b4:b3] "10" then read companding Log-PCM from external micro-controller used ADPCM encoder. linear mode, stored into this register left will placed BR10[b7:b2]. description BR10 more details. Note that this register read-only/write-only.
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8.2.11. Byte Register (BR10)
Encoder BR10 Linear PCM[5] Encoder Linear PCM[4] Encoder Linear PCM[3] Encoder Linear PCM[2] Encoder Linear PCM[1] Encoder Linear PCM[0] Reserved Reserved
This register contains linear value transmit path. value must come from transmit path codec-filter from external micro-controller. left stored into BR9[b7:b0]. description more details. Note that this register read-only. 8.2.12. Byte Register (BR11)
LogBR11 PCM[7]/ PCM[13] LogPCM[6]/ PCM[12] LogPCM[5]/ PCM[11] LogPCM[4]/ PCM[10] LogPCM[3]/ PCM[9] LogPCM[2]/ PCM[8] LogPCM[1]/ PCM[7] LogPCM[0]/ PCM[6]
This register contains value receive path. value comes from companding Log-PCM generated sync adjustment block decoder CCITT test mode, i.e. (b4:b3) logic "10". Note that, this register read-only. combined BR11 (b7:b0) BR12 (b7:b2) value same sending converter 8.2.13. Byte Register (BR12)
BR12 PCM[5] PCM[4] PCM[3] PCM[2] PCM[1] PCM[0] Reserved Reserved
This register contains linear value converter. value cannot entered external microcontroller. left stored into BR11[b7:b0]. description BR11 more details. Note that this register read-only. 8.2.14. Byte Register (BR13)
BR13 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
This register reserved should used user. Publication Release Date: 1999 Revision
Preliminary W9321
8.2.15. Byte Register (BR14)
BR14 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
This register reserved should used user. 8.2.16. Byte Register (BR15) This register shows version number this device.
Reserved BR15 Reserved Reserved Reserved Vers.[3] Vers.[2] Vers.[1] Vers.[0]
Version[3:0] (b3:b0): These four bits determine manufacturing version number this chip.
ELECTRICAL CHARACTERISTICS
9.1. Absolute Maximum Ratings
(Voltage Referenced pin)
PARAMETER Power Supply Voltage Analog Input/Output Voltage Digital Input/Output Voltage Operating Temperature Storage Temperature
SYMBOL VEXT, -TOP TSTG
RATING -0.3 -0.3 -0.3 VEXT
UNIT
Note: Exposure conditions beyond those listed under Absolute Maximum Ratings adversely affect life reliability device.
9.2. Characteristics
(VSS volt +85°
PARAMETER Operating Voltage Operating Current
SYM. VEXT IEXT
CONDITION MCLK 10.24 MHz, Charge Pump load MCLK digital input pins digital input pins
MIN.
TYP.
MAX. 5.25
UNIT
Power Down Current Input High Voltage Input Voltage
IPWDN
-VEXT -0.5
-0.5
Preliminary W9321
9.2. Characteristics, continued
PARAMETER Output High Voltage Output Voltage Input High Current Input Current Input Capacitance
SYM.
CONDITION VEXT VEXT digital input pins
MIN. VEXT -0.5
TYP.
MAX. -0.4
UNIT
9.3. Analog Transmission Characteristics
(VDD ±5%, volt +85° analog signal referenced VAG; Kbps PCM; KHz; BCLKT BCLKR 2.048 MHz; MCLK 10.24 Unless otherwise noted)
9.3.1. Amplitude Response Analog Transmission Performance
PARAMETER SYM. CONDITION TYP. TRANSMIT MIN. Absolute Level Max. Transmit Level Frequency Response, Relative dbm0 1020 LABS TXMAX GRTV dBm0 3000 3300 3400 4000 4600 100, Gain Variation Level Tone (1020 relative dBm0) dBm0 dBm0 dBm0 0.776 1.579 -1.0 -0.20 -0.35 -0.8 -0.3 -1.0 -1.6 MAX. +0.15 +0.15 +0.3 +1.0 +1.6 RECEIVE MIN. -0.5 -0.5 -0.5 -0.5 -0.20 -0.35 -0.8 -0.2 -0.4 -0.8 MAX. +0.15 +0.15 +0.2 +0.4 +0.8 Vrms UNIT
9.3.2. Distortion Characteristics Analog Transmission Performance
PARAMETER SYM. CONDITION TYP. TRANSMIT MIN. Absolute Group Delay DABS 1600 -MAX. RECEIVE MIN. -MAX. UNIT
Publication Release Date: 1999 Revision
Preliminary W9321
9.3.2. Distortion Characteristics Analog Transmission Performance, continued
PARAMETER
SYM.
CONDITION
TYP.
TRANSMIT MIN. MAX.
RECEIVE MIN. MAX.
UNIT
Group Delay Referenced 1600
DRTV
1000 1000 1600 1600 2600 2600 2800 2800 3000
Total Distortion Level Tone (1020 Mu-Law, CMessage)
dBm0 dBm0 dBm0 dBm0
9.3.3. Noise Characteristic Analog Transmission Performance
PARAMETER SYM. CONDITION TYP. TRANSMIT MIN. Idle Channel with Equipment Noise Spurious Out-of-Band SPKO (300 3400 dBm0) In-Band Spurious (1020 dBm0) Crosstalk (1020 dBm0) NCTK 3000 NIBS NIDE NSPO Mu-Law, C-Message 4600 7600 7600 8400 8400 100,000 3000 -MAX. RECEIVE MIN. -MAX. dBrn UNIT
9.4. Analog Electrical Characteristics
Amplifer Power Amplifer AXO, ±5%, +85°
PARAMETER Input Offset voltage Input Common Mode Voltage Load Capacitance Load Resistance Output Voltage
SYM. VOFIN VCMV CLRO
CONDITIONS TI+, TITI+, TIRO
MIN. -1.0
TYP. -2.5
MAX. -2.0 -2.6
UNIT
Preliminary W9321
9.4. Analog Electrical Characteristics, continued
PARAMETER Power Supply Rejection Ratio 100m Vrms with C-Message) Load Capacitance AXO,
SYM. PSRRdd
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Clap
AXO- AXO+;
Load Resistance differentially AXO, Input Offset Voltage
Rldap
AXO- AXO+;
-±25
Vofpi
9.5. Digital Switching Characteristics
9.5.1. Characteristic Serial Data Port Long Frame Short Frame
(VEXT +2.7 5.25V digital circuits referenced VSS; +85°
PARAMETER Master Clock Frequency Clock Frequency Frame Sync. Frequency Clock Duty Cycle Rise Time Fall Time Frame Sync. Pulse Width Transmit Sync. Timing Receive Sync. Timing Setup Time Valid Hold Time Valid Output Delay Time Valid Output Delay Time High Impedance
SYM. TMAST TBCLK TSYNC TFSP TSTDR THDDR TDHI
CONDITIONS MCLK BCLKT, BCLKR FST, MCLK, BCLKT, BCLKR digital input pins digital input pins FST, BCLKT BCLKT BCLKR BCLKR BCLKT BCLKT
MIN. 10.232 -100
TYP. 10.240
MAX. 10.247 2048 -140
UNIT
Note: these parameters shown Figure 9-2.
Publication Release Date: 1999 Revision
Preliminary W9321
tmast
MCLK
tfsp tsync
BCLKT
tdhi
tfsp
tsync
BCLKR
tstdr
thddr
Figure Long Frame Sync, Timing
tfsp
tsync
BCLKT
tdhi
tfsp
tsync
BCLKR
tstdr
thddr
Figure Short Frame Sync, Timing
Preliminary W9321
9.5.2. Characteristic Serial Setup Port (SSP)
tcditdic tenc
tdhc tcen tsspc trvb trva tdvc
R/Wb7
Figure Serial Setup Port (SSP) Timing
(VEXT +2.7 5.25V Digital Circuit Referenced +85°
PARAMETER Clock Frequency Clock Duty Cycle Enable Timing Valid Timing Output Delay Time Valid Output Delay Time High Impedance Disable Timing
SYM. TSSPC DSSP TENC TCEN TRVB TRVA TDVC TDHC TCDI TDIC
CONDITIONS SSPEN Setup Time Hold Time Rising
MIN.
TYP.
MAX. 2.048 -140
UNIT
Note: parameters shown Figure 9-3.
Publication Release Date: 1999 Revision
Preliminary W9321
APPLICATION INFORMATION
10.1. Handset Application Wireless Communication
wireless handset applications, VEXT supplied from 5.25 volt battery power supply. Meanwhile pin, connected with capacitor ground, volt output should connected VEXT. VDSP pin, connected with capacitor ground, volt output. VDSP pins should used supply external systems. chip must also enable charge pump clearing BR0[b2] port. output power amplifier pins drive receiver speaker. ringer driven differential power amplifier outputs AXO- AXO+. input transmitter amplifier from microphone output. application circuit, Figure 10-1 follows.
Battery Power ADPCM Chip Microphone TITI+ AXOAXO+ Battery Power VDSP VEXT Receiver Speaker POPO+ PDI/RESET BCLKR C1Vss MCLK (SCP) BCLKT Micro-Controller
System Clock 10.24
ADPCM Data Input
Ringer Speaker
ADPCM Data Output 2048 Data Rate Frame Sync. Input
Figure 10-1 Typical Handset Application
10.2. Transformer Application Public Switching Telephone Network (PSTN)
this application, VEXT ±5%, input should connected VEXT externally. charge pump capacitor should used device must disable charge pump circuit setting BR0[b2]. Here VEXT share same capacitor. transmitter TI-, receiver PO-, connected secondary terminal telephone line transformer. application circuit, Figure 10-2 follows.
Preliminary W9321
Battery Power
ADPCM Chip TITI+
BCLKR C1Vss MCLK (SCP) BCLKT icro-Controller
System Clock 10.24
ADPCM Data Input N.C. N.C.
N.C. N.C.
AXOAXO+ VDSP VEXT
ADPCM Data Output 2048 Data Rate Frame Sync. Input
Ring
POPO+ PDI/RESET
Figure 10-2 Typical Transformer Application
PROGRAM TONE GENERATOR
11.1. Introduction
chip enable tone generator setting BR7(b3) logic "1". Under this operation, ADPCM decoder will disabled. tone generator implemented engine based function os(nx)". procedure programming W9321 tone generator follows. Setting BR7(b3) logic turns tone generator. addition, BR7(b1:b0) must logic avoid turning tone1 tone2, without first programming coefficients freqency attenuation. Setup 12-bit coefficients freqency attenuation once every cycle(125 µs). First least significant bits(LSB) 12-bit coefficients must written into BR4(b7:b0); then most significant bits(MSB) 12-bit coefficients address parameter will written into BR5(b3:b0) BR5(b7:b6) simultaneously same cycle. Poll BR7(b7) until BR7(b7) becomes logic before writing another 12-bit coefficent BR5. BR7(b1:b0) logic selects tone tone2 generator.
Publication Release Date: 1999 Revision
Preliminary W9321
11.2. Tone Frequency Coefficient Calculation
tone frequency coefficient calculated function "cos(2*PI*f/8000 radian)" where 3.14159, frequency (Hz). number will then converted into 12-bit coefficient whose sign whose remaining bits fractional part found multiplying 2048 rounding number. example, frequency 1209 frequency number followed. (2*3.14159*1209/8000) 0.582053 converted binary number 010010101000 number 4A8, where
11.3. Tone Attenuation Coefficient Calculation
tone attenuation coefficient calculated function "x/1.579 where amplitude (Vp). number will converted into 12-bit coefficient whose sign whose remaining bits fractional part, found multiplying 2048 rounding number. example, attenuation (600 first change units into format follows. sqrt[10*exp(-14/10)*600*0.001] sqrt(2) 0.218570 attenuation "0.218570/1.579 0.138423" binary number 000100011011 number where
11.4. Frequency Coefficients DTMF Signal
Table 11-1 shows 12-bit frequency coefficients DTMF signal. least significant bits stored BR4(b7:b0), most significant bits stored BR5(b3:b0). Table 11-2 illustrates 12-bit attenuation coefficients DTMF signal such (600 (600 column tone (600 (600 tone.
FREQENCY (HZ) 1209 1336 1477 1633 (HEX) (HEX)
Table 11-1 Frequency Coefficients DTMF Signal
ATTENUATION (DBM@600
PEAK VALUE (VP) 0.308738 0.388679 0.436105 0.549023
(HEX)
(HEX)
Table 11-2 Attenuation Coefficients DTMF Signal
Preliminary W9321
PACKAGE DIMENSIONS
Figure12-1 28-Lead Plastic Package
There packages W9321. 28-lead plastic shown Figure 12-1, other 28-lead plastic shown 12-2.
SYMBOL DIMENSION INCH 0.110 Max. 0.004 Min. 0.093 ±0.005 0.016 +0.004 -0.002 0.010 +0.004 -0.002 0.705 TYP. (0.725 Max.) 0.295 ±0.005 0.050 ±0.006 0.370 Nom. 0.406 ±0.012 0.036 ±0.006 0.055 ±0.006 0.043 Max. 0-10 degree DIMENSION 2.794 Max. 0.102 Min. 2.362 ±0.127 0.406 +0.102 -0.051 0.254 +0.102 -0.051 17.90 TYP. (18.415 Max.) 7.493 ±0.127 1.270 ±0.152 9.396 Nom. 10.312 ±0.305 0.914 ±0.203 1.397 ±0.203 0.102 Max. 0-10 degree
Publication Release Date: 1999 Revision
Preliminary W9321
Base Plane Seating Plane
Figure12-2 28-Lead Plastic Package
SYMBOL
DIMENSION INCH 0.210 Max. 0.010 Min. 0.155 ±0.005 0.018 +0.004 -0.002
DIMENSION 5.334 Max. 0.254 Min. 3.937 ±0.127 0.457 0.102 0.051 1.524 +0.102 -0.051 0.254 +0.102 -0.051 37.084 TYP. (37.33 Max.) 15.24 ±0.254 13.843 ±0.127 2.540 ±0.254 3.302 ±0.254 16.51 ±0.508 2.286 Max. 0-15 degree
0.06 0.004 0.002
0.01 0.004 0.002
1.46 TYP. (1.47 Max.) ±0.01 0.545 ±0.005 0.100 ±0.01 0.130 ±0.01 0.650 ±0.02 0.09 Max. 0-15 degree
Preliminary W9321
Headquarters
Creation III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792697 http://www.winbond.com.tw/ Voice Fax-on-demand: 886-2-7197006
Winbond Electronics (H.K.) Ltd.
803, World Trade Square, Tower Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2730 Orchard Parkway, Jose, 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, 115, Sec. Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502
Note: data specifications subject change without notice.
Publication Release Date: 1999 Revision
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