8kHz 48kHz POWER STEREO AUDIO WITH INTEGRATED POWER AMPLIFIERS VOICE C
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STw5094
8kHz 48kHz POWER STEREO AUDIO WITH INTEGRATED POWER AMPLIFIERS VOICE CODEC
FEATURES: Complete STEREO AUDIO FILTERS including: DIGITAL ANALOG CONVERTERS. LINEAR PHASE DIGITAL FILTERS. ACTIVE LINEAR PHASE SMOOTHING FILTER. LOAD STEREO HEADPHONES DRIVERS, LOAD MONO LOUDSPEAKER DRIVER GROUP LISTENING. Stereo Audio Features: MULTIBIT MODULATOR WITH DATA WEIGHTED AVERAGING DAC. DYNAMIC RANGE, 0.01% OVER LOAD PERFORMANCE. SUPPORTS MPEG SAMPLING FREQUENCIES EXTENSION MPEG 2.5: 11.025, 22.05, 44.1, kHz. TONES FROM TONE GENERATOR INJECTED AUDIO PATHS. Stereo Headphones Loudspeaker/Earpiece Power Amplifiers features Stereo Input Radio Features: 20kHz BANDWIDTH STEREO HEADPHONES OUTPUTS. DRIVING CAPABILITY: 20mW (TYP. 0.1% T.H.D) OVER WITH RANGE PROGRAMMABLE GAIN. BALANCED EARPIECE LOUDSPEAKER OUTPUT. DRIVING CAPABILITY: 190mW (TYP. 0.1% T.H.D) OVER WITH 30dB RANGE PROGRAMMABLE GAIN. ANALOG STEREO INPUT RADIO WITH RANGE PROGRAMMABLE GAIN. Complete CODEC FILTER system including: LINEAR DAC. COMPANDED A-LAW µ-LAW. TRANSMIT RECEIVE DIGITAL BAND-PASS FILTERS. ACTIVE ANTIALIAS SMOOTHING FILTERS. LOAD EARPIECE/LOUDSPEAKER DRIVER, LOAD AUXILIARY DRIVER.
TFBGA pins) ORDERING NUMBER: STw5094
Voice CODEC Features: SUPPORT BOTH 8kHz 16kHz SAMPLING RATE. MICROPHONE BIASING OUTPUT. REMOTE CONTROL FUNCTION. LINE INPUT SWITCHABLE MICROPHONE AMPLIFIER INPUTS. 42.5dB RANGE PROGRAMMABLE GAIN. TRANSIENT SUPRESSION DURING POWER POWER DOWN. INTERNAL PROGRAMMABLE SIDETONE CIRCUIT. INTERNAL RING, TONE DTMF GENERATOR. PROGRAMMABLE BUZZER DRIVER. General Features: SINGLE 2.7V 3.3V SUPPLY. EXTENDED TEMPERATURE RANGE OPERATION -40°C 85°C. STANDBY POWER (TYP. 2.7V). OPERATING POWER AUDIO LISTENING MODE (TYP. 2.7V). OPERATING POWER VOICE CODEC MODE (TYP. 2.7V). 1.8V 3.3V CMOS COMPATIBLE DIGITAL INTERFACES. PROGRAMMABLE INTERFACE. COMPATIBLE CONTROL INTERFACE. PROGRAMMABLE SERIAL AUDIO DATA INPUT INTERFACE (I2S OTHER FORMATS).
Functionality guaranteed range 40°C +85°C; Timing Electrical Specifications guaranteed range 30°C +85°C.
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APPLICATIONS: CDMA,GSM,DCS1800,PCS1900,JDC DIGITAL CELLULAR TELEPHONES WITH RADIO STEREO LISTENING FUNCTIONS. PORTABLE DEVICES WITH STEREO DIGITAL AUDIO SOURCE RADIO LISTENING FUNCTION. GENERAL DESCRIPTION STw5094 power Stereo Audio device with Headphones Amplifiers high quality radio listening. STw5094 includes also high performance power combined CODEC FILTER tailored implement audio front-end functions required voltage power consumption digital cellular terminals with added radio listening. STw5094 offers number programmable functions accessed through I2C-bus compatible interface. STw5094 Stereo Audio section suited MP3, other audio stereo source, listening. supports rates from 8kHz 48kHz. audio data serial interface compatible programmed handle word length input data. internal converters work with input resolution. CONNECTIONS (Top view)
MIC2N
Stereo Headphones drivers also used Radio listening auxiliary stereo analog input. Loudspeaker driver also used monophonic group listening. STw5094 Voice Codec section configured either 14-bit linear 8-bit companded coder. Frame Synchronism frequency Voice Codec either standard 8kHz value extended 16kHz one. addition Stereo Audio CODEC FILTER functions, STw5094 includes Tone Ring DTMF generator that used both Audio Listening mode Voice Codec mode, sidetone generation, buzzer driver output remote control function tailored handle external on-hook off-hook button. STw5094 Voice Codec fulfills exceeds CCITT recommendations ETSI requirements digital handset terminals. Stereo Audio part fulfills exceeds requirements quality radio quality listening. Main applications include digital mobile phones, cellular cordless phones, with added low-power high-quality radio listening features, battery powered equipment that requires Stereo Audio with Headphones drivers operating single supply voltage.
MCLK
MIC2P REMOUT
MIC1P MIC1N MBIAS
MIC3 VCCA CAP2 REMIN AUXCLK LRCK
GNDA GNDCM VCCIO
GNDP
VCCP
TFBGA 6x6x1.2 Pin)
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VCCA
GNDA
VCCP
GNDP
GNDCM
VCCIO
MIC1P AUXCLK 0:22.5
MIC1N
MIC2P 0/20dB Gain. Remocon Voice PreAmp Anti Alias Filter Channel Filter
MIC2N
REMOUT REMIN 0:-27 Tone Generator -12:-27 Tone Att.
FUNCTIONAL BLOCK DIAGRAM
MIC3
Buzzer
MCLK
MBIAS
Bandgap
Mic. Bias
SideTone Gain
CAP2
Voice Mode Mode Analog Filter
+18:-20 Step Channel Filter
PreAmp
+18:-20 Step
Reset
Power
PreAmp
Control Logic
Registers
0:-40 Audio Mode Analog Filter Voice Mode
Transient
Mute
Left Driver
Suppression Filter
Modulator
Interpolation Filter
LRCK
+6:-24
Diff Driver Voice Mode
Transient
Suppression Filter
0:-40
Transient
Mute
Right Driver
NOTE: This diagram shows functionality device some register bits does necessarily reflect exact hardware implementation
Audio Mode Analog Filter Modulator Interpolation Filter
Suppression Filter
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FUNCTION
F2,F1 Name MIC1P MIC1N MIC2P MIC2N MIC3 MBIAS LSP, Type Description Positive high impedance input transmit preamplifier microphone connection. Negative high impedance input transmit preamplifier microphone connection. Positive high impedance input transmit preamplifier microphone connection. Negative high impedance input transmit preamplifier microphone connection. High impedance single ended input transmit preamplifier line input connection. Only gain allowed. Microphone Biasing Switch. Auxiliary analog audio Left channel input. Auxiliary analog audio Right channel input. Receive analog amplifier complementary outputs. This differential output drive 50nF (with series resistor) directly earpiece transductor signal this output Receive Speech signal from Internal Tone Generator, Sidetone signal, Audio Left channel Internal Tone Generator, come from input. Audio headphone amplifier Left channel output. This output drive 50nF (with series resistor) directly earpiece transductor signal this output Audio Left channel Internal Tone Generator, Receive Speech signal from Internal Tone Generator, Sidetone signal, come from input. Audio headphone amplifier Right channel output. This output drive 50nF (with series resistor) directly earpiece transductor signal this output Audio Right channel Internal Tone Generator, Receive Speech signal from Internal Tone Generator, Sidetone signal, come from input. Remocon function digital output. Remocon function input. high level this detected pressed key, while level detected pressed key. Pulse width modulated buzzer driver output. I2C-bus interface serial clock input. asynchronous with other system clocks. I2C-bus interface serial data input-output. Left Right clock Audio interface input. Audio interface Clock input. Audio interface Data input. Master Clock Input Audio Mode. also used Master Clock Tone Only Modes. Transmit Data output: Data shifted this during assigned transmit time slots. Elsewhere output high impedance state. delayed non-delayed normal frame sync modes, voice data byte shifted from tristate output MCLK frequency rising edge MCLK, while non-delayed reverse frame sync mode voice data shifted falling edge MCLK. Receive data input: Data shifted during assigned Received time slots delayed non-delayed normal frame sync modes voice data byte shifted MCLK frequency falling edges MCLK, while non-delayed reverse frame sync mode voice data byte shifted rising edge MCLK.
REMOUT REMIN LRCK
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FUNCTION (continued)
Name Type Description Frame Sync input: This signal 16kHz clock which defines start transmit receive frames. three formats used this signal: delayed normal mode, delayed mode, delayed reverse mode. Master Clock Input Voice Mode. also used Master Clock Tone Only Modes. allowed clock frequencies kHz, 1.536 MHz, 2.048 2.56 MHz. MCLK Voice Data Clock. Auxiliary Clock Input. used Master Clock Tone Only Modes. Allowed clock frequencies 512kHz, 1.536MHz, 2.048MHz 2.56MHz. Connect. This must left unconnected. capacitor must connected between this node Ground. Power supply input analog section. VCCA directly connected together cost applications. Analog Ground: analog signals referenced this pin. GNDA connected together cost applications. Power supply input output drivers. VCCP VCCA must connected together. Power ground. Output drivers referenced this pin. GNDP GNDA must connected together. Analog Ground connection. GNDCM connected GNDA. Power supply input digital section. Ground digital section Power supply Input Digital pins.
MCLK
AUXCLK CAP2 VCCA GNDA VCCP GNDP GNDCM VCCIO
Type definitions: Analog input, Analog Output, Digital Input, Digital output, Digital Output Tristate, Digital Input Output Open Drain, Power Supply Ground.
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FUNCTIONAL DESCRIPTION DEVICE MODES STw5094 work different modes, selected bits Control Register (CR18). Depending mode different data interfaces, clock inputs, internal blocks selected. built-in power consumption management function keeps power down blocks that needed selected operating mode. modes Output Drivers activated combinations allowed bits case stereo input driver selected Left channel sent this driver, while case voice input drivers selected same signal sent both drivers). Audio Mode: Audio mode path from output drivers active allow Stereo Audio function. active while inactive. master clock device OCK. frequency must times sampling frequency MPEG1 MPEG2 sampling frequencies times MPEG2.5 sampling frequencies. sampling frequency (LRCK frequency) selected with bits REG6. Since clock used directly Audio blocks, jitter spectral properties must adequate desired Audio quality. Tone Ring DTMF generator activated needed. preamplifiers power down. Voice Mode: Voice mode path from microphone line input path from output drivers active allow CODEC function. active while inactive. master clock device MCLK, frequency clock selected with bits CR0. preamplifiers power down. Tone Only Mode: Tone Only mode path from Tone generator output Drivers Buzzer active allow Tones Ringer listening only. Both inactive, Audio Voice converters functions. master clock device selected AUXCLK, MCLK (bits CR18). Tone Ring DTMF generator activated needed. preamplifiers power down. Mode: mode path from analog inputs output Drivers active allow Stereo Radio listening. Both inactive, Audio Voice converters functions. master clock device selected AUXCLK, MCLK (bits CR18). Tone Ring DTMF generator power down.
DEVICE OPERATION II.1 Power initialization Software Reset: When power first applied, power reset circuitry initializes STw5094 puts into power down state. Registers initialized indicated Control Register description section. functions disabled. registers initialized also writing (software reset) CR18.
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II.2 Power down control: recommended that programmable functions (excluding gain controls) while device powered down. Power state control then included last programming instruction (the power located last address register (CR18) that multi-byte mode control interface easily used program required functions before power up). When power command given, circuits needed selected mode activated Voice mode output will remain high impedance state until second pulse after power arrives). built-in power consumption management function keeps power down blocks that needed selected operating mode. II.3 Power down state: Following period activity, power down state reentered writing CR18. Control Registers remain their current state changed control interface. addition power down instruction, detection absence current Master Clock transition detected) automatically puts device power down state without setting transitions master clock detected device again power II.4 Voice Transmit section: This section active Voice Mode. Voice Transmit analog preamplifier gain designed stages enable gains 42.5 Stage provides selectable gain CR4. Stage programmable gain amplifier which provides from 22.5 additional gain 1.5dB step. programmed with bits CR4. differential microphone inputs (MIC1P MIC2P single ended line input (MIC3) provided. line input MIC3 only used with preamplifier gain both stages. microphone input Transmit Mute selected with bits CR4. Mute case, analog transmit signal grounded. separate MBIAS output used bias microphone (bit CR4). active anti-alias filter then precedes single analog digital converter that followed order digital channel filter. channel filter band-pass frequency 8kHz low-pass frequency 16kHz (bit CR0). precision chip voltage reference ensures accurate highly stable transmission levels. offset voltage arising analog blocks cancelled internal autozero circuit. Voice data sent serially sent output. II.5 Voice Receive section: This section active Voice Mode. Voice Data coming from sent order digital channel filter. filter selected band-pass low-pass, with CR5, when frequency 8kHz, while always low-pass when frequency 16kHz. filter followed digital analog converter order switched-capacitor reconstruction filter. Sidetone summed received signal (bit CR5) amplitude programmed with bits CR5. II.6 Stereo Audio section: This section active Audio Mode. Left Right Audio samples coming from Interface interpolated with filter order feed oversampled multi-bit modulator, digital analog converter followed order switched-capacitor reconstruction filter. II.7 Output Drivers section: There Analog Output Drivers. differential driver delivers 190mW typical power with 0.1% T.H.D. (140mW minimum undistorted) earpiece loudspeaker (piezoceramic loads 50nF also driven, with series resistor), 30dB range gain control (bits CR7). single ended drivers (HPL HPR) deliver 20mW typical power with 0.1% T.H.D. (16.5mW minimum undistorted) stereo headphones, they have 40dB range gain control (CR8 HPR). possible drivers power-down, enable one, enable enable together
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programming bits CR6. These settings dependent from selected operative Mode. enabled together Voice Mode Tone Only Mode same signal sent both Drivers. active Drivers muted (keeping them power-up state) using CR7. power-up after change bits outputs muted avoid unwanted noise. transient suppression filter used avoid clicks when gain value changed. II.8 Tone Generator: Tone Generator activated (writing CR12) Stw5094 operating modes except mode. Voice Audio modes tones summed signal. possible generate summed waveforms (either sinusoidal square wave), their frequencies CR13 first (f1) CR14 second (f2) accordingly values listed Table amplitude generated waveform regulated CR12 over 33dB range. When both selected amplitude lowered respectively with respect amplitude single waveform. this amplitude summed waveforms does overload there difference between amplitude required DTMF generation. Tone Generator output sent Voice Transmit section Voice Mode), Power amplifiers, possibly mixed with audio voice, modes except mode) buzzer output modes except mode). II.9 Buzzer Output: output intended drive Buzzer, external BJT, with squarewave pulse width modulated (PWM) signal. frequency signal stored CR13 (see Table1 frequency values). some applications also possible multiply this signal with squarewave signal having frequency stored CR14. duty cycle buzzer output varied CR15 order change buzzer volume. Maximum load 50pF. II.10 Voice Data Interface (PCM used exchange Voice data both direction, programmed linear format data companded A-law µ-law format (see Fig.1, Frame Sync input determines beginning frame. have duration from single cycle MCLK squarewave. Three different relationships established between Frame Sync input first time slot frame setting bits CR1. delayed normal reverse data mode (long frame timing) first time slot starts rising edge delayed data mode (short frame sync timing) input must high least half cycle MCLK before frame start. When linear code selected (bit CR0) transmitted received first, word length bit. When companded code selected (bit CR0) time slot assignment used timing modes (bit CR1), that allows connection voice data channels. data formats available: Format time slot corresponds MCLK cycles that immediately follow rising edge while time slot corresponds MCLK cycles that immediately follow time slot Format time slot identical Format while time slot appears slots after time slot This bits space left available insertion channel data. Data format selected CR0. enables disables data transfer Outside selected time slot high impedance condition. During selected time slot output input synchronized follow: delayed non-delayed modes selected transmit voice data sent output rising edges MCLK receive voice data read input falling edges MCLK. non-delayed reverse mode selected transmit voice data register sent output falling edges MCLK receive voice data read input rising edges MCLK. When 16kHz Frame Sync frequency selected (bit CR0) filters both low-pass their cutoff frequencies doubled. possible access channel data when companded A-law µ-law formats used (bits CR1). byte written into will sent output place transmit channel data. byte written will sent receive path. current byte received input read CR2.
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II.11 Audio Data Interface (I2S used receive Left Right channel Audio data (see Fig. interface compatible configured other different modes writing CR16. When active (Audio mode) Master Clock device OCK. frequency times sampling frequency (LRCK frequency) when sampling frequency between 16kHz 48kHz (LAY(1) CR6), times when sampling frequency between 8kHz 12kHz (LAY CR6). polarity selected. frequency times LRCK case 16bit Data word times case 18bit 24bit Data word. Left channel data always received first, polarity LRCK selected. first Data frames after power discarded while interpolation filters data memory cleared. II.12 Control Interface (I2C used program device writing reading control registers (see interface compatible, being STw5094 Slave device. bidirectional open-drain data input clock pin. Device Address hex. writing hex. reading. interface internal address register that keeps current address control register read written. each write access interface address register loaded with data register address field. value address register increased after each data byte read write. possible access interface modes: single-byte mode which address data single register specified, multi-byte mode which address first register written read specified following bytes exchanged data successive address registers starting from specified multi-byte mode internal address counter restart from register after last register 18). Using multi-byte mode possible write read registers with single access device bus. Control interface used both power-up power-down state. II.13 Master Clock mode Tone Only modes: mode Tone Only mode Master Clock device selected AUXCLK, MCLK writing bits CR18. Auxiliary clock AUXCLK used when Audio mode clock Voice mode clock MCLK available. AUXCLK MCLK frequency selection done with bits CR0. II.14 REMOCON function: REMOCON (Remote Control) function used detect status headset button. REMOCON function enabled setting CR17. enabled, this function active also when STw5094 power-down state. High level REMIN input detected pressed button, while level detected pressed button. "Pressed Button" information treated ways depending CR17: (Transparent mode) information REMIN seen REMOUT after debounce time 50ms maximum; (Latched Mode) information stored CR17 seen REMOUT. after debounce time 50ms maximum when level REMIN detected. reset with power initialization also reset writing RDL. REMOUT output polarity inverted setting CR17: pressed button information presented REMOUT output logic polarity inverted.
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PROGRAMMABLE REGISTERS Control Register Functions (Address: 0x00)
Function F(1:0) MCLK AUXCLK MCLK AUXCLK MCLK AUXCLK MCLK AUXCLK 1.536 2.048 2.560
Voice Data Voice Data Linear code Companded code Linear Code 2-complement sign magnitude 2-complement 1-complement consecutive separated bits time-slot bits time-slot Companded Code
µ-law: CCITT D3-D4 µ-law: Bare Coding A-law including even inversion A-law: Bare Coding
(1): significant companded mode only state power initialization
Control Register Functions (Address: 0x01)
Function DM(1:0)
significant companded mode only state power initialization reserved: write
delayed data timing non-delayed normal data timing non-delayed reverse data timing
connected path connected path path connected connected disabled enabled channel selected channel selected Normal operation Digital Loopback
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Control Register Functions (Address: 0x02)
Function DRD(7:0)
Significant companded mode only.
Data sent Receive path Data received from input
Control Register Functions (Address: 0x03)
Function DXD(7:0)
Significant companded mode only.
data transmitted
Control Register Functions (Address: 0x04)
Function MS(1:0) TXA(3:0) Transmit input muted MIC1 Selected MIC2 Selected MIC3 Selected MBIAS output disabled MBIAS output enabled 20dB preamplifier gain preamplifier gain Transmit Amplifier gain Transmit Amplifier gain Transmit Amplifier step 22.5 Transmit Amplifier gain
(1)*
state power initialization When single ended line input MIC3 selected, microphone gain must (PG=1, TXA=0000).
Control Register Functions (Address: 0x05)
Voice Codec Receive High Pass filter enabled Voice Codec Receive High Pass filter disabled Voice Codec internal sidetone disabled Voice Codec internal sidetone enabled -12.5 Sidetone -13.5 Sidetone Sidetone gain -27.5 Sidetone gain gain step gain Function
SA(3:0)
state power initialization reserved: write (1): Valid only when Voice Data Fs=8kHz (VFS=0). When Voice data Fs=16kHz (VFS=1) High Pass Filter always disabled.
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Control Register Functions (Address: 0x06)
Function LAY(1:0) AFS(1:0) OS(1:0) Audio Data 44.1 Audio Data 22.025 kHz. Audio Data 11.025 kHz. Audio Data 44.1 22.05 11.025 Audio Data kHz. Audio Data kHz. Output Drivers output Driver selected. output Driver selected. output Drivers selected. Audio Voice Codec Signal disabled Audio Voice Codec Signal enabled. Ring Tone disabled Ring Tone enabled.
(1): frequency must times Audio Data frequency. (2): frequency must times Audio Data frequency. state power initialization reserved: write
Control Register Functions (Address: 0x07)
state power initialization reserved: write
Function
LSA(3:0)
selected output Drivers operative selected output Drivers muted Earpiece Earpiece Earpiece Earpiece Loudspeaker Amplifier gain Loudspeaker Amplifier gain Loudspeaker Amplifier gain step Loudspeaker Amplifier gain
Control Register Functions (Address: 0x08)
HPLA(4:0)
state power initialization reserved: write
Function
Headphones amplifier (Left channel) gain Headphones amplifier (Left channel) gain Headphones amplifier (Left channel) gain step Headphones amplifier (Left channel) gain
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Control Register Functions (Address: 0x09)
HPRA(4:0)
state power initialization write
Function
Headphones amplifier (Right Headphones amplifier (Right Headphones amplifier (Right Headphones amplifier (Right
channel) gain channel) gain channel) gain step channel) gain
Control Register CR10 Functions (Address: 0x0A)
FMLA(4:0)
state power initialization reserved: write
Function
Preamplifier (Left channel) gain Preamplifier (Left channel) gain Preamplifier (Left channel) gain step Preamplifier (Left channel) gain
Control Register CR11 Functions (Address: 0x0B)
FMRA(4:0)
state power initialization reserved: write
Function
Preamplifier (Right Preamplifier (Right Preamplifier (Right Preamplifier (Right
channel) gain channel) gain channel) gain step channel) gain
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Control Register CR12 Functions (Address: 0x0C)
Tone gain Tone gain Tone gain Tone gain
state power initialization reserved write
Function
TONEG(3:0)
FSEL(1:0)
step
muted selected selected summed mode
Squarewave signal selected Sinewave signal selected Tone Ring Generator connected Transmit path Tone Ring Generator connected Transmit path
Control Register CR13 Functions (Address: 0x0D)
Function F1(7:0) Binary equivalent decimal number used calculate Table
Control Register CR14 Functions (Address: 0x0E)
Function F2(7:0) Binary equivalent decimal number used calculate Table
Control Register CR15 Functions (Address: 0x0F)
Function BZ(5:0) Buzzer output disabled (set Buzzer output enabled Duty Cycle intended relative width logic Duty cycle intended relative width logic
Binary equivalent decimal number used calculate duty cycle, using formula: DutyCycle BZ(5:0) 0.78125
state power initialization
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Control Register CR16 Functions (Address: 0x10)
Function PREC(1:0) polarity, changes rising edge polarity, changes falling edge Audio data order, received first (I2S) Audio data order, received first
Audio data alignment, word left justified (I2S)(1) Audio data alignment, word right justified
LRCK polarity, when LRCK=0 Left data received (I2S) LRCK polarity, when LRCK=1 Left data received
Audio format, format (first delayed) Audio format, delayed formats
polarity, LRCK sampled rising edge (I2S) polarity, LRCK sampled falling edge
Audio data width Audio data width Audio data width Audio data width
clocks frame) clocks frame) clocks frame) clocks frame)
significant word mode only Left Channel data always received first. First delay, word mode, applied only word left justified. state power initialization
Control Register CR17 Functions (Address: 0x11)
state power initialization reserved write
Function Remocon Function disabled Remocon Function enabled Remocon output transparent mode Remocon output latched mode Remocon output inverted Remocon output inverted Remocon detection latch reset Remocon detection latch internal logic
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Control Register CR18 Functions (Address: 0x12)
Function MD(1:0)
CFM(1:0)
Voice Mode Audio Mode. Tone Only Mode. Mode.
Master Clock Input Tone Only Mode AUXCLK* Master Clock Input Tone Only Mode MCLK Master Clock Input Tone Only Mode
state power initialization reserved write
Normal Operation Software Reset, registers their default. Device Power Down Device Power
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Table Tone Generator frequency versus CR13 CR14 register value correspondence table
CR13/14 Value (dec.)
F1/F2 Tone Frequency (Hz)
11.7 15.6 19.5 23.4 27.3 31.2 35.2 39.1 43.0 46.9 50.8 54.7 58.6 62.5 66.4 70.3 74.2 78.1 82.0 85.9 89.8 93.8 97.7 101.6 105.5 109.4 113.3 117.2 121.1 125.0 128.9 132.8 136.7 140.6 144.5 148.4 152.3 156.2 160.2 164.1 168.0 171.9 175.8 179.7 183.6 187.5 191.4 195.3 199.2 203.1 207.0 210.9 214.8 218.8 222.7 226.6 230.5 234.4 238.3 242.2 246.1
CR13/14 Value (dec.)
F1/F2 Tone Frequency (Hz)
250.0 257.8 265.6 273.4 281.2 289.1 296.9 304.7 312.5 320.3 328.1 335.9 343.8 351.6 359.4 367.2 375.0 382.8 390.6 398.4 406.2 414.1 421.9 429.7 437.5 445.3 453.1 460.9 468.8 476.6 484.4 492.2 500.0 507.8 515.6 523.4 531.2 539.1 546.9 554.7 562.5 570.3 578.1 585.9 593.8 601.6 609.4 617.2 625.0 632.8 640.6 648.4 656.2 664.1 671.9 679.7 687.5 695.3 703.1 710.9 718.8 726.6 734.4 742.2
CR13/14 Value (dec.)
F1/F2 Tone Frequency (Hz)
750.0 765.6 781.2 796.9 812.5 828.1 843.8 859.4 875.0 890.6 906.2 921.9 937.5 953.1 968.8 984.4 1000.0 1015.6 1031.2 1046.9 1062.5 1078.1 1093.8 1109.4 1125.0 1140.6 1156.2 1171.9 1187.5 1203.1 1218.8 1234.4 1250.0 1265.6 1281.2 1296.9 1312.5 1328.1 1343.8 1359.4 1375.0 1390.6 1406.2 1421.9 1437.5 1453.1 1468.8 1484.4 1500.0 1515.6 1531.2 1546.9 1562.5 1578.1 1593.8 1609.4 1625.0 1640.6 1656.2 1671.9 1687.5 1703.1 1718.8 1734.4
CR13/14 Value (dec.)
F1/F2 Tone Frequency (Hz)
1750.0 1781.2 1812.5 1843.8 1875.0 1906.2 1937.5 1968.8 2000.0 2031.2 2062.5 2093.8 2125.0 2156.2 2187.5 2218.8 2250.0 2281.2 2312.5 2343.8 2375.0 2406.2 2437.5 2468.8 2500.0 2531.2 2562.5 2593.8 2625.0 2656.2 2687.5 2718.8 2750.0 2781.2 2812.5 2843.8 2875.0 2906.2 2937.5 2968.8 3000.0 3031.2 3062.5 3093.8 3125.0 3156.2 3187.5 3218.8 3250.0 3281.2 3312.5 3343.8 3375.0 3406.2 3437.5 3468.8 3500.0 3531.2 3562.5 3593.8 3625.0 3656.2 3687.5 3718.8
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TIMING DIAGRAM Figure Voice Interface (PCM I/F) Delayed Data Timing Mode
tSFM
tWMH
MCLK
tHMF
tHMF
tWLM
tDFD tDMD tDMZ
tSDM
tHMD
Figure Voice Interface (PCM I/F) Delayed Data Timing Mode
tSFM
tWMH
MCLK
tSFM tHMF
tWLM
tDMD
tDMZ
tSDM
tHMD
case companded code timing applied bits instead bits.
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TIMING DIAGRAM Figure Voice Interface (PCM I/F) Delayed Reverse Data Timing Mode
tSFMR
tWMH
MCLK
tHMFR
tHMFR
tWLM
tDFD tDMDR tDMZR
tSDM
tHMD
case companded code timing applied bits instead bits.
Figure Audio Interface (I2S I/F) Timing
tHOCK
tLOCK
(polarity inverted)
LRCK
tDAI
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Figure Audio Interface (I2S I/F) Formats
Format (delayed), Data word bit, first (default)
LRCK
Left channel Right channel
Non-delayed Format, polarity inverted, Data word bit, first
LRCK
Left channel Right channel
Format (delayed), Data word bit, Left justified, first
LRCK
Left channel Right channel
Non-delayed Format, Data word bit, Left justified, first, LRCK polarity inverted
LRCK
Left channel Right channel
Data word bit, Right justified, first
LRCK
Left channel Right channel
other possible formats Control Register CR16 description
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Figure Control Interface (I2C I/F) formats
DATA STOP DATA DATA data bytes STOP
WRITE SINGLE BYTE
DEVICE ADDRESS START
ADDRESS
WRITE MULTI BYTE
DEVICE ADDRESS START
ADDRESS
CURRENT ADDR READ SINGLE BYTE
DEVICE ADDRESS START
Current DATA STOP
CURRENT ADDR READ MULTI BYTE
DEVICE ADDRESS START
Current DATA
Curr REG+m DATA data bytes STOP
RANDOM ADDR READ SINGLE BYTE
DEVICE ADDRESS START ADDRESS
DEVICE ADDRESS START
DATA
STOP DEVICE ADDRESS DATA DATA STOP
RANDOM ADDR READ MULTI BYTE
DEVICE ADDRESS START ADDRESS
START
data bytes
Figure Control Interface (I2C I/F) Timing
tBUF
(STA)
tLOW
(DAT)
tHIGH
(DAT)
(STA)
(STA)
(STO)
STOP START START repeated
Figure A.C. TESTING INPUT, OUTPUT WAVEFORM INPUT OUTPUT
0.8VCCIO 0.2VCCIO 0.7VCCIO 0.3VCCIO 0.7VCCIO
TEST POINTS
0.3VCCIO
Testing: inputs driven 0.8VCCIO logic 0.2VCCIO logic "0". Timing measurements made 0.7VCCIO logic 0.3VCCIO logic "0".
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ABSOLUTE MAXIMUM RATINGS
Parameter Voltage (VCC 3.3V) Current LSP/N Current HPR,HPL Current digital output Voltage digital input (VCCIO 3.3V); limited 50mA Storage temperature range Value +0.5 -0.5 VCCIO -0.5 Unit
OPERATIVE SUPPLY VOLTAGES
Symbol VCCA VCCP VCCIO Min. Max. Unit
TIMING SPECIFICATIONS (unless otherwise specified, VCCIO 1.8V 3.3V,Tamb -30°C 85°C; typical characteristics specified VCCIO 3.0V, Tamb signals referenced GND, next Note timing definitions) NOTICE: timing specifications subject change. Audio Interface Signals Timing
Symbol Parameter Test Condition Audio 8kHz 16kHz Audio 11.025kHz 22.05kHz Audio 12kHz 24kHz Audio 32kHz Audio 44.1kHz Audio 48kHz Measured from Measured from Min. Typ. 4.096 5.6648 6.144 8.192 11.2896 12.288 Max. Unit
fOCK
Frequency
(frequency depends selected Audio sample rate CR6)
tHOCK tLOCK tDAI
Period high Period Delay SCK,SDI LRCK from active edge
MCLK AUXCLK Timing
Symbol Parameter Test Condition Frequency programmable with bits Min. Typ. 1.536 2.048 2.560 Max. Unit
fMCLK
Frequency MCLK, AUXCLK
tWMH tWML
Period MCLK, AUXCLK high Period MCLK, AUXCLK Rise Time MCLK, AUXCLK Fall Time MCLK, AUXCLK
Measured from Measured from Measured from Measured from
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Interface Timing
Symbol tHMF tSFM tDMD tDMZ tDFD Parameter Hold Time MCLK Setup Time, high MCLK Delay Time, MCLK high data valid Delay Time, MCLK disabled Delay Time, high data valid Load 20pF; Applies only rises later than MCLK rising edge Delayed Mode only Load 20pF Load 20pF Test Condition Min. Typ. Max. Unit
tSDM tHMD tHMFR tSFMR tDMDR tDMZR tHMDR
Setup Time, valid MCLK receive edge Hold Time, MCLK invalid Hold Time MCLK High Setup Time, high MCLK High Delay Time, MCLK data valid Delay Time, MCLK High disabled Hold Time, MCLK High invalid
Control Port Timing
Symbol fSCL tHIGH tLOW tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tBUF
Note: signal valid above below invalid between VIH.For purpose this specification following conditions apply (see Fig. input signal defined 0.2VCCIO, 0.8VCCIO, 10ns, 10ns. Delay times measured from inputs signal valid output signal valid. Setup times measured from data input valid clock input invalid. Hold times measured from clock signal valid data input invalid.
Parameter Clock Frequency Clock High Time Clock Time Rise Time Fall Time Start Condition Hold Time Start Condition Setup Time Data Input Hold Time Data Input Setup Time Stop Condition Setup Time Free Time
Test Condition
Min.
Typ.
Max.
Unit
1300 1000 1300
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ELECTRICAL CHARACTERISTICS (unless otherwise specified, VCCIO 1.8V 3.3V, Tamb -30°C 85°C; typical characteristic specified VCCIO 3.0V, Tamb 25°C; signals referenced GND) Digital Interfaces (See Figure
Symbol VILREM Parameter Input Voltage Input High Voltage Input Voltage Test Condition digital inputs except REMIN digital inputs except REMIN REMIN input REMIN input digital outputs, 10µA digital outputs, digital outputs, 10µA digital outputs, digital input, digital input, VCCIO VCCIO-0.1 VCCIO-0.4 0.7VCCIO 0.8VCCIO Min. Typ. Max. 0.3VCCIO 0.2VCCIO Unit
VIHREM Input High Voltage Output Voltage Output High Voltage Input Current Input High Current
Output Current High impedance (Tristate)
Analog Interfaces
Symbol RMBIAS IMIC RMIC RLHP CLHP ROVHP RLLS CLLS ROLS VOSLS Parameter MBIAS Output Resistance Input Leakage Input Resistance Input Resistance Single Ended Drivers Load Resistance Single Ended Drivers Load Capacitance Single Ended Drivers Output Resistance Differential Driver Load Resistance Differential Driver Load Capacitance Differential Driver Output Resistance Differential offset Voltage LSP, Test Condition MBIAS 100mV under VMIC VMIC FML, CAP2 HPL, GNDP HPL, GNDP Steady zero code applied ±1mA Steady zero code applied ±1mA Alternating zero code applied maximum receive gain; -100 Min. Typ. Max. +100 Unit
with series resistor
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ANALOG INPUT/OUTPUT OPERATIVE RANGES Microphone Input Levels Absolute levels MIC1, MIC2
Symbol Parameter dBm0 level Overload level dBm0 level Overload level dBm0 level Overload level Test Condition Transmit gain Transmit gain Transmit gain 20dB Transmit gain 20dB Transmit gain 42.5dB Transmit gain 42.5dB Min. Typ. Max. Unit mVRMS mVRMS mVRMS mVRMS mVpp mVRMS mVRMS mVpp
Line Input Level Absolute levels MIC3
Symbol Parameter Overload level Test Condition Transmit gain Min. Typ. Max. Unit mVRMS
Input Levels Absolute levels FML,
Symbol Parameter Overload level Overload level Test Condition FML, gain FML, gain from -20dB Min. Typ. Max. Unit mVRMS mVRMS
Power Output Levels Absolute levels HPL,
Symbol Parameter Maximum undistorted level Test Condition Load Min. Typ. Max. Unit mVRMS
Power Output Levels Absolute levels LSP-LSN (Differentially measured)
Symbol Parameter dBm0 level dBm0 level Maximum undistorted level Test Condition Min. Typ. 62.1 1.06 Max. Unit mVRMS mVRMS VRMS
gain gain -24dB
Load
Tones Levels
Symbol Parameter Tone level LSP-LSN Tone level HPL, Test Condition Single tone, sinusoidal waveform, tone gain 0dB, gain Single tone, sinusoidal waveform, tone gain 0dB, HPL, gain -6dB Voice mode, Single tone, sinusoidal waveform, tone gain Min. Typ. 1.41 -1.64 Max. Unit VRMS mVRMS dBFS
Tone level
Note: when tones enabled amplitude lowered amplitude lowered with respect amplitude single tone.
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VOICE CODEC CHARACTERISTICS (unless otherwise specified, 2.7V 3.3V, Tamb -30°C 85°C; Frequency 8kHz; typical characteristics specified 3.0V, Tamb 25°C, MIC1 0dBm0, -6dBm0 code, 1015.625 signal referenced GND) AMPLITUDE RESPONSE Transmit path
Symbol Parameter Transmit Gain Absolute Accuracy Test Condition Transmit Gain Programmed minimum. Measure deviation Digital Code from ideal 0dBm0 code Measure Transmit Gain over range from Maximum minimum setting. Calculate deviation from programmed gain relative GXA, i.e. GAXG actual prog. Measured relative GXA. min. gain Max. gain Measured relative Minimum gain Digital filter characteristics 3000 3400 4000 4600 8000 Digital filter characteristics 6000 6800 8000 9200 16000 Sinusoidal Test method. Reference Level dBm0 VMIC dBm0 dBm0 VMIC dBm0 dBm0 VMIC dBm0 dBm0 -1.5 -0.5 -1.5 Min. -0.5 Typ. Max. Unit
GXAG
Transmit Gain Variation with programmed gain
-0.5
GXAT GXAV GXAF8
Transmit Gain Variation with temperature Transmit Gain Variation with supply Transmit Gain Variation with frequency. Frequency 8kHz (VFS=0)
-0.1 -0.1
-1.5 -0.5 -1.5
GXAF16
Transmit Gain Variation with frequency. Frequency 16kHz (VFS=1)
GXAL
Transmit Gain Variation with signal level
-0.5 -0.5 -1.2
limit frequencies between 4600Hz 8000Hz lies straight line connecting frequencies linear (dB) scale versus (Hz) scale.
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AMPLITUDE RESPONSE (continued) Receive path
Symbol GRAHPL GRAHPR GRALS Parameter Receive Gain Absolute Accuracy Test Condition Receive gain programmed maximum Apply dBm0 code Measure HPL, HPR, LSP-LSN Measure HPL, HPR, LSP-LSN Gain over range from Maximum minimum setting. Calculate deviation from programmed gain relative GRA, i.e. GRAGLS actual prog. GRALS Measured relative GRA. (HPL, LSP-LSN) min. gain Max. gain Measured relative GRA. (HPL, LSP-LSN) Maximum Gain Digital filter characteristics 60Hz 100Hz 3000 3400 4000 Digital filter characteristics 50Hz 3000 3400 4000 Digital filter characteristics 100Hz 6000 6800 8000 Sinusoidal Test Method Reference Level dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 -1.5 -0.5 -1.5 -1.5 -0.5 -1.5 Min. -0.5 Typ. Max. Unit
GRAGHPL Receive Gain Variation with GRAGHPR programmed gain GRAGLS
-0.5
GRAT
Receive Gain Variation with temperature Receive Gain Variation with Supply Receive Gain Variation with frequency (HPL, LSP-LSN) frequency 8kHz (VFS=0). High Pass Filter enabled (HPB
-0.1
GRAV
-0.1
GRAF8
-1.5 -0.5 -1.5
Receive Gain Variation with frequency (HPL, LSP-LSN) frequency 8kHz (VFS=0). High Pass Filter disabled (HPB GRAF16 Receive Gain Variation with frequency (HPL, LSP-LSN) frequency 16kHz (VFS=1). GRALHPL GRALHPR GRALLS Receive Gain Variation with signal level (HPL, LSP-LSN)
-0.5 -0.5 -1.2
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ENVELOPE DELAY DISTORTION WITH FREQUENCY
Symbol Parameter Delay, Absolute Delay, Relative Test Condition 1600 1000 1000 1600 1600 2600 2600 2800 2800 3000 1600 1000 1000 1600 1600 2600 2600 2800 2800 3000 Min. Typ. Max. Unit
Delay, Absolute Delay, Relative
NOISE
Symbol Parameter Noise, weighted 35dB) Noise, C-message weighted Load (gain max. undistorted output level) PSRR, Test Condition Receive code Zero, LSA='0100' (gain -2dB) mVRMS; 100Hz 50kHz Code equals Positive Zero, 3.0VDC mVRMS Digital filter characteristics 4600 5600 5600 7600 7600 8400 Min. Typ. Max. Unit dBm0p µVRMS
PSRTX
PSRRX
PSRR,
Spurious Out-Band signal output
CROSSTALK
Symbol CTX-R Parameter Transmit Receive Test Condition Transmit Level dBm0, 3400 Quiet Code Receive Level dBm0, 3400 Min. Typ. -100 Max. Unit
CTR-X
Receive Transmit
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DISTORTION Receive path
Symbol STDRLS Parameter Signal Total Distortion (LSP-LSN) 14dB attenuation) Load Typical values measured with 14dB attenuation. Test Condition Sinusoidal Test Method (measured using linear 3400 weighting, FS=8kHZ) Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Sinusoidal Test Method (measured using linear 6800 weighting, FS=16kHZ) Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Sinusoidal Test Method (measured using linear 3400 weighting, FS=8kHZ) Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Sinusoidal Test Method (measured using linear 6800 weighting, FS=16kHZ) Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Min. Typ. Max. Unit
Signal Total Distortion (LSP-LSN) 14dB attenuation) Load Typical values measured with 14dB attenuation.
Signal Total Distortion (HPL, HPR) 14dB attenuation) Typical values measured with 14dB attenuation
Signal Total Distortion (HPL, HPR) 14dB attenuation) Typical values measured with 14dB attenuation
limit curve shall determined straight lines joining successive coordinates given table.
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DISTORTION Transmit path
Symbol STDX Parameter Signal Total Distortion 35dB gain) frequency 8kHz. Typical values measured with 30.5dB gain Test Condition Sinusoidal Test Method (measured using linear 3400 weighting) Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Sinusoidal Test Method (measured using linear 6800 weighting) Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Min. Typ. Max. Unit
Signal Total Distortion frequency 16kHz. Typical values measured with 30.5dB gain
limit curve shall determined straight lines joining successive coordinates given table.
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STEREO AUDIO CHARACTERISTICS (Unless otherwise specified, 2.7V 3.3V, Tamb -30°C 85°C; typical characteristics specified Tamb 25°C; 12.288MHz; Full-Scale Input Sine Waves, 1015.625Hz; Input Sample Rate (Fs) 48kHz; Input Data 18Bits; 3.072 MHz; Measurement Bandwidth 20Hz 20kHz, unweighted. Resistive load HPL,
Symbol DYNR THDL Parameter Resolution Dynamic Range Total Harmonic Distortion maximum load Total Harmonic Distortion A-weighted 2Vpp output HPL, gain -6dB load 2Vpp output HPL, gain -6dB load Measurement Bandwidth 20Hz 20kHz, 48kHz.Combined digital analog filter characteristics. Combined Digital Analog filter characteristics. Combined Digital Analog filter characteristics. Combined Digital Analog filter characteristics. Combined Digital Analog filter characteristics. Measurement Bandwidth 3.45Fs 0.55Fs 0.01 0.03 Test Condition Min. Typ. Max. Unit Bits
0.004
Deviation from Linear Phase
Passband Passband Ripple
0.45Fs
StopBand StopBand Attenuation
Transient suppression filter cutoff frequency Band Noise Measurement Bandwidth 20kHz 100kHz. Zero input signal
HPR, unloaded
Group Delay Interchannel Isolation Interchannel Gain Mismatch Gain Error
Startup Time from Power
Valid input (Audio Mode). NOTE: range: 8kHz 48kHz.
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POWER DISSIPATION (Unless otherwise specified, 2.7V 3.3V, Tamb -30°C 85°C, LSP, HPL, outputs loaded; typical characteristics specified Tamb 25°C)
Symbol ICC0 Parameter Power down Current, REMOCON Power down Current, REMOCON Test Condition SDA, SCL= VCCIO-0.1V REMOCON function disabled (REN SDA, SCL= VCCIO-0.1V REMOCON function enabled (REN REMIN VILREM REMIN VIHREM Fs=8kHz. LSP/N output selected Fs=48kHz. HPL,HPR outputs selected HPL,HPR outputs selected Min. Typ. Max. Unit
ICC0R
ICC1 ICC2 ICC3
Power Current Voice Codec Mode Power Current Stereo Audio Mode Power Current Stereo Mode
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TYPICAL PERFORMANCE CHARACTERISTICS
Figure Stereo performance audio mode (8192 points). Full scale input/output sinewave (+3dBr) VCC=2.7V, Fs=48kHz, bits input word.
Figure Stereo performance Dynamic range: Noise [dBr] versus signal amplitude [dBm0] VCC=2.7V, Fs=48kHz, bits input word.
Figure Voice performance S/(N+THD) [dB] versus signal amplitude [dBm0] with output load VCC=2.7V, Fs=8kHz
Figure Voice performance S/(N+THD) versus signal amplitude VCC=2.7V, Fs=8kHz
Digital Audio Filter Amplitude [dB] Amplitude [dB] -100 Normalized Freq. [Fs] -0.1 -0.2 -0.3 -0.4 -0.5 0.05 0.15
Digital Audio Filter
0.25 0.35 Normalized Freq. [Fs]
0.45
Figure Digital Audio Filter characteristic Frequency response 3.45
Figure Digital Audio Filter characteristic band Frequency response
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TYPICAL PERFORMANCE CHARACTERISTICS (cont.)
Digital Voice Filter Amplitude [dB] 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 Freq. [Hz] 1000 1500 2000 Freq. [Hz] 2500 3000 3500 Amplitude [dB] Digital Voice Filter
-0.5
Figure Digital Voice Filter characteristic Frequency response 2.5Fs (Fs=8kHz)
Figure Digital Voice Filter characteristic band Frequency response (Fs=8kHz).
Digital Voice Filter High Pass Filt.)
Amplitude [dB]
-0.5
1000
1500 2000 Freq. [Hz]
2500
3000
3500
Figure Digital Voice Filter characteristic band Frequency response (Fs=8kHz). High Pass filter disabled (HPB=1).
Figure Voice Filter characteristic Full path frequency response (Fs=8kHz).
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APPLICATION NOTE
MBIAS 1.8k 100nF MIC1P 10µF Electret 100nF MIC1N 100k 1.8k 10µF 1.5k REMIN 100nF MIC2P Electret Call/Answer Button 100nF MIC2N 100k BC546 BC556
REMOUT
Microprocessor Auxiliary Clock
AUXCLK
Buzzer
MCLK 100nF Line input 10µF CAP2 Min. 150µF 150µF MIC3
STw5094
Interface
0.47µF Line (From Stereo Decoder) 0.47µF LRCK Min. SCKT OCLK
LRCKT
GNDCM
VCCIO
GNDA
GNDP
VCCA
VCCP
STA015
Decoder
VDDIO
100nF
100nF
100nF
100nF 10µF
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DIM. MIN. 0.72 0.85 5.85 0.35 5.85 1.01 0.21 0.82 0.40 6.00 4.00 6.00 4.00 0.80 1.00 0.88 1.15 0.10 0.028 0.033 6.15 0.23 0.45 6.15 0.014 0.23 TYP. MAX. 1.20 MIN. 0.040 0.008
inch TYP. MAX. 0.047
OUTLINE MECHANICAL DATA
0.032 0.016 0.236 0.157 0.236 0.157 0.031 0.039 0.035 0.045 0.004 0.242 0.018 0.242
Body: 1.2mm
TFBGA36 Fine Pitch Ball Grid Array
TFBGA36
7225043
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Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics. other names property their respective owners 2003 STMicroelectronics rights reserved STMicroelectronics GROUP COMPANIES Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States www.st.com
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