DSP56652 Baseband Digital Signal Processor Manual Motorola,
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Order this document DSP56652UM/D Rev. 04/1999
DSP56652
Baseband Digital Signal Processor Manual
Motorola, Incorporated Semiconductor Products Sector 6501 William Cannon Drive West Austin 78735-8598
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This document contains information product. Specifications information herein subject change without notice. This manual three documents. Three manuals required complete product information: family manual, manual, technical data sheet.
Copyright Motorola, Inc., 1999. rights reserved.
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including must validated each customer application technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. other tradenames, trademarks, registered trademarks property their respective owners.
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Table Contents
Preface Chapter Introduction DSP56652 Features Architecture Overview 1.2.1 1.2.2 DSP. 1.2.3 Interface. Chapter Signal/Connection Description 2.10 2.11 2.12 2.13 2.14 2.15 2.16 Power Ground Clock Phase-Locked Loop External Interface Module Reset, Mode, Multiplexer Control. Internal Interrupts. Protocol Timer Keypad Port 2-10 UART. 2-13 QSPI 2-15 SCP. 2-16 2-16 2-18 Emulation Port 2-18 Debug Port Control 2-18 JTAG Test Access Port 2-19 Chapter Memory Maps Memory 3.1.1 3.1.2
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3.1.3 Memory-Mapped Peripherals. 3.1.4 External Memory Space 3.1.5 Reserved Memory Memory Descriptions 3.2.1 Data Memory 3.2.2 Data Memory 3.2.3 Program Memory 3.2.4 Reserved Memory Chapter Core Operation Configuration 4.1.1 4.1.2 4.1.3 4.3.1 4.3.2 4.4.1 4.4.2 4.4.3 4.5.1 4.5.2
Clock Generation MCU_CLK. DSP_CLK Clock Registers Power Modes Reset Reset. 4-11 Reset. 4-11 Configuration. 4-12 Operating Mode Register 4-12 Patch Address Registers 4-14 Device Identification Register 4-15 Multiplexing 4-15 Debug Port Timer Multiplexing 4-15 Address Visibility 4-20 Chapter Interface
Memory. 5.1.1 DSP-Side Memory Mapping 5.1.2 MCU-Side Memory Mapping 5.1.3 Shared Memory Access Contention. 5.1.4 Shared Memory Timing Messages Control 5.2.1 Messaging System 5.2.2 Message Protocols 5.2.3 Interrupt Sources 5-10 5.2.4 Event Update Timing 5-11
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5.2.5 5.3.1 5.3.2 5.3.3 5.6.1 5.6.2
MCU-DSP Troubleshooting. Low-Power Modes. Low-Power Modes Low-Power Modes. Shared Memory STOP Mode Resetting Software Restriction Summary Registers MCU-Side Registers DSP-Side Registers Chapter External Interface Module
5-11 5-11 5-12 5-12 5-13 5-14 5-15 5-17 5-18 5-25
6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7
Signals Chip Select Address Ranges Features Configurable Sizing External Boot Control Watchdog Operation Error Conditions. Displaying Internal (Show Cycles) Programmable Output Generation Emulation Port Registers Chapter Interrupts
Interrupt Controller 7.1.1 Functional Overview 7.1.2 Exception Priority 7.1.3 Enabling Interrupt Sources. 7.1.4 Interrupt Sources 7.1.5 Interrupt Registers Interrupt Controller 7-10 7.2.1 Interrupt Sources 7-10 7.2.2 Enabling Interrupt Sources 7-13 7.2.3 Interrupt Control Registers 7-14 Edge Port 7-15
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Chapter Queued Serial Peripheral Interface 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 8.1.8 8.2.1 8.2.2 8.2.3 8.2.4 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.4.1 8.4.2 8.4.3 8.4.4 Features Programmable Baud Rates Programmable Queue Lengths Continuous Transfers. Programmable Peripheral Chip-Selects Programmable Queue Pointers. Four Transfer Activation Triggers Programmable Delay after Transfer. Loading Programmable Address Queue Pause Enable Queue Entry Boundaries QSPI Architecture QSPI Pins Control Registers Functional Modules RAM. QSPI Operation Initialization Queue Transfer Cycle Ending Transfer Cycle. 8-10 Breaking Transfer Cycle 8-10 Halting QSPI 8-11 Error Interrupts. 8-11 Power Modes 8-11 QSPI Registers Memory 8-12 QSPI Control Registers 8-13 Transfer Triggers 8-22 Control Data 8-22 GPIO Registers. 8-24 Chapter Timers Periodic Interrupt Timer 9.1.1 Operation. 9.1.2 Registers Watchdog Timer 9.2.1 Watchdog Timer Operation 9.2.2 Watchdog Timer Registers. Timer
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9.3.1 9.3.2 9.3.3
Timer Pulse Width Modulator 9-11 Timer Registers. 9-13 Chapter Protocol Timer
10.1 Protocol Timer Architecture 10-1 10.1.1 Timing Signals Components 10-3 10.1.2 Event Table 10-4 10.1.3 Event Generation 10-4 10.2 Operation 10-6 10.2.1 Frame Events 10-6 10.2.2 Macro Tables 10-7 10.2.3 Operating Modes 10-10 10.2.4 Error Detection. 10-11 10.2.5 Interrupts 10-11 10.2.6 General Purpose Input/Output (GPIO). 10-12 10.3 Event Codes 10-13 10.4 Registers. 10-15 10.4.1 Control Registers 10-17 10.4.2 GPIO Registers. 10-26 10.5 Protocol Timer Programming Example. 10-27 Chapter UART 11.1 UART Definitions 11.2 UART Architecture 11.2.1 Transmitter 11.2.2 Receiver 11.2.3 Clock Generator 11.2.4 Infrared Interface 11.2.5 UART Pins 11.2.6 Frame Configuration 11.3 UART Operation 11.3.1 Transmission 11.3.2 Reception 11.3.3 UART Clocks. 11.3.4 Baud Rate Detection (Autobaud) 11.3.5 Low-Power Modes 11-1 11-2 11-3 11-3 11-4 11-4 11-4 11-4 11-5 11-5 11-5 11-6 11-6 11-7
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11.3.6 Debug Mode. 11-7 11.4 UART Registers. 11-8 11.4.1 UART Control Registers 11-9 11.4.2 GPIO Registers. 11-16 Chapter Smart Card Port 12.1 Architecture 12-1 12.1.1 Pins. 12-2 12.1.2 Data Communication 12-2 12.1.3 Power Up/Down. 12-3 12.2 Operation 12-3 12.2.1 Activation/Deactivation Control 12-3 12.2.2 Clock Generation 12-4 12.2.3 Data Transactions. 12-5 12.2.4 Power Modes 12-8 12.2.5 Interrupts 12-9 12.3 Registers 12-10 12.3.1 Control Registers 12-11 12.3.2 GPIO 12-16 Chapter Keypad Port 13.1 Keypad Operation 13.1.1 Configuration 13.1.2 Keypad Matrix Polling 13.1.3 Standby Power Operation 13.1.4 Noise Suppression Keypad Inputs 13.2 Keypad Port Registers Chapter Serial Audio Baseband Ports 14.1 Data Control Pins 14.2 Transmit Receive Clocks 14.2.1 Clock Sources. 14.2.2 Clock Frequency 14.2.3 Clock Polarity. 14.2.4 Rate Multiplier (SAP Only) 14.3 Options.
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13-1 13-2 13-3 13-3 13-3 13-4
14-3 14-3 14-3 14-4 14-5 14-5 14-6
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14.3.1 Synchronous Asynchronous Modes 14-6 14.3.2 Frame Configuration 14-6 14.3.3 Frame Sync. 14-7 14.3.4 Serial Flags. 14-8 14.3.5 Interrupts 14-8 14.4 Data Transmission Reception 14-9 14.4.1 Data Transmission 14-9 14.4.2 Data Reception 14-11 14.4.3 Data Formats 14-12 14.5 Software Reset 14-12 14.6 General-Purpose Timer (SAP Only) 14-13 14.7 Frame Counters (BBP Only) 14-13 14.8 Interrupts 14-14 14.9 Control Registers 14-15 14.9.1 Control Registers 14-17 14.9.2 GPIO Registers. 14-24 Chapter JTAG Port 15.1 DSP56600 Core JTAG Operation 15-3 15.1.1 JTAG Pins 15-3 15.1.2 Controller. 15-4 15.1.3 Instruction Register 15-5 15.2 Test Registers. 15-10 15.2.1 Boundary Scan Register (BSR) 15-10 15.2.2 Bypass Register 15-10 15.2.3 Identification Register 15-10 15.3 DSP56652 JTAG Port Restrictions 15-11 15.3.1 Normal Operation. 15-11 15.3.2 Test Modes 15-11 15.3.3 STOP Mode 15-11 15.4 Controller 15-12 15.4.1 Entering OnCE Mode JTAG Control. 15-12 15.4.2 Release from Debug Mode 15-13 Appendix DSP56652 Bootloader Boot Modes Mode Normal Boot A.2.1 Short Long Messages
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A.2.2 Message Descriptions. A.2.3 Comments Normal Boot Mode Usage A-13 A.2.4 Example Program Download Execution. A-14 Mode Shared Memory Boot A-15 Mode Messaging Unit Boot A-16 Bootstrap Program A-17 Appendix Equates Header Files Equates. Include File B-22 Equates B-32 Appendix Boundary Scan Register Definitions. Boundary Scan Description Language Appendix Reference Instruction Reference Tables Instruction Reference Tables. Internal Memory D-14 Internal Memory D-19 Register Index D-22 Acronym Changes D-26 Appendix Data Sheets
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List Figures
Figure 1-1. Figure 2-1. Figure 3-1. Figure 3-2. Figure 4-1. DSP56652 Block Diagram Signal Group Organization Memory Memory DSP56652 Clock Scheme Clock Generator. DSP56652 Reset Circuit 4-10 Connectivity Scheme 4-17 Block Diagram MDI: DSP-Side Memory Mapping. MDI: MCU-Side Memory Mapping Register Symmetry. Message Exchange DSP-to-MCU General Purpose Interrupt Block Diagram Example Interface Memory Peripherals Interrupt Controller Hardware Priority Flowchart Internal Connection 7-11 Edge 7-16 QSPI Signal Flow QSPI Serial Transfer Timing 8-21 Block Diagram Timing Using PITMR Watchdog Timer Block Diagram Timer/PWM Clocks Timer Block Diagram
Figure 4-2. Figure 4-3. Figure 4-4. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 5-6. Figure 6-1. Figure 6-2. Figure 7-1. Figure 7-2. Figure 7-3. Figure 7-4. Figure 8-1. Figure 8-2. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 9-5.
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Figure 9-6.
Block Diagram 9-12
Figure 10-1. Protocol Timer Block Diagram 10-2 Figure 10-2. Event Table Structure 10-5 Figure 10-3. Frame Table Entry 10-7 Figure 10-4. Macro Table Entry 10-8 Figure 10-5. Delay Table Entry. 10-9 Figure 11-1. UART Block Diagram 11-3 Figure 12-1. Smart Card Port Interface 12-1
Figure 12-2. SCP: Port Interface Auto Power Down Logic 12-3 Figure 12-3. SCP: Clocks Data. 12-5 Figure 12-4. Data Formats 12-8 Figure 12-5. Interrupts. 12-9 Figure 13-1. Keypad Port Block Diagram. 13-1 Figure 13-2. Glitch Suppressor Functional Diagram 13-4 Figure 14-1. Block Diagram 14-2 Figure 14-2. Block Diagram 14-2 Figure 15-1. DSP56652 JTAG Block Diagram. 15-2 Figure 15-2. DSP56600 Core JTAG Block Diagram 15-3 Figure 15-3. Controller State Machine 15-5 Figure 15-4. JTAG Instruction Register 15-5 Figure 15-5. JTAG Bypass Register 15-10 Figure 15-6. JTAG Register 15-11 Figure A-1. Short Message Format Figure A-2. Long Message Format Figure A-3. Format memory_write.request Message Figure A-4. Figure A-5. Figure A-6. Figure A-7. Figure A-8. Figure A-9.
Format message_write.response Message. Format memory_read.request Message. Format memory_read.response Message Format memory_check.request Message Format memory_check.request Message A-10 Format start_application.request Message A-11
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Figure A-10. Format invalid_opcode.response Message A-12 Figure A-11. Mapping Program Memory words message words. A-13
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List Tables
Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. DSP56652 Signal Functional Group Allocations Power Ground Clock Signals Address Data Buses Control Chip Select Signals Reset, Mode, Multiplexer Control Signals Interrupt Signals
Table 2-6. Table 2-7. Table 2-8. Table 2-9.
Table 2-10. Protocol Timer Output Signals Table 2-11. Keypad Port Signals 2-10 Table 2-12. UART Signals 2-13 Table 2-13. QSPI Signals 2-15 Table 2-14. Signals 2-16 Table 2-15. Signals 2-16 Table 2-16. Signals 2-18 Table 2-17. Emulation Port Signals 2-18 Table 2-18. Debug Control Signals 2-19 Table 2-19. JTAG Port Signals 2-19 Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 4-8. Peripherals Clock Source CKCTL Description PCTL0 Descriptions PCTL1 Description Peripherals Power Mode. Peripherals Power Modes. Programmable Power-Saving Features. Description 4-11
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Table 4-9.
Description 4-13
Table 4-10. Patch JUMP Targets 4-14 Table 4-11. Debug Port Multiplexing 4-16 Table 4-12. Timer Multiplexing 4-16 Table 4-13. GPCR Description 4-18 Table 4-14. Function Address Visibility Mode. 4-20 Table 5-1. Table 5-2. Access Timing Registers Symmetry Wake-up Events 5-12 Reset Sources 5-14 General Restrictions 5-15 DSP-Side Restrictions 5-15 MCU-Side Restrictions 5-16 Signalling Control Registers 5-17 Register Correspondence 5-17
Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 5-8. Table 5-9.
Table 5-10. MCVR Description. 5-18 Table 5-11. Description 5-19 Table 5-12. Description 5-21 Table 5-13. MTR1 Description 5-24 Table 5-14. MTR0 Description 5-24 Table 5-15. MRR1 Description 5-24 Table 5-16. MRR0 Description 5-24 Table 5-17. Description 5-25 Table 5-18. Description 5-26 Table 5-19. DTR1 Description. 5-28 Table 5-20. DTR0 Description. 5-28 Table 5-21. DRR1 Description 5-28 Table 5-22. DRR0 Description 5-28 Table 6-1. Table 6-2. Table 6-3.
Signal Description Chip Select Address Range Interface Requirements Read Write Cycles
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Table 6-4. Table 6-5. Table 6-6. Table 6-7. Table 6-8. Table 6-9. Table 7-1. Table 7-2.
SIZ[1:0] Encoding PSTAT[3:0] Encoding CSCRn Description EIMCR Description 6-12 QDDR Description 6-13 QPDR Description 6-13 Interrupt Sources Description NIER/FIER Description NIPR FIPR Description Description 7-10 Interrupt Sources 7-11 Interrupt Source Priorities within 7-13 IPRP Description 7-14 IPRC Description 7-15
Table 7-3. Table 7-4. Table 7-5. Table 7-6. Table 7-7. Table 7-8. Table 7-9.
Table 7-10. EPPAR Description 7-17 Table 7-11. EPDDR Description 7-17 Table 7-12. EPDR Description 7-18 Table 7-13. EPFR Description 7-18 Table 8-1. Table 8-2. Table 8-3. Table 8-4. Table 8-5. Table 8-6. Table 8-7. Table 8-8. Table 8-9. Table 9-1. Table 9-2.
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Serial Control Port Signals QSPI Register/Memory Summary 8-12 SPCR Description 8-13 Description 8-15 SPSR Description 8-17 SCCR Description 8-19 QSPI Control Description 8-22 QPCR Description 8-24 QDDR Description 8-25 ITCSR Description Description
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Table 8-10. QPDR Description 8-25
Table 9-3. Table 9-4. Table 9-5. Table 9-6.
TPWCR Description. 9-13 TPWMR Description 9-14 TPWSR Description 9-15 GNRC Description 9-16
Table 10-1. Protocol Timer Operation Mode Summary 10-10 Table 10-2. Protocol Timer Interrupt Sources 10-12 Table 10-3. Port Assignment 10-13 Table 10-4. Protocol Timer Event List 10-13
Table 10-5. Protocol Timer Register Summary 10-15 Table 10-6. PTCR Description. 10-17 Table 10-7. Additional Conditions Generating Interrupts 10-18 Table 10-8. PTIER Description 10-19 Table 10-9. PTSR Description 10-20 Table 10-10. PTEVR Description 10-21 Table 10-11. TIMR Description. 10-21 Table 10-12. CTIC Description 10-22 Table 10-13. CTIMR Description 10-22 Table 10-14. Description 10-22 Table 10-15. CFMR Description 10-23 Table 10-16. Description 10-23 Table 10-17. RSMR Description 10-23 Table 10-18. FTPTR Description. 10-24 Table 10-19. MTPTR Description 10-24 Table 10-20. FTBAR Description 10-24 Table 10-21. MTBAR Description 10-25 Table 10-22. DTPTR Description 10-25 Table 10-23. PTPCR Description 10-26 Table 10-24. PTDDR Description 10-26 Table 10-25. PTPDR Description 10-26 Table 11-1. Suggested GPIO Pins UART Signals 11-4 Table 11-2. UART Power Mode Operation 11-7
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Table 11-3. UART Register Summary. 11-8 Table 11-4. Description 11-9 Table 11-5. Description 11-10 Table 11-6. UCR1 Description 11-11 Table 11-7. UCR2 Description 11-13 Table 11-8. UBRGR Description. 11-14 Table 11-9. Description. 11-14 Table 11-10. Description 11-15
Table 11-11. UPCR Description 11-16 Table 11-12. UDDR Description 11-16 Table 11-13. UPDR Description 11-16 Table 12-1. Register Summary 12-10 Table 12-2. SCPCR Description 12-11 Table 12-3. SCACR Description 12-12 Table 12-4. SCPIER Description 12-13 Table 12-5. SCPSR Description 12-14 Table 12-6. SCPDR Description 12-15 Table 12-7. GPIO Assignments 12-16 Table 12-8. SCPPCR Description 12-16 Table 13-1. Keypad Port pull-up Resistor Control 13-2 Table 13-2. Keypad Port Register Summary 13-4 Table 13-3. KPCR Description 13-5 Table 13-4. Generic Description 13-5 Table 13-5. KDDR Description 13-6 Table 13-6. KPDR Description 13-6 Table 14-1. Pins 14-3 Table 14-2. SAP/BBP Clock Sources 14-4 Table 14-3. Frame Configuration. 14-6 Table 14-4. Interrupts 14-14 Table 14-5. Serial Audio Port Register Summary 14-15 Table 14-6. Baseband Port Register Summary 14-16
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Table 14-7. SAP/BBP Description 14-18 Table 14-8. SAP/BBP Description 14-19 Table 14-9. SAP/BBP Description 14-21 Table 14-10. SAP/BBP Status Register Description 14-22 Table 14-11. SAP/BBP Description 14-24 Table 14-12. SAP/BBP Description 14-24 Table 14-13. SAP/BBP Description 14-25 Table 15-1. JTAG Pins 15-4
Table 15-2. JTAG Instructions 15-6 Table 15-3. Entering OnCE Mode 15-13 Table 15-4. Releasing from Debug Modes 15-14 Table A-1. Table A-2. Table A-3. Table C-1. Table D-1. Table D-2. Table D-3. Table D-4. Table D-5. Table D-6. Table D-7. Table D-8. Table D-9. DSP56652 Boot Modes Message Summary Field Definitions Instruction Summary Instruction Syntax Notation Instruction Opcode Notation Instruction Summary Program Word Timing Symbols D-13 Condition Code Register (CCR) Symbols D-13 Condition Code Register Notation D-13 Internal Memory D-14 Internal Memory D-19
Table D-10. Register Index D-22 Table D-11. DSP56652 Acronym Changes D-26 Table E-1. List Sheets
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List Examples
Example 5-1. Program Loop That Stalls Access Shared Memory Example 5-2. Program Loop With Stall Example 5-3. Dummy Event Allow Track Power Mode Change 5-13 Example 11-1.UART Baud Error Calculation 11-6 Example A-1.Normal Boot A-14
Example A-2.Shared Memory Boot A-15 Example A-3.Messaging Unit Boot A-16
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Preface
This section provides information data conventions used this manual, well list complete product documentation.
Conventions
following conventions used this manual: Bits within registers always listed from most significant (MSB) least significant (LSB). byte bits halfword bits bytes word bits bytes Bits within register indicated AA[n:0] when more than involved description. purposes description, bits presented they were contiguous within register, regardless their actual physical locations register. bits register read/write unless otherwise noted. When described value When described value Register bits that unused reserved future read should written with ensure future compatibility. register descriptions, each these bits indicated with shaded word used three different contexts this manual: There reset instruction that always written lower case, refers reset function. leading capital letter used grammar dictates. refers Reset state. word generic term chip. Because on-chip multiplexing, more than signal present given pin. Pins signals that asserted (made active when pulled ground) have overbar over their name; example, asserted low.
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values indicated with dollar sign preceding value follows: X:$FFFF memory address Interrupt Priority (IPR-C).
Code examples displayed monospaced font, shown Example
Example BFSET #$0007,X:PCC Code Example
Configure: line MISO0, MOSI0, SCK0 masterline ~SS0 GPIO line
code examples, names pins signals that asserted preceded tilde. previous example, line refers (shown ~SS0). word means that high true (active high) signal pulled high that true (active low) signal pulled ground. word means that high true signal pulled ground that true signal pulled high VCC. These conventions summarized Table
Table
Signal/Symbol
Signal States
Signal State Asserted Deasserted Asserted Deasserted Voltage Ground1 VCC2 Ground
Logic State True False True False
Ground acceptable low-voltage level. appropriate data sheet range acceptable low-voltage levels (typically logic low). acceptable high-voltage level. appropriate data sheet range acceptable high-voltage levels (typically logic high).
Documentation
This manual (DSP56652UM/D) five documents that provides complete product information DSP56652. other four documents include following: Reference Manual (MCORERM/AD) MMC2001 Reference Manual (MMC2001M/AD DSP56600 Family Manual (DSP56600FM/AD) DSP56652 Technical Data Sheet (DSP56652/D)
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Chapter Introduction
Motorola designed ROM-based DSP56652 support rigorous demands cellular subscriber market. high level on-chip integration DSP56652 minimizes application system design complexity component count, resulting very compact implementations. This integration also yields very power consumption cost-effective system performance. DSP56652 chip combines 32-bit MicroRISC Engine DSP56600 Digital Signal Processor (DSP) core with on-chip memory, protocol timer, custom peripherals provide single-chip cellular base-band processor. block diagram 56652 shown Figure 1-1.
DSP56652 Features
following list summarizes features DSP56652. (MCU) core 32-bit load/store RISC architecture Fixed 16-bit instruction length 16-entry 32-bit general-purpose register file 32-bit internal address data buses Efficient four-stage, fully interlocked execution pipeline Single-cycle execution most instructions, cycles branches memory accesses Special branch, byte, manipulation instructions Support byte, halfword, word memory accesses Fast interrupt support vectoring/auto-vectoring 16-entry dedicated alternate register file
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DSP56652 Features
Timer/PWM
Watchdog Timer
Programmable Interrupt Timer
Edge
External Memory Clocks OnCE JTAG OnCE Data Data Data
Smart Card
MicroRISC Core
Keypad Queued UART
Interface Dual-Port Data Messaging Unit JTAG Serial Audio CODEC
Data (7+1)K Data Program
56600 Core
Protocol Timer Serial Audio Codec Baseband Codec
DSP56652
Figure 1-1. DSP56652 Block Diagram
core DSP56600 architecture Single-cycle arithmetic instructions Fully pipelined 16-bit parallel multiply accumulator (MAC) 40-bit accumulators including extension bits 40-bit parallel barrel shifter Highly parallel instruction with unique addressing modes Position-independent code support Nested hardware loops
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DSP56652 Features
Fast auto-return interrupts On-chip support software patching enhancements Real-time trace capability external address On-chip memory 32-bit 32-bit 24-bit program 24-bit program
16-bit data 16-bit data (7+1)K 16-bit data 16-bit data On-chip peripherals Fully programmable phase-locked loop (PLL) clock generation External interface module (EIM) glueless system integration External 22-bit address 16-bit data buses 32-source interrupt controller Intelligent MCU/DSP interface (MDI) with 16-bit dual-port well messaging status control unit Serial audio codec port (SAP) Serial baseband codec port (BBP) Protocol timer frees from radio channel timing events Queued serial peripheral interface (QSPI) Keypad port capable scanning matrix keypad General-purpose timers Pulse width modulation (PWM) output Universal asynchronous receiver/transmitter (UART) with FIFO IEEE 1149.1-compliant boundary scan JTAG test access port (TAP) Integrated DSP/MCU On-Chip Emulation module program address visibility mode system development 7816-compatible smart card port
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Architecture Overview
Operating features Comprehensive static dynamic power management operating frequency: 16.8 operating frequency: 58.8 Internal operating voltage range: with V-tolerant Operating temperature: ambient Package option: 196-lead PBGA
Architecture Overview
DSP56652 combines control capability with data processing power DSP56600 core provide complete system solution cellular baseband system. subsystem closed architecture, meaning that memory contained device address data buses appear external device. subsystem provides both on-chip memory external interface. Both processors provide external interrupt pins. cores communicate through MDI, which includes block dual-access RAM. Each core generates independent clock, core contains part clock generation subsystem. Each processor associated peripherals have several low-power standby modes. single JTAG port shared cores debug test purposes. JTAG port integrated with on-chip emulation modules both DSP, providing non-intrusive interact with processors their peripherals memory. additional external debug pins in-circuit emulation. program address multiplexed other DSP56652 pins. pins associated with most peripherals programmed individually function general-purpose input/output signals (GPIO) their primary functions required. (The exceptions pulse width modulator general-purpose timer, which have GPIO capability, SmartCard Port (SCP), whose five pins must function either pins GPIO (i.e., cannot individually programmed).
1.2.1
This section describes core, peripherals, memory.
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Architecture Overview
1.2.1.1 Core Description utilizes four-stage pipeline instruction execution. instruction fetch, instruction decode/register file read, execute, register write-back stages operate overlapped fashion, allowing most instructions execute single clock cycle. Sixteen general-purpose registers provided source operands instruction results. execution unit consists 32-bit arithmetic/logic unit (ALU), 32-bit barrel shifter, find-first-one unit (FFO), result feed-forward hardware, miscellaneous support hardware multiplication multiple register loads stores. Arithmetic logical operations executed single cycle with exception multiply divide instructions. unit operates single clock cycle. program counter unit contains incrementer dedicated branch address adder minimize delays during change-of-flow operations. Memory load store operations provided byte, halfword, word (32-bit) data with automatic zero extension byte halfword load data. These instructions execute clock cycles. Load store multiple register instructions allow overhead context save restore operations. single condition code/carry provided condition testing implement arithmetic logical operations greater than bits. 16-entry alternate register file provided minimize exception processing overhead, supports both vectored auto-vectored interrupts. user programming model contains program counter, sixteen 32-bit generalpurpose registers, carry bit. separate supervisor mode provided exception processing. supervisor programming model includes user registers plus additional sixteen 32-bit general-purpose registers, control registers, scratch registers. complete description architecture, refer Reference Manual. 1.2.1.2 MCU-Side Peripherals MCU-side peripherals DSP56652 support variety functions, including radio channel timing, signal generation, periodic interrupts, smart card interface, displays, pads. keypad port supports rows columns. QSPI enables serial communication multiple peripheral devices through single port.
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Architecture Overview
provides user information external device through smart card port. UART connects modem another computer. edge port enables eight external interrupts. interrupt controller prioritizes peripheral interrupts. Four timers provided, including periodic interval timer generate periodic interrupts watchdog timer protect against system failure general-purpose timer generate custom signals
protocol timer with TDMA counters radio channel control, event scheduling, QSPI triggers generating interrupts either core. OnCE facilitates test debug.
1.2.1.3 MCU-Side Memory memory bits word) wide. On-chip memory includes words words ROM. addition, provides 22-bit address/16-bit data with control signals access external memory. Programmable timing this allows wide range memory devices. many external memory banks connected.
1.2.2
This section describes core, peripherals, memory. 1.2.2.1 Core Description DSP56600 core contains data arithmetic logic unit, address generation unit, program control unit, program patch logic. 1.2.2.1.1 Data Arithmetic Logic Unit data arithmetic logic unit (ALU) performs data arithmetic logical operations core. components data include following: Four 16-bit input general purpose registers: parallel, fully pipelined data registers (A2, that concatenated into general-purpose, 40-bit accumulators, accumulator shifter that asynchronous parallel shifter with 40-bit input 40-bit output
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Architecture Overview
field unit (BFU) with 40-bit barrel shifter data shifter/limiter circuits
data registers read written over data (XDB) data (YDB) 32-bit operands. source operands data ALU, which bits, always originate from data registers. results data operations stored accumulator. seven-stage pipeline executes instruction clock cycle. destination every arithmetic operation used source operand immediate following operation without penalty.
unit comprises main arithmetic processing unit core performs calculations data operands. arithmetic instructions, unit accepts many three input operands outputs 40-bit result, formatted Extension:Most Significant Product:Least Significant Product (EXT:MSP:LSP). multiplier executes 16-bit 16-bit, parallel, fractional multiplies, between signed, unsigned, mixed operands. 32-bit product right-justified added 40-bit contents either accumulator. 40-bit result stored 16-bit operand. either truncated rounded into MSP. Rounding performed specified. 1.2.2.1.2 Address Generation Unit address generation unit (AGU) performs effective address calculations using integer arithmetic necessary address data operands memory contains registers used generate addresses. implements four types arithmetic: linear, modulo, multiple wrap-around modulo, reverse-carry. operates parallel with other chip resources minimize address-generation overhead. divided into halves, each with address ALU. Each address four sets register triplets, each register triplet composed address register, offset register, modifier register. address ALUs identical. Each contains 16-bit full adder (referred offset adder). second full adder (referred modulo adder) adds summed result first full adder modulo value that stored respective modifier register. third full adder (called reverse-carry adder) also provided. offset adder reverse-carry adder parallel share common inputs. only difference between them that they carry propagates opposite directions. Test logic determines which three summed results full adders output.
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Architecture Overview
Each address update address register from respective address register file during instruction cycle. contents associated modifier register specifies type arithmetic used address register update calculation. modifier value decoded address ALU. 1.2.2.1.3 Program Control Unit program control unit (PCU) performs instruction prefetch, instruction decoding, hardware loop control exception processing. implements seven-stage pipeline controls different processing states core. consists three hardware blocks:
program decode controller (PDC) program address generator (PAG) program interrupt controller (PIC)
decodes 24-bit instruction loaded into instruction latch generates signals necessary pipeline control. contains hardware needed program address generation, system stack loop control. arbitrates among interrupt requests generates appropriate interrupt vector address. implements functions using following registers: Counter register Register Address register Counter register Base Address register register Pointer Mode Register Counter register
also includes hardware System Stack (SS). 1.2.2.1.4 Program Patch Logic program patch logic (PPL) block provides adjust program code onchip without generating mask. Implementing code correction done replacing piece ROM-based code with patch program stored RAM. consists four patch address registers four patch address
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Architecture Overview
comparators. Each points starting location code where program flow changed. register compared each PAR. When address fetched instruction identical address stored PARs, program data forced corresponding instruction, replacing instruction that otherwise would have been fetched from ROM. 1.2.2.2 DSP-Side Peripherals DSP-side peripherals DSP56652 primarily targeted handling baseband audio processing.
improved synchronous serial ports connect external codecs process received baseband information. connects standard audio codec. This port also provides generalpurpose timer. connects standard RF/IF codec.
OnCE facilitates test debug.
1.2.2.3 DSP-Side Memory memory contained on-chip. program memory bits wide, while data memory bits halfword) wide. Program 24-bits, program 24-bits. Data memory organized into separate areas, each accessed address data buses. data bits each. data bits, data bits. addition, data memory space serves dual-port MDI.
1.2.3 Interface
provides cores communicate with each other. contains message control unit well 16-bit dual-ported RAM.
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Architecture Overview
1-10
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Chapter Signal/Connection Description
DSP56652 input output signals organized into functional groups Table below Figure page 2-2. Many pins DSP56652 have multiple functions. Table 2-1, function described reflect primary function. Subsequent tables this section named these primary functions provide full descriptions signals pins.
Table 2-1. DSP56652 Signal Functional Group Allocations
Functional Group Power (VCCX) Function-specific ground (GNDX) General ground (GND) clocks Address External Interface Module (EIM) Data control Chip selects Reset, mode, multiplexer control External interrupts Protocol Timer Keypad port UART Queued Serial Peripheral Interface (QSPI) Smart Card Port (SCP) Serial Audio Codec Port (SAP) Baseband Codec Port (BBP) Development Test Emulation port Debug control port JTAG test access port (TAP) Number Signals Table Table Table Table Table 2-10 Table 2-11 Table 2-12 Table 2-13 Table 2-14 Table 2-15 Table 2-16 Table 2-17 Table 2-18 Table 2-19 Table Table Detailed Description Table Table
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DSP56652
VCCA VCCB VCCC VCCD VCCE VCCF VCCG VCCH VCCHQ VCCK VCCP VCCQ GNDA GNDB GNDC GNDD GNDE GNDF GNDG GNDH GNDK GNDP GNDP1 GNDQ CKIH CKIL CKOH PCAP RESET_IN RESET_OUT MUX_CTL INT6/STDA/DSR TRST INT7/SRDA/DTR/SCK DSP_IRQ COL6/OC1 COL7/PWM ROW5/IC2B ROW6/SC2A/DCD DSP_DE ROW7/SCKA/RI RxD/IC1 RTS/IC2 RESET_IN MCU_DE MISO MOSI SIMCLK SENSE SIMDATA SIMRESET PWR_EN STDA SRDA SCKA STDB SRDB SCKB MCU_DE DSP_DE TRST TEST External Interrupts Protocol Timer
Power
Keypad Port
FunctionSpecific Ground
General Ground
UART
Queued Serial Peripheral Interface (QSPI)
Smart Card Port (SCP)
Clocks
Serial Audio Codec Port (SAP)
Baseband Codec Port (BBP) Emulation Port Debug Control Port
External Interface Module (EIM)
Reset, Mode Multiplexer Control
JTAG Test Access Port (TAP)
Figure 2-1. Signal Group Organization
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Power
Power
DSP56652 power pins listed Table 2-2.
Table 2-2. Power
Power Signals VCCA VCCB VCCC Description Address supply isolated power address drivers. supplies isolated power smart card drivers. control supplies power control logic. Data lines supply power data bus. Audio codec port line supplies power audio codec drivers. Clock output line supplies quiet power source CKOUT output. Ensure that input voltage this line well-regulated uses extremely impedance path power rail. bypass capacitor located close possible chip package connect between VCCF line GNDF line. GPIO line supplies power GPIO, keypad, data port, interrupts, STO, JTAG drivers. Baseband codec timer line supplies power baseband codec Timer drivers. Quiet power lines supply quiet power source pre-driver voltage converters. This value should equal maximum value power supplies chip drivers (i.e., maximum VCCA, VCCB, VCCC, VCCD, VCCE, VCCF, VCCG, VCCH, VCCK). Emulation port line supplies power emulation port drivers. Analog circuit line dedicated analog circuits must remain noise-free ensure stable frequency performance. Ensure that input voltage this line well-regulated uses extremely impedance path power rail. capacitor 0.01 capacitor located close possible chip package connect between VCCP line GNDP lines. Quiet lines supply quiet power source internal logic circuits. Ensure that input voltage this line well-regulated uses extremely impedance path power rail. bypass capacitor located close possible chip package connect between VCCQ lines GNDQ lines.
VCCD VCCE VCCF
VCCG VCCH VCCHQ
VCCK VCCP
VCCQ
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Ground
Ground
DSP56652 ground pins listed Table 2-3.
Table 2-3. Ground
Ground Signals GNDA GNDB GNDC Description Address lines connect system ground address bus. lines connect system ground smart card bus. control line connects ground control logic. Data lines connect system ground data bus. Audio codec port lines connect system ground audio codec port. Clock output line supplies quiet ground connection clock output drivers. GPIO lines connect system ground GPIO, keypad, data port, interrupts, STO, JTAG drivers. Baseband codec timer lines connect system ground baseband codec timer drivers. Emulation port lines connect system ground emulation port drivers. Analog circuit line supplies dedicated quiet ground connection analog circuits. Analog circuit line supplies dedicated quiet ground connection analog circuits. Quiet lines supply quiet ground connection internal logic circuits. Substrate lines must tied ground.
GNDD GNDE GNDF GNDG GNDH GNDK GNDP GNDP1 GNDQ
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Clock Phase-Locked Loop
Clock Phase-Locked Loop
pins controlling DSP56652 clocks listed Table 2-4.
Table 2-4. Clock Signals
Signal Name CKIH CKIL Type Input Input Reset State Input Input Signal Description High frequency clock input connected either CMOS square wave sinusoid clock source. frequency clock input should connected square wave with frequency less than equal CKIH. This default input clock after reset. DSP/MCU output signal provides output clock synchronized core internal clock phases, according selected programming option. choices clock source enabling/disabling output signal software selectable. High frequency clock signal provides output clock derived from CKIH input. This signal enabled disabled software. signal used connect required external filter capacitor filter.
Output
Driven
CKOH
Output
Driven
PCAP
Input/ Output
Indeterminate
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External Interface Module
External Interface Module
bus, control, chip select signals listed Table 2-5, Table 2-6, andTable respectively.
Table 2-5. Address Data Buses
Signal Name Type Output Reset State Driven Signal Description Address signals specify address external memory accesses. there external activity, remain their previous values reduce power consumption. Data signals provide bidirectional data external memory accesses. They remain their previous logic state when there external activity reduce power consumption.
Input/ Output
Input
Table 2-6. Control
Signal Name Type Output Reset State Driven high Signal Description signal indicates access type. high signal indicates read. signal indicates write bus. This signal also used memory write enable (WE) signal. When accessing peripheral chip, signal acts read/write. Enable Byte driven low, this signal indicates access data byte during read write cycle. This also write byte enable, programmed. This output used when accessing 8-bit wide SRAM. Enable Byte driven low, this signal indicates access data byte during read write cycle. This also write byte enable, programmed. This output used when accessing 8-bit wide SRAM. driven low, this signal indicates that current access read cycle enables slave devices drive data with read.
Output
Driven high
Output
Driven high
Output
Driven high
Table 2-7. Chip Select Signals
Signal Name Type Output Reset State Chip-driven Signal Description Chip Select signal asserted based decode internal address bits A[31:24] typically used external flash memory chip select. After reset, accesses using have default wait states. Chip Selects signals asserted based decode internal address bits A[31:24] access address. When configured chip selects, these signals become general purpose outputs (GPOs). After reset, these signals GPOs that driven high. Chip Select signal asserted high based decode internal address bits A[31:24] access address. When configured chip select, this signal functions GPO. After reset, this signal that driven low.
Output
Driven high
Output
Driven
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Reset, Mode, Multiplexer Control
Reset, Mode, Multiplexer Control
reset, mode select, multiplexer control pins listed Table 2-8.
Table 2-8. Reset, Mode, Multiplexer Control Signals
Signal Name RESET_IN Type Input Reset State Input Signal Description Reset signal active Schmitt trigger input that provides reset signal internal circuitry. input valid asserted least three CKIL clock cycles. Note: MUX_CTL held high, signal serial data port (UART) becomes RESET_IN input line. (See Table 2-12 page 2-13.)
RESET_OUT
Output
Pulled
Reset signal asserted least seven CKIL clock cycles under following three conditions: RESET_IN pulled least three CKIL clock cycles alternate RESET_IN signal enabled MUX_CTL pulled least three CKIL clock cycles watchdog count expires. This signal asserted immediately after qualifier detects valid RESET_IN signal, remains asserted during RESET_IN assertion, stretched least seven more CKIL clock cycles after RESET_IN deasserted. Three CKIL clock cycles before RESET_OUT deasserted, boot mode latched from signal. Mode signal selects boot mode during hardware reset. should driven least four CKIL clock cycles before RESET_OUT deasserted. driven fetches first word from internal ROM. driven fetches first word from external flash memory. Multiplexer input allows designer select alternate pins used RESET_IN, debug control port signals, JTAG signals follows: Normal (MUX_CTL low) Interrupt signals (See Table 2-9) Keypad signals (See Table 2-11) Serial Data Port (UART) signals (See Table 2-12) INT6/STDA/DSR INT7/SRDA/DTR/SCLK ROW6/SC2A/DCD ROW7/SCKA/RI RxD/IC1 RTS/IC2A Alternate (MUX_CTL high) TRST DSP_DE RESET_IN MCU_DE
Input
Input
MUX_CTL
Input
Input
Output
Chip driven
Soft Turn pin. logic state affected reset.
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Internal Interrupts
Internal Interrupts
With exception alternate signal functions TRST, TMS, DSP_IRQ, signals described Table GPIO when programmed otherwise, default general-purpose inputs (GPI) after reset.
Table 2-9. Interrupt Signals
Signal Name Type Input Output Reset State Input Signal Description Interrupts signals programmed interrupt inputs GPIO signals. interrupt inputs, they programmed level sensitive, positive edge-triggered, negative edge-triggered.
driven INT6 Input Output Input Interrupt selected, this signal programmed interrupt input GPIO signal. interrupt input, programmed level sensitive, positive edge-triggered, negative edge-triggered. Audio Codec Serial Transmit Data programmed STDA, this signal transmits data from serial transmit shift register serial audio codec port. Note: Output When this signal functions STDA, primary STDA signal disabled. (See Table 2-15 page 2-16.)
STDA
Output
Data programmed GPIO output, this signal used output serial data port. (See Table 2-12.)
driven high TRST Input Input Test Reset selected, this signal acts TRST input JTAG test access port (TAP) controller. signal Schmitt trigger input that asynchronously initializes JTAG test controller when asserted. Note: When this signal enabled, primary TRST signal disconnected from controller. (See Table 2-19 page 2-19.)
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Protocol Timer
Table 2-9. Interrupt Signals (Continued)
Signal Name Type Reset State Signal Description
driven INT7 Input Output Input Interrupt selected, this signal programmed interrupt input GPIO signal. interrupt input, programmed level sensitive, positive edge-triggered, negative edge-triggered. Audio Codec Serial Receive Data programmed SRDA, this signal receives data into serial receive shift register serial audio codec port. Note: When this signal used SRDA, primary SRDA signal disabled. (See Table 2-15 page 2-16.)
SRDA
Input
Input
Data Terminal programmed GPIO, this signal used positive negative edge-triggered interrupt input serial data port. (See Table 2-12 page 2-13.) Serial signal provides input clock serial data port (UART). (See Table 2-12 page 2-13.)
SCLK
Input
driven high Input Input Test Mode Select signal input JTAG test access port (TAP) controller. used sequence controller state machine. sampled rising edge TCK. Note: When this signal enabled, primary signal disconnected from controller. Table 2-19 page 2-19
DSP_IRQ
Input
Input
External Interrupt active Schmitt trigger input programmed level-sensitive negative edge-triggered maskable interrupt request input during normal instruction processing. STOP state DSP_IRQ asserted, exits STOP state.
Schmitt trigger interrupt inputs, these signals programmed level sensitive, positive edge-triggered, negative edge-triggered. edge-triggered interrupt initiated when input signal reaches particular voltage level, regardless rise fall time. However, signal transition time increases, probability noise generating extraneous interrupts also increases.
Protocol Timer
Table 2-10 describes eight Protocol Timer signals.
Table 2-10. Protocol Timer Output Signals
Name TOUT7 Type Input Output Reset State Input Signal Description Timer Outputs timer output signals also configured GPIO. default function after reset GPI.
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Keypad Port
Keypad Port
With exception alternate signal functions DSP_DE TCK, signals described Table 2-11 GPIO when programmed otherwise default after reset.
Table 2-11. Keypad Port Signals
Signal Name COL6 Type Input Output Input Output Output Reset State Input Input Signal Description Column Strobe keypad column strobes, these signals programmed regular open drain outputs. Column Strobe keypad column strobe, this signal programmed regular open drain output. Timer Output Compare signal timer output compare signal. Programming this signal function performed using general port control register keypad control register. COL7 Input Output Output Input Column Strobe keypad column strobe, this signal programmed regular open drain output. Output Note: ROW4 ROW5 Input Output Input Output Input Input Input Programming this signal function performed using general port control register keypad control register.
Sense signals function keypad senses. Sense signal functions keypad sense. Timer Input Capture signal input capture input capture timer. Note: Programming this signal function performed using general port control register.
2-10
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Keypad Port
Table 2-11. Keypad Port Signals (Continued)
Signal Name Type Reset State Signal Description
driven ROW6 SC2A Input Output Input Output Input Sense signal functions keypad sense. Audio Codec Serial Control signal provides frame synchronization serial audio codec port. synchronous mode, signal provides frame sync both transmitter receiver. asynchronous mode, signal provides frame sync transmitter only. Note: When this signal used SC2A, primary SC2A signal disabled. (See Table 2-15 page 2-16.)
Output
Data Carrier signal used output serial data port. (See Table 2-12 page 2-13.) Note: Programming these functions done through general port control register control register.
driven high DSP_DE Input Output Input Digital Signal Processor Debug signal functions DSP_DE. normal operation, DSP_DE input that provides means enter debug mode operation from external command converter. When enters debug mode debug request result meeting breakpoint condition, asserts DSP_DE output signal three clock cycles acknowledge that entered debug mode. Note: When this signal enabled, primary DSP_DE signal disabled.
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2-11
Keypad Port
Table 2-11. Keypad Port Signals (Continued)
Signal Name Type Reset State Signal Description
driven ROW7 SCKA Input Output Input Input Sense signal functions keypad sense. Audio Codec Serial Clock signal provides serial rate clock serial audio codec port. synchronous mode, signal provides clock input output both transmitter receiver. asynchronous mode, signal provides clock transmitter only. Note: When this signal used SCKA, primary SCKA signal disabled. (See Table 2-15 page 2-16.)
Output
Ring signal used output serial data port. (See Table 2-12 page 2-13.) Note: Programming these functions done through general port control register control register.
driven high Input Input Test Clock signal provides input JTAG test access port (TAP) controller. used synchronize JTAG test logic. Note: When this signal enabled, primary signal disconnected from controller. (See Table 2-19 page 2-19.)
2-12
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UART
UART
With exception alternate signal functions TDO, TDI, RESET_IN, MCU_DE, signals described Table 2-12 GPIO when programmed otherwise default after reset. remaining UART signals implemented with GPIO pins. Suggested allocations include following: function INT6. (See Table page 2-8.) function INT7. (See Table page 2-8.) function ROW6. (See Table 2-11 page 2-10.) function ROW7. (See Table 2-11 page 2-10.)
Table 2-12. UART Signals
Signal Name Type Reset State Signal Description
driven Input Output Input UART signal transmits data from UART.
driven high Output Test Data Output signal provides serial output test instructions data from JTAG controller. tri-state signal that actively driven shift-IR shift-DR controller states. Note: When this signal enabled, primary signal disconnected from controller. (See Table 2-19 page 2-19.)
driven Input Output Input Input UART signal receives data into UART. Timer Input Capture signal connects input capture/output compare timer used autobaud mode support.
driven high Input Input Test Data signal provides serial input test instructions data JTAG controller. sampled rising edge TCK. Note: When this signal enabled, primary signal disconnected from controller. (See Table 2-19 page 2-19.)
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2-13
UART
Table 2-12. UART Signals (Continued)
Signal Name Type Reset State Signal Description
driven Input Output Input Input Request signal functions UART signal. Timer Input Capture signal connects input capture timer channel.
driven high RESET_IN Input Input Reset signal active Schmitt trigger input that provides reset signal internal circuitry. input valid asserted least three CKIL clock cycles. Note: driven Input Output Input Clear signal functions UART signal. When this signal enabled, primary RESET_IN signal disabled. (See Table page 2-7.)
driven high MCU_DE Input Output Microcontroller Debug input, this signal provides means enter debug mode operation from external command converter. output signal, acknowledges that entered debug mode. When enters debug mode debug request result meeting breakpoint condition, asserts MCU_DE output signal several clock cycles. Note: When this signal enabled, primary MCU_DE signal disabled.
2-14
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QSPI
2.10 QSPI
signals described Table 2-13 GPIO when programmed otherwise default after reset.
Table 2-13. QSPI Signals
Signal Name SPICS4 Type Output Reset State Input Signal Description Serial Peripheral Interface Chip Select output signals provide chip select signals QSPI. signals programmable active high active low. Serial output signal provides serial clock from QSPI accessed peripherals. delay (number clock cycles) between assertion chip select signals first transmission serial clock programmable. polarity phase also programmable. Synchronous Master Slave input signal provides serial data input QSPI. Input data sampled rising falling edge received QSPI most significant least significant first. Synchronous Master Slave output signal provides serial data output from QSPI. Output data sampled rising falling edge transmitted most significant least significant first.
Output
Input
MISO
Input
Input
MOSI
Output
Input
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2-15
2.11
signals described Table 2-14 GPIO when programmed otherwise, default after reset.
Table 2-14. Signals
Signal Name SIMCLK SENSE Type Output Input Input Output Output Output Reset State Input Input Input Input Input Signal Description signal output clock from smart card. signal Schmitt trigger input that signals when smart card inserted removed. bidirectional signal used transmit data receive data from smart card. activate reset inserted smart card driving SIMRESET low. Power active high signal enables external device that supplies smart card, providing effective power management power sequencing SIM. port drives this signal high, external device supplies power smart card. Driving signal disables power card.
SIMDATA SIMRESET PWR_EN
2.12
signals described Table 2-15 GPIO when programmed otherwise default after reset. Note: signals STDA, SRDA, SCKA, SC2A have alternate functions described Table page Table 2-11 page 2-10). When those alternate functions selected, signals disabled.
Table 2-15. Signals
Signal Name STDA SRDA SCKA Type Output Input Input Output Input Output Reset State Input Input Input Signal Description Audio Codec Transmit output signal transmits serial data from audio codec serial transmitter shift register. Audio Codec Receive input signal receives serial data transfers data audio codec receive shift register. Audio Codec Serial bidirectional signal provides serial rate clock. used both transmitter receiver synchronous mode transmitter only asynchronous mode. Audio Codec Serial Clock function determined transmission mode. Synchronous flag Asynchronous receive clock
SC0A
Input
2-16
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Table 2-15. Signals (Continued)
Signal Name SC1A Type Input Output Reset State Input Signal Description Audio Codec Serial Clock function determined transmission mode. Synchronous flag Asynchronous frame sync Audio Codec Serial Clock function determined transmission mode. Synchronous receiver frame sync Asynchronous frame sync
SC2A
Input Output
Input
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2-17
2.13
signals described Table 2-16 GPIO when programmed otherwise default after reset.
Table 2-16. Signals
Signal Name STDB SRDB Type Output Input Input Output Input Output Reset State Input Input Input Signal Description Baseband Codec Transmit output signal transmits serial data from baseband codec serial transmitter shift register. Baseband Codec Receive input signal receives serial data transfers data baseband codec receive shift register. Baseband Codec Serial bidirectional signal provides serial rate clock. used both transmitter receiver synchronous mode transmitter only asynchronous mode. Baseband Codec Serial Clock function determined SCLK mode. Synchronous flag Asynchronous clock Baseband Codec Serial Clock function determined SCLK mode. Synchronous flag Asynchronous frame sync Baseband Codec Serial Clock function determined SCLK mode. Synchronous receiver frame sync Asynchronous frame sync
SCKB
SC0B
Input
SC1B
Input Output
Input
SC2B
Input Output
Input
2.14 Emulation Port
signals described Table 2-17 GPIO when programmed otherwise default after reset.
Table 2-17. Emulation Port Signals
Signal Name PSTAT3 Type Output Output Reset State Input Input Signal Description Data output signals encode data size current access. Pipeline output signals encode internal execution status.
2.15 Debug Port Control
signals described Table 2-18 GPIO when programmed otherwise default after reset.
2-18
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JTAG Test Access Port
Table 2-18. Debug Control Signals
Signal Name MCU_DE Type Input Output Reset State Input Signal Description Microcontroller Debug input, this signal provides means enter debug mode operation from external command converter. output signal, acknowledges that entered debug mode. When enters debug mode debug request result meeting breakpoint condition, asserts MCU_DE output signal several clock cycles. DSP_DE Input Output Input Digital Signal Processor Debug signal functions DSP_DE. normal operation, DSP_DE input that provides means enter debug mode operation from external command converter. When enters debug mode debug request result meeting breakpoint condition, asserts DSP_DE output signal three clock cycles acknowledge that entered debug mode.
2.16 JTAG Test Access Port
When bottom connector pins selected holding MUX_CTL logic high, JTAG pins become inactive, i.e., disconnected from JTAG controller.
Table 2-19. JTAG Port Signals
Signal Name Type Input Input Output Reset State Input Input Tri-stated Signal Description Test Mode input signal used sequence test state machine. sampled rising edge TCK. Test Data input signal used test instructions data. sampled rising edge TCK. Test Data output signal used test instructions data. tri-stated actively driven shift-IR shift-DR controller states. changes falling edge TCK. Test input signal used synchronize JTAG test logic. Test active-low Schmitt-trigger input signal used asynchronously initialize test controller. Factory Test factory test mode. Reserved.
TRST TEST
Input Input Input
Input Input Input
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2-19
JTAG Test Access Port
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Chapter Memory Maps
This section describes internal memory DSP56652. memory maps described separately.
Memory
side DSP56652 single, contiguous memory space with four separate partitions: Internal Internal Memory-mapped peripherals External memory space
These spaces shown Figure page 3-2.
3.1.1
memory allocates Mbyte internal ROM. actual size kbytes, starting address $0000_0000, modulo-mapped into remainder Mbyte space. Read access internal space returns transfer acknowledge (TA) signal except user mode while supervisor protection active, which case transfer error acknowledge signal (TEA) returned, resulting termination access error exception. attempt write space also returns TEA. Software should rely modulo-mapping because future DSP5665x chip implementations behave differently.
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Memory
Base Address $FFFF_FFFF $4500_0000 Reserved $4300_0000 $4600_0000 External Memory Mbytes Allocated Mbytes Addressable $4000_0000 $4100_0000 $4000_0000 $4200_0000 $4400_0000
Reserved General Port Control Emulation Port Control Register CKCTL Register Reserved (12M) Card $0020_B000 Keypad/GPIO $0020_A000 Interrupt Pins Control $0020_9000 Watchdog Timer $0020_8000 $0020_7000 Timers/PWM $0040_0000 QSPI Peripherals (2M) UART $0020_0000 kbytes Internal RAM, Modulo-Mapped Mbyte Space $0010_0000 kbytes Internal ROM, Modulo-Mapped Mbyte Space $0000_0000 External Interface Module $0020_1000 Interrupt Controller $0020_0000 Protocol Timer $0020_3000 $0020_2000 $0020_4000 $0020_5000 $0020_6000 $0020_D000 $0020_CC00 $0020_C800 $0020_C400 $0020_C000
Figure 3-1. Memory
3.1.2
memory allocates Mbyte internal RAM. actual size starting address $0010_0000, modulo-mapped into remainder Mbyte space. Read write access internal space returns except user
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Memory
mode while supervisor protection active, which case returned, resulting termination access error exception. Software should rely modulo-mapping because future DSP5665x chip implementations behave differently.
3.1.3 Memory-Mapped Peripherals
Interface requirements peripherals defined simplify hardware interface implementation while providing reasonable extendable software model. following requirements currently defined (others added future): given peripheral device appears only 4-kbytes region(s) allocated on-chip devices, registers defined bits wide. registers that implement bits, unimplemented bits return zero when read, writes unimplemented bits have effect. general, unimplemented bits should written zero ensure future compatibility. peripherals define exact results 32-bit, 16-bit, 8-bit accesses, according individual peripheral definitions. Misaligned accesses supported, sizing performed accesses registers smaller than access size.
memory allocates Mbyte internal peripherals starting address $0020_0000. Twelve sixteen DSP56652 peripherals allocated kbytes each, four peripherals allocated kbyte each total kbytes. remainder 2-Mbyte space reserved future peripheral expansion. Each peripheral space contain several registers. Details these registers located respective peripheral description sections. Software should explicitly address these registers, making assumptions regarding modulo-mapping. complete list these registers their addresses given Table page D-14. Read accesses unmapped areas within first kbytes peripheral address space returns signal supervisor permission allows. Uninitialized write accesses within first kbytes also return signal alter peripheral register contents. attempted access within reserved portion peripheral memory space ($0020_D000 $003F_FFFF) results termination access error exception from watchdog time-out after clock cycles.
3.1.4 External Memory Space
memory allocates Mbytes external chip access, starting address $4000_0000. external chip selects allocated Mbytes each. Only first 4Mbytes each 16-Mbyte space addressable address lines
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Memory Descriptions
access address more than Mbytes above chip select base address modulo-mapped into first Mbytes. Table page 6-4, more information regarding this portion memory map.
3.1.5 Reserved Memory
portions memory reserved: $0040_0000 $3FFF_FFFF, $4600_0000 $FFFF_FFFF. attempted access within these reserved portions memory space results termination access error exception from watchdog time-out after clock cycles.
Memory Descriptions
DSP56652 core contains three distinct memory spaces: data memory space data memory space program memory space
Each these spaces contains both ROM. addition, data space partitions peripherals MCU-DSP interface (MDI). memory side contained provision connection external memory. three memory spaces shown Figure 3-2.
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Memory Descriptions
Data (16-Bit) $FFFF Internal X-I/O $FF80 $FFFF
Data (16-Bit) $FFFF
Program (24-Bit)
Reserved (14K) $C800 Internal Reserved (22K)
Internal Reserved (~22K)
$A800
$A800 Internal Internal $8000 Internal Reserved (24K) Internal Reserved (26K) $1800 $0800 Internal $0000 $0200 $0000
Internal
$8000
$2000 $1C00
(1K) Internal
Reserved (0.5K) 0.5K Internal
$0000
Figure 3-2. Memory
3.2.1 Data Memory
data 16-bit-wide, internal, static memory occupying lowest locations memory space. upper this space dedicated MDI. data 16-bit-wide, internal, static memory occupying located locations data memory contain DSP-side peripheral registers addressable core registers. This area, referred X-I/O space, accessed MOVE, MOVEP, bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR JSSET). specific addresses registers listed Table page D-19.
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Memory Descriptions
3.2.2 Data Memory
data 16-bit-wide, internal, static memory occupying lowest locations memory space, data 16-bit-wide, internal, static memory occupying locations memory space
3.2.3 Program Memory
Program 24-bit-wide, high-speed, static memory occupying lowest locations memory space,
Program 24-bit-wide, internal, static memory occupying locations first this space contains factory code that enables user download code program MDI. This code described listed Appendix
3.2.4 Reserved Memory
memory locations specified above description reserved should accessed. These areas include following:
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Chapter Core Operation Configuration
This section describes features DSP56652 covered sections describing individual peripherals. These features include following:
Clock configurations both power operation Reset mode, patch addresses, device identification. I/O/ multiplexing
Clock Generation
internal processor clocks, MCU_CLK DSP_CLK, drive cores respectively. Each these clocks derived from either CKIH CKIL clock input pins. Both pins should driven, even input used both internal clocks. CKIH typically frequency range MHz. DSP56652 converts CKIH buffered CMOS square wave which brought externally CKOH clearing CKOHD Clock Control Register (CKCTL). buffer disabled setting CKIHD CKCTL, only MCU_CLK driven CKIL. CKIL usually 32.768 square wave input.
frequency each core clock adjusted manipulating control register bits. reset, MCU_CLK output pin. Software change output DSP_CLK setting CKOS CKCTL. disabled setting CKOD CKCTL. DSP56652 clock scheme shown Figure 4-1.
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Clock Generation
CKIHD
Buffered CKIH
Peripherals Clock Generator DCS_REF
CKIH Sine-to-CMOS
Selector Power-On-Reset Logic
CKOHD
DSP_CLK
CKOH
CKIL
Peripherals
CKOD
Selector
Clock Divider MCD[0:2]
MCU_CLK
Selector
CKOS
Figure 4-1. DSP56652 Clock Scheme
4.1.1 MCU_CLK
MCU_CLK driven either CKIL (buffered) CKIH, according CKCTL. input divided power (i.e., selected bits CKCTL. divider outputs, core clock peripherals, support various low-power modes. peripherals combination CKIL, CKIH, MCU_CLK, shown Table 4-1.
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Clock Generation
Table 4-1. Peripherals Clock Source
Peripheral Protocol Timer QSPI UART MCU_CLK MCU_CLK MCU_CLK CKIH (MCU_CLK interface MCU) Serial clock should slower than MCU_CLK rate. MCU_CLK MCU_CLK CKIL (MCU_CLK interface MCU) CKIL (MCU_CLK interface MCU) MCU_CLK (CKIL interrupt debouncer) CKIH (MCU_CLK interface MCU) Serial clock should slower than equal MCU_CLK. Peripheral Clock Source
Interrupt Controller
Timers Watchdog Timer Interrupt (PIT) GPIO/Keypad
4.1.2 DSP_CLK
clock input, DSP_REF, selected from either CKIL (buffered) CKIH CKCTL. DSP_REF drives clock generator either directly through PLL, according Control Register (PCTL1). clock generator divides input puts core DSP_CLK signal two-phase clock drive peripherals. peripherals also CKIH input. Figure block diagram clock system.
DSP_REF Predivider Loop Frequency Multiplication Power Divider PEN=1 PDF: 4096 PEN=0 2-Phase Chip Clock DSP_REF CLKGEN
Fext
Fext
PVCC
PGND
PVCC
PCAP
Figure 4-2. Clock Generator
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Clock Generation
When enabled, input divided predivide factor bits PCTL1 PCTL0) another divide factor bits PCTL1) which intended decrease DSP_CLK frequency power modes. bits adjusted without losing lock. also multiplies input factor determined bits PCTL0. output frequency PLLOUT DSP_REF clock generator output frequency
DSP_CLK DSP_REF bypassed clearing PCTL1. also disabled power modes clearing PSTP PCTL1. either case, clock generator output DSP_CLK DSP_REF
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Clock Generation
4.1.3 Clock Registers
CKCTL
Clock Control Register
MCD[2:0] CKOHD CKOD CKOS
$0020_C000
CKIHD
RESET
Table 4-2. CKCTL Description
Name Description Clock input clock generator. CKOH output CKOH pin. output pin. CKIH (default). CKIL. CKOH buffered CKIH (default). CKOH held low. outputs either MCU_CLK DSP_CLK according CKOS (default). held high. MCU_CLK (default). DSP_CLK. Settings
CKOHD CKOD
CKOS MCD[2:0] Bits
Source clock reflected pin. Clock Divide divisor clock.
MCD[2:0] $5.$7
Divisor Reserved
CKIHD
Clock clock input CKIH CKIH input buffer
CKIL (default). CKIH. Buffer enabled (default). Buffer disabled cleared.
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Clock Generation
PCTL0
PD[3:0] RESET
Control Register
MF[11:0]
X:$FFFD
Table 4-3. PCTL0 Descriptions
Name PD[3:0] Bits Description Predivider Factor with PD[6:4] (PCTL1 bits define input PDF. Multiplication Factor applied input frequency. Settings Table page 4-7.
MF[11:0] Bits
MF[11:0] $000 $001 $002 $FFE $FFF
(default) 4095 4096
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Clock Generation
PCTL1
Control Register
PD[6:4] PSTP XTLD XTLR
X:$FFFC
DF[2:0]
RESET
Table 4-4. PCTL1 Description
Name PD[6:4] Bits Description Predivider with PD[3:0] from PCTL0 define input frequency divisor. divisor equal plus value PD[6:0]. Settings
PD[6:0] -$7F
Divisor (default)
Clock Output disconnects DSP_CLK from some implementations. DSP56652 this effect. operation. Disabling shuts down lowers power consumption. cleared software time during chip operation. STOP Processing behavior during STOP processing state. Shutting down STOP mode decreases power consumption increases recovery time. disabled (default). DSP_CLK derived directly from DSP_REF. enabled. DSP_CLK derived from output. Disable STOP mode (default). Enable STOP mode.
PSTP
XTLD, XTLR Bits DF[2:0] Bits
These bits affect on-chip crystal oscillator certain implementations. They used DSP56652.
Division clock divisor that determines frequency low-power clock. Changing value bits does cause loss lock condition. These bits should changed rather than MF[11:0] change clock frequency (e.g., when entering low-power mode conserve power).
DF[2:0] -111
(default)
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Power Modes
Power Modes
DSP56652 features several modes operation conserve power under various conditions. Each core independently either normal, WAIT, STOP mode. also DOZE mode, which operates activity level between WAIT STOP. Each low-power mode initiated software instruction, terminated interrupt. wake-up interrupt come from running peripheral. STOP mode, certain stopped peripherals also generate wake-up interrupt. Peripheral operation power modes summarized Table Table 4-6, respectively.
Table 4-5. Peripherals Power Mode
Peripheral Protocol Timer QSPI UART Interrupt Controller Timers Watchdog Timer (O/S interrupt) GPIO/Keypad (MCU side) JTAG/OnCE External interrupt Normal Running Running Running Running Running Running Running Running Running Running Running Running Running WAIT Stopped Running Running Running Running Running Running Running Running Running Running Running Running DOZE Stopped Programmable Programmable Programmable Running Programmable Programmable Running Running Programmable Programmable Programmable Running Stopped Stopped Stopped Stopped; trigger wake-up Stopped; trigger wake-up Stopped Stopped Running Stopped; trigger wake-up Stopped; trigger wake-up Stopped Stopped; trigger wake-up Stopped; trigger wake-up STOP
Table 4-6. Peripherals Power Modes
Peripheral (DSP side) Normal Running Running Running WAIT Running Running Running STOP Stopped; trigger wake-up Stopped Stopped
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Reset
further power conservation, running peripheral given mode, well features summarized Table 4-7, explicitly disabled software.
Table 4-7. Programmable Power-Saving Features
Description Disable CKOH Disable Disable CKIH buffer Disable DSP_CLK Disable Disable STOP mode Register CKCTL Reference Table
PCTL1
Table
Reset
Four events cause DSP56652 reset: Power-on reset RESET_IN asserted Bottom connector (acting RESET_IN) asserted Watchdog timer times Reset from power-on watchdog timer time-out immediately qualified. input circuit qualifies RESET_IN signal from either pin, based duration signal CKIL clock cycles: qualified qualified
qualified reset signal asserts RESET_OUT signal, following reset conditions established:
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Reset
peripherals both cores initialized their default values. Both MCU_CLK DSP_ derived from CKIL. enabled, driving MCU_CLK. CKIH CMOS converter enabled, drives CKOH pin.
eight-cycle circuit guarantees that RESET_OUT asserted least eight CKIL clock cycles. This circuit also stretches negation RESET_OUT. (The precise time between negation RESET_IN RESET_OUT between seven eight CKIL cycles.) Four cycles before RESET_OUT negated, latched. This externally-driven determines whether first instruction fetched from internal external flash memory connected CS0, described Section 4.3.1 page 4-11. Reset timing illustrated Figure 4-3.
RESET_OUT
Low-Frequency Reference RESET_IN Detector Cycle Qualified Watchdog Timer Power-Up Bypass Reset Status Register Cycle Stretcher Cycle Stretcher Internal Resets
RTS/RESET_IN
Latch Signal
Internal Signal
Figure 4-3. DSP56652 Reset Circuit
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Reset
DSP56652 provides read-only Reset Source Register (RSR) determine cause last hardware reset.
Reset Source Register
$0020_C400
RESET
Table 4-8. Description
Name Description Watchdog timer time-out Settings Last reset caused watchdog timer. Last reset caused watchdog timer. Last reset caused RESET_IN. Last reset caused RESET_IN.
External assertion
both external watchdog reset conditions occur simultaneously, external reset precedence, only set. power-on reset occurs with external reset watchdog reset, both bits remain cleared.
4.3.1 Reset
peripherals core configured with their default values when RESET_OUT asserted. Note: General-Purpose Configuration Register (GPCR), which reflected pin, affected reset. uninitialized power-on reset retains current value after RESET_OUT asserted.
input specifies location reset boot device. must driven least four CKIL cycles before RESET_OUT deasserted. driven low, internal disabled asserted first cycle. fetches reset vector from address memory space, which located absolute address $4000_0000 address space. internal disabled first cycle only available subsequent accesses. reset, configured wait states 16-bit port size. Refer Table page more detailed description CS0. driven high, internal enabled fetches reset vector from internal address $0000_0000.
4.3.2 Reset
qualified reset also resets core peripherals their default values. addition, issue hardware software reset through
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Configuration
MCU-DSP Interface (MDI). hardware reset generated setting MCR. software reset generated setting MCVR issue interrupt. this case, interrupt service routine might include following tasks: Issue RESET instruction. Reset other core registers that affected RESET instruction such stack pointer. Jump initial address reset routine, P:$0800.
Once exits reset state, executes bootloader program described Appendix "DSP56652 Bootloader".
reset, CKIL drives clock until RESET_OUT negated, when clock source switched DSP_REF. ensure stable clock, held reset state DSP_REF clocks after RESET_OUT negated. disabled default source DSP_REF CKIH, DSP_CLK frequency equal CKIH recommended that clock sources present both CKIH CKIL pins. However, should CKIH inactive reset, remains reset until sets CKCTL register, selecting CKIL clock source. this case, following sequence recommended: bit. After minimum CKIL cycles, clear bit.
Configuration
contains Operating Mode Register (OMR) configure many features. Four Patch Address Registers (PARs) allow user insert code corrections ROM. Device Identification Register (IDR) also provided.
4.4.1 Operating Mode Register
16-bit read/write core register that controls operating mode DSP56652 provides status flags operation. affected only processor reset, instructions that directly reference (for example, ANDI ORI), instructions that specify destination, such MOVEC instruction.
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Configuration
RESET
Operating Mode Register
Table 4-9. Description
Name Description Address Trace debugging internal activity that traced logic analyzer. Stack Extension Enable Settings Disabled operation. Enabled. External reflects internal program address bus. Disabled (default). Enabled. copy required (default). Copy on-chip hardware stack stack extension memory required.
Extended Stack Wrap sets this when recognizes that stack extension memory requires copy on-chip hardware stack. This flag useful debugging determine speed software-implemented algorithms must increased. Once this only cleared reset MOVE operation OMR. Extended Stack Overflow flag when stack overflow occurs Stack Extended mode. Extended Stack Overflow generated when equals additional push operation requested while Extended mode enabled bit. (i.e., cleared only hardware reset explicit MOVE operation OMR). transition from causes Stack Error interrupt. Extended Stack Underflow when stack underflow occurs Stack Extended mode. Extended Stack Underflow generated when equals additional pull operation requested while Extended mode enabled bit. (i.e., cleared only hardware reset explicit MOVE operation OMR). transition from causes Interrupt Priority Level (IPL) Level Stack Error interrupt. Select Stack memory space stack extension Stop amount delay after wake-up from STOP mode. long delay necessary allow internal clock stabilize. Note: overridden PSTP PCTL1 set, forcing wake-up with delay.
overflow occurred (default). Stack overflow stack extended mode.
underflow occurred (default). Stack underflow stack extended mode.
memory space (default). memory space. Long DSP_CLK cycles (default). Short DSP_CLK cycles.
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Configuration
Table 4-9. Description
Name Description Relative Logic reduce power consumption when PC-relative instructions (branches loops) used. PC-relative instruction issued while causes undetermined results. this then cleared, software should wait instruction pipeline clear least seven instruction cycles) before issuing next instruction. External this disables core external drivers, recommended normal operation reduce power consumption. must cleared Address Tracing. Settings PC-relative instructions used (default). PC-relative instructions disabled.
External circuitry enabled (default). External circuitry disabled.
Operating Mode determine operating mode certain devices. DSP56652, this reflects state DSP_IRQ negation RESET_IN. Operating Mode determine operating mode certain devices. DSP56652, this after reset.
4.4.2 Patch Address Registers
Program patch logic block provides amend program code on-chip without generating mask. Implementing code correction done replacing piece ROM-based code with patch program stored RAM. There four patch address registers addresses Each associated address comparator. When address fetched instruction identical address stored PAR, that instruction replaced instruction jump target address, where patch code resides. patch registers, register addresses jump targets listed Table 4-10.
Table 4-10. Patch JUMP Targets
Patch Register PAR0 PAR1 PAR2 PAR3 Register Address X:$FFF8 X:$FFF7 X:$FFF6 X:$FFF5 JUMP Target $0018 $0078 $0098 $00F8
more information, refer DSP56600 Family Manual (DSP56600FM/AD).
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Multiplexing
4.4.3 Device Identification Register
16-bit read-only factory-programmed register used identify different DSP56600 core-based family members. This information used testing software.
Revision number RESET
Device Identification Register
Derivative number $652
X:$FFF9
Multiplexing
accommodate functions DSP56652 196-pin package, pins multiplex more functions. Eleven these pins multiplex various peripherals, primarily with JTAG Debug Port. other pins multiplex peripherals with Address Trace function.
4.5.1 Debug Port Timer Multiplexing
eight pins listed Table 4-11 multiplex various peripherals with Debug Port. pins Table 4-12 also multiplex different peripherals, part Debug Port. functions these pins determined following controls: Asserting MUX_CTL configures pins Table 4-11 debugging signals, effectively creating alternate pins RESET_IN, MCU_DE, DSP_DE, five JTAG signals. These eight pins brought externally facilitate debugging. Asserting MUX_CTL overrides other controls these pins. MUX_CTL does affect pins Table 4-12. Each eight bits GPCR selects peripheral which associated connected. Five GPCR bits control pins Table 4-11 MUX_CTL asserted); other three bits control pins Table 4-12. Once assigned peripheral (MUX_CTL and/or associated GPCR written), that Port Configuration Register determines configured peripheral function GPIO.
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Multiplexing
Table 4-11. Debug Port Multiplexing
MUX_CTL GPCR MUX_CTL GPCR Module TRST STDA Module Interrupt Controller Interrupt Controller UART GPCR INT6 UART DSR1 SCLK2 DCD3
SRDA
INT7
DSP_DE RESET_IN MCU_DE
Timer
SC2A SCKA IC2A
ROW6 ROW7
function enabled setting GPCR using GPIO Edge Port. function enabled setting GPCR using Edge Port interrupt. SCLK function enabled setting GPCR setting CLKSRC UCR2. function enabled clearing GPCR using GPIO Keypad Port. function enabled clearing GPCR using GPIO Keypad Port. When MUX_CTL connected both UART input Timer input.
Table 4-12. Timer Multiplexing
GPCR GPCR Port Timer Timer Timer IC2B Port COL6 COL7 ROW5 GPCR
Figure shows relationship between these pins their controls.
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Multiplexing
GPC2 COLUMN6/GPIO COLUMN6 GPC3 COLUMN7/GPIO COLUMN7 (UART) ROW5/GPIO IC2B GPC0 GPC4 ROW5 MUX_CTL INT6/DSR/GPIO STDA/GPIO GPC1 INT7/DTR/GPIO SRDA/GPIO GPC5 ROW6/DCD/GPIO SC2A/GPIO GPC6 ROW7/RI/GPIO SCKA/GPIO MUX_CTL GPC7 Input (MCU Timer) GPC7 RTS/GPIO IC2A RESET_IN MUX_CTL CTS/GPIO MCU_DE Tx/GPIO MUX_CTL Rx/GPIO MUX_CTL ROW7 DSP_DE MUX_CTL ROW6 MUX_CTL INT7 TRST MUX_CTL INT6
Figure 4-4. Connectivity Scheme
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Multiplexing
GPCR
RESET
General Port Control Register
$0020_CC00
GPC7 GPC6 GPC5 GPC4 GPC3 GPC2 GPC1 GPC0
Table 4-13. GPCR Description
Name GPC7 Description Settings
Soft Turn value written this reflected pin. This affected reset state MUX_CTL pin. General Port Control functions UART signal Timer signal. Setting MUX_CTL configures alternate RESET_IN signal. (default). IC2.
GPC6
General Port Control functions Keypad ROW7 signal SCKA signal. UART signal implemented using ROW7 general-purpose output. Setting MUX_CTL configures alternate JTAG signal.
ROW7 SCKA.
GPC5
General Port Control functions Keypad ROW6 signal SC2A signal. UART signal implemented clearing GPC5 using ROW6 general-purpose output. Setting MUX_CTL configures alternate DSP_DE signal.
ROW6 DCD. SC2A.
GPC4
General Port Control functions Keypad ROW5 signal Timer signal. This affected MUX_CTL. General Port Control functions Keypad COL7 signal Timer signal. This affected MUX_CTL. General Port Control functions Keypad COL6 signal Timer signal. This affected MUX_CTL.
ROW5 (default). IC2.
GPC3
COL7 (default). PWM.
GPC2
COL6 (default). OC1.
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Multiplexing
Table 4-13. GPCR Description (Continued)
Name GPC1 Description General Port Control functions INT7 signal SRDA signal. Either UART signals implemented GPC1 cleared. signal requires programming interrupt edge port. SCLK signal requires disabling edge port interrupt enabling SCLK UCR2. Setting MUX_CTL configures alternate JTAG signal. Settings INT7 SCLK SRDA.
GPC0
General Port Control functions INT6 signal STDA signal. UART signal implemented clearing GPC0, clearing NIER FIER disable interrupt, configuring GPIO. Setting MUX_CTL configures alternate JTAG TRST signal.
INT6 (default). STDA.
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Multiplexing
4.5.2 Address Visibility
internal activity accessed debugging enabling Address Visibility Mode. this mode, program address lines address strobe signal brought pins listed Table 4-14.
Table 4-14. Function Address Visibility Mode
Peripheral Port Primary Signal COLUMN0 COLUMN1 Borrowed from Keypad Port COLUMN2 COLUMN3 COLUMN4 COLUMN5 ROW0 ROW1 ROW2 ROW3 ROW4 Borrowed from SmartCard Port SIMCLK SENSE SIMDATA SIMRESET PWR_EN Function Trace Address DSP_AT (DSP Address Tracing Strobe) DSP_ADDR0 DSP_ADDR1 DSP_ADDR2 DSP_ADDR3 DSP_ADDR4 DSP_ADDR5 DSP_ADDR6 DSP_ADDR7 DSP_ADDR8 DSP_ADDR9 DSP_ADDR10 DSP_ADDR11 DSP_ADDR12 DSP_ADDR13 DSP_ADDR14 DSP_ADDR15
Address Visibility Multiplexing enabled writing OnCE Test Logic Control Register (OTLCR). OTCLR accessed writing 10011 RS[4:0] field OnCE Command Register (OCR). more information OnCE operation, refer DSP56600 Family Manual.
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Chapter Interface
provides mechanism transferring data control functions between cores DSP56652. consists independent sub-blocks: shared memory space with read/write access both processors status message control unit. primary features include following: 1024 16-bit shared memory data memory space interrupt- poll-driven message control flexible, software-controlled message protocols trigger interrupt (regular non-maskable) writing command vector control register. Each core wake other from low-power modes.
basic block diagram module shown Figure 5-1.
Shared Memory Data Peripheral Address Data Buffers Dual Access Module MCU-Side Control DSP-Side Control
Message Control MCU-Side Registers DSP-Side Registers
Figure 5-1. Block Diagram
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Memory
Memory
DSP56652 provides special memory areas both sides. This section describes where these areas mapped, access contention between areas resolved, memory access timing. Note: There mechanism hardware prevent either core from overwriting area shared memory written other core. responsibility software ensure data integrity shared memory each core.
5.1.1 DSP-Side Memory Mapping
shared mapped data memory space internal data RAM. From functional point view DSP, shared memory indistinguishable from regular data RAM. parallel data path allows write shared memory without restricting stalling accesses way. case simultaneous access from both same memory space, access precedence. programmer must aware, however, that data written that area changed MCU. message control status registers mapped memory regular peripheral, accessible special instructions.
Data Memory X:$FFFF Memory X:$FF80 Base Address X:$F Base Address Control Registers
X:$2000 Shared Memory X:$1C00
X:$0000
Figure 5-2. MDI: DSP-Side Memory Mapping
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Memory
5.1.2 MCU-Side Memory Mapping
allocates 4-kbyte peripheral space MDI, shown Figure 5-3. Control status registers mapped upper words this space, shared memory mapped lower kbytes.
$FFFF_FFFF
$0020_2FFF Control Registers $0020_2FF0
Reserved $0020_27FF $0040_0000 Peripherals (2M) $0020_0000 $0020_2000 Shared Memory
$0000_0000
Figure 5-3. MDI: MCU-Side Memory Mapping
Note:
Writes reserved locations ignored. Reads from reserved locations latch indeterminate data. Neither access terminates access error.
offset conversion formula between internal address offset (which also equal offset) 16-bit addresses offset OFFMCU OFFINT accesses shared memory should evenly aligned, 16-bit accesses ensure valid operation.
5.1.3 Shared Memory Access Contention
Access contentions resolved hardware. access precedence because runs faster clock than MCU, which stalled until access completed. defined simultaneous access (read write) both same Kword shared memory. Simultaneous access different 1/4K blocks shared memory control registers proceed without stall.
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Memory
side contains data buffer store halfword from write request, enabling write with stall even memory array busy with access. However, second access (read write) attempted before buffer cleared, will stall MCU. Some stalls last less then clock, even evident side. other hand, several consecutive 1-cycle accesses memory stall access equivalent number clock cycles. example, Example show program loop that transfers data from memory. attempt access shared memory while loop running will stalled until loop terminates.
Example 5-1. Program Loop That Stalls Access Shared Memory
move move x:(r0)+,a x:(r0)+,b points memory points other memory
#(N/2-1), _BE_NASTY_TO_MCU move x:(r0)+,a a,y:(r4)+ move x:(r0)+,b b,y:(r4)+ _BE_NASTY_TO_MCU move a,y:(r4)+ move b,y:(r4)+
avoid lengthy stall, loop above written allow cycles move, making time slots available accesses, illustrated Example 5-2.
Example 5-2. Program Loop With Stall
#N,_IM_OK_MCU_OK move x:(r0)+,x0 move x0,y:(r4)+ _IM_OK_MCU_OK points memory points other memory
second instruction loop allows pending accesses execute.
5.1.4 Shared Memory Timing
always priority over when accessing shared memory. Every access shared memory control register lasts cycle, executed part pipeline without stalling general, peripheral access clock cycles, excluding instruction fetch time. accesses control registers always clock cycles, shared memory accesses usually take longer, according following parameters: Clock source shared memory: STOP mode, shared memory will operate using clocks generated half frequency.
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Memory
active, will generate memory clocks full frequency accesses should synchronized Access type: write done buffer side. buffer empty, takes cycles write buffer proceeds without stall; writes buffer shared memory later, minimum another cycles, freeing buffer. case read, write when buffer free from previous write, access will stall. Relative frequency clocks: access generates request side that must synchronized clock clocks worst case), acknowledge from side, that must synchronized clock clocks worst case). synchronization stall therefore depends frequency both processors. slower frequency relative frequency, longer access time (measured clocks). typical system configuration, frequency higher equal frequency. this assumption, maximum stall frequencies equal. frequency lower than frequency, access time (measured clocks) principle very long, depending slow parallel accesses: access parallel access same 1/4K memory block further stall pending access. does consecutive one-cycle accesses frequency faster than frequency, contention stall will more than cycle. PLL: reprogrammed during program execution, (e.g., after reset) should access shared memory until reacquired lock. attempts access shared memory before acquires lock, time generate error. avoid this condition take following steps: software sets flag immediately after setting PLL. software polls flag until before accessing shared memory. MCU-side access timing summarized Table 5-1.
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Messages Control
Table 5-1. Access Timing
Access Type Clocks Inactive Active Shared memory write Buffer busy after shared memory write Either Inactive Active Active Cycles1 Comments Minimum Maximum Assumes write buffer empty. Consecutive accesses incur stall cycles. stalls until access completes. Multiple one-cycle instructions stall further. Assumes write buffer empty.
Shared memory read
MCU-DSP shared memory contention Control registers
Either
Minimum case: clock frequency clock frequency. Maximum case: clock frequency clock frequency. (More cycles required clock clock.)
Messages Control
provides means exchange messages independent shared memory array. typical message might have just written message words, starting offset have just finished reading last data block ease flexibility, protocol exchanging these messages predefined hardware implemented with simple software commands.
5.2.1 Messaging System
Messages exchanged between processors through special-purpose control registers. Most these registers symmetric work together exchange messages following ways: Each 16-bit write-only transmit registers copied corresponding read-only receive register other side. These registers used transfer 16-bit messages frame information about messages written shared memory, such number words, initial address, message code type. Writing transmit register clears status register transmitter side sets status register receiver side, which trigger maskable receive interrupt receiver side programmed.
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Messages Control
Reading receive register automatically clears status register receiver side sets status register transmitter side, which trigger maskable transmit interrupt transmitter side programmed. Three general purpose flags provided each transmitter reflected status register receiver side. symmetry registers illustrated Figure Table 5-2.
Module
MTR0 MCVR MRR0 MRR1
MTR1
DTR0 Peripheral DTR1
DRR0
DRR1
Figure 5-4. Register Symmetry Table 5-2. Registers Symmetry
Registers Acronym MRR0 MRR1 MTR0 MTR1 MCVR Name Receive Register Receive Register Transmit Register Transmit Register Status Register Control Register Command Vector Register Acronym DTR0 DTR1 DRR0 DRR1 Registers Name Transmit Register Transmit Register Receive Register Receive Register Control Register Status Register
message exchange mechanism shown greater detail Figure 5-5.
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Messages Control
Transmit Side Data Write Status Register
Transmit Register
Receive Register
Receiver Side Data Read Status Register
Clear TEIE TEIE RFIE Name Transmit Register Empty Receive Register Full Transmit Register Empty Interrupt Enable Receive Register Full Interrupt Enable
Clear
Control Register
Control Register Receive Interrupt Request
Transmit Interrupt Request
RFIE
Figure 5-5. Message Exchange
addition exchanging messages, registers also provide following specialpurpose control functions: Each power mode reflected other status register. Each core issue interrupt wake other core from low-power modes (STOP WAIT modes either side, plus DOZE mode side). issue Command Interrupt setting Command Vector Register (MCVR). Software write vector address this interrupt register side. Command Interrupt maskable non-maskable. issue hardware reset DSP. (The cannot issue hardware reset MCU.) issue general-purpose interrupt requests setting DGIR0 DGIR1 DSP-Side Status Register (DSR). These interrupts user-maskable side. Figure details mechanism which issues general-purpose interrupt MCU.
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Motorola
Messages Control
DSP-Side Status Register Write1 Clear
MCU-Side Status Register Write1 Clear
Control Register Name General-Purpose Interrupt Request General-Purpose Interrupt Pending General-Purpose Interrupt Enable General Interrupt Request
Figure 5-6. DSP-to-MCU General Purpose Interrupt
MCU-to-DSP interrupt mechanism (Command Interrupt) differs from Figure following ways: interrupt pending (the DSR) cleared automatically when interrupt acknowledged. trigger side (the bit) MCVR. When non-maskable interrupt generated, interrupt enable side (the MCIE DCR) ignored.
5.2.2 Message Protocols
message hardware used software implement message protocols wide array message types. Full support given both interrupt polling management. following examples different message protocols: message bits written directly transmit registers. Both transmit registers used pass 2-word message. corresponding receive register first word disables interrupt; register receiving second word enables interrupt. interrupt triggered when second word received. Transmit registers pass frame information describing longer messages written shared memory. Such frame information usually includes initial address, number words, often message type code. general interrupt Command Interrupt signals event request that does include data words, such acknowledging read long message from shared memory.
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Messages Control
Fixed-length, formatted data written predetermined location shared memory. general purpose interrupt (DSP) command interrupt (MCU) signals other processor that data ready. processor uses three general-purpose flags inform other processor current program state.
5.2.3 Interrupt Sources
provides several ways generate interrupts both MCU.
5.2.3.1 Interrupts There five independent ways interrupt through MDI: Command Vector interrupt receive/transmit interrupt wake from STOP general-purpose interrupt (using IRQC interrupt input) Protocol Timer wake from STOP general-purpose interrupt (using IRQD interrupt input) External wake from STOP general-purpose interrupt (using IRQB interrupt input) first three interrupts functions. other protocol timer functions that make hardware have specific instructions. interrupts prioritized Core Interrupt Priority Register (IPRC). Table page 7-15. relative priority receive/transmit interrupts fixed follows: Receive register full (RFIE0) Receive register full (RFIE1) Transmit register empty (TEIE0) Transmit register empty (TEIE1) 5.2.3.2 Interrupts There only interrupt request line interrupt controller. interrupt service routine must examine MCU-Side Status Register (MSR) determine interrupt source. Find First (FF1) instruction used this purpose. some interrupts disabled, software read Control Register (MCR)
5-10 DSP56652 Manual More Information This Product, www.freescale.com Motorola
Low-Power Modes
perform operation with before executing instruction. interrupt service routine should clear General Purpose Interrupt Pending bits (MGIP[1:0], bits deassert request interrupt controller.
5.2.4 Event Update Timing
information exchange between processors that reflected status register receiving processor incurs some latency. This latency delay between event occurrence processor resulting update status register other processor. latency expressed number transmitting-side clocks (TC) receiving-side clocks (RC). minimum event latency occurs when there other events pending, equal 2(RC). maximum event latency incurred when event occurs immediately after previous event issued. equal 4(TC) 6(RC).
5.2.5 MCU-DSP Troubleshooting
following three ways identify correct source malfunction: Examine determine stuck STOP mode. wake setting bit. Issue using Command Interrupt (setting MCVR). service routine incorporate diagnostic procedure designed such event. Note that MNMI must also enable non-maskable interrupts. neither first measures effective, issue hardware reset setting MCR.
Low-Power Modes
Each side fully active low-power modes except STOP. Each processor enter exit low-power mode independently. processor state unchanged transition from low-power control registers return default values.
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Low-Power Modes
5.3.1 Low-Power Modes
Various events awaken from low-power mode (WAIT, DOZE, STOP) generating corresponding interrupt. Table lists events associated interrupt enable bits MCR.
Table 5-3. Wake-up Events
Event Transmitting message MRR0 Transmitting message MRR1 Interrupt Enable (MRIE0) (MRIE1) (MTIE0) (MTIE1) (MGIE0) (MGIE1)
Receiving message from MTR0 Receiving message from MTR1 Setting DGIR0 (General Interrupt request Setting DGIR1 (General Interrupt request
software designer should consider following points before placing STOP mode: Compatibility with STOP mode protocol. software should accommodate possibility that STOP when awakens from STOP mode. Pending shared memory writes. shared memory write that completed when enters STOP mode will execute reliably after awakened. Nevertheless, user wish ensure that shared memory writes completed before entering STOP. This done polling until cleared before issuing STOP instruction. Pending events. software should poll until cleared just before issuing STOP instruction. This ensures that acknowledged previous MCU-generated events that made aware power mode change.
5.3.2 Low-Power Modes
wake from WAIT mode issuing interrupts listed Section 5.2.3.1 page 5-10. software wake from STOP following three ways: Wake from STOP command (setting MSR). Protocol Timer interrupt. hardware reset (setting MCR).
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Low-Power Modes
also wake externally with external interrupt, external debug request, JTAG debug command, system reset. software should ensure that track each transition from STOP mode before next occurs. This essential proper control shared memory clock (see Section 5.3.3). accomplish this provide minimum delay (measured clocks) between consecutive entrances STOP mode. Another method involves waiting register events terminate supply needed delay. With this method sends least register event waits until cleared before enters STOP mode. sure that event takes place, code issue dummy event such illustrated Example 5-3. check should last access before issuing STOP instruction guarantee that updated properly.
Example 5-3. Dummy Event Allow Track Power Mode Change
movep movep jset stop x:<<DCR,x0 x0,x:<<DCR; ;dummy event write back flags ;nops pipeline delay
_wait
#DEP,x:<<DSR,_wait
After wake from STOP command, IRQC should deasserted writing DWSC DSR. Similarly, after protocol timer interrupt event, IRQD should deasserted writing DTIC DSR. Clearing either these bits just exits STOP serve register event delay required before next entry STOP mode.
5.3.3 Shared Memory STOP Mode
shared memory array operates from clock either processor unless STOP mode. access shared memory internally synchronized clock. Memory access signals from require cycles synchronize clock, cycles synchronize acknowledgment clock. runs relatively frequency, extra wait states added access. Note: synchronization wait states related wait states resulting from memory contention.
When STOP mode normal mode, shared memory operates from clock. memory controller alerted when exited
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Resetting
STOP mode stalls pending shared memory access until memory clocks switched back DSP. Note: Waking from STOP take several clocks. parameters affecting relative time length include frequency relative frequency, need relock, state OMR. total wake from STOP delay greater than clocks, pending shared memory access lost time-out interrupt. share
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