Random Access Time Page Mode Read Time Synchronous Burst Frequency Con

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Random Access Time Page Mode Read Time Synchronous Burst Frequency Con

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1.65V 1.95V Read/Write High Performance
Random Access Time Page Mode Read Time Synchronous Burst Frequency Configurable Burst Operation Sector Erase Architecture Eight Word Sectors with Individual Write Lockout Hundred Twenty-seven Word Main Sectors with Individual Write Lockout Typical Sector Erase Time: Word Sectors Word Sectors Four Plane Organization, Permitting Concurrent Read Three Planes Being Programmed/Erased Memory Plane Memory Including Eight Word Sectors Memory Plane Memory Consisting Word Sectors Memory Plane Memory Consisting Word Sectors Memory Plane Memory Consisting Word Sectors Suspend/Resume Feature Erase Program Supports Reading Programming Data from Sector Suspending Erase Different Sector Supports Reading Word Suspending Programming Other Word Low-power Operation Active Standby Write Protection Accelerated Program Operations RESET Input Device Initialization CBGA Package Bottom Boot Block Configuration Available 128-bit Protection Register Common Flash Interface (CFI)
64-megabit Burst/Page Mode 1.8-volt Flash Memory AT49SN6416 AT49SN6416T
Description
AT49SN6416(T) 1.8-volt 64-megabit Flash memory. memory divided into multiple sectors planes erase operations. device read reprogrammed single 1.8V power supply, making ideally suited In-System programming. device configured operate asynchronous/page read (default mode) burst read mode. burst read mode used achieve faster data rate than possible asynchronous/page read mode. signals both tied burst configuration register configured perform asynchronous reads, device will behave like standard asynchronous Flash memory. page mode, signal tied pulsed latch page address. both cases tied GND. AT49SN6416(T) divided into four memory planes. read operation occur three planes which being programmed erased. This concurrent operation allows improved system performance requiring system wait program erase operation complete before read performed. further increase flexibility device, contains Erase Suspend Program Suspend feature. This feature will erase program hold amount
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time user read data from program data remaining sectors. There reason suspend erase program operation data read another memory plane. provides data protection faster programming times. When input below 0.4V, program erase functions inhibited. When 0.9V above, normal program erase operations performed. With 10.0V, program (Dualword Program command) operation accelerated.
Configurations
Name I/O0 I/O15 RESET WAIT VCCQ Function Data Inputs/Outputs Addresses Chip Enable Output Enable Write Enable Address Latch Enable Clock Reset Write Protect Write Protection Power Supply Accelerated Program Operations WAIT Output Power Supply Connect
56-ball CBGA (Top View)
RESET
WAIT I/O12
VCCQ I/O15 I/O6 I/O4 I/O2 I/O1
I/O14 I/013 I/O11 I/O10 I/O9 I/O0 I/O7 I/O5 I/O3 VCCQ I/O8
AT49SN6416(T)
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AT49SN6416(T)
Device Operation
Command Sequences
When device first powered will read mode. Command sequences used place device other operating modes such program erase. command sequences written applying pulse input with high applying low-going pulse input with high. Prior low-going pulse signal, address input latched low-to-high transition signal. pulsed low, address will latched first rising edge Valid data latched rising edge pulse, whichever occurs first. addresses used command sequences affected entering command sequences.
Burst Configuration Command
Program Burst Configuration Register command used program burst configuration register. burst configuration register determines several parameters that control read operation device. determines whether synchronous burst reads enabled asynchronous reads enabled. Since page read operation asynchronous operation, must asynchronous reads enable page read feature. rest bits burst configuration register used only burst read mode. Bits burst configuration register determine clock latency burst mode. latency two, three, four, five cycles. "Clock Latency versus Input Clock Frequency" table shown page "Burst Read Waveform" shown page illustrates clock latency four; data output from device four clock cycles after first valid clock edge following high-to-low edge. configuration register determines polarity WAIT signal. burst configuration register determines number clocks that data will held valid (see Figure 8-1). Hold Data Clock Cycles Read Waveform shown page clock latency affected value bit. burst configuration register determines when WAIT signal will asserted. When synchronous burst reads enabled, linear burst sequence selected setting selects whether burst starts data output will relative falling edge rising edge clock. Bits burst configuration register determine whether continuous fixed-length burst will used also determine whether four-, eight- sixteen-word length will used fixed-length mode. other bits burst configuration register should programmed shown page default state (after power-up reset) burst configuration register also shown page
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Asynchronous Read
There types asynchronous reads pulsed standard asynchronous reads. pulsed read operation device controlled inputs. outputs high-impedance state whenever high. This dual-line control gives designers flexibility preventing contention. data address location defined captured signal will read when low. address location passes into device when low; address latched low-tohigh transition AVD. input levels pins allow data driven device. access time measured from stable address, falling edge falling edge whichever occurs last. During pulsed read, signal static high static low. standard asynchronous reads, signal should tied GND. asynchronous read diagrams shown page
Page Read
page read operation device controlled inputs. input ignored during page read operation should tied GND. page size four words. During page read, signal transition then transition high, transition remain low, tied GND. high transition signal occurs, shown Page Read Cycle Waveform page address latched low-to-high transition signal. However, signal remains after high-to-low transition signal tied GND, shown Page Read Cycle Waveform then page address (determined cannot change during page read operation. first word access page read same asynchronous read. first word read asynchronous speed Once first word read, toggling will result subsequent reads within page being output speed pins both tied GND, device will behave like standard asynchronous Flash memory. page read diagrams shown page
Synchronous Reads
Synchronous reads used achieve faster data rate than possible asynchronous/page read mode. device configured continuous fixed-length burst access. burst read operation device controlled inputs. initial read location determined pulsed asynchronous read operation; memory location device. burst access, address latched first valid clock edge when rising edge signal, whichever occurs first. input signal controls flow data from device burst operation. After clock latency cycles, data next burst address location read each following clock cycle. Figure 3-1. Word Boundary
Word Word Word Word
4-word Boundary
16-word Boundary
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AT49SN6416(T)
Continuous Burst Read
During continuous burst read, number addresses read from memory. When operating linear burst read mode with burst wrap set, device incur output delay when burst sequence crosses first 16-word boundary memory (see Figure 3-1). starting address aligned with 4-word boundary (D0, D12), there delay. starting address aligned with 4-word boundary, output delay incurred. delay depends starting address (see Table 3-1). delay takes place only once, only burst sequence crosses 16-word boundary. indicate that device ready continue burst, device will drive WAIT (B10 during clock cycles which data being presented. Once WAIT driven high (B10 current data will valid. WAIT signal will tri-stated when signal high. Table 3-1. Output Delay
Output Delay Hold Data Clock Cycle, Clock Cycle Clock Cycles Clock Cycles Output Delay Hold Data Clock Cycles, Clock Cycle Clock Cycles Clock Cycles
Starting Address D10, D11,
"Burst Read Waveform" shown page valid address latched point specified clock latency four, data valid within clock edge low-to-high transition clock point results being read. transition clock point results burst read D15. clock transition point does cause data appear output lines because WAIT signal goes (B10 after clock transition, which signifies that first boundary memory been crossed that data available. clock transition point does cause burst read data because WAIT signal goes high (B10 after clock transition indicating that data available. Additional clock transitions, like point will continue result burst reads.
Fixed-length Burst Reads
During fixed-length burst mode read, four, eight sixteen words data burst from device, depending upon configuration. device supports linear burst mode. burst sequence shown page When operating linear burst read mode with burst wrap set, device incur output delay when burst sequence crosses first 16-word boundary memory. starting address aligned with 4-word boundary (D0, D12), there delay. starting address aligned with 4-word boundary output delay incurred. delay depends starting address (see Table 3-1). delay takes place only once, only burst sequence crosses 16-word boundary. indicate that device ready continue burst, device will drive WAIT (B10 during clock cycles which data being presented. Once WAIT driven high (B10 current data will valid. WAIT signal will tri-stated when signal high. "Four-word Burst Read Waveform" page illustrates fixed-length burst cycle. valid address latched point specified clock latency four, data valid within clock edge low-to-high transition clock point results being read. Similarly, output following next clock cycles. Returning high ends read cycle. There output delay burst access wrap mode
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Burst Suspend
Burst Suspend feature allows system temporarily suspend synchronous burst operation system needs Flash address data other purposes. Burst accesses suspended during initial latency (before data received) after device output data. When burst access suspended, internal array sensing continues previously latched internal data retained. Burst Suspend occurs when asserted, current address been latched (either rising edge valid edge), halted, deasserted. halted when VIL. resume burst access, reasserted restarted. Subsequent edges resume burst sequence where left off. Within device, gates WAIT signal. Therefore, during Burst Suspend WAIT signal reverts high-impedance state when deasserted. "Burst Suspend Waveform" page
Reset
RESET input provided ease some system applications. When RESET logic high level, device standard operating mode. level RESET halts present device operation puts outputs device high-impedance state. When high level reasserted RESET pin, device returns read mode.
3.10
Erase
Before word reprogrammed must erased. erased state memory bits logical "1". entire memory erased using Chip Erase command individual planes erased using Plane Erase command individual sectors erased using Sector Erase command.
3.10.1
Chip Erase Chip Erase two-bus cycle operation. automatic erase begins rising edge last pulse. Chip Erase does alter data protected sectors. hardware reset during chip erase will stop erase, data will unknown state.
3.10.2
Plane Erase alternative full Chip Erase, device organized into four planes that individually erased. Plane Erase command two-bus cycle operation. plane whose address valid second rising edge will erased. Plane Erase command does alter data protected sectors.
3.10.3
Sector Erase device organized into multiple sectors that individually erased. Sector Erase command two-bus cycle operation. sector whose address valid second rising edge will erased provided given sector been protected.
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AT49SN6416(T)
3.11 Word Programming
device programmed word-by-word basis. Programming accomplished internal device command register two-bus cycle operation. programming address data latched second cycle. device will automatically generate required internal programming pulses. Please note that cannot programmed back "1"; only erase operations convert "0"s "1"s.
3.12
Flexible Sector Protection
AT49SN6416(T) offers sector protection modes, Softlock Hardlock. Softlock mode optimized sector protection sectors whose content changes frequently. Hardlock protection mode recommended sectors whose content changes infrequently. Once either these modes enabled, contents selected sector read-only cannot erased programmed. Each sector independently programmed either Softlock Hardlock sector protection mode. power-up reset, sectors have their Softlock protection mode enabled.
3.12.1
Softlock Unlock Softlock protection mode disabled issuing two-bus cycle Unlock command selected sector. Once sector unlocked, contents erased programmed. enable Softlock protection mode, two-bus cycle Softlock command must issued selected sector. Hardlock Write Protect (WP) Hardlock sector protection mode operates conjunction with Write Protection (WP) pin. Hardlock sector protection mode enabled issuing two-bus cycle Hardlock software command selected sector. state Write Protect affects whether Hardlock protection mode overridden. When Hardlock protection mode enabled, sector cannot unlocked contents sector read-only. When high, Hardlock protection mode overridden sector unlocked Unlock command. disable Hardlock sector protection mode, chip must either reset power cycled.
3.12.2
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Table 3-2.
Hardlock Softlock Protection Configurations Conjunction with
Hardlock Softlock Erase/ Prog Allowed?
Comments sector locked Sector Softlocked. Unlock command unlock sector. Hardlock protection mode enabled. sector cannot unlocked. sector locked. Sector Softlocked. Unlock command unlock sector. Hardlock protection mode overridden sector locked. Hardlock protection mode overridden sector unlocked Unlock command. Erase Program Operations cannot performed.
Figure 3-2.
Sector Locking State Diagram
UNLOCKED
60h/ [000]
LOCKED
60h/01h [001]
60h/
Power-Up/Reset Default
[011]
Hardlocked
60h/D0h [110]
60h/
[111]
Hardlocked disabled
60h/ [100]
60h/
60h/
Power-Up/Reset Default
60h/ [101]
60h/D0h Unlock Command 60h/01h Softlock Command 60h/2Fh Hardlock Command
Note:
notation denotes locking state sector. current locking state sector defined state bits sector-lock status D[1:0].
AT49SN6416(T)
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AT49SN6416(T)
3.12.3 Sector Protection Detection software method available determine sector protection Softlock Hardlock features enabled. When device software product identification mode read from I/O0 I/O1 address location 00002H within sector will show sector unlocked, softlocked, hardlocked. Table 3-3.
I/O1
Sector Protection Status
I/O0 Sector Protection Status Sector Locked Softlock Enabled Hardlock Enabled Both Hardlock Softlock Enabled
3.13
Read Status Register
status register indicates status device operations success/failure that operation. Read Status Register command causes subsequent reads output data from status register until another command issued. return reading from memory, issue Read command. status register bits output I/O7 I/O0. upper byte, I/O15 I/O8, outputs when Read Status Register command issued. contents status register [SR7:SR0] latched falling edge (whichever occurs last), which prevents possible errors that might occur status register contents change while being read. must toggled with each subsequent status read, status register will indicate completion Program Erase operation. When Write State Machine (WSM) active, will indicate status WSM; remaining bits status register indicate whether successful performing preferred operation (see Table 3-4).
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3.14
Read Status Register Burst Mode
waveform below shows status register read during program operation. two-bus cycle command program operation given followed read status register command. Following read status register command, signal pulsed latch valid address point With signal pulsed specified clock latency three, status register output valid within from clock edge same status register data output successive clock edges. update status register output, signal needs pulsed next data available after clock latency three. status register output also available after chosen clock latency during erase operation.
Figure 3-3.
Read Status Register Burst Mode
ADDRESS
I/O0 I/O15
40H/10H
DATA
WAIT
Note:
WAIT signal burst configuration setting
AT49SN6416(T)
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AT49SN6416(T)
Table 3-4.
WSMS
Status Register Definition
VPPS Notes
WRITE STATE MACHINE STATUS (WSMS) Ready Busy ERASE SUSPEND STATUS (ESS) Erase Suspended Erase Progress/Completed ERASE STATUS (ES) Error Sector Erase Successful Sector Erase PROGRAM STATUS (PRS) Error Programming Successful Programming STATUS (VPPS) Detect, Operation Abort PROGRAM SUSPEND STATUS (PSS) Program Suspended Program Progress/Completed SECTOR LOCK STATUS Prog/Erase attempted locked sector; Operation aborted. operation locked sectors Plane Status (PLS) Note:
Check Write State Machine first determine Word Program Sector Erase completion, before checking program erase status bits. When Erase Suspend issued, halts execution sets both WSMS bits remains until Erase Resume command issued. When this "1", applied number erase pulses sector still unable verify successful sector erasure. When this "1", attempted failed program word status does provide continuous indication level. interrogates level only after Program Erase command sequences have been entered informs system been switched also checked before operation verified WSM. When Program Suspend issued, halts execution sets both WSMS bits "1". remains until Program Resume command issued. Program Erase operation attempted locked sectors, this WSM. operation specified aborted device returned read status mode. Indicates program erase status addressed plane.
Command Sequence Error indicated when SR1, SR3, set.
Table 3-5.
WSMS (SR7)
Status Register Device WSMS Write Status Definition
(SR0) Description addressed plane performing program/erase operation. plane other than currently addressed performing program/erase operation. program/erase operation progress plane. Erase Program suspend bits (SR6, SR2) indicate whether other planes suspended.
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3.15
Erase Suspend/erase Resume
Erase Suspend command allows system interrupt sector erase plane erase operation. erase suspend command does work with Chip Erase feature. Using erase suspend command suspend sector erase operation, system program read data from different sector within same plane. Since this device organized into four planes, there need erase suspend feature while erasing sector when want read data from sector another plane. After Erase Suspend command given, device requires maximum time suspend erase operation. After erase operation been suspended, plane that contains suspended sector enters erase-suspend-read mode. system then read data program data other sector within device. address required during Erase Suspend command. During sector erase suspend, another sector cannot erased. resume sector erase operation, system must write Erase Resume command. Erase Resume command one-bus cycle command, which does require plane address. Read, Read Status Register, Product Entry, Clear Status Register, Program, Program Suspend, Erase Resume, Sector Softlock/Hardlock, Sector Unlock valid commands during erase suspend.
3.16
Program Suspend/program Resume
Program Suspend command allows system interrupt programming operation then read data from different word within memory. After Program Suspend command given, device requires maximum suspend programming operation. After programming operation been suspended, system then read from other word within device. address required during program suspend operation. resume programming operation, system must write Program Resume command. program suspend resume one-bus cycle commands. command sequence erase suspend program suspend same, command sequence erase resume program resume same. Read, Read Status Register, Product Entry, Program Resume valid commands during Program Suspend.
3.17
128-bit Protection Register
AT49SN6416(T) contains 128-bit register that used security purposes system design. protection register divided into 64-bit blocks. blocks designated block block data block non-changeable programmed factory with unique number. data block programmed user locked such that data block cannot reprogrammed. program block protection register, two-bus cycle Program Protection Register command must used shown "Command Definition Table" page lock block two-bus cycle lock protection register command must used shown "Command Definition Table". Data must zero during second cycle. other data bits during second cycle don't cares. determine whether block locked out, status sector command given. data zero, block locked. data one, block reprogrammed. Please "Protection Register Addressing Table" page address locations protection register. read protection register, Product Entry command given followed normal read operation from address within protection register. After determining whether block protected reading protection register, Read command must given return read mode.
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3.18 Common Flash Interface (CFI)
published, standardized data structure that read from flash device. allows system software query installed device determine configurations, various electrical timing parameters, functions supported device. used allow system learn interface flash device most optimally. primary benefits using ease upgrading second source availability. command enter Query mode one-bus cycle command which requires writing data address. Query command written when device ready read data also written when part product mode. Once Query mode, system read data addresses given "Common Flash Interface Definition Table" page return read mode, read command should issued.
3.19
Hardware Data Protection
Hardware features protect against inadvertent programs AT49SN6416(T) following ways: sense: below 1.2V (typical), device reset program erase functions inhibited. power-on delay: once reached sense level, device will automatically time-out (typical) before programming. Program inhibit: holding low, high high inhibits program cycles. Noise filter: pulses less than (typical) inputs will initiate program cycle. less than VILPP.
3.20
Input Levels
While operating with 1.65V 1.95V power supply, address inputs control inputs (OE, driven from 2.5V without adversely affecting operation device. lines driven from VCCQ 0.6V.
3.21
Output Levels
AT49SN6416(T), output high levels equal VCCQ 0.1V (not VCC). VCCQ must regulated between 1.65V 2.25V.
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3.22
Word Program Flowchart
Start
3.23
Word Program Procedure
Command Program Setup Data Comments Data Addr Location program Data Data program Addr Location program Status register data: Toggle update status register Check Ready Busy
Operation Write
Write Word Address
(Setup)
Write
Write Data, Word Address Read Status Register
(Confirm)
Read
Program Suspend Loop
None
Idle
None
Suspend?
Full Status Check Desired)
Repeat subsequent Word Program operations. Full status register check done after each program, after sequence program operations. Write after last operation Read state.
Program Complete
3.24
Full Status Check Flowchart
Read Status Register
3.25
Full Status Check Procedure
Command None None Comments Check SR3: Error Check SR4: Data Program Error Check SR1: Sector locked; operation aborted
Operation Idle
Range Error
Idle
Program Error
Idle
None
Device Protect Error
MUST cleared before Write State Machine allows further program attempts. error detected, clear status register before continuing operations only Clear Status Register command clears status register error bits.
Program Successful
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AT49SN6416(T)
3.26 Program Suspend/Resume Flowchart
Start
3.27
Program Suspend/Resume Procedure
Command Program Suspend Read Status Comments Data Addr Sector address Suspend (SA) Data Addr address within Same Plane Status register data: Toggle update status register Addr address Check Ready Busy Check Program suspended Program completed Data Addr address within Suspended Plane Read data from sector memory other than being programmed Data Addr address
Operation
(Program Suspend)
Write Address
Write
Write Address (Read Status) within Same Plane Read Status Register
Write
Read
None
Program Completed
Idle
None
Write Suspend Plane
(Read Array)
Idle
None
Read Data
Write
(Read Array)
Write
Read Array
Done Reading
Read Data
Read
(Program Resume)
None Program Resume
Write Address
Write
Program Resumed
Suspend Plane placed Read mode: Read Status Return Plane Status mode: Data Addr address within Same Plane
Write Address within Same Plane
(Read Status)
Write
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3.28
Erase Suspend/Resume Flowchart
Start
3.29
Erase Suspend/Resume Procedure
Command Erase Suspend Read Status Comments Data Addr address within Same Plane Data Addr address Status register data: Toggle update status register Addr address within Same Plane Check Ready Busy Check Erase suspended Erase completed Data Addr address Read program data from/to sector other than being erased Data Addr address
Operation
(Erase Suspend)
Write Address
Write
Write Address Read Status Register
(Read Status)
Write
Read
None
Erase Completed
Idle
None
Read Program? Read
Program Loop
Idle
None
Done?
(Erase Resume)
Write Read Write Write
Read Program None Program Resume
Write Address Erase Resumed
Write
(Read Array)
Read Array Data
Write Address within Same Plane
(Read Status)
Suspended Plane placed Read mode Program loop: Read Status Return Plane Status mode: Data Addr address within Same Plane
Write
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AT49SN6416(T)
3.30 Sector Erase Flowchart
Start
3.31
Sector Erase Procedure
Command Sector Erase Setup Erase Confirm None Comments Data Addr Sector erased (SA) Data Addr Sector erased (SA) Status register data: Toggle update status register data Check WSMS Ready WSMS Busy
Operation
(Sector Erase)
Write Sector Address
Write
Write (Erase Confirm) Sector Address Read Status Register
Write
Suspend Erase Loop
Read
Suspend Erase
Idle
None
Full Erase Status Check Desired)
Sector Erase Complete
Repeat subsequent sector erasures. Full status register check done after each sector erase, after sequence sector erasures. Write after last operation enter read mode.
3.32
Full Erase Status Check Flowchart
Read Status Register
3.33
Full Erase Status Check Procedure
Command None Comments Check SR3: Range Error Check SR4, SR5: Both Command Sequence Error Check SR5: Sector Erase Error Check SR1: Attempted erase locked sector; erase aborted.
Operation
Range Error Command Sequence Error
SR4,
Idle
Idle
None
Sector Erase Error
Idle
None
Sector Locked Error
Idle
None
Sector Erase Successful
SR1, must cleared before Write State Machine allows further erase attempts. Only Clear Status Register command clears SR1, SR3, SR4, SR5. error detected, clear status register before attempting erase retry other error recovery.
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3.34
Protection Register Programming Flowchart
Start
3.35
Protection Register Programming Procedure
Command Program Setup Protection Program None Comments Data Addr First Location Program Data Data Program Addr Location Program Status register data: Toggle update status register data Check WSMS Ready WSMS Busy
Operation
(Program Setup)
Write Address
Write Write
Write Address Data
(Confirm Data)
Read Status Register
Read
Idle
None
Full Status Check Desired)
Program Complete
Program Protection Register operation addresses must within protection register address space. Addresses outside this space will return error. Repeat subsequent programming operations. Full status register check done after each program, after sequence program operations. Write after last operation return Read mode.
3.36
Full Status Check Flowchart
Read Status Register Data
3.37
Full Status Check Procedure
Command None None Comments Check SR1, SR3, SR4: 0,1,1 Range Error Check SR1, SR3, SR4: 0,0,1 Programming Error Check SR1, SR3, SR4: Sector locked; operation aborted
Operation
Idle
Range Error
SR3,
Idle
SR1,
Program Error
Idle
None
SR1,
Register Locked; Program Aborted
Program Successful
must cleared before Write State Machine allows further program attempts. Only Clear Status Register command clears SR1, SR3, SR4. error detected, clear status register before attempting program retry other error recovery.
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Command Definition Table
Command Sequence Read Chip Erase Plane Erase Sector Erase Word Program Dual Word Program
(10)
Cycles
Cycle Addr
Cycle Data 40/10 XX(9) XXXX XXXX
(13) (13)
Cycle Data Addr Data
Addr
Addr Addr
DIN0 Addr1 DIN1
Addr
Addr
Addr0
Addr0
Erase/Program Suspend Erase/Program Resume Product Entry Sector Softlock Sector Hardlock Sector Unlock Read Status Register Clear Status Register Program Protection Register Lock Protection Register Sector Status Sector Protection Program Burst Configuration Register Read Burst Configuration Register Query Notes:
(11)(12)
SA(3)
DOUT(5) FFFD DOUT(6) DOUT
(13) (13)
XXXX
XXXX
Addr(7)
Addr(7)
DATA FORMAT shown each cycle follows; I/O7 I/O0 (Hex). I/O15 I/O8 don't care. ADDRESS FORMAT shown each cycle follows: (Hex). Address through don't care. plane address (A21 A20). address within plane used. sector address. word address within sector used designate sector address (see pages details). first cycle address should same word address programmed. status register bits output I/O7 I/O0. data "0", sector locked. data "1", sector reprogrammed. "Burst Configuration Register Table" page Bits burst configuration register determine Addresses select plane. AT49SN6416T: AT49SN6416:
000005 Burst Configuration Register Data from Plane 100005 Burst Configuration Register Data from Plane 200005 Burst Configuration Register Data from Plane 300005 Burst Configuration Register Data from Plane 000005 Burst Configuration Register Data from Plane 100005 Burst Configuration Register Data from Plane 200005 Burst Configuration Register Data from Plane 300005 Burst Configuration Register Data from Plane
address within user programmable protection register region. Please "Protection Register Addressing Table" page This fast programming option enables user program words parallel only when 10V. addresses, Addr0 Addr1, words, DIN0 DIN1, must only differ address This command should used during manufacturing purposes only. During second sycle, manufacturer code read from address PA+00000H, device code read from address PA+00001H, data protection register read from addresses 000081H 000088H (AT49SN6416) addresses 3F8081H 3F8088H (AT49SN6416T). plane address should same during first second cycle. AT49SN6416, xxxx 0000H. AT49SN6416T, xxxx 3F80H.
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Absolute Maximum Ratings*
Temperature under Bias -55°C +125°C Storage Temperature -65°C +150°C Input Voltages Except (Including Pins) with Respect Ground .-0.6V +6.25V Input Voltage with Respect Ground 10.0V Output Voltages with Respect Ground .-0.6V VCCQ 0.6V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Protection Register Addressing Table
Word Notes: Factory Factory Factory Factory User User User User Block
AT49SN6416, address lines specified above table, must when accessing Protection Register. AT49SN6416T, address lines specified above table, must 3F80H when accessing Protection Register.
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AT49SN6416(T)
Burst Configuration Register Table
Program (AT49SN6416) Program (AT49SN6416T) Read B11:(2) 110(1) 1(1)(3) 1(1) 1(1) 1(1) 1(1) 111(1)
1(1) 0(1)
Synchronous Burst Reads Enabled Asynchronous BurstReads Enabled Synchronous Burst Reads Enabled Asynchronous BurstReads Enabled Synchronous Burst Reads Enabled Asynchronous BurstReads Enabled Reserved future Clock Latency Clock Latency Three Clock Latency Four Clock Latency Five Clock Latency WAIT Signal Asserted WAIT Signal Asserted High Hold Data Clock Hold Data Clocks WAIT Asserted during Clock Cycle which Data Valid WAIT Asserted Clock Cycle before Data Valid Linear Burst Sequence Burst Starts Data Output Falling Clock Edge Burst Starts Data Output Rising Clock Edge Reserved Future Reserved future Don't Wrap Accesses Within Burst Length Four-word Burst Eight-word Burst Sixteen-word Burst Continuous Burst
Notes:
Default State Burst configuration setting (clock latency two), (hold data clock cycles) (WAIT asserted clock cycle before data valid) supported. Data ready when WAIT asserted.
Clock Latency versus Input Clock Frequency
Minimum Clock Latency (Minimum Number Clocks Following Address Latch) Input Clock Frequency
Figure 8-1.
Output Configuration
Data Hold Data Hold I/00 I/015 VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT
I/00 I/015
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Sequence Burst Length
Burst Addressing Sequence (Decimal) 4-word Burst Length Linear 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 8-word Burst Length Linear 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14 16-word Burst Length Linear 0-1-2.14-15 1-2-3.15-16 2-3-4.16-17 3-4-5.17-18 4-5-6.18-19 5-6-7.19-20 6-7-8.20-21 7-8-9.21-22 14-15.28-29 15-16.29-30 Continuous Burst Linear 0-1-2-3-4-5-6. 1-2-3-4-5-6-7. 2-3-4-5-6-7-8. 3-4-5-6-7-8-9. 4-5-6-7-8-9-10. 5-6-7-8-9-10-11. 6-7-8-9-10-11-12. 7-8-9-10-11-12-13. 14-15-16-17-18-19-20 15-16-17-18-19-20-21
Start Addr. (Decimal)
Wrap
AT49SN6416(T)
3464C-FLASH-2/05
AT49SN6416(T)
Memory Organization AT49SN6416
Plane Sector SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 Size (Words) Address Range (A21 00000 00FFF 01000 01FFF 02000 02FFF 03000 03FFF 04000 04FFF 05000 05FFF 06000 06FFF 07000 07FFF 08000 0FFFF 10000 17FFF 18000 1FFFF 20000 27FFF 28000 2FFFF 30000 37FFF 38000 3FFFF 40000 47FFF 48000 4FFFF 50000 57FFF 58000 5FFFF 60000 67FFF 68000 6FFFF 70000 77FFF 78000 7FFFF 80000 87FFF 88000 8FFFF 90000 97FFF 98000 9FFFF A0000 A7FFF A8000 AFFFF B0000 B7FFF B8000 BFFFF C0000 C7FFF C8000 CFFFF D0000 D7FFF D8000 DFFFF E0000 E7FFF Plane Sector SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 Size (Words)
Memory Organization AT49SN6416 (Continued)
Address Range (A21 E8000 EFFFF F0000 F7FFF F8000 FFFFF 100000 107FFF 108000 10FFFF 110000 117FFF 118000 11FFFF 120000 127FFF 128000 12FFFF 130000 137FFF 138000 13FFFF 140000 147FFF 148000 14FFFF 150000 157FFF 158000 15FFFF 160000 167FFF 168000 16FFFF 170000 177FFF 178000 17FFFF 180000 187FFF 188000 18FFFF 190000 197FFF 198000 19FFFF 1A0000 1A7FFF 1A8000 1AFFFF 1B0000 1B7FFF 1B8000 1BFFFF 1C0000 1C7FFF 1C8000 1CFFFF 1D0000 1D7FFF 1D8000 1DFFFF 1E0000 1E7FFF 1E8000 1EFFFF 1F0000 1F7FFF 1F8000 1FFFFF 200000 207FFF
3464C-FLASH-2/05
Memory Organization AT49SN6416 (Continued)
Plane Sector SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 Size (Words) Address Range (A21 208000 20FFFF 210000 217FFF 218000 21FFFF 220000 227FFF 228000 22FFFF 230000 237FFF 238000 23FFFF 240000 247FFF 248000 24FFFF 250000 257FFF 258000 25FFFF 260000 267FFF 268000 26FFFF 270000 277FFF 278000 27FFFF 280000 287FFF 288000 28FFFF 290000 297FFF 298000 29FFFF 2A0000 2A7FFF 2A8000 2AFFFF 2B0000 2B7FFF 2B8000 2BFFFF 2C0000 2C7FFF 2C8000 2CFFFF 2D0000 2D7FFF 2D8000 2DFFFF 2E0000 2E7FFF 2E8000 2EFFFF 2F0000 2F7FFF 2F8000 2FFFFF
Memory Organization AT49SN6416 (Continued)
Plane Sector SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Size (Words) Address Range (A21 300000 307FFF 308000 30FFFF 310000 317FFF 318000 31FFFF 320000 327FFF 328000 32FFFF 330000 337FFF 338000 33FFFF 340000 347FFF 348000 34FFFF 350000 357FFF 358000 35FFFF 360000 367FFF 368000 36FFFF 370000 377FFF 378000 37FFFF 380000 387FFF 388000 38FFFF 390000 397FFF 398000 39FFFF 3A0000 3A7FFF 3A8000 3AFFFF 3B0000 3B7FFF 3B8000 3BFFFF 3C0000 3C7FFF 3C8000 3CFFFF 3D0000 3D7FFF 3D8000 3DFFFF 3E0000 3E7FFF 3E8000 3EFFFF 3F0000 3F7FFF 3F8000 3FFFFF
AT49SN6416(T)
3464C-FLASH-2/05
AT49SN6416(T)
Memory Organization AT49SN6416T
Plane Sector SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 Size (Words) Address Range (A21 00000 07FFF 08000 0FFFF 10000 17FFF 18000 1FFFF 20000 27FFF 28000 2FFFF 30000 37FFF 38000 3FFFF 40000 47FFF 48000 4FFFF 50000 57FFF 58000 5FFFF 60000 67FFF 68000 6FFFF 70000 77FFF 78000 7FFFF 80000 87FFF 88000 8FFFF 90000 97FFF 98000 9FFFF A0000 A7FFF A8000 AFFFF B0000 B7FFF B8000 BFFFF C0000 C7FFF C8000 CFFFF D0000 D7FFF D8000 DFFFF E0000 E7FFF E8000 EFFFF F0000 F7FFF F8000 FFFFF 100000 107FFF 108000 10FFFF 110000 117FFF 118000 11FFFF Plane Sector SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 Size (Words)
Memory Organization AT49SN6416T (Continued)
Address Range (A21 120000 127FFF 128000 12FFFF 130000 137FFF 138000 13FFFF 140000 147FFF 148000 14FFFF 150000 157FFF 158000 15FFFF 160000 167FFF 168000 16FFFF 170000 177FFF 178000 17FFFF 180000 187FFF 188000 18FFFF 190000 197FFF 198000 19FFFF 1A0000 1A7FFF 1A8000 1AFFFF 1B0000 1B7FFF 1B8000 1BFFFF 1C0000 1C7FFF 1C8000 1CFFFF 1D0000 1D7FFF 1D8000 1DFFFF 1E0000 1E7FFF 1E8000 1EFFFF 1F0000 1F7FFF 1F8000 1FFFFF 200000 207FFF 208000 20FFFF 210000 217FFF 218000 21FFFF 220000 227FFF 228000 22FFFF 230000 237FFF 238000 23FFFF
3464C-FLASH-2/05
Memory Organization AT49SN6416T (Continued)
Plane Sector SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 Size (Words) Address Range (A21 240000 247FFF 248000 24FFFF 250000 257FFF 258000 25FFFF 260000 267FFF 268000 26FFFF 270000 277FFF 278000 27FFFF 280000 287FFF 288000 28FFFF 290000 297FFF 298000 -29FFFF 2A0000 2A7FFF 2A8000 2AFFFF 2B0000 2B7FFF 2B8000 2BFFFF 2C0000 2C7FFF 2C8000 2CFFFF 2D0000 2D7FFF 2D8000 2DFFFF 2E0000 2E7FFF 2E8000 2EFFFF 2F0000 2F7FFF 2F8000 2FFFFF 300000 307FFF 308000 30FFFF 310000 317FFF 318000 31FFFF 320000 327FFF 328000 32FFFF 330000 337FFF 338000 33FFFF 340000 347FFF
Memory Organization AT49SN6416T (Continued)
Plane Sector SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Size (Words) Address Range (A21 348000 34FFFF 350000 357FFF 358000 35FFFF 360000 367FFF 368000 36FFFF 370000 377FFF 378000 37FFFF 380000 387FFF 388000 38FFFF 390000 397FFF 398000 39FFFF 3A0000 3A7FFF 3A8000 3AFFFF 3B0000 3B7FFF 3B8000 3BFFFF 3C0000 3C7FFF 3C8000 3CFFFF 3D0000 3D7FFF 3D8000 3DFFFF 3E0000 3E7FFF 3E8000 3EFFFF 3F0000 3F7FFF 3F8000 3F8FFF 3F9000 3F9FFF 3FA000 3FAFFF 3FB000 3FBFFF 3FC000 3FCFFF 3FD000 3FDFFF 3FE000 3FEFFF 3FF000 3FFFFF
AT49SN6416(T)
3464C-FLASH-2/05
AT49SN6416(T)
Operating Range
AT49SN6416(T)-70 Operating Temperature (Case) Power Supply Industrial -40°C 85°C 1.65V 1.95V
Operating Modes
Mode Read Burst Read Program/Erase
X(1)
RESET
VPP(4) VIHPP(5) VILPP(6)
DOUT DOUT High
Standby/Program Inhibit
Program Inhibit
Output Disable Reset Product Identification Software Notes:
High VIL, VIH, High Manufacturer Code(3) Device Code(3)
VIH.
Refer programming waveforms. Manufacturer Code: 001FH; Device Code: 00DE AT49SN6416; 00D8H AT49SN6416T. tied VCC. faster program operations, 9.5V 0.5V. VIHPP (min) 0.9V. VILPP (max) 0.4V.
3464C-FLASH-2/05
Characteristics
Symbol ISB1 ICC(1) ICCRE ICCRW Parameter Input Load Current Output Leakage Current Standby Current CMOS Active Current Read While Erase Current Read While Write Current Input Voltage Input High Voltage Output Voltage -100 -400 VCCQ VCCQ 0.25 Condition VI/O VCCQ 0.3V MHz; IOUT MHz; IOUT MHz; IOUT Units
Output High Voltage
Note:
erase mode,
Input Test Waveforms Measurement Level
1.4V DRIVING LEVELS 0.4V 0.9V MEASUREMENT LEVEL
Output Test Load
VCCQ 1.8K OUTPUT 1.3K
Capacitance
MHz, 25°C(1)
COUT Note: Units Conditions VOUT
This parameter characterized 100% tested.
AT49SN6416(T)
3464C-FLASH-2/05
AT49SN6416(T)
Asynchronous Read Timing Characteristics
Symbol tACC1 tACC2 tAHAV tAVLP tAVHP tAAV Parameter Access, Data Valid Access, Address Data Valid Access, Data Valid Data Valid Address Hold from Pulse Width High Pulse Width Address Valid High Data Float Output Hold from Address, Whichever Occurred First RESET Output Delay Units
Pulsed Asynchronous Read Cycle Waveform(1)(2)
I/O0-I/O15 tACC2 -A21 tAAV tAHAV tACC2 tAAV tAVHP tAVLP tACC1 RESET tAHAV DATA VALID
Notes:
After high-to-low transition AVD, remain long address stable. static high static low.
Asynchronous Read Cycle Waveform(1)(2)(3)(4)
ADDRESS VALID
tACC2 HIGH OUTPUT VALID
RESET
I/O0 I/O15
Notes:
delayed tACC after address transition without impact tACC. delayed after falling edge without impact tACC after address change without impact tACC. specified from whichever occurs first pF). should tied low.
3464C-FLASH-2/05
Asynchronous Read Timing Characteristics
Symbol tACC1 tACC2 tAHAV tAVLP tAVHP tAAV tPAA Parameter Access, Data Valid Access, Address Data Valid Access, Data Valid Data Valid Address Hold from Pulse Width High Pulse Width Address Valid High Data Float RESET Output Delay Page Address Access Time Units
Page Read Cycle Waveform 1(1)
I/O0-I/O15 tACC2 -A21 tAAV tAHAV tACC2 tAAV tAVHP tAVLP tACC1 RESET tAHAV tPAA DATA VALID
Note:
After high-to-low transition AVD, remain long page address stable.
Page Read Cycle Waveform 2(1)
I/O0-I/O15 tACC2 -A21 tPAA tACC2 DATA VALID
RESET
Note:
remain long page address stable.
AT49SN6416(T)
3464C-FLASH-2/05
AT49SN6416(T)
Burst Read Timing Characteristics
Symbol tCLK tCKH tCKL tCKRT tCKFT tACK tAVCK tCECK tCKAV tQHCK tAHCK tCKRY tCESAV tAAV tAHAV tCKQV tCEQZ Parameter Period High Time Time Rise Time Fall Time Address Valid Clock Clock Clock Clock High Output Hold from Clock Address Hold from Clock Clock WAIT Delay Setup Address Valid Address Hold From Data Delay High Output High-Z Units
Burst Read Cycle Waveform
tCLK tAHCK tCECK tCESAV tAVCK
tCKH tCKL
tACK
tCKAV tAAV
tAHAV tQHCK
tCKQV
tCEQZ
I/O0-I/O15
A0-A21
tCKRY WAIT tCKRY
Notes:
WAIT signal (dashed line) shown burst configuration register setting WAIT Signal (solid line) shown burst configuration setting After high-to-low transition AVD, remain low.
3464C-FLASH-2/05
Burst Read Waveform (Clock Latency
A0-A21
VALID
I/O0-I/O15
WAIT
HIGH
HIGH
Note:
Dashed line reflects setting configuration register. Solid line reflects setting setting configuration register.
Hold Data Clock Cycles Read Waveform (Clock Latency
A0-A21
I/O0-I/O15
WAIT(1)
Note:
Dashed line reflects burst configuration register setting Solid line reflects burst configuration register setting
AT49SN6416(T)
3464C-FLASH-2/05
AT49SN6416(T)
Four-word Burst Read Waveform (Clock Latency
A0-A21
VALID
I/O0-I/O15
HIGH
HIGH
WAIT
Note:
WAIT signal shown burst configuration register
Burst Suspend Waveform
tCLK
tCKH tCKL
tAHCK tCECK
tCEAV tAVCK tACK tCKAV tAAV I/O0-I/O15 tAHAV tQHCK tCKQV tCEQZ
A0-A21
WAIT
Notes:
WAIT signal (dashed line) shown burst configuration register setting WAIT Signal (solid line) shown burst configuration setting During Burst Suspend, signal held high.
3464C-FLASH-2/05
Word Load Characteristics
Symbol tAAV tAHAV tAVLP tCESAV tWPH tWEAV tCEAV Parameter Address Valid High Address Hold Time from High Pulse Width Data Setup Time Data Hold Time Setup Pulse Width High Pulse Width High Time High Time Units
Word Load Waveforms
31.1 Controlled(1)
I/O0-I/O15
DATA VALID
-A21 tAAV tAHAV tAVLP tWEAV
Note:
After high-to-low transition AVD, remain long input does toggle.
31.2
Controlled(1)
I/O0-I/O15
DATA VALID
-A21 tAAV tAHAV tAVLP tCESAV tCEAV
Note:
After high-to-low transition AVD, remain long input does toggle.
AT49SN6416(T)
3464C-FLASH-2/05
AT49SN6416(T)
Word Load Characteristics
Symbol tWPH Parameter Address Setup Time High Address Hold Time Data Setup Time Data Hold Time Pulse Width High Pulse Width Units
Word Load Waveforms
33.1 Controlled(1)
I/O0 I/O15
DATA VALID
Note:
input should toggle.
33.2
Controlled(1)
I/O0 I/O15
DATA VALID
Note:
input should toggle.
3464C-FLASH-2/05
Program Cycle Characteristics
Symbol tSEC1 tSEC2 tERES Parameter Word Programming Time Write Cycle Time Sector Erase Cycle Time word sectors) Sector Erase Cycle Time (32K word sectors) Erase Suspend Time Program Suspend Time Delay between Erase Resume Erase Suspend Units
Program Cycle Waveforms
PROGRAM CYCLE
tWPH
ADDRESS
INPUT DATA
I/O0 I/O15
Note
Sector, Plane Chip Erase Cycle Waveforms
tWPH
Note
tSEC1/2
I/O0 I/O15
Note WORD
WORD
Notes:
address used load data. must high only when both low. data 10H. chip erase, address used. plane erase sector erase, address depends what plane sector erased. chip erase, data should 21H, plane erase, data should 22H, sector erase, data should 20H.
AT49SN6416(T)
3464C-FLASH-2/05
AT49SN6416(T)
Common Flash Interface Definition Table
Address AT49SN6416T 0051h 0052h 0059h 0003h 0000h 0041h 0000h 0000h 0000h 0000h 0000h 0016h 0019h 00B5h 00C5h 0004h 0000h 0009h 0010h 0004h 0000h 0003h 0003h 0017h 0001h 0000h 0000h 0000h 0002h 007Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h AT49SN6416 0051h 0052h 0059h 0003h 0000h 0041h 0000h 0000h 0000h 0000h 0000h 0016h 0019h 0009h 000Ah 0004h 0000h 0009h 0010h 0004h 0000h 0003h 0003h 0017h 0001h 0000h 0000h 0000h 0002h 0007h 0000h 0020h 0000h 007Eh 0000h 0000h 0001h block erase chip erase 64,300 word write/typ time block erase/typ block erase chip erase/ chip erase Device size device device Multiple byte write supported Multiple byte write supported regions, bytes, (Top); bytes, (Bottom) bytes, (Top); bytes, (Bottom) bytes, (Top); bytes, (Bottom) bytes, (Top); bytes, (Bottom) bytes, (Top); bytes, (Bottom) bytes, (Top); bytes, (Bottom) bytes, (Top);64K bytes, (Bottom) bytes, (Top);64K bytes, (Bottom) write/erase write/erase voltage voltage word write Comments
3464C-FLASH-2/05
Common Flash Interface Definition Table (Continued)
Address AT49SN6416T AT49SN6416 Comments VENDOR SPECIFIC EXTENDED QUERY 0050h 0052h 0049h 0031h 0030h 0050h 0052h 0049h 0031h 0030h Major version number, ASCII Minor version number, ASCII chip erase supported, erase suspend supported, program suspend supported, simultaneous operations supported, burst mode read supported, page mode read supported, queued erase supported, protection bits supported, ("0") bottom ("1") boot block device Undefined bits word linear burst with wrap around, word linear burst with wrap around, word linear burst with wrap around, continuous burst, Undefined bits word page, word page, Undefined bits Location protection register lock byte, section's first byte bytes factory prog section prot register bytes user prog section prot register
00BFh
00BFh
0000h
0001h
000Fh
000Fh
0001h 0080h 0003h 0003h
0001h 0080h 0003h 0003h
AT49SN6416(T)
3464C-FLASH-2/05
AT49SN6416(T)
Ordering Information
38.1
tACC (ns)
Standard Package
(mA) Active Standby 0.035 0.035 Ordering Code AT49SN6416-70CI AT49SN6416T-70CI Package 56C2 56C2 Operation Range Industrial (-40° 85°C) Industrial (-40° 85°C)
Package Type 56C2 56-ball, Plastic Chip-size Ball Grid Array Package (CBGA)
3464C-FLASH-2/05
Packaging Information
39.1 56C2 CBGA
0.12
Seating Plane
Side View
View
0.875
COMMON DIMENSIONS (Unit Measure SYMBOL 0.21 6.90 7.00 5.25 9.90 10.00 4.50 0.75 0.35 10.10 1.00 7.10 NOTE
2.75
Bottom View
1/9/04 2325 Orchard Parkway Jose, 95131 TITLE 56C2, 56-ball Array), Body, 0.75 Ball Pitch Ceramic Ball Grid Array Package (CBGA) DRAWING 56C2 REV.
AT49SN6416(T)
3464C-FLASH-2/05
AT49SN6416(T)
Revision History
Revision Revision March 2004 History Revision April 2004 Initial Release Timing diagrams pages were changed such that default state shown solid line (shown dashed line before). Added note "Burst Configuration Register Table" regarding usee Clock Latency Two. Wrap option removed pages Converted datasheet Template. Removed "Preliminary" from datasheet. Changed value 9.5V 0.5V text, table page table. text also changed show that high voltage improves only programming time. Changed ISB1 spec Modified note added note page Modified note added note page Modified section "Burst Configuration Register Table" page
Revision January 2005
3464C-FLASH-2/05
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3464C-FLASH-2/05

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