Si9143 Current Sharing Controller High Performance Processors

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Si9143 Current Sharing Controller High Performance Processors

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Si9143
Si9143
Current Sharing Controller High Performance Processors
FEATURES
Automatic True Current Sharing with Parallel Converters External Drive Fault Protection Over-Voltage Protection Programmable Over-Current Protection Voltage Mode Control Precision 1.3-V, ±1.6% Reference Drives N-Channel Switch Rectifier 800-µA Quiescent Current kHz) 150-µA Standby Current Integrated "Power Good" Output Synchronization Under-Voltage Lockout
DESCRIPTION
voltage mode, synchronous buck controller designed point-of-use dc/dc conversion high performance server desktop computers. High efficiency accomplished full load driving high- low-side n-channel MOSFETs. input voltage range been designed 4.75 13.2 allow either 1-MHz switching frequency combined with 10-MHz error amplifier provides ultra-fast transient response necessary high performance microprocessor power supply. Si9143 designed provide automatic true current sharing with parallel power supplies. True current sharing reduces stress single supply increases system reliability. system reliability further increased short circuit protection external drive signal disconnect power supply during fault conditions. Si9143 available wide-body 24-pin SSOP package specified operate over commercial 70°C) temperature range. demo board, Si9143DB, available.
FUNCTIONAL BLOCK DIAGRAM
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Si9143
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced AGND VSYNC_IN .-0.3 VSYNC_OUT .-0.3 .-0.3 Voltages Referenced PGND VBST .-0.3 VPGND VAGND Short Continuous VREF Short Continuous VSUPPLY .-0.3 Continuous Power Dissipation 25°C)a 24-Pin SSOPb Operating Temperature Range 70°C Storage Temperature Range 125°C Lead Temperature (soldering, sec). 300°C TJMAX 150°C 104°C/W Notes Device mounted with leads soldered welded board. Derate mW/°C above 25°C.
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS
4.75 13.2 VSUPPLY .13.2 ROSC .100 (100 kHz) MHz) VL(out), (in) Capacitance .4.7 VL(out) Load VREF Capacitance VREF Load Analog Digital Inputs
SPECIFICATIONS
Limits Test Conditions Unless Otherwise Specified Specifications Reference
Output Voltage Regulation Line Rejection IREF IREF 1.30 -1.6% 1.30 1.30 +1.6% 4.75 13.2 70°C
Mina
Typb
Maxa
Unit
Oscillator
Operating Frequency Maximum Duty Cycle High SYNC High SYNC Sync Open fOSC fOSC -100 -100 1000
Output Drivers
Source/Sink (Peak) 4.75 Driver Driver 1000 1000
Supply
Quiescent Current Standby Current Shutdown fosc 1200
Output Voltage Line Rejection 13.2 4.95 6.05
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Si9143
SPECIFICATIONS
Limits Test Conditions Unless Otherwise Specified Specifications SS/Enable
Source Current Fault Sink Current Logic Logic High -2.5 -7.5 4.75 13.2 70°C
Mina
Typb
Maxa
Unit
UVLO (VL)
Lockout Voltage Hysteresis Falling
Error Amplifier
Unity-Gain Product Input Bias Current Offset Voltage Output Current VREF VREF Source (VFB VREF) Sink (VFB VREF) -15.0 15.0
PWR_GOOD
VPWR_GOOD High VPWR_GOOD Output Sink Current Typical Hysteresis VREF +12% -12%
Threshold Voltage VDRIVE Shutdown Delay VREF, 4.75 VICS 13.2
Sink Current
External Drive
VSUPPLY Quiescent Current VDRIVE Source/Sink Current VDRIVE High Voltage VDRIVE Voltage Notes algebraic convention whereby most negative value minimum most positive maximum. Typical values DESIGN ONLY, guaranteed subject production testing. VSUPPLY 13.2 ISOURCE -100 4.75 VSUPPLY 13.2 ISINK 4.75 VSUPPLY 13.2 VSUPPLY
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Si9143
TYPICAL CHARACTERISTICS (25°C UNLESS OTHERWISE NOTED)
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Si9143
TYPICAL CHARACTERISTICS (25°C UNLESS OTHERWISE NOTED)
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Si9143
CONFIGURATION ORDERING INFORMATION
Part Number
Si9143CG Si9143CG-T1
Temperature Range
70°C
Packaging
Bulk Tape Reel
Si9143
Temperature Range
70°C
Board Type
Surface Mount
DESCRIPTION
Number
Symbol
SS/Enable COMP VREF AGND ROSC SYNC VSUPPLY VDRIVE PWR_GOOD PGND VL(out) VL(in) Error amplifier non-inverting input
Description
Soft-Start: Capacitor programmable logic level controlled shutdown Feedback Compensation node external feedback circuit Input Voltage: 4.75 13.2 1.30 precision reference Ground: Connect quiet ground. External resistor determine switching frequency internally connected Synchronizing Clock External supply voltage drive External drive voltage Power_Good window comparator output Power Ground Low-side gate driver synchronous rectifier 5.5-V reference gate drive supply Reference input, connect filter from VL(out) Inductor connection node High-side gate driver power switch Boost capacitor connection node generate high-side gate drive Programmable over current limit output node current sharing
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TIMING DIAGRAMS
FIGURE Start-up Timing Sequence
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Si9143
FIGURE Timing Diagrams
FIGURE Timing Diagrams
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Si9143
DESCRIPTION OPERATION
Si9143 voltage mode synchronous buck controller designed power high performance microprocessor power supply. voltage mode control provides efficiency cost saving advantages over current mode control high output current converters eliminating current sense resistor. Si9143 provides ultra-fast (5-µsec) transient response time necessary protection circuits demanded microprocessor supply designers. Non-Inverting Input non-inverting input error amplifier. converter output voltages equal greater than connected directly VREF. converter output voltages less than connected VREF through voltage divider. SS/Enable Soft-Start/Enable Soft-start accomplished connecting capacitor from this AGND. soft-start functions constant current source into this capacitor. logic (v0.8 this disables output gate drives; oscillator continues function. logic high (w2.4 enables output gate drives, assuming input voltage above UVLO threshold, that over-voltage over-current condition exists. Pins COMP Error Amplifier inverting input error amplifier. voltage this also connected internally input terminals PWR_GOOD comparators fault detection protection. error amplifier 10-MHz gainbandwidth when connected 20-pF load with input voltage. COMP output error amplifier. output voltage clamped maximum level avoid long delays saturation during large transient conditions. minimum COMP voltage diode drop below duty cycle voltage; maximum voltage diode drop above duty cycle voltage. Pins Input Voltage Both pins should connected input voltage optimum performance. input voltage range Si9143 specified operate with either VDC. order accommodate tolerance possibility using this controller 2-cell notebook applications with battery charger, input voltage rated +15-V absolute maximum. VREF Reference Voltage reference voltage designed produce 1.30 ±1.6% over line temperature range, produce equally tight output regulation converter. reference should decoupled with least 100-nF capacitance. reference capable driving external load. AGND Analog Ground AGND analog ground power circuitry converter. This ground should separated locally from PGND, should have separate back input bypass capacitors. ROSC Oscillator Timing Resistor resistor from this AGND determines internal switching frequency oscillator. internal circuitry produces frequency accuracy with timing resistor. oscillator capable switching MHz. SYNC Synchronization SYNC signal generated from internal oscillator. When oscillator ramping positive, SYNC will logic high; when oscillator ramping negative, SYNC will logic low. SYNC used synchronize Si9143 external clock. particular, several Si9143s have their SYNC pins shorted together, they will switch same frequency phase, with frequency being fastest oscillator. Pins VSUPPLY VDRIVE External Drive VDRIVE intended protect converter's load from potentially damaging over-voltage. output voltage exceeds regulation 17%, VDRIVE goes high, driving external blow fuse. VSUPPLY powers VDRIVE signal, could connected separate supply ensure adequate gate drive. PWR_GOOD Open Collector Power Good Signal This signals status output voltage. window comparator ±12% voltage pin, with tolerance PWR_GOOD signal open drain output capable sinking Pins PGND Power Ground PGND power ground high power circuitry converter. This ground should separated locally from AGND, should have separate plane back input bypass capacitors. Pins High- Low-Side Gate Drives high-side low-side gate drive external MOSFETs. Both source sink 2.5-A peak with 4.5-V gate drives. timing sequence high- low-side gate drives shown Figure internal break-beforemake time interval (tBBM) nsec prevents shootthrough current external MOSFETs. ringing from gate drive output's trace inductance produce negative voltages much negative with respect PGND.
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Si9143
gate drive circuit capable withstanding these negative voltages without functional defects. Pins VL(out) VL(in) 5.5-V Linear Regulator VL(out) produces +5.5-V output used gate drive voltage both high- low-side external MOSFETs. gate drive voltage high-side MOSFET bootstrapped (VL(out) VDIODE) above input voltage. VL(out) should bypassed with least decoupling capacitance, should used other external loads. VL(in) drives internal circuitry. should connected through filter VL(out). Inductor Node node used internally float high-side n-channel MOSFET gate drive. During on-time this MOSFET, gate source voltage will (VL(out) VDIODE). node also used internally negative sense voltage overcurrent protection. Bootstrap Voltage external high-side n-channel MOSFET gate drive voltage derived bootstrapping VL(out) voltage input supply voltage. external 100-nF capacitor connected across pins charged (VL(out) VDIODE) when external low-side MOSFETs Then, when low-side MOSFETs turned off, internally connected order turn high-side MOSFET. turned startup ensure initial charging capacitor. Programmable Over-Current Protection over-current protection circuit senses voltage across external high-side n-channel MOSFET determine presence over-current condition. Current sensing occurs only during on-time this MOSFET. trigger level over-current circuit programmable selecting external resistor value connected from ICS. Once over-current circuit been triggered, disables both output gate drives within nsec. circuit also discharges soft-start capacitor shown timing diagram Figure Comparator Output signal used provide true current sharing when multiple Si9143s used system; pins must shorted together enable this feature. signal internally configured open-drain output forming gate logic section. Thus, Si9143s will have precisely same duty cycle, determined with shortest duty cycle, permitting true current sharing. Under Voltage Lock-Out (UVLO) internal UVLO circuit designed prevent converter from starting when insufficient input voltage present. UVLO
S-60752-Rev. 05-Apr-99
disables oscillator, soft-start output drives Si9143 until VL(out) reaches Figure UVLO circuit 200-mV hysteresis prevent turn-on -off oscillations. When oscillator disabled, Si9143 stand-by mode, consumes only supply current. Start-up Timing Sequence Please refer Figure this description. When reaches VL(out) produces least VREF stabilized regulating. UVLO circuit enables oscillator soft-start circuits. Once soft-start voltage exceeds gate drive pulses begin, with duty cycle high-side MOSFET beginning gradually increasing until output voltage regulation.
APPLICATIONS
Current Sharing Si9143 designed permit true load current sharing between multiple paralleled voltage-mode controllers. Traditional voltage-mode controllers support load sharing all-the controller with highest output voltage will attempt provide load current. Even current-mode controllers properly share unless their error amps tied together. Si9143 concept current sharing (Pat. Pend.) that works forcing duty cycles multiple controllers identical. This accomplished tieing together SYNCH pins controllers. SYNCH pins force each controller start their duty cycle same time, which that they same frequency phase; controller with highest frequency controls others. pins force each controller finish their duty cycle same time, causing them have exactly equal duty cycles; controller with smallest duty cycle controls others. current that each converter delivers will thus total current, there total converters parallel. Limitations this scheme dependent primarily matching resistances converter: mismatch resistance results converter delivering more current than another. However, this effect minor practical converter designs, typical current sharing expected within 10%. Paralleling Redundancy Si9143 specifically designed paralleling converters, meaning that multiple converters from same power source deliver power same output (see Figure typical reason such arrangement limitation much power single converter able deliver. limitations often thermal, arise example from finite on-resistance available MOSFETs, causing them self-heat. More power cannot then derived
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Si9143
from single converter, would result thermal runaway devices. Although Si9143 specifically designed redundancy, still usefully used some such situations. Redundancy refers power system design which failure single converter does interfere with continuous delivery power load, current being sourced from other paralleled converters. Paralleled converters thus necessary, sufficient, redundant system: redundant system must also have some preventing failed converter from affecting other converters output power bus. redundant power system utilizing Si9143, isolation shorted converters accomplished orring diodes (see Figure example, output capacitor low-side MOSFET supplies failed short, diode prevents other converters from sourcing current into thus output power remains converter fails having output high, example having highside MOSFET fail shorted, VDRIVE goes high, firing that blows input fuse, disconnecting power from failed MOSFET. Orring Diodes Remote Sensing typical paralleled converter application, outputs multiple Si9143 converters simply attached together. Since converters have true current sharing, orring diodes unnecessary. This makes possible remote sensing: feedback node output voltage converters right load, eliminating voltage droop between converter output load. redundant system, orring diodes necessary isolate failed converters. Voltage feedback must done inside diode, that each controller determine converter causing overvoltage condition. Although there will some degradation regulation forward voltage diode temperature dependence, such degradation minimized using high performance Schottky, such Motorola MBRB2515L. This type part extremely minimizing power loss, very little variation with current temperature. Driving Si9143 provides separate driver driving gate event output overvoltage redundant system. driver source which sufficient drive sensitive gate SCR. normal used, necessary buffer driver, which done shown Figure Setting Current Limit current limit comparing voltage drop across external high-side n-channel MOSFET with voltage dropped across sense resistor connected between ICS. draws constant current, thus equation governing overcurrent threshold
ILimit RMOSFET
Once on-state resistance MOSFET known, selected desired current limit. caution order: since MOSFET will normally quite warm, resistance used equation should maximum resistance elevated temperatures, typical resistance 25°C. designer should also leave adequate margin above normal output current, both account tolerances noise well permit initial high currents while charging output capacitors. Boost Diode application circuit shows 1N4148 diode boost circuit. This provides low-cost component this application. However, advantageous some circuits Schottky diode instead. difference that Schottky less forward drop than regular rectifier, this turn means somewhat greater gate drive voltage external high-side MOSFET. MOSFETs with high gate threshold and/or transconductance, additional gate drive prove very beneficial terms heating MOSFET, turn efficiency converter. 30-V Schottky works well this application. Grounding Si9143 provided with both analog power ground pins (AGND PGND, respectively). Because high gate drive currents Si9143 source, essential that these grounds separated. PGND should attached source external low-side MOSFET; AGND should attached small-signal components circuit, such timing resistor feedback resistor. Each these grounds should back independently input line capacitors, avoid ground loops.
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APPLICATIONS
FIGURE Paralleled Converters
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FIGURE Paralleled Converters with Fault Protection
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FIGURE Driving High-Current Gate
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