P87C51MB2/P87C51MC2 80C51 8-bit microcontroller family with extended m

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P87C51MB2/P87C51MC2 80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
Preliminary specification
2001
Philips Semiconductors
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
GENERAL DESCRIPTION
P87C51Mx2 represents first microcontroller based Philips Semiconductors' 51MX core. P87C51MC2 features Kbytes program memory Kbytes data SRAM, while P87C51MB2 Kbytes Kbytes RAM. addition, both devices equipped with Programmable Counter Array (PCA), watchdog timer that configured different time ranges through bits, well enhanced UARTs enhanced UART SPI. Philips Semiconductors' 51MX (Memory eXtension) core accelerated 80C51 architecture that executes instructions twice rate standard 80C51 devices. linear address range 51MX been expanded support Mbytes program memory 8Mbytes data memory. retains full program code compatibility enable design engineers re-use 80C51 development tools, eliminating need move new, unfamiliar architecture. 51MX core also retains 80C51 compatibility allow continued 80C51-interfaced peripherals Application Specific Integrated Circuits (ASICs). P87C51Mx2 provides greater functionality, increased performance overall lower system cost. offering embedded memory solution combined with enhancements manage memory extension, P87C51Mx2 eliminates need software work-arounds. increased program memory enables design engineers develop more complex programs highlevel language like example, without struggling contain program within traditional Kbytes program memory. These enhancements also greatly improve Language efficiency code size below Kbytes. 51MX core described more details 51MX Architecture Reference.
FEATURES
Extended features 51MX Core: 23-bit program memory space 23-bit data memory space linear program data address range expanded support Mbytes each Program counter expanded bits Stack pointer extended bits enabling stack space beyond 80C51 limitation 23-bit extended data pointer 24-bit universal pointers greatly improve compiler code efficiency using pointers access variables different spaces. 100% binary compatibility with classic 80C51 that existing code completely reusable clock with clock cycles machine cycle Kbytes Kbytes on-chip Kbytes Kbytes on-chip Programmable Counter Array (PCA) full-duplex enhanced UARTs Industry-standard Serial Peripheral Interface (SPI)
BENEFITS
Increases program/data address range Mbytes each Enhances performance efficiency programs Fully 80C51-compatible microcontroller Provides seamless compelling upgrade path from classic 80C51 Preserves 80C51 code base, investment/knowledge, peripherals ASICs Supported 80C51 development programming tools (Keil, Nohau, Micro, etc.) P87C51Mx2 makes possible develop applications lower cost with reduced time-to-market
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
COMPLETE FEATURES
Fully static clock with clock cycles machine cycle Kbytes Kbytes on-chip Kbytes Kbytes on-chip 23-bit program memory space 23-bit data memory space Four-level interrupt priority lines ports) Three Timers: Timer0, Timer1 Timer2 full-duplex enhanced UARTs with baud rate generator Framing error detection Automatic address recognition Supports industry-standard Serial Peripheral Interface (SPI) with baud rate Mbits/sec Power control modes Clock stopped resumed Idle mode Power down mode Second DPTR register Asynchronous port reset Programmable Counter Array (PCA) (compatible with 8xC51Rx+) with five Capture/Compare modules (inhibit ALE) Watchdog timer with programmable prescaler different time ranges (compatible with 8xC66x with added prescaler)
ORDERING INFORMATION
MEMORY PART ORDER NUMBER P87C51MB2BA P87C51MC2BA FREQUENCY VOLTAGE RANGE 2.7-5.5V 2.7-5.5V 4.5-5.5V 4.5-5.5V 2.7-5.5V 0-12MHz 0-12MHz 4.5-5.5V 0-24MHz 0-24MHz
TEMPERATURE RANGE PACKAGE
2048 +70°C, PLCC44 3072 +70°C, PLCC44
SOT187-2 SOT187-2
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
LOGIC SYMBOL
T2EX CEX0 CEX1 CEX2 CEX3 CEX4
Address
Data
PORT0
PORT1
MOSI SPICLK
RXD0 TXD0 INT0 INT1 MISO RXD1 TXD1
P87C51Mx2
PORT4
EA/Vpp PSEN ALE/PROG
XTAL2 XTAL1
2001
Address 8-15
Address 16-22
PORT3
PORT2
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
CONFIGURATION
Function
PLCC44
PLASTIC LEADED CHIP CARRIER
Function
(NC/VDD)1 P2.0/A8/A16 P2.1/A9/A17 P2.2/A10/A18 P2.3/A11/A19 P2.4/A12/A20 P2.5/A13/A21 P2.6/A14/A22 P2.7/A15 PSEN P4.1/TXD1/SS1 EA/Vpp P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0
(NC/VSS) P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1/MOSI P1.5/CEX2/SPICLK P1.6/CEX3 P1.7/CEX4 P3.0/RXD0 P4.0/RXD1/MISO1 P3.1/TXD0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1
Pins were internally connected some derivatives. Please refer section Descriptions details.
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
BLOCK DIAGRAM
High Performance 80C51 (51MX Core)
96K/64K Byte Code EPROM UART
Internal
3K/2K Byte Data Baud Rate Generator
Port Configurable I/Os
UART
Port Configurable I/Os
Port Configurable I/Os
Timer0 Timer1
Port Configurable I/Os
Watchdog Timer
Port Configurable I/Os
(Programmable Counter Array)
Crystal Resonator
Oscillator
Timer2
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
DESCRIPTIONS
MNEMONIC P0.0 P0.7 TYPE NAME FUNCTION Port Port open drain, bidirectional port. Port pins that have written them float used high-impendance inputs. Port also multiplexed loworder address data during accesses external program data memory. this application, uses strong internal pull-ups when emitting Port Port 8-bit bidirectional port with internal pull-ups pins. Port pins that have written them pulled high internal pull-ups used inputs. inputs, port pins that externally pulled will source current because internal pull-ups. (Note: When SPEN (SPCTL.6) '1', pull-ups P1.4 P1.5 disabled.) P1.0 P1.1 P1.2 P1.3 P1.4 T2EX CEX0 CEX1 MOSI P1.5 CEX2 SPICLK P1.6 P1.7 CEX3 CEX4 Timer/Counter external count input/Clockout Timer/Counter Reload/Capture/Direction Control External Clock Input Capture/Compare External module Capture/Compare External module (with pull-up pin) Master Out/Slave (Selected when SPEN (SPCTL.6) '1', which case pull-up this disabled) Capture/Compare External module (with pull-up pin) Clock (Selected when SPEN (SPCTL.6) '1', which case pull-up this disabled) Capture/Compare External module Capture/Compare External module
P1.0 P1.7
P2.0 P2.7
Port Port 8-bit bidirectional port with internal pull-ups. Port pins that have written them pulled high internal pull-ups used inputs. inputs, port pins that externally being pulled will source current because internal pull-ups. (See Electrical Characteristics: Port emits high-order address byte during fetches from external program memory during accesses external data memory that 16-bit addresses MOVX DPTR) 23-bit addresses (MOVX @EPTR, EMOV). this application, uses strong internal pull-ups when emitting During accesses external data memory that 8-bit addresses Ri), port2 emits contents Special Function Register. Note that when 23-bit address used, address bits A16-A22 will output P2.0-P2.6 when High, address bits A8-A14 output P2.0-P2.6 when Low. Address output P2.7 regardless ALE.
P3.0 P3.7
11,13
Port Port 8-bit bidirectional port with internal pull-ups. Port pins that have written them pulled high internal pull-ups used inputs. inputs, port pins that externally pulled will source current because internal pull-ups. P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 RXD0 TXD0 INT0 INT1 Serial input port Serial output port External interrupt External interrupt Timer0 external input Timer1 external input External data memory write strobe External data memory read strobe
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
MNEMONIC P4.0 P4.1
12,34
TYPE NAME FUNCTION Port Port 8-bit bidirectional port with internal pull-ups pin. Port pins that have written them pulled high internal pull-ups used inputs. inputs, port pins that externally pulled will source current because internal pull-ups. (Note: When SPEN (SPCTL.6) '1', pull-ups these port pins disabled.) P4.0 RXD1 MISO P4.1 TXD1 Serial input port (Note: This connect some derivatives.) (with pull-up pin) Master In/Slave (Selected when SPEN (SPCTL.6) '1', which case pull-up this disabled) Serial output port (Note: This connect some derivatives.) (with pull-up pin) Slave Select (Selected when SPEN (SPCTL.6) '1', which case pull-up this disabled)
Reset: high this machine cycles while oscillator running, resets device. internal diffused resistor permits power-on reset using only external capacitor VDD. Address Latch Enable: Output pulse latching byte address during access external memory. normal operation, emitted constant rate oscillator frequency, used external timing clocking. Note that pulse skipped during each access external data memory. (AUXR.0) '0', emitted constant rate indicated above. With this '1', will active only during MOVX instruction. Program Store Enable: read strobe external program memory. When executing code from external program memory, PSEN activated twice each machine cycle, except that PSEN activations skipped during each access external data memory. PSEN activated during fetches from internal program memory. External Access Enable/Programming Supply Voltage: must externally held enable device fetch code from external program memory locations. held high, device executes from internal program memory. value latched when released subsequent changes have effect. Crystal Input inverting oscillator amplifier input internal clock generator circuits. Crystal Output from inverting oscillator amplifier. Ground: reference. Power Supply: This power supply voltage normal operation well Idle Power Down modes. Connect/Ground: This connect some derivatives, internally connected P87C51Mx2. connected externally, this must only connected same (Note: Connecting second pair pins required. However, they connected addition primary pins improve power distribution, reduce noise output signals, improve system-level characteristics.) Connect/Power Supply: This connect some derivatives, internally connected P87C51Mx2. connected externally, this must only connected same (Note: Connecting second pair pins required. However, they connected addition primary pins improve power distribution, reduce noise output signals, improve system-level characteristics.)
PSEN
EA/Vpp
XTAL1 XTAL2 (NC/VSS)
(NC/VDD)
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
SPECIAL FUNCTION REGISTERS
Note: Special Function Register (SFR) accesses restricted following ways: User must attempt access locations defined. bits labeled '-', ONLY written read follows: MUST written with '0', return value when read (even written with '0'). reserved used future derivatives. MUST written with '0', will return when read. MUST written with '1', will return when read.
Special Function Registers
SYMBOL DESCRIPTION DIRECT ADDRESS ADDRESS, SYMBOL, ALTERNATE PORT FUNCTION Reset Value
ACC* Accumulator
AUXR#
Auxiliary Function Register
EXTRAM
00H%
AUXR1#
Auxiliary Function Register
LPEP
00H%
Register
Baud Rate Generator Rate Baud Rate Generator Rate High
BRATE11 BRATE10 BRATE9 BRATE3 BRATE2 BRATE1
BRATE8 BRATE0
BRATE7
BRATE6
BRATE5
BRATE4
00H%
BRGCON# Baud Rate Generator Control
S0BRGS
BRGEN
00H%
CCAP0H# CCAP1H# CCAP2H# CCAP3H# CCAP4H# CCAP0L# CCAP1L# CCAP2L# CCAP3L# CCAP4L#
Module Capture High Module Capture High Module Capture High Module Capture High Module Capture High Module Capture Module Capture Module Capture Module Capture Module Capture
ECOM_0 ECOM_1 ECOM_2 ECOM_3 ECOM_4 CAPP_0 CAPP_1 CAPP_2 CAPP_3 CAPP_4 CAPN_0 CAPN_1 CAPN_2 CAPN_3 CAPN_4 MAT_0 MAT_1 MAT_2 MAT_3 MAT_4 TOG_0 TOG_1 TOG_2 TOG_3 TOG_4 PWM_0 PWM_1 PWM_2 PWM_3 PWM_4 ECCF_0 ECCF_1 ECCF_2 ECCF_3 ECCF_4
00H% 00H% 00H% 00H% 00H%
CCAPM0# Module Mode CCAPM1# Module Mode CCAPM2# Module Mode CCAPM3# Module Mode CCAPM4# Module Mode
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
Special Function Registers (Continued)
SYMBOL DESCRIPTION DIRECT ADDRESS ADDRESS, SYMBOL, ALTERNATE PORT FUNCTION Reset Value
CCON# CMOD# Counter Control Counter High Counter Counter Mode CIDL
CCF4
CCF3
CCF2
CCF1
CCF0 00H%
WDTE
CPS1
CPS0
00H%
DPTR
Data Pointer bytes) Data Pointer High Data Pointer
EPL# EPM# EPH#
Extended Data Pointer Extended Data Pointer Middle Extended Data Pointer High
IEN0* Interrupt Enable
ES0/ ES0R
IEN1* Interrupt Enable
ESPI
ES1T
ES0T
ES1/ ES1R 00H%
IP0* Interrupt Priority
PS0/ PS0R
IP0H
Interrupt Priority High
PPCH
PT2H
PS0H/ PS0RH
PT1H
PX1H
PT0H
PX0H
IP1* Interrupt Priority
PSPI
PS1T
PS0T
PS1/ PS1R 00H%
IP1H
Interrupt Priority High
PSPIH
PS1TH
PS0TH
PS1H/ PS1RH
00H%
MXCON#
Control Register
ESMM
EIFM
00H%
Port
Port CEX4
CEX3
CEX2/ SPICLK
CEX1/ MOSI
CEX0
T2EX
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
Special Function Registers (Continued)
SYMBOL DESCRIPTION DIRECT ADDRESS ADDRESS, SYMBOL, ALTERNATE PORT FUNCTION Reset Value
Port AD15
AD14/ AD22
ADA13/ AD21
AD12/AD20
AD11/ AD19
AD10/ AD18
AD9/ AD17
AD8/ AD16
Port
INT1
INT0
TxD0
RxD0
P4*# Port
TxD1/SS
RxD1/ MISO
PCON#
Power Control Register
SMOD1
SMOD0
00H/10H&
PSW* RCAP2H# RCAP2L#
Program Status Word Timer2 Capture High Timer2 Capture
S0CON* S0BUF S0ADDR S0ADEN S0STAT# Serial Port Control Serial Port Data Buffer Register Serial Port Address Register Serial Port Address Enable Serial Port Status
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
SM0_0/ FE_0
DBMOD_
INTLO_0
CIDIS_0 DBISEL_0
FE_0
BR_0
OE_0
STINT_0
00H%
S1CON#* S1BUF# S1ADDR# S1ADEN# S1STAT# Serial Port Control Serial Port Data buffer Register Serial Port Address Register Serial Port Address Enable Serial Port Status
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
SM0_1/ FE_1
DBMOD_ INTLO_1
CIDIS_1
DBISEL1
FE_1
BR_1
OE_1
STINT_1
00H%
Stack Pointer Stack Pointer Byte When EDATA Supported)
SPCTL# SPCFG# SPDAT#
Control Register Configuration Register Data
SSIG SPIF
SPEN SPWCOL
DORD
MSTR
CPOL PSC3
CPHA PSC2
PSC1
PSC0
00H% 00H%
SPE#
Stack Pointer High
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
Special Function Registers (Continued)
SYMBOL DESCRIPTION DIRECT ADDRESS ADDRESS, SYMBOL, ALTERNATE PORT FUNCTION Reset Value
TCON* Timer Control Register
T2CON#* Timer2 Control Register
EXF2
RCLK
TCLK
EXEN2
C/T2
CP/RL2
T2MOD#
Timer2 Mode Control
T2OE
DCEN
00H%
Timer High Timer High Timer High Timer Timer Timer
TMOD
Timer Mode
GATE
GATE
WDTRST# Watchdog Timer Reset
WDCON#
Watchdog Timer Control
WDPRE2 WDPRE1 WDPRE0
00H%
Notes: SFRs addressable. SFRs modified from added 80C51 SFRs. Extended SFRs accessed preceeding instruction with 51MX escape (opcode A5h). Reserved bits, must written with 0's. Power reset 10H. Other reset 00H. BRGR1 BRGR0 must only written BRGEN BRGCON '0'. them written BRGEN result unpredictable. unimplemented bits (labeled '-') SFRs 'X's (unknown) times. '1's should written these bits, they used other purposes future derivatives. reset values shown these bits '0's although they unknown when read.
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
FUNCTIONAL DESCRIPTION
following paragraphs briefly describe features P87C51Mx2. more detailed information, please refer P87C51Mx2 User Manual 51MX Architecture Reference.
INTERRUPTS
Table summarizes interrupt sources, flag bits, vector addresses, enable bits, priority bits, polling priority, whether each interrupt wake from Power Down mode.
Description External Interrupt Timer Interrupt External Interrupt Timer Interrupt Serial Port Serial Port Rx1,5 Timer Interrupt interrupt Serial Port Serial Port Rx2,6 Serial Port Serial Port Interrupt Rx2,6 Rx1,5
Interrupt Flag Bit(s) TI_0 RI_05 RI_05 TF2, EXF2 CCFn* TI_1 RI_16 RI_16 TI_0 TI_1
Vector Address 0003h 000Bh 0013h 001Bh 0023h 002Bh 0033h 0053h 003Bh 0043h 004Bh 005Bh 0063h 006Bh 0073h
Interrupt Enable Bit(s) (IEN0.0) (IEN0.1) (IEN0.2) (IEN0.3) ES0(IEN0.4) (IEN0.5) (IEN0.6) (IEN1.0) EI10 (IEN1.1) EI11 (IEN1.2) EI11 (IEN1.3) EI12 (IEN1.4) EI13 (IEN1.5) EI13 (IEN1.6) EI14 (IEN1.7)
Interrupt Priority IP0H.0, IP0.0 IP0H.1, IP0.1 IP0H.2, IP0.2 IP0H.3, IP0.3 IP0H.4, IP0.4 IP0H.5, IP0.5 IP0H.6, IP0.6 IP1H.0, IP1.0 IP1H.1, IP1.1 IP1H.2, IP1.2 IP1H.3, IP1.3 IP1H.4, IP1.4 IP1H.5, IP1.5 IP1H.6, IP1.6 IP1H.7, IP1.7
Polling Priority (highest) (lowest)
Power Down Wakeup
Reserved
S0STAT.5 selects combined Serial Port interrupt; S0STAT.5 selects Serial Port interrupt only (and interrupt will different, Note below). S1STAT.5 selects combined Serial Port interrupt; S1STAT.5 selects Serial Port interrupt only (and interrupt will different, Note below). This interrupt used Serial Port interrupt only S0STAT.5 disabled otherwise. This interrupt used Serial Port interrupt only S1STAT.5 disabled otherwise. S0STAT.0 following Serial Port additional flag bits cause this interrupt: FE_0, BR_0, OE_0. S1STAT.0 following Serial Port additional flag bits cause this interrupt: FE_1, BR_1, OE_1. Table Summary Interrupts
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
DATA
P87C51MB2 P87C51MC2 have Kbytes bytes on-chip respectively. Usages different data segments described 51MX Architecture Reference. Data Memory Type DATA IDATA EDATA XDATA Description memory that addressed directly indirectly memory that addressed indirectly (where direct address only) memory that only addressed indirectly memory (on-chip "External Data") that accessed using MOVX instructions Total Table On-Chip Data Memory Usage. Size Bytes) P87C51MB2 1024 2048 P87C51MC2 1024 1792 3072
PORT
P87C51Mx2 fifth port (Port that shared with second UART pins (RXD1 TXD1) pins (MISO SS). This port also addressable accessed same manner other ports, except that associated extended space. Accesses this space same those conventional space except that instructions must preceeded escape code (A5h), described 51MX Architecture Reference.
POWER MODES
P87C51Mx2 supports standard 51MX power modes Stop Clock Mode, Idle Mode Power-Down Mode. PCON register same standard 51MX PCON register. Note that bits PCON.7 PCON.6 UART configurations (see section "UARTs").
ONCEMODE
ONCE ("On-Circuit Emulation") Mode facilitates testing debugging systems without device having removed from circuit. supported P87C51Mx2.
PERIPHERALS
P87C51Mx2 peripherals described more detail User Manual. on-chip peripherals include: Timers: Timers Timer Note: When Timer Timer only used baud rate generator UART UART enhanced UARTs with independent Baud Rate Generator section "UARTs" provides information regarding UARTs. Note: UART shares RXD1 TXD1 with pins. SPEN (SPCTL.6) must cleared (reset value) enable UART operation. Serial Peripheral Interface (SPI). Note: shares pins with UART shares RXD1 TXD1 with pins. SPEN (SPCTL.6) must enable operation. Watchdog Timer. Programmable Counter Array (PCA).
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
UARTS
P87C51Mx2 includes enhanced UART ports with independent Baud Rate Generator: UART standard 51MX enhanced UART described User Manual. selected Timer1 overflow, Timer2 overflow independent Baud Rate Generator. UART only uses independent Baud Rate Generator generate baud rate. same baud rate both transmission reception. Baud Rate Generator described User Manual. Each UARTs enhanced UART SFRs. Please refer descriptions corresponding SFRs User Manual: Register S0CON S0BUF S0ADDR S0ADEN S0STAT S1CON S1BUF S1ADDR S1ADEN S1STAT Description Serial Port Control Serial Port Data Buffer Serial Port Address Serial Port Address Enable Serial Port Status Serial Port Control Serial Port Data Buffer Serial Port Address Serial Port Address Enable Serial Port Status Location 51MX Extended Location Description User Manual SCON SBUF SADDR SADEN SSTAT SCON SBUF SADDR SADEN SSTAT
Table UARTs SFRs.
PCON.7 PCON.6 Bits
PCON.7 PCON.6 bits configure UARTs follows: PCON.7 (SMOD1) Baud Rate Control serial port When baud rate UART will input rate timer baud rate generator, determined BRGCON extended SFR) divided two. When baud rate UART will input rate timer baud rate generator). UART affected this PCON.6 (SMOD0) Framing Error Location: When S0CON S1CON will function UARTs respectively. When S0CON S1CON will used framing error status UART respectively. PCON.6 also determines when UART receive interrupts RI_0 RI_1 occur UART modes (Refer User Manual details.)
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
Baud Rate Selection
UART UART selects baud rate differently shown Tables S0CON.7 (SM0_0) S0CON.6 (SM1_0) T2CON.5/4 (RCLK Receive TCLK Transmit) PCON.7 (SMOD1) BRGCON.1 (S0BRGS) Receive/Transmit Baud Rate UART fOSC/6 T1_rate/32* T1_rate/16* T2_rate/16* fOSC/32 fOSC/16 T1_rate/32* T1_rate/16* T2_rate/16*
UART have different receive transmit baud rates. Table Baud Rate Generation UART T2CON.5 (RCLK) Receive Baud Rate Selection, T2CON.4 (TCLK) Transmit Baud Rate Selection
S1CON.7 (SM0_1)
S1CON.6 (SM1_1)
Baud Rate UART fOSC/6
UART same receive transmit baud rate. Table Baud Rate Generation UART
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
SECURITY BITS
P87C51Mx2 security bits protect users' firmware codes. With none security bits programmed, code program memory verified. With only security (see Table programmed, MOVC instructions executed from external program memory disabled from fetching code bytes from internal memory. latched Reset further programming EPROM disabled. When security bits programmed, addition above, verify mode disabled. When three security bits programmed, conditions above apply external program memory execution disabled.
Security Bits1,2 Protection Description program security features enabled. EEPROM programmable verifiable. MOVC instructions executed from external program memory disabled from fetching code bytes from internal memory, sampled latched Reset, further programming EPROM disabled. Same also verification disabled. Same external execution disabled.
Notes: programmed. unprogrammed. other combination security bits defined. Table EPROM Security Bits
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
ABSOLUTE MAXIMUM RATINGS
PARAMETER Operating temperature under bias Storage temperature range Voltage EA/VPP Voltage other Maximum Power dissipation (based package heat transfer, device power consumption) RATING +125 +150 13.0 -0.5 VDD+0.5V UNIT
Notes: Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these conditions other than those described Electrical Characteristics section this specification implied. This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted.
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
ELECTRICAL CHARACTERISTICS
2.7V 5.5V unless otherwise specified; Tamb +70°C commercial, unless otherwise specified. SYMBOL VIH1 VOL1 VOH1 PARAMETER Input voltage Input high voltage (ports Input high voltage, XTAL1, Output voltage, ports Output voltage, port ALE, PSEN7,8
TEST CONDITIONS
LIMITS -0.5 0.2VDD+0.9 0.7VDD TYP1 0.2VDD-0.1 VDD+0.5 VDD+0.5 -650 /MHz fOSC /MHz fOSC /MHz fOSC /MHz fOSC
UNIT
2.7V, 1.6mA 2.7V, 3.2mA 4.5V, -30µA 2.7V, -10µA
Output high voltage, ports
Output high voltage (port 2.7V, -3.2mA external mode), ALE9, PSEN3 Logical input current, ports 0.4V 4.5V 5.5V, Logical -to-0 transition current, 2.0V, Note ports 0.45 VDD-0.3 Input leakage current, port Power supply current 5.5V Active mode (see Note 3.6V
Idle mode (see Note
5.5V 3.6V Power-down mode clock stopped (see Figure conditions) 5.0V 5.5V
RRST
Internal reset pull-down resistor capacitance10 (except
Notes: Typical ratings guaranteed. values listed room temperature (+25°C), unless otherwise stated. Capacitive loading ports cause spurious noise superimposed ports noise external capacitance discharging into port port pins when these pins make 1-to-0 transitions during operations. worst cases (capacitive loading>100 pF), noise pulse exceed such cases, desirable qualify with Schmitt Trigger, address latch with Schmitt Trigger STROBE input. exceed these conditions provided that single output sinks more than more than outputs exceed test conditions. Capacitive loading ports cause PSEN momentarily fall below VDD-0.7V specification when address bits stabilizing. Pins ports source transition current when they being externally driven from transition current reaches maximum value when approximately 4.5V 5.5V. Figures through test conditions. fOSC oscillator frequency MHz. This value applies Tamb +70°C.
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
Load capacitance port ALE, PSEN load capacitance other outputs 80pF Under steady state (non-transient) conditions, must externally limited follows: Maximum port pin: Maximum 8-bit port: Maximum total outputs: exceeds test condition, exceed related specification. Pins guaranteed sink current greater than listed test conditions. tested VOH1, except when then voltage specification. capacitance characterized tested.
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
ELECTRICAL CHARACTERISTICS
Tamb +70°C commercial unless otherwise specified.1,2,3
2.7V 5.5V SYMBOL FIGURE(S) PARAMETER Variable Clock fOSC tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tAVIV1 tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tAVDV1 tLLWL tAVWL tAVWL1 tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL External Clock High time time Rise time Fall Time tCLCL-tCLCX tCLCL-tCHCX tCLCL-tCLCX tCLCL-tCHCX 24.5 24.5 3,4, 3,4, pulse width pulse width valid data Data hold after Data float after valid data Address (A8-A15) valid data (non-Extended Addressing Mode) Address (A8-A15) valid data (Extended Addressing Mode) Address (A8-A15) valid (non-Extended Addressing Mode) Address (A8-A15) valid (Extended Addressing Mode) Data valid transition Data hold after Data valid high address float high high tCHCX-24 tCLCL +tCLCX-83 2tCLCL-15 tCLCL-20 tCLCX-33 tCHCX-24 3tCLCL +tCLCX-207 tCHCX+25 tCLCL-34 4tCLCL-250 4tCLCL +tCHCX-36 3tCLCL +tCHCX-44 tCLCL +tCLCX+83 tCHCX-11 3tCLCL-166 3tCLCL-166 2tCLCL +tCHCX-141 tCLCL +tCLCX-41 2tCLCL-20 tCLCL-25 tCLCX-16 tCHCX-11 3tCLCL +tCLCX-103 tCHCX+12 tCLCL-17 4tCLCL-125 4tCLCL +tCHCX-28 3tCLCL +tCHCX-34 tCLCL +tCLCX+41 16.5 37.5 3tCLCL-83 3tCLCL-83 2tCLCL +tCHCX-70 41.5 41.5 Oscillator frequency CLock cycle pulse width tCLCL-66 tCHCX-25 tCLCX-25 2tCLCL-108 tCLCX-25 tCLCL+tCHCX tCLCL +tCHCX-91 tCLCX-25 2tCLCL +tCHCX-36 tCLCL +tCHCX-44 tCLCX-12 2tCLCL +tCHCX-28 2tCLCL +tCHCX-34
4.5V 5.5V Variable Clock4 41.5 tCLCL-33 tCHCX-12 tCLCX-12 tCLCX-12 tCLCL+tCHCX tCLCL +tCHCX-46 2tCLCL-54 fOSC=24MHz4 UNIT
fOSC=12MHz4
1,2,3, 4,5,6 Address valid 1,2,3, 4,5,6 Address hold after valid instruction PSEN PSEN pulse width PSEN valid instruction Input instruction hold after PSEN Input instruction float after PSEN Address (A8-A15) valid instruction (non-Extended Addressing Mode) Address (A8-A15) valid instruction (Extended Addressing Mode) PSEN address float
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
2.7V 5.5V SYMBOL FIGURE(S) PARAMETER Variable Shift Register tXLXL tQVXH tXHQX tXHDX tXHDV Interface Operating frequency fSPI 3.0MHz 6.0MHz Cycle time tSPICYC 3.0MHz 6.0MHz Enable lead time (Slave) tSPILEAD 3.0MHz 6.0MHz Enable time (Slave) tSPILAG 3.0MHz 6.0MHz SPICLK high time tSPICLKH Master Slave SPICLK time tSPICLKL tSPIDSU tSPIDH tSPIA tSPIDIS Master Slave Data setup time (Master Slave) Data hold time (Master Slave) Access time (Slave) Disable time (Slave) 3.0MHz 6.0MHz Enable output data valid tSPIDV tSPIOH 3.0MHz 6.0MHz Output data hold time Rise time tSPIR outputs (SPICLK,MOSI, MISO) inputs (SPICLK,MOSI, MISO, Fall time tSPIF outputs (SPICLK,MOSI, MISO) inputs (SPICLK,MOSI, MISO, Serial port clock cycle time Output data setup clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge input data valid 6tCLCL 5tCLCL-221 tCLCL-50 5tCLCL-222 6tCLCL 5tCLCL-110 tCLCL-25 5tCLCL-111 Clock4 fOSC=12MHz4
P87C51MB2/P87C51MC2
4.5V 5.5V Variable Clock4 fOSC=24MHz4 UNIT
Notes: Parameters valid over operating temperature range unless otherwise specified. Load capacitance port ALE, PSEN 100pF, load capacitance other outputs 80pF. Interfacing microcontroller devices with float times 45ns permitted. This limited contention will cause damage Port drivers. Parts tested down MHz, guaranteed operate down 0Hz.
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
EXPLANATION SYMBOLS
Each timing symbol five characters. first character always time). other characters, depending their positions, indicate name signal logical status that signal. designations are: Address Clock Input data Logic level high Instruction (program memory contents) Logic level low, PSEN Output data signal Time Valid signal longer valid logic level Float Examples: tAVLL Time address valid low. tLLPL Time PSEN
tLHLL tLLPL tLLIV PSEN tAVLL tLLAX PORT A0-A7 tAVIV PORT P2.0-P2.7 A8-A15 tPLAZ tPXIX INSTR A0-A7 tPLIV tPXIZ tPLPH
Figure External Program Memory Read Cycle (Non-Extended Memory Cycle)
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
tLHLL tLLPL tLLIV PSEN tAVLL tLLAX PORT A0-A7 tAVIV1 PORT A16-A22,P2.7 A8-A15 tPLAZ tPXIX INSTR A0-A7 tPLIV tPXIZ tPLPH
Figure External Program Memory Read Cycle (Extended Memory Cycle)
tWHLH PSEN tLLDV tLLWL tLLAX tAVLL PORT tAVWL tAVDV PORT P2.0-P2.7 A8-A15 A0-A7 tRLAZ tRLDV tRHDX DATA A0-A7 FROM INSTR tRHDZ tRLRH
Figure External Data Memory Read Cycle (Non-Extended Memory Cycle)
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
tWHLH PSEN tLLDV tLLWL tLLAX tAVLL PORT A0-A7 tAVWL1 tAVDV1 PORT A16-A22,P2.7 A8-A15 tRLAZ tRLDV tRHDX DATA A0-A7 FROM INSTR tRHDZ tRLRH
Figure External Data Memory Read Cycle (Extended Memory Cycle)
tWHLH PSEN
tLLWL tLLAX tAVLL PORT A0-A7 tAVWL PORT tQVWX
tWLWH
tQVWH DATA
tWHQX A0-A7 FROM INSTR
P2.0-P2.7 A8-A15
Figure External Data Memory Write Cycle (Non-Extended Memory Cycle)
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
tWHLH PSEN
tLLWL tLLAX tAVLL PORT A0-A7 tAVWL1 PORT A16-A22,P2.7 tQVWX
tWLWH
tQVWH DATA
tWHQX A0-A7 FROM INSTR
A8-A15
Figure External Data Memory Write Cycle (Extended Memory Cycle)
INSTRUCTION
tXLXL CLOCK tXHQX tQVXH OUTPUT DATA WRITE SBUF tXHDX tXHDV INPUT DATA VALID CLEAR VALID VALID VALID VALID VALID VALID VALID
Figure Shift Register Mode Timing
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
tSPICYC tSPIF tSPICLKH SPICLK (CPOL (output) tSPIF SPICLK (CPOL (output) tSPIDSU tSPIDH tSPICLKL tSPIR tSPICLKH tSPICLKL tSPIR
MISO (input) tSPIDV tSPIF MOSI (output)
MSB/LSB
LSB/MSB
tSPIOH
tSPIDV
tSPIR
Master MSB/LSB
Master LSB/MSB
Figure Master Timing (CPHA
tSPICYC tSPIR tSPICLKH
tSPIF SPICLK (CPOL (output)
tSPICLKL
tSPIF tSPICLKH SPICLK (CPOL (output) tSPIDSU tSPIDH
tSPICLKL
tSPIR
MISO (input) tSPIDV tSPIF MOSI (output)
MSB/LSB
LSB/MSB tSPIDV tSPIR
tSPIOH
tSPIDV
Master MSB/LSB
Master LSB/MSB
Figure Master Timing (CPHA
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
tSPIR tSPILEAD SPICLK (CPOL (input) tSPIF SPICLK (CPOL (input) tSPIA tSPIOH tSPIDV Slave MSB/LSB tSPIOH tSPIDV tSPIOH tSPIDIS tSPICLKL tSPIR tSPICLKH tSPICYC tSPIF tSPICLKH tSPICLKL tSPIR tSPILAG tSPIR
MISO (output)
Slave LSB/MSB
defined
tSPIDSU MOSI (input)
tSPIDH
tSPIDSU
tSPIDSU
tSPIDH
MSB/LSB
LSB/MSB
Figure Slave Timing (CPHA
tSPIR tSPILEAD SPICLK (CPOL (input) tSPIF SPICLK (CPOL (input) tSPIA tSPIOH tSPIDV defined Slave MSB/LSB tSPIOH tSPIDV tSPIOH tSPIDV Slave LSB/MSB tSPIDIS tSPICLKL tSPIR tSPICLKH tSPICYC tSPIF tSPICLKH tSPICLKL tSPIR tSPILAG tSPIR
MISO (output)
tSPIDSU MOSI (input)
tSPIDH
tSPIDSU
tSPIDSU
tSPIDH
MSB/LSB
LSB/MSB
Figure Slave Timing (CPHA
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
VDD-0.5V 0.45V
0.7VDD 0.2VDD-0.1V tCHCL tCLCX tCLCL tCHCX tCLCH
Figure External Clock Drive
(NC) CLOCK SIGNAL XTAL2 XTAL1
Figure Test Condition, Active Mode (All other pins disconnected)
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
(NC) CLOCK SIGNAL XTAL2 XTAL1
Figure Test Condition, Idle Mode (All other pins disconnected)
VDD-0.5V 0.45V
0.7VDD 0.2VDD-0.1V tCHCL tCLCX tCLCL tCHCX tCLCH
Figure Clock Signal Waveform Tests Active Idle Modes tCLCH tCHCL
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
(NC) XTAL2 XTAL1
Figure Test Condition, Power Down Mode (All other pins disconnected, 2.0V 5.5V)
2001
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB with 2KB/3KB
P87C51MB2/P87C51MC2
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition This data sheet contains design target goal specifications product development. Specification change manner without notice. This data sheet contains preliminary data, supplementary data will published later date. Philips Semiconductors reserves right make changes time without notice order improve design supply best possible product. This data sheet contains final specifications. Philips Semiconductors reserves right make changes time without notice order improve design supply best possible product.
Production
Please consult most recently issued datasheet before initiating completing design.
Definitions
Short-form specification data short-form specification extracted from full data sheet with same type number title. detailed information relevant data sheet data handbook. Limiting values definition Limiting values given accordance with Absolute Maximum Rating System (IEC 134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Applications that described herein these products illustrative purposes only. Philips Semiconductors make representation warranty that such applications will suitable specified without further testing modification.
Disclaimers
Life support These products designed life support appliances, devices systems where malfunction these products reasonably expected result personal injury. Philips Semiconductors customers using selling these products such applications their risk agree fully indemnify Philips Semiconductors damages resulting from such application. Right make changes Philips Semiconductors reserves right make changes, without notice, products, including circuits, standard cells, and/or software, described contained herein order improve design and/or performance. Philips Semiconductors assumes responsibility liability these products, conveys license title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified. Philips Semiconductors East Arques Avenue P.O. 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Copyright Philips Electronics North America Corporation 2001 rights reserved. Printed U.S.A. Date release: 04-01 Document order number: 9397 08199
Philips Semiconductors
yyyy
Philips Semiconductors
Errata
Errata sheet
P87C51MB2/P87C51MC2
FUNCTIONAL DEVIATIONS Deviation
RxD1 open drain configuration.
Work-around:
resistor must used this used output. These pins will become port next release fixing this issue.
Deviation
Port does exist RxD1 TxD1 pins. parameters differ from standard port pins.
Work-around:
None. These pins will become port next release.
Deviation
RxD1, TxD1, pins will into once mode.
Work-around:
None. This will fixed next release.
Deviation
UART, contents SBUF change when they shouldn't SM2=1 modes
Work-around:
None. Will fixed next release.
Deviation
UART double buffering will implemented next release.
Work-around:
None.
Deviation
block will implemented next release.
Work-around:
None.
Deviation
Security bits 100% compatible with past 80c51 products.
Work-around:
security bits will compatible next release.
2001
Version
Philips Semiconductors
Errata
Errata sheet
P87C51MB2/P87C51MC2
Deviation
UART mode receive data sampled clock later than standard 80C51 UARTS.
Work-around:
This requires increased data hold time. This will fixed next release.
Deviation
Watchdog timer function function properly fOSC when Count Pulse selection "internal clock, fOSC/2".
Work-around:
None. This will fixed next release.
2001

P87C51MB2/P87C51MC2 80C51 8-bit microcontroller family with extended m

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